diff --git a/Arkanoid.bsf b/Arkanoid.bsf
index 489ebbf..467d433 100644
--- a/Arkanoid.bsf
+++ b/Arkanoid.bsf
@@ -26,8 +26,8 @@ applicable agreement for further details.
(port
(pt 0 32)
(input)
- (text "clk50MHz" (rect 0 0 47 12)(font "Arial" ))
- (text "clk50MHz" (rect 21 27 68 39)(font "Arial" ))
+ (text "clk25MHz" (rect 0 0 47 12)(font "Arial" ))
+ (text "clk25MHz" (rect 21 27 68 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
@@ -96,29 +96,29 @@ applicable agreement for further details.
(port
(pt 152 112)
(output)
- (text "num1[6..0]" (rect 0 0 53 12)(font "Arial" ))
- (text "num1[6..0]" (rect 78 107 131 119)(font "Arial" ))
+ (text "hex0[6..0]" (rect 0 0 49 12)(font "Arial" ))
+ (text "hex0[6..0]" (rect 82 107 131 119)(font "Arial" ))
(line (pt 152 112)(pt 136 112)(line_width 3))
)
(port
(pt 152 128)
(output)
- (text "num2[6..0]" (rect 0 0 53 12)(font "Arial" ))
- (text "num2[6..0]" (rect 78 123 131 135)(font "Arial" ))
+ (text "hex1[6..0]" (rect 0 0 49 12)(font "Arial" ))
+ (text "hex1[6..0]" (rect 82 123 131 135)(font "Arial" ))
(line (pt 152 128)(pt 136 128)(line_width 3))
)
(port
(pt 152 144)
(output)
- (text "num3[6..0]" (rect 0 0 53 12)(font "Arial" ))
- (text "num3[6..0]" (rect 78 139 131 151)(font "Arial" ))
+ (text "hex2[6..0]" (rect 0 0 49 12)(font "Arial" ))
+ (text "hex2[6..0]" (rect 82 139 131 151)(font "Arial" ))
(line (pt 152 144)(pt 136 144)(line_width 3))
)
(port
(pt 152 160)
(output)
- (text "num4[6..0]" (rect 0 0 53 12)(font "Arial" ))
- (text "num4[6..0]" (rect 78 155 131 167)(font "Arial" ))
+ (text "hex3[6..0]" (rect 0 0 49 12)(font "Arial" ))
+ (text "hex3[6..0]" (rect 82 155 131 167)(font "Arial" ))
(line (pt 152 160)(pt 136 160)(line_width 3))
)
(port
@@ -128,16 +128,6 @@ applicable agreement for further details.
(text "led[7..0]" (rect 91 171 131 183)(font "Arial" ))
(line (pt 152 176)(pt 136 176)(line_width 3))
)
- (parameter
- "SCREEN_WIDTH"
- "640"
- ""
- (type "PARAMETER_SIGNED_DEC") )
- (parameter
- "SCREEN_HEIGHT"
- "480"
- ""
- (type "PARAMETER_SIGNED_DEC") )
(parameter
"CELL_SIZE"
"20"
@@ -150,17 +140,12 @@ applicable agreement for further details.
(type "PARAMETER_SIGNED_DEC") )
(parameter
"BALL_SPEED"
- "2"
+ "1"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PLATFORM_WIDTH"
- "8"
- ""
- (type "PARAMETER_SIGNED_DEC") )
- (parameter
- "PLATFORM_SPEED"
- "1"
+ "7"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
diff --git a/Arkanoid.v b/Arkanoid.v
index 460c538..1d8c6f2 100644
--- a/Arkanoid.v
+++ b/Arkanoid.v
@@ -1,187 +1,36 @@
module Arkanoid
-#(
- // Parameters
- parameter SCREEN_WIDTH = 640, // Horizontal screen resolution (in pixels)
- parameter SCREEN_HEIGHT = 480, // Vertical screen resolution (in pixels)
-
- parameter CELL_SIZE = 20, // 1 cell has size of 20x20 pixels.
-
- parameter BALL_SIZE = 1, // Game ball is a square of side 1 cell
- parameter BALL_SPEED = 2, // Number of cells per second
-
- parameter PLATFORM_WIDTH = 8, // Game platform width
- parameter PLATFORM_SPEED = 1, // Number of cells per second
-
- parameter [3:0] BK_COLOR_R = 4'b1111, // Red background
- parameter [3:0] BK_COLOR_G = 4'b0000,
- parameter [3:0] BK_COLOR_B = 4'b0000,
-
- parameter [3:0] STABLE_COLOR_R = 4'b0011, // ??? color :)
- parameter [3:0] STABLE_COLOR_G = 4'b1100,
- parameter [3:0] STABLE_COLOR_B = 4'b0110,
-
- parameter [3:0] BALL_COLOR_R = 4'b0000, // Blue ball
- parameter [3:0] BALL_COLOR_G = 4'b0000,
- parameter [3:0] BALL_COLOR_B = 4'b1111,
-
- parameter [3:0] PLATFORM_COLOR_R = 4'b1111, // Red platforms
- parameter [3:0] PLATFORM_COLOR_G = 4'b0000,
- parameter [3:0] PLATFORM_COLOR_B = 4'b0000
-)
+ `include "arkanoid_header.v"
+ `include "int_to_digital.v"
+ `include "vga_sync.v"
-(
- // Input Ports
- input clk50MHz, // 50 MHz clock on DE1
- input button1, button2, button3, button4, // 4 buttons on DE1 (left<->right for 2 players)
-
- // Output Ports
- output h_sync,
- output v_sync,
- output [3:0] red, green, blue, // Current pixel color (4096 colors = 12 bit)
- output [6:0] num1, num2, num3, num4, // Digital LED's on DE1
- output [7:0] led
-);
-
- //////////////////////////////////////
- // **** BEGIN OF MODULE HEADER **** //
- //////////////////////////////////////
-
- // Output registers
- reg [3:0] red_, green_, blue_;
- reg [6:0] num1_, num2_, num3_, num4_;
- reg [7:0] led_;
-
- localparam FIELD_WIDTH = SCREEN_WIDTH/CELL_SIZE; // Horizontal screen resolution (in cells)
- localparam FIELD_HEIGHT = SCREEN_HEIGHT/CELL_SIZE; // Vertical screen resolution (in cells)
-
- // VGA Module
- localparam line = 799;
- localparam frame = 524;
-
- // 25 MHz clock
- reg clk25MHz_;
- wire clk25MHz;
-
- // 2D array of cells, stores game field state
- reg [1:0] field[0:FIELD_HEIGHT-1][0:FIELD_WIDTH-1];
-
- // Possible cell values: (no comments)
- localparam [1:0] EMPTY_CELL = 2'b00;
- localparam [1:0] STABLE_CELL = 2'b11;
- localparam [1:0] BALL_CELL = 2'b01;
- localparam [1:0] PLATFORM_CELL = 2'b10;
-
- // ATTENTION!!!
- // All definitions below are in cells only.
- //
-
- // Informaton about game ball
- integer ball_position_x; // Current coordinates
- integer ball_position_y;
- reg ball_state; // Current state (0 - stopped, 1 - moving)
- reg [1:0] ball_direction; // Current moving direction
-
- // Possible ball directions:
- localparam [1:0] LEFT_UP = 2'b00;
- localparam [1:0] RIGHT_UP = 2'b01;
- localparam [1:0] LEFT_DOWN = 2'b10;
- localparam [1:0] RIGHT_DOWN = 2'b11;
-
- // Information about game platforms
- integer platform1_position; // Current position (X axis, left border coordinate)
- integer platform2_position;
-
- // VGA variables
- integer h_counter; // Horizontal pixel counter
- integer v_counter; // Vertical pixel counter
- integer h_cell; // Horizontal cell counter
- integer v_cell; // Vertical cell counter
- reg [1:0] current_cell; // Current cell value
-
- // Loops variables
- integer i, j;
-
- // Last buttons state
- reg button1_state;
- reg button2_state;
- reg button3_state;
- reg button4_state;
-
-
- ////////////////////////////////////
- // **** END OF MODULE HEADER **** //
- ////////////////////////////////////
-
- // Initialization of all module variables
- initial
+ task GameRestart;
begin
-
- // Place ball to the center of the screen
- ball_position_x = FIELD_WIDTH/2;
- ball_position_y = FIELD_HEIGHT/2;
- ball_state = 0;
-
- // Place platforms at the center of the borders
+ ball_x = FIELD_WIDTH/2;
+ ball_y = FIELD_HEIGHT-1;
+ ball_direction = RIGHT_UP;
platform1_position = (FIELD_WIDTH-PLATFORM_WIDTH)/2; // central position
platform2_position = platform1_position;
-
- button1_state = 1'b0;
- button2_state = 1'b0;
- button3_state = 1'b0;
- button4_state = 1'b0;
-
- h_counter = 0;
- v_counter = 0;
-
- for (i = 0; i < FIELD_HEIGHT; i = i + 1)
- for (j = 0; j< FIELD_WIDTH; j = j + 1)
- field[i][j] = EMPTY_CELL;
-
- field[ball_position_y][ball_position_x] = BALL_CELL;
-
- num1_ = 7'b0000000;
- num2_ = 7'b0000000;
- num3_ = 7'b0000000;
- num4_ = 7'b0000000;
-
+ game_state = 1'b1;
end
-
- // Frequency divider (50 MHz to 25 MHz, needed for VGA)
- always @ (posedge clk50MHz)
- begin
- clk25MHz_ = ~clk25MHz_;
- end
-
- // VGA sync
- always @ (posedge clk25MHz)
- begin
- if(h_counter == line)
- h_counter <= 0;
- else
- h_counter <= (h_counter + 1);
- end
-
- always @ (posedge clk25MHz)
- begin
- if (v_counter == frame)
- v_counter <= 0;
- else if (h_counter == line)
- v_counter <= (v_counter + 1);
- end
-
+ endtask
-
+ // Main logic
always @ (posedge clk25MHz)
begin
+ // Processing button presses
+
if (button1 != button1_state)
begin
if (button1 == 1'b1)
begin
led_[7] = 1'b1;
led_[6] = 1'b1;
- if (platform1_position > 0)
+
+ if (game_state == 1'b0)
+ GameRestart;
+ else if (platform1_position > 0)
platform1_position = platform1_position - 1;
end
else
@@ -198,7 +47,10 @@ module Arkanoid
begin
led_[5] = 1'b1;
led_[4] = 1'b1;
- if (platform1_position < FIELD_WIDTH-PLATFORM_WIDTH-1)
+
+ if (game_state == 1'b0)
+ GameRestart;
+ else if (platform1_position < FIELD_WIDTH-PLATFORM_WIDTH-1)
platform1_position = platform1_position + 1;
end
else
@@ -215,7 +67,10 @@ module Arkanoid
begin
led_[3] = 1'b1;
led_[2] = 1'b1;
- if (platform2_position > 0)
+
+ if (game_state == 1'b0)
+ GameRestart;
+ else if (platform2_position > 0)
platform2_position = platform2_position - 1;
end
else
@@ -232,7 +87,10 @@ module Arkanoid
begin
led_[1] = 1'b1;
led_[0] = 1'b1;
- if (platform2_position < FIELD_WIDTH-PLATFORM_WIDTH-1)
+
+ if (game_state == 1'b0)
+ GameRestart;
+ else if (platform2_position < FIELD_WIDTH-PLATFORM_WIDTH-1)
platform2_position = platform2_position + 1;
end
else
@@ -241,9 +99,10 @@ module Arkanoid
led_[0] = 1'b0;
end
button4_state = button4;
- end
+ end
+ // Update field (move platforms)
for (i = 0; i < FIELD_WIDTH; i = i + 1)
begin
if ((i >= platform2_position) && (i <= platform2_position+PLATFORM_WIDTH))
@@ -255,7 +114,184 @@ module Arkanoid
field[FIELD_HEIGHT-1][i] = PLATFORM_CELL;
else
field[FIELD_HEIGHT-1][i] = EMPTY_CELL;
- end
+ end
+
+
+ //Update field (move ball)
+ if (game_state)
+ if (ball_clock_counter < BALL_DELAY)
+ ball_clock_counter = ball_clock_counter + 1;
+ else
+ begin
+ ball_clock_counter = 0;
+
+ field[ball_y][ball_x] = EMPTY_CELL;
+
+ case (ball_direction)
+
+ LEFT_UP:
+ begin
+
+ if ((ball_x > 0) && (ball_y > 1))
+ begin
+ ball_x = ball_x - 1;
+ ball_y = ball_y - 1;
+ end
+ else if ((ball_x > 0) && (ball_y == 1))
+ if ((ball_x >= platform2_position) && (ball_x <= platform2_position + PLATFORM_WIDTH))
+ begin
+ ball_direction = LEFT_DOWN;
+ ball_x = ball_x - 1;
+ ball_y = ball_y + 1;
+ end
+ else
+ begin
+ // Goal
+ player1_score = player1_score + 1;
+ game_state = 1'b0;
+ end
+
+ else if ((ball_x == 0) && (ball_y > 1))
+ begin
+ ball_direction = RIGHT_UP;
+ ball_x = ball_x + 1;
+ ball_y = ball_y - 1;
+ end
+
+ else
+ begin
+ ball_direction = RIGHT_DOWN;
+ ball_x = ball_x + 1;
+ ball_y = ball_y + 1;
+ end
+
+ end
+
+ RIGHT_UP:
+ begin
+
+ if ((ball_x < FIELD_WIDTH-1) && (ball_y > 1))
+ begin
+ ball_x = ball_x + 1;
+ ball_y = ball_y - 1;
+ end
+ else if ((ball_x < FIELD_WIDTH-1) && (ball_y == 1))
+ if ((ball_x >= platform2_position) && (ball_x <= platform2_position + PLATFORM_WIDTH))
+ begin
+ ball_direction = RIGHT_DOWN;
+ ball_x = ball_x + 1;
+ ball_y = ball_y + 1;
+ end
+ else
+ begin
+ // Goal
+ player1_score = player1_score + 1;
+ game_state = 1'b0;
+ end
+
+ else if ((ball_x == FIELD_WIDTH-1) && (ball_y > 1))
+ begin
+ ball_direction = LEFT_UP;
+ ball_x = ball_x - 1;
+ ball_y = ball_y - 1;
+ end
+
+ else
+ begin
+ ball_direction = LEFT_DOWN;
+ ball_x = ball_x - 1;
+ ball_y = ball_y + 1;
+ end
+
+ end
+
+ LEFT_DOWN:
+ begin
+
+ if ((ball_x > 0) && (ball_y < FIELD_HEIGHT-2))
+ begin
+ ball_x = ball_x - 1;
+ ball_y = ball_y + 1;
+ end
+ else if ((ball_x > 0) && (ball_y == FIELD_HEIGHT-2))
+ if ((ball_x >= platform1_position) && (ball_x <= platform1_position + PLATFORM_WIDTH))
+ begin
+ ball_direction = LEFT_UP;
+ ball_x = ball_x - 1;
+ ball_y = ball_y - 1;
+ end
+ else
+ begin
+ // Goal
+ player2_score = player2_score + 1;
+ game_state = 1'b0;
+ end
+
+ else if ((ball_x == 0) && (ball_y < FIELD_HEIGHT-2))
+ begin
+ ball_direction = RIGHT_DOWN;
+ ball_x = ball_x + 1;
+ ball_y = ball_y + 1;
+ end
+
+ else
+ begin
+ ball_direction = RIGHT_UP;
+ ball_x = ball_x + 1;
+ ball_y = ball_y - 1;
+ end
+
+ end
+
+ RIGHT_DOWN:
+ begin
+
+ if ((ball_x < FIELD_WIDTH-1) && (ball_y < FIELD_HEIGHT-2))
+ begin
+ ball_x = ball_x + 1;
+ ball_y = ball_y + 1;
+ end
+ else if ((ball_x < FIELD_WIDTH-1) && (ball_y == FIELD_HEIGHT-2))
+ if ((ball_x >= platform1_position) && (ball_x <= platform1_position + PLATFORM_WIDTH))
+ begin
+ ball_direction = RIGHT_UP;
+ ball_x = ball_x + 1;
+ ball_y = ball_y - 1;
+ end
+ else
+ begin
+ // Goal
+ player2_score = player2_score + 1;
+ game_state = 1'b0;
+ end
+
+ else if ((ball_x == FIELD_WIDTH-1) && (ball_y < FIELD_HEIGHT-2))
+ begin
+ ball_direction = LEFT_DOWN;
+ ball_x = ball_x - 1;
+ ball_y = ball_y + 1;
+ end
+
+ else
+ begin
+ ball_direction = LEFT_UP;
+ ball_x = ball_x - 1;
+ ball_y = ball_y - 1;
+ end
+
+ end
+
+ endcase
+
+ if (game_state)
+ field[ball_y][ball_x] = BALL_CELL;
+
+ end
+
+
+ // Update scores
+ IntToDigital(player1_score, hex3_, hex2_);
+ IntToDigital(player2_score, hex1_, hex0_);
// VGA output
@@ -307,9 +343,45 @@ module Arkanoid
end
end
-
- assign clk25MHz = clk25MHz_;
+
+ // Initialization of all module variables
+ initial
+ begin
+
+ game_state = 1'b0;
+
+ // Reset scores
+ player1_score = 0;
+ player2_score = 0;
+
+ // Place ball to the center of the screen
+ ball_clock_counter = 0;
+ ball_x = FIELD_WIDTH/2;
+ ball_y = FIELD_HEIGHT-1;
+ ball_direction = RIGHT_UP;
+
+ // Place platforms at the center of the borders
+ platform1_position = (FIELD_WIDTH-PLATFORM_WIDTH)/2; // central position
+ platform2_position = platform1_position;
+
+ // Clear field
+ for (i = 0; i < FIELD_HEIGHT; i = i + 1)
+ for (j = 0; j< FIELD_WIDTH; j = j + 1)
+ field[i][j] = EMPTY_CELL;
+
+ // Reset buttons state
+ button1_state = 1'b0;
+ button2_state = 1'b0;
+ button3_state = 1'b0;
+ button4_state = 1'b0;
+
+ // Reset VGA counters
+ h_counter = 0;
+ v_counter = 0;
+
+ end
+
assign h_sync = ~((h_counter > 0) && (h_counter < 95));
assign v_sync = ~((v_counter == 0) || (v_counter == 1));
@@ -317,10 +389,11 @@ module Arkanoid
assign green = green_;
assign blue = blue_;
- assign led = led_;
- assign num1 = num1_;
- assign num2 = num2_;
- assign num3 = num3_;
- assign num4 = num4_;
+ assign hex0 = ~hex0_;
+ assign hex1 = ~hex1_;
+ assign hex2 = ~hex2_;
+ assign hex3 = ~hex3_;
+
+ assign led = ~led_;
endmodule
diff --git a/Arkanoid.v.bak b/Arkanoid.v.bak
deleted file mode 100644
index 0420c2e..0000000
--- a/Arkanoid.v.bak
+++ /dev/null
@@ -1,328 +0,0 @@
-module Arkanoid
-
-#(
- // Parameters
- parameter SCREEN_WIDTH = 640, // Horizontal screen resolution (in pixels)
- parameter SCREEN_HEIGHT = 480, // Vertical screen resolution (in pixels)
-
- parameter CELL_SIZE = 20, // 1 cell has size of 20x20 pixels.
-
- parameter BALL_SIZE = 1, // Game ball is a square of side 1 cell
- parameter BALL_SPEED = 2, // Number of cells per second
-
- parameter PLATFORM_WIDTH = 8, // Game platform width
- parameter PLATFORM_SPEED = 1, // Number of cells per second
-
- parameter [3:0] BK_COLOR_R = 4'b1111, // Red background
- parameter [3:0] BK_COLOR_G = 4'b0000,
- parameter [3:0] BK_COLOR_B = 4'b0000,
-
- parameter [3:0] STABLE_COLOR_R = 4'b0011, // ??? color :)
- parameter [3:0] STABLE_COLOR_G = 4'b1100,
- parameter [3:0] STABLE_COLOR_B = 4'b0110,
-
- parameter [3:0] BALL_COLOR_R = 4'b0000, // Blue ball
- parameter [3:0] BALL_COLOR_G = 4'b0000,
- parameter [3:0] BALL_COLOR_B = 4'b1111,
-
- parameter [3:0] PLATFORM_COLOR_R = 4'b1111, // Red platforms
- parameter [3:0] PLATFORM_COLOR_G = 4'b0000,
- parameter [3:0] PLATFORM_COLOR_B = 4'b0000
-)
-
-(
- // Input Ports
- input clk50MHz, // 50 MHz clock on DE1
- input button1, button2, button3, button4, // 4 buttons on DE1 (left<->right for 2 players)
-
- // Output Ports
- output h_sync,
- output v_sync,
- output [3:0] red, green, blue, // Current pixel color (4096 colors = 12 bit)
- output [6:0] num1, num2, num3, num4, // Digital LED's on DE1
- output [7:0] led
-);
-
- //////////////////////////////////////
- // **** BEGIN OF MODULE HEADER **** //
- //////////////////////////////////////
-
- // Output registers
- reg [3:0] red_, green_, blue_;
- reg [6:0] num1_, num2_, num3_, num4_;
- reg [7:0] led_;
-
- localparam FIELD_WIDTH = SCREEN_WIDTH/CELL_SIZE; // Horizontal screen resolution (in cells)
- localparam FIELD_HEIGHT = SCREEN_HEIGHT/CELL_SIZE; // Vertical screen resolution (in cells)
-
- // VGA Module
- localparam line = 799;
- localparam frame = 524;
-
- // 25 MHz clock
- reg clk25MHz_;
- wire clk25MHz;
-
- // 2D array of cells, stores game field state
- reg [1:0] field[0:FIELD_HEIGHT-1][0:FIELD_WIDTH-1];
-
- // Possible cell values: (no comments)
- localparam [1:0] EMPTY_CELL = 2'b00;
- localparam [1:0] STABLE_CELL = 2'b11;
- localparam [1:0] BALL_CELL = 2'b01;
- localparam [1:0] PLATFORM_CELL = 2'b10;
-
- // ATTENTION!!!
- // All definitions below are in cells only.
- //
-
- // Informaton about game ball
- integer ball_position_x; // Current coordinates
- integer ball_position_y;
- reg ball_state; // Current state (0 - stopped, 1 - moving)
- reg [1:0] ball_direction; // Current moving direction
-
- // Possible ball directions:
- localparam [1:0] LEFT_UP = 2'b00;
- localparam [1:0] RIGHT_UP = 2'b01;
- localparam [1:0] LEFT_DOWN = 2'b10;
- localparam [1:0] RIGHT_DOWN = 2'b11;
-
- // Information about game platforms
- integer platform1_position; // Current position (X axis, left border coordinate)
- integer platform2_position;
-
- // VGA variables
- integer h_counter; // Horizontal pixel counter
- integer v_counter; // Vertical pixel counter
- integer h_cell; // Horizontal cell counter
- integer v_cell; // Vertical cell counter
- reg [1:0] current_cell; // Current cell value
-
- // Loops variables
- integer i, j;
-
- // Last buttons state
- reg button1_state;
- reg button2_state;
- reg button3_state;
- reg button4_state;
-
-
- ////////////////////////////////////
- // **** END OF MODULE HEADER **** //
- ////////////////////////////////////
-
- // Initialization of all module variables
- initial
- begin
-
- // Place ball to the center of the screen
- ball_position_x = FIELD_WIDTH/2;
- ball_position_y = FIELD_HEIGHT/2;
- ball_state = 0;
-
- // Place platforms at the center of the borders
- platform1_position = (FIELD_WIDTH-PLATFORM_WIDTH)/2; // central position
- platform2_position = platform1_position;
-
- button1_state = 1'b0;
- button2_state = 1'b0;
- button3_state = 1'b0;
- button4_state = 1'b0;
-
- h_counter = 0;
- v_counter = 0;
-
- for (i = 0; i < FIELD_HEIGHT; i = i + 1)
- for (j = 0; j< FIELD_WIDTH; j = j + 1)
- field[i][j] = EMPTY_CELL;
-
- field[ball_position_y][ball_position_x] = BALL_CELL;
-
- // Print platforms
-
- num1_ = 7'b0000000;
- num2_ = 7'b0000000;
- num3_ = 7'b0000000;
- num4_ = 7'b0000000;
-
- end
-
- // Frequency divider (50 MHz to 25 MHz, needed for VGA)
- always @ (posedge clk50MHz)
- begin
- clk25MHz_ = ~clk25MHz_;
- end
-
- // VGA sync
- always @ (posedge clk25MHz)
- begin
- if(h_counter == line)
- h_counter <= 0;
- else
- h_counter <= (h_counter + 1);
- end
-
- always @ (posedge clk25MHz)
- begin
- if (v_counter == frame)
- v_counter <= 0;
- else if (h_counter == line)
- v_counter <= (v_counter + 1);
- end
-
-
-
- always @ (posedge clk25MHz)
- begin
-
- if (button1 != button1_state)
- begin
- if (button1 == 1'b1)
- begin
- led_[7] = 1'b1;
- led_[6] = 1'b1;
- if (platform1_position > 0)
- platform1_position = platform1_position - 1;
- end
- else
- begin
- led_[7] = 1'b0;
- led_[6] = 1'b0;
- end
- button1_state = button1;
- end
-
- if (button2 != button2_state)
- begin
- if (button2 == 1'b1)
- begin
- led_[5] = 1'b1;
- led_[4] = 1'b1;
- if (platform1_position < FIELD_WIDTH-PLATFORM_WIDTH-1)
- platform1_position = platform1_position + 1;
- end
- else
- begin
- led_[5] = 1'b0;
- led_[4] = 1'b0;
- end
- button2_state = button2;
- end
-
- if (button3 != button3_state)
- begin
- if (button3 == 1'b1)
- begin
- led_[3] = 1'b1;
- led_[2] = 1'b1;
- if (platform2_position > 0)
- platform2_position = platform2_position - 1;
- end
- else
- begin
- led_[3] = 1'b0;
- led_[2] = 1'b0;
- end
- button3_state = button3;
- end
-
- if (button4 != button4_state)
- begin
- if (button4 == 1'b1)
- begin
- led_[1] = 1'b1;
- led_[0] = 1'b1;
- if (platform2_position < FIELD_WIDTH-PLATFORM_WIDTH-1)
- platform2_position = platform2_position + 1;
- end
- else
- begin
- led_[1] = 1'b0;
- led_[0] = 1'b0;
- end
- button4_state = button4;
- end
-
-
- for (i = 0; i < FIELD_WIDTH; i = i + 1)
- begin
- if ((i >= platform2_position) && (i <= platform2_position+PLATFORM_WIDTH))
- field[0][i] = PLATFORM_CELL;
- else
- field[0][i] = EMPTY_CELL;
-
- if ((i >= platform1_position) && (i <= platform1_position+PLATFORM_WIDTH))
- field[FIELD_HEIGHT-1][i] = PLATFORM_CELL;
- else
- field[FIELD_HEIGHT-1][i] = EMPTY_CELL;
- end
-
-
- // VGA output
- h_cell = (h_counter-143)/CELL_SIZE;
- v_cell = (v_counter-34)/CELL_SIZE;
- if ((v_counter > 34) && (v_counter < 514) && (h_counter > 143) && (h_counter < 783))
- begin
-
- current_cell = field[v_cell][h_cell];
-
- case(current_cell)
-
- EMPTY_CELL:
- begin
- red_ = BK_COLOR_R;
- green_ = BK_COLOR_G;
- blue_ = BK_COLOR_B;
- end
-
- STABLE_CELL:
- begin
- red_ = STABLE_COLOR_R;
- green_ = STABLE_COLOR_G;
- blue_ = STABLE_COLOR_B;
- end
-
- BALL_CELL:
- begin
- red_ = BALL_COLOR_R;
- green_ = BALL_COLOR_G;
- blue_ = BALL_COLOR_B;
- end
-
- PLATFORM_CELL:
- begin
- red_ = PLATFORM_COLOR_R;
- green_ = PLATFORM_COLOR_G;
- blue_ = PLATFORM_COLOR_B;
- end
-
- endcase
-
- end
- else
- begin
- red_ = 4'b0000;
- green_ = 4'b0000;
- blue_ = 4'b0000;
- end
-
- end
-
- assign clk25MHz = clk25MHz_;
-
- assign h_sync = ~((h_counter > 0) && (h_counter < 95));
- assign v_sync = ~((v_counter == 0) || (v_counter == 1));
-
- assign red = red_;
- assign green = green_;
- assign blue = blue_;
-
- assign led = led_;
- assign num1 = num1_;
- assign num2 = num2_;
- assign num3 = num3_;
- assign num4 = num4_;
-
-endmodule
diff --git a/ClockDivider.bsf b/ClockDivider.bsf
new file mode 100644
index 0000000..b84581d
--- /dev/null
+++ b/ClockDivider.bsf
@@ -0,0 +1,43 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 64 64 216 128)
+ (text "ClockDivider" (rect 5 0 68 12)(font "Arial" ))
+ (text "inst" (rect 8 48 25 60)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "clk50MHz" (rect 0 0 47 12)(font "Arial" ))
+ (text "clk50MHz" (rect 21 27 68 39)(font "Arial" ))
+ (line (pt 0 32)(pt 16 32)(line_width 1))
+ )
+ (port
+ (pt 152 32)
+ (output)
+ (text "clk25MHz" (rect 0 0 47 12)(font "Arial" ))
+ (text "clk25MHz" (rect 84 27 131 39)(font "Arial" ))
+ (line (pt 152 32)(pt 136 32)(line_width 1))
+ )
+ (drawing
+ (rectangle (rect 16 16 136 48)(line_width 1))
+ )
+)
diff --git a/ClockDivider.v b/ClockDivider.v
new file mode 100644
index 0000000..9cbdade
--- /dev/null
+++ b/ClockDivider.v
@@ -0,0 +1,14 @@
+module ClockDivider (clk50MHz, clk25MHz);
+input clk50MHz;
+output clk25MHz;
+
+reg clk25MHz_;
+
+always @ (posedge clk50MHz)
+begin
+ clk25MHz_ = ~clk25MHz_;
+end
+
+assign clk25MHz = clk25MHz_;
+
+endmodule
diff --git a/Debouncer.bsf b/Debouncer.bsf
new file mode 100644
index 0000000..ed44502
--- /dev/null
+++ b/Debouncer.bsf
@@ -0,0 +1,50 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 16 16 152 112)
+ (text "Debouncer" (rect 5 0 58 12)(font "Arial" ))
+ (text "inst" (rect 8 80 25 92)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "noisy" (rect 0 0 27 12)(font "Arial" ))
+ (text "noisy" (rect 21 27 48 39)(font "Arial" ))
+ (line (pt 0 32)(pt 16 32)(line_width 1))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "clk" (rect 0 0 14 12)(font "Arial" ))
+ (text "clk" (rect 21 43 35 55)(font "Arial" ))
+ (line (pt 0 48)(pt 16 48)(line_width 1))
+ )
+ (port
+ (pt 136 32)
+ (output)
+ (text "debounced" (rect 0 0 53 12)(font "Arial" ))
+ (text "debounced" (rect 62 27 115 39)(font "Arial" ))
+ (line (pt 136 32)(pt 120 32)(line_width 1))
+ )
+ (drawing
+ (rectangle (rect 16 16 120 80)(line_width 1))
+ )
+)
diff --git a/Debouncer.v b/Debouncer.v
new file mode 100644
index 0000000..533f972
--- /dev/null
+++ b/Debouncer.v
@@ -0,0 +1,22 @@
+module Debouncer (noisy, clk, debounced);
+
+input clk;
+input noisy;
+output reg debounced;
+
+reg [7:0] button_reg;
+
+always @ (posedge clk)
+begin
+
+ button_reg[7:0] <= {button_reg[6:0],noisy}; //shift register
+
+ if(button_reg[7:0] == 8'b00000000)
+ debounced <= 1'b0;
+ else if(button_reg[7:0] == 8'b11111111)
+ debounced <= 1'b1;
+ else
+ debounced <= debounced;
+end
+
+endmodule
diff --git a/TotalScheme.bdf b/TotalScheme.bdf
index 9ba07ce..d2da771 100644
--- a/TotalScheme.bdf
+++ b/TotalScheme.bdf
@@ -22,7 +22,7 @@ applicable agreement for further details.
(header "graphic" (version "1.3"))
(pin
(input)
- (rect 296 152 464 168)
+ (rect -72 -168 96 -152)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "clk_50MHz" (rect 5 0 58 12)(font "Arial" ))
(pt 168 8)
@@ -35,11 +35,11 @@ applicable agreement for further details.
(line (pt 117 12)(pt 121 8)(line_width 1))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
- (annotation_block (location)(rect 240 152 288 168))
+ (annotation_block (location)(rect -128 -168 -80 -152))
)
(pin
(input)
- (rect 296 168 464 184)
+ (rect -72 -72 96 -56)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "button1" (rect 5 0 41 12)(font "Arial" ))
(pt 168 8)
@@ -52,11 +52,11 @@ applicable agreement for further details.
(line (pt 117 12)(pt 121 8)(line_width 1))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
- (annotation_block (location)(rect 240 168 296 184))
+ (annotation_block (location)(rect -128 -72 -72 -56))
)
(pin
(input)
- (rect 296 184 464 200)
+ (rect -72 24 96 40)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "button2" (rect 5 0 41 12)(font "Arial" ))
(pt 168 8)
@@ -69,11 +69,11 @@ applicable agreement for further details.
(line (pt 117 12)(pt 121 8)(line_width 1))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
- (annotation_block (location)(rect 240 184 296 200))
+ (annotation_block (location)(rect -128 24 -72 40))
)
(pin
(input)
- (rect 296 200 464 216)
+ (rect -72 120 96 136)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "button3" (rect 5 0 41 12)(font "Arial" ))
(pt 168 8)
@@ -86,11 +86,11 @@ applicable agreement for further details.
(line (pt 117 12)(pt 121 8)(line_width 1))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
- (annotation_block (location)(rect 240 200 296 216))
+ (annotation_block (location)(rect -128 120 -72 136))
)
(pin
(input)
- (rect 296 216 464 232)
+ (rect -72 216 96 232)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "button4" (rect 5 0 41 12)(font "Arial" ))
(pt 168 8)
@@ -103,79 +103,11 @@ applicable agreement for further details.
(line (pt 117 12)(pt 121 8)(line_width 1))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
- (annotation_block (location)(rect 240 216 296 232))
+ (annotation_block (location)(rect -128 216 -72 232))
)
(pin
(output)
- (rect 912 304 1088 320)
- (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
- (text "led1[6..0]" (rect 90 0 136 12)(font "Arial" ))
- (pt 0 8)
- (drawing
- (line (pt 0 8)(pt 52 8)(line_width 1))
- (line (pt 52 4)(pt 78 4)(line_width 1))
- (line (pt 52 12)(pt 78 12)(line_width 1))
- (line (pt 52 12)(pt 52 4)(line_width 1))
- (line (pt 78 4)(pt 82 8)(line_width 1))
- (line (pt 82 8)(pt 78 12)(line_width 1))
- (line (pt 78 12)(pt 82 8)(line_width 1))
- )
- (annotation_block (location)(rect 1320 320 1368 424))
-)
-(pin
- (output)
- (rect 912 320 1088 336)
- (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
- (text "led2[6..0]" (rect 90 0 136 12)(font "Arial" ))
- (pt 0 8)
- (drawing
- (line (pt 0 8)(pt 52 8)(line_width 1))
- (line (pt 52 4)(pt 78 4)(line_width 1))
- (line (pt 52 12)(pt 78 12)(line_width 1))
- (line (pt 52 12)(pt 52 4)(line_width 1))
- (line (pt 78 4)(pt 82 8)(line_width 1))
- (line (pt 82 8)(pt 78 12)(line_width 1))
- (line (pt 78 12)(pt 82 8)(line_width 1))
- )
- (annotation_block (location)(rect 1248 336 1296 440))
-)
-(pin
- (output)
- (rect 912 336 1088 352)
- (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
- (text "led3[6..0]" (rect 90 0 136 12)(font "Arial" ))
- (pt 0 8)
- (drawing
- (line (pt 0 8)(pt 52 8)(line_width 1))
- (line (pt 52 4)(pt 78 4)(line_width 1))
- (line (pt 52 12)(pt 78 12)(line_width 1))
- (line (pt 52 12)(pt 52 4)(line_width 1))
- (line (pt 78 4)(pt 82 8)(line_width 1))
- (line (pt 82 8)(pt 78 12)(line_width 1))
- (line (pt 78 12)(pt 82 8)(line_width 1))
- )
- (annotation_block (location)(rect 1176 352 1224 456))
-)
-(pin
- (output)
- (rect 912 352 1088 368)
- (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
- (text "led4[6..0]" (rect 90 0 136 12)(font "Arial" ))
- (pt 0 8)
- (drawing
- (line (pt 0 8)(pt 52 8)(line_width 1))
- (line (pt 52 4)(pt 78 4)(line_width 1))
- (line (pt 52 12)(pt 78 12)(line_width 1))
- (line (pt 52 12)(pt 52 4)(line_width 1))
- (line (pt 78 4)(pt 82 8)(line_width 1))
- (line (pt 82 8)(pt 78 12)(line_width 1))
- (line (pt 78 12)(pt 82 8)(line_width 1))
- )
- (annotation_block (location)(rect 1104 368 1152 472))
-)
-(pin
- (output)
- (rect 912 152 1088 168)
+ (rect 856 96 1032 112)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "h_sync" (rect 90 0 126 12)(font "Arial" ))
(pt 0 8)
@@ -188,11 +120,11 @@ applicable agreement for further details.
(line (pt 82 8)(pt 78 12)(line_width 1))
(line (pt 78 12)(pt 82 8)(line_width 1))
)
- (annotation_block (location)(rect 1088 152 1144 168))
+ (annotation_block (location)(rect 1032 96 1088 112))
)
(pin
(output)
- (rect 912 184 1088 200)
+ (rect 856 184 1032 200)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "red[3..0]" (rect 90 0 131 12)(font "Arial" ))
(pt 0 8)
@@ -205,11 +137,11 @@ applicable agreement for further details.
(line (pt 82 8)(pt 78 12)(line_width 1))
(line (pt 78 12)(pt 82 8)(line_width 1))
)
- (annotation_block (location)(rect 1248 200 1296 256))
+ (annotation_block (location)(rect 1192 200 1240 256))
)
(pin
(output)
- (rect 912 200 1088 216)
+ (rect 856 200 1032 216)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "green[3..0]" (rect 90 0 143 12)(font "Arial" ))
(pt 0 8)
@@ -222,11 +154,11 @@ applicable agreement for further details.
(line (pt 82 8)(pt 78 12)(line_width 1))
(line (pt 78 12)(pt 82 8)(line_width 1))
)
- (annotation_block (location)(rect 1176 216 1232 272))
+ (annotation_block (location)(rect 1120 216 1176 272))
)
(pin
(output)
- (rect 912 216 1088 232)
+ (rect 856 216 1032 232)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "blue[3..0]" (rect 90 0 136 12)(font "Arial" ))
(pt 0 8)
@@ -239,11 +171,11 @@ applicable agreement for further details.
(line (pt 82 8)(pt 78 12)(line_width 1))
(line (pt 78 12)(pt 82 8)(line_width 1))
)
- (annotation_block (location)(rect 1104 232 1160 288))
+ (annotation_block (location)(rect 1048 232 1104 288))
)
(pin
(output)
- (rect 912 168 1088 184)
+ (rect 856 112 1032 128)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "v_sync" (rect 90 0 127 12)(font "Arial" ))
(pt 0 8)
@@ -256,11 +188,11 @@ applicable agreement for further details.
(line (pt 82 8)(pt 78 12)(line_width 1))
(line (pt 78 12)(pt 82 8)(line_width 1))
)
- (annotation_block (location)(rect 1088 168 1144 184))
+ (annotation_block (location)(rect 1032 112 1088 128))
)
(pin
(output)
- (rect 912 424 1088 440)
+ (rect 856 448 1032 464)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "led[7..0]" (rect 90 0 130 12)(font "Arial" ))
(pt 0 8)
@@ -273,11 +205,80 @@ applicable agreement for further details.
(line (pt 82 8)(pt 78 12)(line_width 1))
(line (pt 78 12)(pt 82 8)(line_width 1))
)
+ (annotation_block (location)(rect 1048 464 1104 576))
+)
+(pin
+ (output)
+ (rect 856 280 1032 296)
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+ (text "hex0[6..0]" (rect 90 0 139 12)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8)(line_width 1))
+ (line (pt 52 4)(pt 78 4)(line_width 1))
+ (line (pt 52 12)(pt 78 12)(line_width 1))
+ (line (pt 52 12)(pt 52 4)(line_width 1))
+ (line (pt 78 4)(pt 82 8)(line_width 1))
+ (line (pt 82 8)(pt 78 12)(line_width 1))
+ (line (pt 78 12)(pt 82 8)(line_width 1))
+ )
+ (annotation_block (location)(rect 1264 296 1312 400))
+)
+(pin
+ (output)
+ (rect 856 296 1032 312)
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+ (text "hex1[6..0]" (rect 90 0 139 12)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8)(line_width 1))
+ (line (pt 52 4)(pt 78 4)(line_width 1))
+ (line (pt 52 12)(pt 78 12)(line_width 1))
+ (line (pt 52 12)(pt 52 4)(line_width 1))
+ (line (pt 78 4)(pt 82 8)(line_width 1))
+ (line (pt 82 8)(pt 78 12)(line_width 1))
+ (line (pt 78 12)(pt 82 8)(line_width 1))
+ )
+ (annotation_block (location)(rect 1192 312 1240 416))
+)
+(pin
+ (output)
+ (rect 856 312 1032 328)
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+ (text "hex2[6..0]" (rect 90 0 139 12)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8)(line_width 1))
+ (line (pt 52 4)(pt 78 4)(line_width 1))
+ (line (pt 52 12)(pt 78 12)(line_width 1))
+ (line (pt 52 12)(pt 52 4)(line_width 1))
+ (line (pt 78 4)(pt 82 8)(line_width 1))
+ (line (pt 82 8)(pt 78 12)(line_width 1))
+ (line (pt 78 12)(pt 82 8)(line_width 1))
+ )
+ (annotation_block (location)(rect 1120 328 1168 432))
+)
+(pin
+ (output)
+ (rect 856 328 1032 344)
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+ (text "hex3[6..0]" (rect 90 0 139 12)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8)(line_width 1))
+ (line (pt 52 4)(pt 78 4)(line_width 1))
+ (line (pt 52 12)(pt 78 12)(line_width 1))
+ (line (pt 52 12)(pt 52 4)(line_width 1))
+ (line (pt 78 4)(pt 82 8)(line_width 1))
+ (line (pt 82 8)(pt 78 12)(line_width 1))
+ (line (pt 78 12)(pt 82 8)(line_width 1))
+ )
+ (annotation_block (location)(rect 1048 344 1096 448))
)
(symbol
- (rect 528 128 680 352)
- (text "Arkanoid" (rect 5 0 47 12)(font "Arial" ))
- (text "inst" (rect 8 208 25 220)(font "Arial" ))
+ (rect 160 -192 312 -128)
+ (text "ClockDivider" (rect 5 0 68 12)(font "Arial" ))
+ (text "inst1" (rect 8 48 31 60)(font "Arial" ))
(port
(pt 0 32)
(input)
@@ -285,6 +286,144 @@ applicable agreement for further details.
(text "clk50MHz" (rect 21 27 68 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
+ (port
+ (pt 152 32)
+ (output)
+ (text "clk25MHz" (rect 0 0 47 12)(font "Arial" ))
+ (text "clk25MHz" (rect 84 27 131 39)(font "Arial" ))
+ (line (pt 152 32)(pt 136 32)(line_width 1))
+ )
+ (drawing
+ (rectangle (rect 16 16 136 48)(line_width 1))
+ )
+)
+(symbol
+ (rect 168 -96 304 0)
+ (text "Debouncer" (rect 5 0 58 12)(font "Arial" ))
+ (text "inst2" (rect 8 80 31 92)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "noisy" (rect 0 0 27 12)(font "Arial" ))
+ (text "noisy" (rect 21 27 48 39)(font "Arial" ))
+ (line (pt 0 32)(pt 16 32)(line_width 1))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "clk" (rect 0 0 14 12)(font "Arial" ))
+ (text "clk" (rect 21 43 35 55)(font "Arial" ))
+ (line (pt 0 48)(pt 16 48)(line_width 1))
+ )
+ (port
+ (pt 136 32)
+ (output)
+ (text "debounced" (rect 0 0 53 12)(font "Arial" ))
+ (text "debounced" (rect 62 27 115 39)(font "Arial" ))
+ (line (pt 136 32)(pt 120 32)(line_width 1))
+ )
+ (drawing
+ (rectangle (rect 16 16 120 80)(line_width 1))
+ )
+)
+(symbol
+ (rect 168 0 304 96)
+ (text "Debouncer" (rect 5 0 58 12)(font "Arial" ))
+ (text "inst3" (rect 8 80 31 92)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "noisy" (rect 0 0 27 12)(font "Arial" ))
+ (text "noisy" (rect 21 27 48 39)(font "Arial" ))
+ (line (pt 0 32)(pt 16 32)(line_width 1))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "clk" (rect 0 0 14 12)(font "Arial" ))
+ (text "clk" (rect 21 43 35 55)(font "Arial" ))
+ (line (pt 0 48)(pt 16 48)(line_width 1))
+ )
+ (port
+ (pt 136 32)
+ (output)
+ (text "debounced" (rect 0 0 53 12)(font "Arial" ))
+ (text "debounced" (rect 62 27 115 39)(font "Arial" ))
+ (line (pt 136 32)(pt 120 32)(line_width 1))
+ )
+ (drawing
+ (rectangle (rect 16 16 120 80)(line_width 1))
+ )
+)
+(symbol
+ (rect 168 96 304 192)
+ (text "Debouncer" (rect 5 0 58 12)(font "Arial" ))
+ (text "inst4" (rect 8 80 31 92)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "noisy" (rect 0 0 27 12)(font "Arial" ))
+ (text "noisy" (rect 21 27 48 39)(font "Arial" ))
+ (line (pt 0 32)(pt 16 32)(line_width 1))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "clk" (rect 0 0 14 12)(font "Arial" ))
+ (text "clk" (rect 21 43 35 55)(font "Arial" ))
+ (line (pt 0 48)(pt 16 48)(line_width 1))
+ )
+ (port
+ (pt 136 32)
+ (output)
+ (text "debounced" (rect 0 0 53 12)(font "Arial" ))
+ (text "debounced" (rect 62 27 115 39)(font "Arial" ))
+ (line (pt 136 32)(pt 120 32)(line_width 1))
+ )
+ (drawing
+ (rectangle (rect 16 16 120 80)(line_width 1))
+ )
+)
+(symbol
+ (rect 168 192 304 288)
+ (text "Debouncer" (rect 5 0 58 12)(font "Arial" ))
+ (text "inst5" (rect 8 80 31 92)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "noisy" (rect 0 0 27 12)(font "Arial" ))
+ (text "noisy" (rect 21 27 48 39)(font "Arial" ))
+ (line (pt 0 32)(pt 16 32)(line_width 1))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "clk" (rect 0 0 14 12)(font "Arial" ))
+ (text "clk" (rect 21 43 35 55)(font "Arial" ))
+ (line (pt 0 48)(pt 16 48)(line_width 1))
+ )
+ (port
+ (pt 136 32)
+ (output)
+ (text "debounced" (rect 0 0 53 12)(font "Arial" ))
+ (text "debounced" (rect 62 27 115 39)(font "Arial" ))
+ (line (pt 136 32)(pt 120 32)(line_width 1))
+ )
+ (drawing
+ (rectangle (rect 16 16 120 80)(line_width 1))
+ )
+)
+(symbol
+ (rect 464 128 616 352)
+ (text "Arkanoid" (rect 5 0 47 12)(font "Arial" ))
+ (text "inst" (rect 8 208 25 220)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "clk25MHz" (rect 0 0 47 12)(font "Arial" ))
+ (text "clk25MHz" (rect 21 27 68 39)(font "Arial" ))
+ (line (pt 0 32)(pt 16 32)(line_width 1))
+ )
(port
(pt 0 48)
(input)
@@ -351,29 +490,29 @@ applicable agreement for further details.
(port
(pt 152 112)
(output)
- (text "num1[6..0]" (rect 0 0 53 12)(font "Arial" ))
- (text "num1[6..0]" (rect 78 107 131 119)(font "Arial" ))
+ (text "hex0[6..0]" (rect 0 0 49 12)(font "Arial" ))
+ (text "hex0[6..0]" (rect 82 107 131 119)(font "Arial" ))
(line (pt 152 112)(pt 136 112)(line_width 3))
)
(port
(pt 152 128)
(output)
- (text "num2[6..0]" (rect 0 0 53 12)(font "Arial" ))
- (text "num2[6..0]" (rect 78 123 131 135)(font "Arial" ))
+ (text "hex1[6..0]" (rect 0 0 49 12)(font "Arial" ))
+ (text "hex1[6..0]" (rect 82 123 131 135)(font "Arial" ))
(line (pt 152 128)(pt 136 128)(line_width 3))
)
(port
(pt 152 144)
(output)
- (text "num3[6..0]" (rect 0 0 53 12)(font "Arial" ))
- (text "num3[6..0]" (rect 78 139 131 151)(font "Arial" ))
+ (text "hex2[6..0]" (rect 0 0 49 12)(font "Arial" ))
+ (text "hex2[6..0]" (rect 82 139 131 151)(font "Arial" ))
(line (pt 152 144)(pt 136 144)(line_width 3))
)
(port
(pt 152 160)
(output)
- (text "num4[6..0]" (rect 0 0 53 12)(font "Arial" ))
- (text "num4[6..0]" (rect 78 155 131 167)(font "Arial" ))
+ (text "hex3[6..0]" (rect 0 0 49 12)(font "Arial" ))
+ (text "hex3[6..0]" (rect 82 155 131 167)(font "Arial" ))
(line (pt 152 160)(pt 136 160)(line_width 3))
)
(port
@@ -383,16 +522,6 @@ applicable agreement for further details.
(text "led[7..0]" (rect 91 171 131 183)(font "Arial" ))
(line (pt 152 176)(pt 136 176)(line_width 3))
)
- (parameter
- "SCREEN_WIDTH"
- "640"
- ""
- (type "PARAMETER_SIGNED_DEC") )
- (parameter
- "SCREEN_HEIGHT"
- "480"
- ""
- (type "PARAMETER_SIGNED_DEC") )
(parameter
"CELL_SIZE"
"20"
@@ -405,32 +534,27 @@ applicable agreement for further details.
(type "PARAMETER_SIGNED_DEC") )
(parameter
"BALL_SPEED"
- "2"
+ "3"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PLATFORM_WIDTH"
- "8"
- ""
- (type "PARAMETER_SIGNED_DEC") )
- (parameter
- "PLATFORM_SPEED"
- "1"
+ "7"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"BK_COLOR_R"
- "0000"
+ "1111"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"BK_COLOR_G"
- "0000"
+ "1111"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"BK_COLOR_B"
- "0000"
+ "1111"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
@@ -478,161 +602,238 @@ applicable agreement for further details.
"0000"
""
(type "PARAMETER_UNSIGNED_BIN") )
- (parameter
- "PLATFORM_HEIGHT"
- "1"
- ""
- (type "PARAMETER_SIGNED_DEC") )
(drawing
(rectangle (rect 16 16 136 208)(line_width 1))
)
- (annotation_block (parameter)(rect 528 -168 760 128))
-)
-(symbol
- (rect 816 416 864 448)
- (text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
- (text "inst1" (rect 3 21 26 33)(font "Arial" ))
- (port
- (pt 0 16)
- (input)
- (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
- (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
- (line (pt 0 16)(pt 13 16)(line_width 1))
- )
- (port
- (pt 48 16)
- (output)
- (text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
- (text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
- (line (pt 39 16)(pt 48 16)(line_width 1))
- )
- (drawing
- (line (pt 13 25)(pt 13 7)(line_width 1))
- (line (pt 13 7)(pt 31 16)(line_width 1))
- (line (pt 13 25)(pt 31 16)(line_width 1))
- (circle (rect 31 12 39 20)(line_width 1))
- )
+ (annotation_block (parameter)(rect 464 -112 696 128))
)
(connector
- (pt 680 240)
- (pt 808 240)
- (bus)
+ (pt 792 104)
+ (pt 856 104)
)
(connector
- (pt 680 256)
- (pt 792 256)
- (bus)
+ (pt 808 120)
+ (pt 856 120)
)
(connector
- (pt 680 272)
- (pt 776 272)
- (bus)
+ (pt 792 104)
+ (pt 792 160)
)
(connector
- (pt 680 288)
- (pt 760 288)
- (bus)
+ (pt 808 120)
+ (pt 808 176)
)
(connector
- (pt 528 160)
- (pt 464 160)
-)
-(connector
- (pt 528 176)
- (pt 464 176)
-)
-(connector
- (pt 528 192)
- (pt 464 192)
-)
-(connector
- (pt 528 208)
+ (pt 320 208)
(pt 464 208)
)
(connector
- (pt 528 224)
- (pt 464 224)
+ (pt 336 192)
+ (pt 464 192)
)
(connector
- (pt 680 160)
- (pt 912 160)
+ (pt 352 176)
+ (pt 464 176)
)
(connector
- (pt 680 176)
- (pt 912 176)
+ (pt 616 160)
+ (pt 792 160)
)
(connector
- (pt 680 192)
- (pt 912 192)
+ (pt 616 176)
+ (pt 808 176)
+)
+(connector
+ (pt 616 192)
+ (pt 856 192)
(bus)
)
(connector
- (pt 680 208)
- (pt 912 208)
+ (pt 616 208)
+ (pt 856 208)
(bus)
)
(connector
- (pt 680 224)
- (pt 912 224)
+ (pt 616 224)
+ (pt 856 224)
+ (bus)
+)
+(connector
+ (pt 856 288)
+ (pt 808 288)
+ (bus)
+)
+(connector
+ (pt 616 240)
+ (pt 808 240)
(bus)
)
(connector
(pt 808 240)
- (pt 808 312)
+ (pt 808 288)
(bus)
)
(connector
- (pt 808 312)
- (pt 912 312)
+ (pt 856 304)
+ (pt 792 304)
+ (bus)
+)
+(connector
+ (pt 616 256)
+ (pt 792 256)
(bus)
)
(connector
(pt 792 256)
- (pt 792 328)
+ (pt 792 304)
(bus)
)
(connector
- (pt 792 328)
- (pt 912 328)
+ (pt 856 320)
+ (pt 776 320)
+ (bus)
+)
+(connector
+ (pt 856 336)
+ (pt 760 336)
+ (bus)
+)
+(connector
+ (pt 616 272)
+ (pt 776 272)
(bus)
)
(connector
(pt 776 272)
- (pt 776 344)
+ (pt 776 320)
(bus)
)
(connector
- (pt 776 344)
- (pt 912 344)
+ (pt 616 288)
+ (pt 760 288)
(bus)
)
(connector
(pt 760 288)
- (pt 760 360)
+ (pt 760 336)
(bus)
)
(connector
- (pt 760 360)
- (pt 912 360)
+ (pt 856 456)
+ (pt 696 456)
(bus)
)
(connector
- (pt 680 304)
- (pt 720 304)
+ (pt 616 304)
+ (pt 696 304)
(bus)
)
(connector
- (pt 720 304)
- (pt 720 432)
+ (pt 696 456)
+ (pt 696 304)
(bus)
)
(connector
- (pt 912 432)
- (pt 864 432)
- (bus)
+ (pt 464 160)
+ (pt 416 160)
)
(connector
- (pt 720 432)
- (pt 816 432)
- (bus)
+ (pt 144 240)
+ (pt 168 240)
)
+(connector
+ (pt 96 224)
+ (pt 168 224)
+)
+(connector
+ (pt 304 224)
+ (pt 464 224)
+)
+(connector
+ (pt 144 144)
+ (pt 168 144)
+)
+(connector
+ (pt 320 208)
+ (pt 320 128)
+)
+(connector
+ (pt 320 128)
+ (pt 304 128)
+)
+(connector
+ (pt 144 144)
+ (pt 144 240)
+)
+(connector
+ (pt 96 128)
+ (pt 168 128)
+)
+(connector
+ (pt 416 -160)
+ (pt 312 -160)
+)
+(connector
+ (pt 96 -160)
+ (pt 160 -160)
+)
+(connector
+ (pt 144 -48)
+ (pt 168 -48)
+)
+(connector
+ (pt 352 176)
+ (pt 352 -64)
+)
+(connector
+ (pt 352 -64)
+ (pt 304 -64)
+)
+(connector
+ (pt 96 -64)
+ (pt 168 -64)
+)
+(connector
+ (pt 144 48)
+ (pt 168 48)
+)
+(connector
+ (pt 336 192)
+ (pt 336 32)
+)
+(connector
+ (pt 336 32)
+ (pt 304 32)
+)
+(connector
+ (pt 144 48)
+ (pt 144 144)
+)
+(connector
+ (pt 96 32)
+ (pt 168 32)
+)
+(connector
+ (pt 416 -112)
+ (pt 144 -112)
+)
+(connector
+ (pt 416 -160)
+ (pt 416 -112)
+)
+(connector
+ (pt 416 -112)
+ (pt 416 160)
+)
+(connector
+ (pt 144 -112)
+ (pt 144 -48)
+)
+(connector
+ (pt 144 -48)
+ (pt 144 48)
+)
+(junction (pt 144 144))
+(junction (pt 144 -48))
+(junction (pt 144 48))
+(junction (pt 416 -112))
diff --git a/arkanoid_header.v b/arkanoid_header.v
new file mode 100644
index 0000000..8da7832
--- /dev/null
+++ b/arkanoid_header.v
@@ -0,0 +1,117 @@
+`ifndef _arkanoid_header_
+`define _arkanoid_header_
+
+#(
+ // Parameters
+
+ parameter CELL_SIZE = 20, // 1 cell has size of 20x20 pixels.
+
+ parameter BALL_SIZE = 1, // Game ball is a square of side 1 cell
+ parameter BALL_SPEED = 1, // Number of cells per second
+
+ parameter PLATFORM_WIDTH = 7, // Game platform width
+
+ parameter [3:0] BK_COLOR_R = 4'b1111, // Red background
+ parameter [3:0] BK_COLOR_G = 4'b0000,
+ parameter [3:0] BK_COLOR_B = 4'b0000,
+
+ parameter [3:0] STABLE_COLOR_R = 4'b0011, // ??? color :)
+ parameter [3:0] STABLE_COLOR_G = 4'b1100,
+ parameter [3:0] STABLE_COLOR_B = 4'b0110,
+
+ parameter [3:0] BALL_COLOR_R = 4'b0000, // Blue ball
+ parameter [3:0] BALL_COLOR_G = 4'b0000,
+ parameter [3:0] BALL_COLOR_B = 4'b1111,
+
+ parameter [3:0] PLATFORM_COLOR_R = 4'b1111, // Red platforms
+ parameter [3:0] PLATFORM_COLOR_G = 4'b0000,
+ parameter [3:0] PLATFORM_COLOR_B = 4'b0000
+)
+
+(
+ // Input Ports
+ input clk25MHz, // 25 MHz clock
+ input button1, button2, button3, button4, // 4 buttons on DE1 (left<->right for 2 players)
+
+ // Output Ports
+ output h_sync,
+ output v_sync,
+ output [3:0] red, green, blue, // Current pixel color (4096 colors = 12 bit)
+ output [6:0] hex0, hex1, hex2, hex3, // Digital tables on DE1
+ output [7:0] led
+);
+
+ //////////////////////////////////////
+ // **** BEGIN OF MODULE HEADER **** //
+ //////////////////////////////////////
+
+ // Output registers
+ reg [3:0] red_, green_, blue_;
+ reg [6:0] hex0_, hex1_, hex2_, hex3_;
+ reg [7:0] led_;
+
+ // Constants depending on the global parameters
+ localparam SCREEN_WIDTH = 640; // Horizontal screen resolution (in pixels)
+ localparam SCREEN_HEIGHT = 480; // Vertical screen resolution (in pixels)
+ localparam FIELD_WIDTH = SCREEN_WIDTH/CELL_SIZE; // Horizontal screen resolution (in cells)
+ localparam FIELD_HEIGHT = SCREEN_HEIGHT/CELL_SIZE; // Vertical screen resolution (in cells)
+ localparam BALL_DELAY = 25000000/BALL_SPEED; // Clocks per 1 move
+
+
+ // 2D array of cells, stores game field state
+ reg [1:0] field[0:FIELD_HEIGHT-1][0:FIELD_WIDTH-1];
+
+ // Possible cell values: (no comments)
+ localparam [1:0] EMPTY_CELL = 2'b00;
+ localparam [1:0] STABLE_CELL = 2'b11;
+ localparam [1:0] BALL_CELL = 2'b01;
+ localparam [1:0] PLATFORM_CELL = 2'b10;
+
+ // Current game state (0 - stopped, 1 - active)
+ reg game_state;
+
+ // Player's scores
+ integer player1_score;
+ integer player2_score;
+
+ // ATTENTION!!!
+ // All definitions behigh are in cells only.
+ //
+
+ // Informaton about game ball
+ integer ball_clock_counter; // Clocks counter
+ integer ball_x, ball_y; // Current coordinates
+ reg [1:0] ball_direction; // Current moving direction
+
+ // Possible ball directions:
+ localparam [1:0] LEFT_UP = 2'b00;
+ localparam [1:0] RIGHT_UP = 2'b01;
+ localparam [1:0] LEFT_DOWN = 2'b10;
+ localparam [1:0] RIGHT_DOWN = 2'b11;
+
+ // Information about game platforms
+ integer platform1_position; // Current position (X axis, left border coordinate)
+ integer platform2_position;
+
+ // VGA variables
+ integer h_counter; // Horizontal pixel counter
+ integer v_counter; // Vertical pixel counter
+ integer h_cell; // Horizontal cell counter
+ integer v_cell; // Vertical cell counter
+ reg [1:0] current_cell; // Current cell value
+
+ // Loops variables
+ integer i, j;
+
+ // Last buttons state
+ reg button1_state;
+ reg button2_state;
+ reg button3_state;
+ reg button4_state;
+
+
+ ////////////////////////////////////
+ // **** END OF MODULE HEADER **** //
+ ////////////////////////////////////
+
+`endif // _arkanoid_header_
\ No newline at end of file
diff --git a/db/abs_divider_kbg.tdf b/db/abs_divider_kbg.tdf
new file mode 100644
index 0000000..789cefa
--- /dev/null
+++ b/db/abs_divider_kbg.tdf
@@ -0,0 +1,88 @@
+--abs_divider DEN_REPRESENTATION="SIGNED" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="SIGNED" SKIP_BITS=0 WIDTH_D=5 WIDTH_N=32 denominator numerator quotient remainder
+--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_lpm_divide 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2009 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+
+FUNCTION alt_u_div_k2f (denominator[4..0], numerator[31..0])
+RETURNS ( quotient[31..0], remainder[4..0]);
+FUNCTION lpm_abs_gq9 (data[4..0])
+RETURNS ( overflow, result[4..0]);
+FUNCTION lpm_abs_0s9 (data[31..0])
+RETURNS ( result[31..0]);
+
+--synthesis_resources = lut 246
+SUBDESIGN abs_divider_kbg
+(
+ denominator[4..0] : input;
+ numerator[31..0] : input;
+ quotient[31..0] : output;
+ remainder[4..0] : output;
+)
+VARIABLE
+ divider : alt_u_div_k2f;
+ my_abs_den : lpm_abs_gq9;
+ my_abs_num : lpm_abs_0s9;
+ compl_add_quot_result_int[32..0] : WIRE;
+ compl_add_quot_cin : WIRE;
+ compl_add_quot_dataa[31..0] : WIRE;
+ compl_add_quot_datab[31..0] : WIRE;
+ compl_add_quot_result[31..0] : WIRE;
+ compl_add_rem_result_int[5..0] : WIRE;
+ compl_add_rem_cin : WIRE;
+ compl_add_rem_dataa[4..0] : WIRE;
+ compl_add_rem_datab[4..0] : WIRE;
+ compl_add_rem_result[4..0] : WIRE;
+ diff_signs : WIRE;
+ gnd_wire : WIRE;
+ neg_quot[31..0] : WIRE;
+ neg_rem[4..0] : WIRE;
+ norm_den[4..0] : WIRE;
+ norm_num[31..0] : WIRE;
+ num_sign : WIRE;
+ protect_quotient[31..0] : WIRE;
+ protect_remainder[4..0] : WIRE;
+ vcc_wire : WIRE;
+
+BEGIN
+ divider.denominator[] = norm_den[];
+ divider.numerator[] = norm_num[];
+ my_abs_den.data[] = denominator[];
+ my_abs_num.data[] = numerator[];
+ compl_add_quot_result_int[] = (compl_add_quot_dataa[], compl_add_quot_cin) + (compl_add_quot_datab[], compl_add_quot_cin);
+ compl_add_quot_result[] = compl_add_quot_result_int[32..1];
+ compl_add_quot_cin = vcc_wire;
+ compl_add_quot_dataa[] = (! protect_quotient[]);
+ compl_add_quot_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
+ compl_add_rem_result_int[] = (compl_add_rem_dataa[], compl_add_rem_cin) + (compl_add_rem_datab[], compl_add_rem_cin);
+ compl_add_rem_result[] = compl_add_rem_result_int[5..1];
+ compl_add_rem_cin = vcc_wire;
+ compl_add_rem_dataa[] = (! protect_remainder[]);
+ compl_add_rem_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
+ diff_signs = (numerator[31..31] $ denominator[4..4]);
+ gnd_wire = B"0";
+ neg_quot[] = compl_add_quot_result[];
+ neg_rem[] = compl_add_rem_result[];
+ norm_den[] = my_abs_den.result[];
+ norm_num[] = my_abs_num.result[];
+ num_sign = numerator[31..31];
+ protect_quotient[] = divider.quotient[];
+ protect_remainder[] = divider.remainder[];
+ quotient[] = ((protect_quotient[] & (! diff_signs)) # (neg_quot[] & diff_signs));
+ remainder[] = ((protect_remainder[] & (! num_sign)) # (neg_rem[] & num_sign));
+ vcc_wire = B"1";
+END;
+--VALID FILE
diff --git a/db/abs_divider_lbg.tdf b/db/abs_divider_lbg.tdf
new file mode 100644
index 0000000..98a7fb8
--- /dev/null
+++ b/db/abs_divider_lbg.tdf
@@ -0,0 +1,88 @@
+--abs_divider DEN_REPRESENTATION="SIGNED" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="SIGNED" SKIP_BITS=0 WIDTH_D=6 WIDTH_N=32 denominator numerator quotient remainder
+--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_lpm_divide 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2009 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+
+FUNCTION alt_u_div_m2f (denominator[5..0], numerator[31..0])
+RETURNS ( quotient[31..0], remainder[5..0]);
+FUNCTION lpm_abs_hq9 (data[5..0])
+RETURNS ( overflow, result[5..0]);
+FUNCTION lpm_abs_0s9 (data[31..0])
+RETURNS ( overflow, result[31..0]);
+
+--synthesis_resources = lut 306
+SUBDESIGN abs_divider_lbg
+(
+ denominator[5..0] : input;
+ numerator[31..0] : input;
+ quotient[31..0] : output;
+ remainder[5..0] : output;
+)
+VARIABLE
+ divider : alt_u_div_m2f;
+ my_abs_den : lpm_abs_hq9;
+ my_abs_num : lpm_abs_0s9;
+ compl_add_quot_result_int[32..0] : WIRE;
+ compl_add_quot_cin : WIRE;
+ compl_add_quot_dataa[31..0] : WIRE;
+ compl_add_quot_datab[31..0] : WIRE;
+ compl_add_quot_result[31..0] : WIRE;
+ compl_add_rem_result_int[6..0] : WIRE;
+ compl_add_rem_cin : WIRE;
+ compl_add_rem_dataa[5..0] : WIRE;
+ compl_add_rem_datab[5..0] : WIRE;
+ compl_add_rem_result[5..0] : WIRE;
+ diff_signs : WIRE;
+ gnd_wire : WIRE;
+ neg_quot[31..0] : WIRE;
+ neg_rem[5..0] : WIRE;
+ norm_den[5..0] : WIRE;
+ norm_num[31..0] : WIRE;
+ num_sign : WIRE;
+ protect_quotient[31..0] : WIRE;
+ protect_remainder[5..0] : WIRE;
+ vcc_wire : WIRE;
+
+BEGIN
+ divider.denominator[] = norm_den[];
+ divider.numerator[] = norm_num[];
+ my_abs_den.data[] = denominator[];
+ my_abs_num.data[] = numerator[];
+ compl_add_quot_result_int[] = (compl_add_quot_dataa[], compl_add_quot_cin) + (compl_add_quot_datab[], compl_add_quot_cin);
+ compl_add_quot_result[] = compl_add_quot_result_int[32..1];
+ compl_add_quot_cin = vcc_wire;
+ compl_add_quot_dataa[] = (! protect_quotient[]);
+ compl_add_quot_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
+ compl_add_rem_result_int[] = (compl_add_rem_dataa[], compl_add_rem_cin) + (compl_add_rem_datab[], compl_add_rem_cin);
+ compl_add_rem_result[] = compl_add_rem_result_int[6..1];
+ compl_add_rem_cin = vcc_wire;
+ compl_add_rem_dataa[] = (! protect_remainder[]);
+ compl_add_rem_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
+ diff_signs = (numerator[31..31] $ denominator[5..5]);
+ gnd_wire = B"0";
+ neg_quot[] = compl_add_quot_result[];
+ neg_rem[] = compl_add_rem_result[];
+ norm_den[] = my_abs_den.result[];
+ norm_num[] = my_abs_num.result[];
+ num_sign = numerator[31..31];
+ protect_quotient[] = divider.quotient[];
+ protect_remainder[] = divider.remainder[];
+ quotient[] = ((protect_quotient[] & (! diff_signs)) # (neg_quot[] & diff_signs));
+ remainder[] = ((protect_remainder[] & (! num_sign)) # (neg_rem[] & num_sign));
+ vcc_wire = B"1";
+END;
+--VALID FILE
diff --git a/db/add_sub_lkc.tdf b/db/add_sub_lkc.tdf
new file mode 100644
index 0000000..861114c
--- /dev/null
+++ b/db/add_sub_lkc.tdf
@@ -0,0 +1,43 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone II" LPM_DIRECTION="SUB" LPM_WIDTH=1 cout dataa datab result
+--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2009 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+
+
+--synthesis_resources =
+SUBDESIGN add_sub_lkc
+(
+ cout : output;
+ dataa[0..0] : input;
+ datab[0..0] : input;
+ result[0..0] : output;
+)
+VARIABLE
+ carry_eqn[0..0] : WIRE;
+ cin_wire : WIRE;
+ datab_node[0..0] : WIRE;
+ sum_eqn[0..0] : WIRE;
+
+BEGIN
+ carry_eqn[] = ( ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & cin_wire)));
+ cin_wire = B"1";
+ cout = carry_eqn[0..0];
+ datab_node[] = (! datab[]);
+ result[] = sum_eqn[];
+ sum_eqn[] = ( ((dataa[0..0] $ datab_node[0..0]) $ cin_wire));
+END;
+--VALID FILE
diff --git a/db/add_sub_mkc.tdf b/db/add_sub_mkc.tdf
new file mode 100644
index 0000000..ee85304
--- /dev/null
+++ b/db/add_sub_mkc.tdf
@@ -0,0 +1,43 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone II" LPM_DIRECTION="SUB" LPM_WIDTH=2 cout dataa datab result
+--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2009 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+
+
+--synthesis_resources =
+SUBDESIGN add_sub_mkc
+(
+ cout : output;
+ dataa[1..0] : input;
+ datab[1..0] : input;
+ result[1..0] : output;
+)
+VARIABLE
+ carry_eqn[1..0] : WIRE;
+ cin_wire : WIRE;
+ datab_node[1..0] : WIRE;
+ sum_eqn[1..0] : WIRE;
+
+BEGIN
+ carry_eqn[] = ( ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & carry_eqn[0..0])), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & cin_wire)));
+ cin_wire = B"1";
+ cout = carry_eqn[1..1];
+ datab_node[] = (! datab[]);
+ result[] = sum_eqn[];
+ sum_eqn[] = ( ((dataa[1..1] $ datab_node[1..1]) $ carry_eqn[0..0]), ((dataa[0..0] $ datab_node[0..0]) $ cin_wire));
+END;
+--VALID FILE
diff --git a/db/alt_u_div_k2f.tdf b/db/alt_u_div_k2f.tdf
new file mode 100644
index 0000000..60ca689
--- /dev/null
+++ b/db/alt_u_div_k2f.tdf
@@ -0,0 +1,371 @@
+--alt_u_div DEVICE_FAMILY="Cyclone II" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=5 WIDTH_N=32 WIDTH_Q=32 WIDTH_R=5 denominator numerator quotient remainder
+--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_lpm_divide 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2009 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+
+FUNCTION add_sub_lkc (dataa[0..0], datab[0..0])
+RETURNS ( cout, result[0..0]);
+FUNCTION add_sub_mkc (dataa[1..0], datab[1..0])
+RETURNS ( cout, result[1..0]);
+
+--synthesis_resources = lut 204
+SUBDESIGN alt_u_div_k2f
+(
+ denominator[4..0] : input;
+ numerator[31..0] : input;
+ quotient[31..0] : output;
+ remainder[4..0] : output;
+)
+VARIABLE
+ add_sub_0 : add_sub_lkc;
+ add_sub_1 : add_sub_mkc;
+ add_sub_10_result_int[6..0] : WIRE;
+ add_sub_10_cout : WIRE;
+ add_sub_10_dataa[5..0] : WIRE;
+ add_sub_10_datab[5..0] : WIRE;
+ add_sub_10_result[5..0] : WIRE;
+ add_sub_11_result_int[6..0] : WIRE;
+ add_sub_11_cout : WIRE;
+ add_sub_11_dataa[5..0] : WIRE;
+ add_sub_11_datab[5..0] : WIRE;
+ add_sub_11_result[5..0] : WIRE;
+ add_sub_12_result_int[6..0] : WIRE;
+ add_sub_12_cout : WIRE;
+ add_sub_12_dataa[5..0] : WIRE;
+ add_sub_12_datab[5..0] : WIRE;
+ add_sub_12_result[5..0] : WIRE;
+ add_sub_13_result_int[6..0] : WIRE;
+ add_sub_13_cout : WIRE;
+ add_sub_13_dataa[5..0] : WIRE;
+ add_sub_13_datab[5..0] : WIRE;
+ add_sub_13_result[5..0] : WIRE;
+ add_sub_14_result_int[6..0] : WIRE;
+ add_sub_14_cout : WIRE;
+ add_sub_14_dataa[5..0] : WIRE;
+ add_sub_14_datab[5..0] : WIRE;
+ add_sub_14_result[5..0] : WIRE;
+ add_sub_15_result_int[6..0] : WIRE;
+ add_sub_15_cout : WIRE;
+ add_sub_15_dataa[5..0] : WIRE;
+ add_sub_15_datab[5..0] : WIRE;
+ add_sub_15_result[5..0] : WIRE;
+ add_sub_16_result_int[6..0] : WIRE;
+ add_sub_16_cout : WIRE;
+ add_sub_16_dataa[5..0] : WIRE;
+ add_sub_16_datab[5..0] : WIRE;
+ add_sub_16_result[5..0] : WIRE;
+ add_sub_17_result_int[6..0] : WIRE;
+ add_sub_17_cout : WIRE;
+ add_sub_17_dataa[5..0] : WIRE;
+ add_sub_17_datab[5..0] : WIRE;
+ add_sub_17_result[5..0] : WIRE;
+ add_sub_18_result_int[6..0] : WIRE;
+ add_sub_18_cout : WIRE;
+ add_sub_18_dataa[5..0] : WIRE;
+ add_sub_18_datab[5..0] : WIRE;
+ add_sub_18_result[5..0] : WIRE;
+ add_sub_19_result_int[6..0] : WIRE;
+ add_sub_19_cout : WIRE;
+ add_sub_19_dataa[5..0] : WIRE;
+ add_sub_19_datab[5..0] : WIRE;
+ add_sub_19_result[5..0] : WIRE;
+ add_sub_2_result_int[3..0] : WIRE;
+ add_sub_2_cout : WIRE;
+ add_sub_2_dataa[2..0] : WIRE;
+ add_sub_2_datab[2..0] : WIRE;
+ add_sub_2_result[2..0] : WIRE;
+ add_sub_20_result_int[6..0] : WIRE;
+ add_sub_20_cout : WIRE;
+ add_sub_20_dataa[5..0] : WIRE;
+ add_sub_20_datab[5..0] : WIRE;
+ add_sub_20_result[5..0] : WIRE;
+ add_sub_21_result_int[6..0] : WIRE;
+ add_sub_21_cout : WIRE;
+ add_sub_21_dataa[5..0] : WIRE;
+ add_sub_21_datab[5..0] : WIRE;
+ add_sub_21_result[5..0] : WIRE;
+ add_sub_22_result_int[6..0] : WIRE;
+ add_sub_22_cout : WIRE;
+ add_sub_22_dataa[5..0] : WIRE;
+ add_sub_22_datab[5..0] : WIRE;
+ add_sub_22_result[5..0] : WIRE;
+ add_sub_23_result_int[6..0] : WIRE;
+ add_sub_23_cout : WIRE;
+ add_sub_23_dataa[5..0] : WIRE;
+ add_sub_23_datab[5..0] : WIRE;
+ add_sub_23_result[5..0] : WIRE;
+ add_sub_24_result_int[6..0] : WIRE;
+ add_sub_24_cout : WIRE;
+ add_sub_24_dataa[5..0] : WIRE;
+ add_sub_24_datab[5..0] : WIRE;
+ add_sub_24_result[5..0] : WIRE;
+ add_sub_25_result_int[6..0] : WIRE;
+ add_sub_25_cout : WIRE;
+ add_sub_25_dataa[5..0] : WIRE;
+ add_sub_25_datab[5..0] : WIRE;
+ add_sub_25_result[5..0] : WIRE;
+ add_sub_26_result_int[6..0] : WIRE;
+ add_sub_26_cout : WIRE;
+ add_sub_26_dataa[5..0] : WIRE;
+ add_sub_26_datab[5..0] : WIRE;
+ add_sub_26_result[5..0] : WIRE;
+ add_sub_27_result_int[6..0] : WIRE;
+ add_sub_27_cout : WIRE;
+ add_sub_27_dataa[5..0] : WIRE;
+ add_sub_27_datab[5..0] : WIRE;
+ add_sub_27_result[5..0] : WIRE;
+ add_sub_28_result_int[6..0] : WIRE;
+ add_sub_28_cout : WIRE;
+ add_sub_28_dataa[5..0] : WIRE;
+ add_sub_28_datab[5..0] : WIRE;
+ add_sub_28_result[5..0] : WIRE;
+ add_sub_29_result_int[6..0] : WIRE;
+ add_sub_29_cout : WIRE;
+ add_sub_29_dataa[5..0] : WIRE;
+ add_sub_29_datab[5..0] : WIRE;
+ add_sub_29_result[5..0] : WIRE;
+ add_sub_3_result_int[4..0] : WIRE;
+ add_sub_3_cout : WIRE;
+ add_sub_3_dataa[3..0] : WIRE;
+ add_sub_3_datab[3..0] : WIRE;
+ add_sub_3_result[3..0] : WIRE;
+ add_sub_30_result_int[6..0] : WIRE;
+ add_sub_30_cout : WIRE;
+ add_sub_30_dataa[5..0] : WIRE;
+ add_sub_30_datab[5..0] : WIRE;
+ add_sub_30_result[5..0] : WIRE;
+ add_sub_31_result_int[6..0] : WIRE;
+ add_sub_31_cout : WIRE;
+ add_sub_31_dataa[5..0] : WIRE;
+ add_sub_31_datab[5..0] : WIRE;
+ add_sub_31_result[5..0] : WIRE;
+ add_sub_4_result_int[5..0] : WIRE;
+ add_sub_4_cout : WIRE;
+ add_sub_4_dataa[4..0] : WIRE;
+ add_sub_4_datab[4..0] : WIRE;
+ add_sub_4_result[4..0] : WIRE;
+ add_sub_5_result_int[6..0] : WIRE;
+ add_sub_5_cout : WIRE;
+ add_sub_5_dataa[5..0] : WIRE;
+ add_sub_5_datab[5..0] : WIRE;
+ add_sub_5_result[5..0] : WIRE;
+ add_sub_6_result_int[6..0] : WIRE;
+ add_sub_6_cout : WIRE;
+ add_sub_6_dataa[5..0] : WIRE;
+ add_sub_6_datab[5..0] : WIRE;
+ add_sub_6_result[5..0] : WIRE;
+ add_sub_7_result_int[6..0] : WIRE;
+ add_sub_7_cout : WIRE;
+ add_sub_7_dataa[5..0] : WIRE;
+ add_sub_7_datab[5..0] : WIRE;
+ add_sub_7_result[5..0] : WIRE;
+ add_sub_8_result_int[6..0] : WIRE;
+ add_sub_8_cout : WIRE;
+ add_sub_8_dataa[5..0] : WIRE;
+ add_sub_8_datab[5..0] : WIRE;
+ add_sub_8_result[5..0] : WIRE;
+ add_sub_9_result_int[6..0] : WIRE;
+ add_sub_9_cout : WIRE;
+ add_sub_9_dataa[5..0] : WIRE;
+ add_sub_9_datab[5..0] : WIRE;
+ add_sub_9_result[5..0] : WIRE;
+ DenominatorIn[197..0] : WIRE;
+ DenominatorIn_tmp[197..0] : WIRE;
+ gnd_wire : WIRE;
+ nose[1055..0] : WIRE;
+ NumeratorIn[1055..0] : WIRE;
+ NumeratorIn_tmp[1055..0] : WIRE;
+ prestg[191..0] : WIRE;
+ quotient_tmp[31..0] : WIRE;
+ sel[164..0] : WIRE;
+ selnose[1055..0] : WIRE;
+ StageIn[197..0] : WIRE;
+ StageIn_tmp[197..0] : WIRE;
+ StageOut[191..0] : WIRE;
+
+BEGIN
+ add_sub_0.dataa[0..0] = NumeratorIn[31..31];
+ add_sub_0.datab[0..0] = DenominatorIn[0..0];
+ add_sub_1.dataa[] = ( StageIn[6..6], NumeratorIn[62..62]);
+ add_sub_1.datab[1..0] = DenominatorIn[7..6];
+ add_sub_10_result_int[] = (0, add_sub_10_dataa[]) - (0, add_sub_10_datab[]);
+ add_sub_10_result[] = add_sub_10_result_int[5..0];
+ add_sub_10_cout = !add_sub_10_result_int[6];
+ add_sub_10_dataa[] = ( StageIn[64..60], NumeratorIn[341..341]);
+ add_sub_10_datab[] = DenominatorIn[65..60];
+ add_sub_11_result_int[] = (0, add_sub_11_dataa[]) - (0, add_sub_11_datab[]);
+ add_sub_11_result[] = add_sub_11_result_int[5..0];
+ add_sub_11_cout = !add_sub_11_result_int[6];
+ add_sub_11_dataa[] = ( StageIn[70..66], NumeratorIn[372..372]);
+ add_sub_11_datab[] = DenominatorIn[71..66];
+ add_sub_12_result_int[] = (0, add_sub_12_dataa[]) - (0, add_sub_12_datab[]);
+ add_sub_12_result[] = add_sub_12_result_int[5..0];
+ add_sub_12_cout = !add_sub_12_result_int[6];
+ add_sub_12_dataa[] = ( StageIn[76..72], NumeratorIn[403..403]);
+ add_sub_12_datab[] = DenominatorIn[77..72];
+ add_sub_13_result_int[] = (0, add_sub_13_dataa[]) - (0, add_sub_13_datab[]);
+ add_sub_13_result[] = add_sub_13_result_int[5..0];
+ add_sub_13_cout = !add_sub_13_result_int[6];
+ add_sub_13_dataa[] = ( StageIn[82..78], NumeratorIn[434..434]);
+ add_sub_13_datab[] = DenominatorIn[83..78];
+ add_sub_14_result_int[] = (0, add_sub_14_dataa[]) - (0, add_sub_14_datab[]);
+ add_sub_14_result[] = add_sub_14_result_int[5..0];
+ add_sub_14_cout = !add_sub_14_result_int[6];
+ add_sub_14_dataa[] = ( StageIn[88..84], NumeratorIn[465..465]);
+ add_sub_14_datab[] = DenominatorIn[89..84];
+ add_sub_15_result_int[] = (0, add_sub_15_dataa[]) - (0, add_sub_15_datab[]);
+ add_sub_15_result[] = add_sub_15_result_int[5..0];
+ add_sub_15_cout = !add_sub_15_result_int[6];
+ add_sub_15_dataa[] = ( StageIn[94..90], NumeratorIn[496..496]);
+ add_sub_15_datab[] = DenominatorIn[95..90];
+ add_sub_16_result_int[] = (0, add_sub_16_dataa[]) - (0, add_sub_16_datab[]);
+ add_sub_16_result[] = add_sub_16_result_int[5..0];
+ add_sub_16_cout = !add_sub_16_result_int[6];
+ add_sub_16_dataa[] = ( StageIn[100..96], NumeratorIn[527..527]);
+ add_sub_16_datab[] = DenominatorIn[101..96];
+ add_sub_17_result_int[] = (0, add_sub_17_dataa[]) - (0, add_sub_17_datab[]);
+ add_sub_17_result[] = add_sub_17_result_int[5..0];
+ add_sub_17_cout = !add_sub_17_result_int[6];
+ add_sub_17_dataa[] = ( StageIn[106..102], NumeratorIn[558..558]);
+ add_sub_17_datab[] = DenominatorIn[107..102];
+ add_sub_18_result_int[] = (0, add_sub_18_dataa[]) - (0, add_sub_18_datab[]);
+ add_sub_18_result[] = add_sub_18_result_int[5..0];
+ add_sub_18_cout = !add_sub_18_result_int[6];
+ add_sub_18_dataa[] = ( StageIn[112..108], NumeratorIn[589..589]);
+ add_sub_18_datab[] = DenominatorIn[113..108];
+ add_sub_19_result_int[] = (0, add_sub_19_dataa[]) - (0, add_sub_19_datab[]);
+ add_sub_19_result[] = add_sub_19_result_int[5..0];
+ add_sub_19_cout = !add_sub_19_result_int[6];
+ add_sub_19_dataa[] = ( StageIn[118..114], NumeratorIn[620..620]);
+ add_sub_19_datab[] = DenominatorIn[119..114];
+ add_sub_2_result_int[] = (0, add_sub_2_dataa[]) - (0, add_sub_2_datab[]);
+ add_sub_2_result[] = add_sub_2_result_int[2..0];
+ add_sub_2_cout = !add_sub_2_result_int[3];
+ add_sub_2_dataa[] = ( StageIn[13..12], NumeratorIn[93..93]);
+ add_sub_2_datab[] = DenominatorIn[14..12];
+ add_sub_20_result_int[] = (0, add_sub_20_dataa[]) - (0, add_sub_20_datab[]);
+ add_sub_20_result[] = add_sub_20_result_int[5..0];
+ add_sub_20_cout = !add_sub_20_result_int[6];
+ add_sub_20_dataa[] = ( StageIn[124..120], NumeratorIn[651..651]);
+ add_sub_20_datab[] = DenominatorIn[125..120];
+ add_sub_21_result_int[] = (0, add_sub_21_dataa[]) - (0, add_sub_21_datab[]);
+ add_sub_21_result[] = add_sub_21_result_int[5..0];
+ add_sub_21_cout = !add_sub_21_result_int[6];
+ add_sub_21_dataa[] = ( StageIn[130..126], NumeratorIn[682..682]);
+ add_sub_21_datab[] = DenominatorIn[131..126];
+ add_sub_22_result_int[] = (0, add_sub_22_dataa[]) - (0, add_sub_22_datab[]);
+ add_sub_22_result[] = add_sub_22_result_int[5..0];
+ add_sub_22_cout = !add_sub_22_result_int[6];
+ add_sub_22_dataa[] = ( StageIn[136..132], NumeratorIn[713..713]);
+ add_sub_22_datab[] = DenominatorIn[137..132];
+ add_sub_23_result_int[] = (0, add_sub_23_dataa[]) - (0, add_sub_23_datab[]);
+ add_sub_23_result[] = add_sub_23_result_int[5..0];
+ add_sub_23_cout = !add_sub_23_result_int[6];
+ add_sub_23_dataa[] = ( StageIn[142..138], NumeratorIn[744..744]);
+ add_sub_23_datab[] = DenominatorIn[143..138];
+ add_sub_24_result_int[] = (0, add_sub_24_dataa[]) - (0, add_sub_24_datab[]);
+ add_sub_24_result[] = add_sub_24_result_int[5..0];
+ add_sub_24_cout = !add_sub_24_result_int[6];
+ add_sub_24_dataa[] = ( StageIn[148..144], NumeratorIn[775..775]);
+ add_sub_24_datab[] = DenominatorIn[149..144];
+ add_sub_25_result_int[] = (0, add_sub_25_dataa[]) - (0, add_sub_25_datab[]);
+ add_sub_25_result[] = add_sub_25_result_int[5..0];
+ add_sub_25_cout = !add_sub_25_result_int[6];
+ add_sub_25_dataa[] = ( StageIn[154..150], NumeratorIn[806..806]);
+ add_sub_25_datab[] = DenominatorIn[155..150];
+ add_sub_26_result_int[] = (0, add_sub_26_dataa[]) - (0, add_sub_26_datab[]);
+ add_sub_26_result[] = add_sub_26_result_int[5..0];
+ add_sub_26_cout = !add_sub_26_result_int[6];
+ add_sub_26_dataa[] = ( StageIn[160..156], NumeratorIn[837..837]);
+ add_sub_26_datab[] = DenominatorIn[161..156];
+ add_sub_27_result_int[] = (0, add_sub_27_dataa[]) - (0, add_sub_27_datab[]);
+ add_sub_27_result[] = add_sub_27_result_int[5..0];
+ add_sub_27_cout = !add_sub_27_result_int[6];
+ add_sub_27_dataa[] = ( StageIn[166..162], NumeratorIn[868..868]);
+ add_sub_27_datab[] = DenominatorIn[167..162];
+ add_sub_28_result_int[] = (0, add_sub_28_dataa[]) - (0, add_sub_28_datab[]);
+ add_sub_28_result[] = add_sub_28_result_int[5..0];
+ add_sub_28_cout = !add_sub_28_result_int[6];
+ add_sub_28_dataa[] = ( StageIn[172..168], NumeratorIn[899..899]);
+ add_sub_28_datab[] = DenominatorIn[173..168];
+ add_sub_29_result_int[] = (0, add_sub_29_dataa[]) - (0, add_sub_29_datab[]);
+ add_sub_29_result[] = add_sub_29_result_int[5..0];
+ add_sub_29_cout = !add_sub_29_result_int[6];
+ add_sub_29_dataa[] = ( StageIn[178..174], NumeratorIn[930..930]);
+ add_sub_29_datab[] = DenominatorIn[179..174];
+ add_sub_3_result_int[] = (0, add_sub_3_dataa[]) - (0, add_sub_3_datab[]);
+ add_sub_3_result[] = add_sub_3_result_int[3..0];
+ add_sub_3_cout = !add_sub_3_result_int[4];
+ add_sub_3_dataa[] = ( StageIn[20..18], NumeratorIn[124..124]);
+ add_sub_3_datab[] = DenominatorIn[21..18];
+ add_sub_30_result_int[] = (0, add_sub_30_dataa[]) - (0, add_sub_30_datab[]);
+ add_sub_30_result[] = add_sub_30_result_int[5..0];
+ add_sub_30_cout = !add_sub_30_result_int[6];
+ add_sub_30_dataa[] = ( StageIn[184..180], NumeratorIn[961..961]);
+ add_sub_30_datab[] = DenominatorIn[185..180];
+ add_sub_31_result_int[] = (0, add_sub_31_dataa[]) - (0, add_sub_31_datab[]);
+ add_sub_31_result[] = add_sub_31_result_int[5..0];
+ add_sub_31_cout = !add_sub_31_result_int[6];
+ add_sub_31_dataa[] = ( StageIn[190..186], NumeratorIn[992..992]);
+ add_sub_31_datab[] = DenominatorIn[191..186];
+ add_sub_4_result_int[] = (0, add_sub_4_dataa[]) - (0, add_sub_4_datab[]);
+ add_sub_4_result[] = add_sub_4_result_int[4..0];
+ add_sub_4_cout = !add_sub_4_result_int[5];
+ add_sub_4_dataa[] = ( StageIn[27..24], NumeratorIn[155..155]);
+ add_sub_4_datab[] = DenominatorIn[28..24];
+ add_sub_5_result_int[] = (0, add_sub_5_dataa[]) - (0, add_sub_5_datab[]);
+ add_sub_5_result[] = add_sub_5_result_int[5..0];
+ add_sub_5_cout = !add_sub_5_result_int[6];
+ add_sub_5_dataa[] = ( StageIn[34..30], NumeratorIn[186..186]);
+ add_sub_5_datab[] = DenominatorIn[35..30];
+ add_sub_6_result_int[] = (0, add_sub_6_dataa[]) - (0, add_sub_6_datab[]);
+ add_sub_6_result[] = add_sub_6_result_int[5..0];
+ add_sub_6_cout = !add_sub_6_result_int[6];
+ add_sub_6_dataa[] = ( StageIn[40..36], NumeratorIn[217..217]);
+ add_sub_6_datab[] = DenominatorIn[41..36];
+ add_sub_7_result_int[] = (0, add_sub_7_dataa[]) - (0, add_sub_7_datab[]);
+ add_sub_7_result[] = add_sub_7_result_int[5..0];
+ add_sub_7_cout = !add_sub_7_result_int[6];
+ add_sub_7_dataa[] = ( StageIn[46..42], NumeratorIn[248..248]);
+ add_sub_7_datab[] = DenominatorIn[47..42];
+ add_sub_8_result_int[] = (0, add_sub_8_dataa[]) - (0, add_sub_8_datab[]);
+ add_sub_8_result[] = add_sub_8_result_int[5..0];
+ add_sub_8_cout = !add_sub_8_result_int[6];
+ add_sub_8_dataa[] = ( StageIn[52..48], NumeratorIn[279..279]);
+ add_sub_8_datab[] = DenominatorIn[53..48];
+ add_sub_9_result_int[] = (0, add_sub_9_dataa[]) - (0, add_sub_9_datab[]);
+ add_sub_9_result[] = add_sub_9_result_int[5..0];
+ add_sub_9_cout = !add_sub_9_result_int[6];
+ add_sub_9_dataa[] = ( StageIn[58..54], NumeratorIn[310..310]);
+ add_sub_9_datab[] = DenominatorIn[59..54];
+ DenominatorIn[] = DenominatorIn_tmp[];
+ DenominatorIn_tmp[] = ( DenominatorIn[191..0], ( gnd_wire, denominator[]));
+ gnd_wire = B"0";
+ nose[] = ( B"00000000000000000000000000000000", add_sub_31_cout, B"00000000000000000000000000000000", add_sub_30_cout, B"00000000000000000000000000000000", add_sub_29_cout, B"00000000000000000000000000000000", add_sub_28_cout, B"00000000000000000000000000000000", add_sub_27_cout, B"00000000000000000000000000000000", add_sub_26_cout, B"00000000000000000000000000000000", add_sub_25_cout, B"00000000000000000000000000000000", add_sub_24_cout, B"00000000000000000000000000000000", add_sub_23_cout, B"00000000000000000000000000000000", add_sub_22_cout, B"00000000000000000000000000000000", add_sub_21_cout, B"00000000000000000000000000000000", add_sub_20_cout, B"00000000000000000000000000000000", add_sub_19_cout, B"00000000000000000000000000000000", add_sub_18_cout, B"00000000000000000000000000000000", add_sub_17_cout, B"00000000000000000000000000000000", add_sub_16_cout, B"00000000000000000000000000000000", add_sub_15_cout, B"00000000000000000000000000000000", add_sub_14_cout, B"00000000000000000000000000000000", add_sub_13_cout, B"00000000000000000000000000000000", add_sub_12_cout, B"00000000000000000000000000000000", add_sub_11_cout, B"00000000000000000000000000000000", add_sub_10_cout, B"00000000000000000000000000000000", add_sub_9_cout, B"00000000000000000000000000000000", add_sub_8_cout, B"00000000000000000000000000000000", add_sub_7_cout, B"00000000000000000000000000000000", add_sub_6_cout, B"00000000000000000000000000000000", add_sub_5_cout, B"00000000000000000000000000000000", add_sub_4_cout, B"00000000000000000000000000000000", add_sub_3_cout, B"00000000000000000000000000000000", add_sub_2_cout, B"00000000000000000000000000000000", add_sub_1.cout, B"00000000000000000000000000000000", add_sub_0.cout);
+ NumeratorIn[] = NumeratorIn_tmp[];
+ NumeratorIn_tmp[] = ( NumeratorIn[1023..0], numerator[]);
+ prestg[] = ( add_sub_31_result[], add_sub_30_result[], add_sub_29_result[], add_sub_28_result[], add_sub_27_result[], add_sub_26_result[], add_sub_25_result[], add_sub_24_result[], add_sub_23_result[], add_sub_22_result[], add_sub_21_result[], add_sub_20_result[], add_sub_19_result[], add_sub_18_result[], add_sub_17_result[], add_sub_16_result[], add_sub_15_result[], add_sub_14_result[], add_sub_13_result[], add_sub_12_result[], add_sub_11_result[], add_sub_10_result[], add_sub_9_result[], add_sub_8_result[], add_sub_7_result[], add_sub_6_result[], add_sub_5_result[], GND, add_sub_4_result[], B"00", add_sub_3_result[], B"000", add_sub_2_result[], B"0000", add_sub_1.result[], B"00000", add_sub_0.result[]);
+ quotient[] = quotient_tmp[];
+ quotient_tmp[] = ( (! selnose[0..0]), (! selnose[33..33]), (! selnose[66..66]), (! selnose[99..99]), (! selnose[132..132]), (! selnose[165..165]), (! selnose[198..198]), (! selnose[231..231]), (! selnose[264..264]), (! selnose[297..297]), (! selnose[330..330]), (! selnose[363..363]), (! selnose[396..396]), (! selnose[429..429]), (! selnose[462..462]), (! selnose[495..495]), (! selnose[528..528]), (! selnose[561..561]), (! selnose[594..594]), (! selnose[627..627]), (! selnose[660..660]), (! selnose[693..693]), (! selnose[726..726]), (! selnose[759..759]), (! selnose[792..792]), (! selnose[825..825]), (! selnose[858..858]), (! selnose[891..891]), (! selnose[924..924]), (! selnose[957..957]), (! selnose[990..990]), (! selnose[1023..1023]));
+ remainder[4..0] = StageIn[196..192];
+ sel[] = ( gnd_wire, (sel[164..164] # DenominatorIn[196..196]), (sel[163..163] # DenominatorIn[195..195]), (sel[162..162] # DenominatorIn[194..194]), (sel[161..161] # DenominatorIn[193..193]), gnd_wire, (sel[159..159] # DenominatorIn[190..190]), (sel[158..158] # DenominatorIn[189..189]), (sel[157..157] # DenominatorIn[188..188]), (sel[156..156] # DenominatorIn[187..187]), gnd_wire, (sel[154..154] # DenominatorIn[184..184]), (sel[153..153] # DenominatorIn[183..183]), (sel[152..152] # DenominatorIn[182..182]), (sel[151..151] # DenominatorIn[181..181]), gnd_wire, (sel[149..149] # DenominatorIn[178..178]), (sel[148..148] # DenominatorIn[177..177]), (sel[147..147] # DenominatorIn[176..176]), (sel[146..146] # DenominatorIn[175..175]), gnd_wire, (sel[144..144] # DenominatorIn[172..172]), (sel[143..143] # DenominatorIn[171..171]), (sel[142..142] # DenominatorIn[170..170]), (sel[141..141] # DenominatorIn[169..169]), gnd_wire, (sel[139..139] # DenominatorIn[166..166]), (sel[138..138] # DenominatorIn[165..165]), (sel[137..137] # DenominatorIn[164..164]), (sel[136..136] # DenominatorIn[163..163]), gnd_wire, (sel[134..134] # DenominatorIn[160..160]), (sel[133..133] # DenominatorIn[159..159]), (sel[132..132] # DenominatorIn[158..158]), (sel[131..131] # DenominatorIn[157..157]), gnd_wire, (sel[129..129] # DenominatorIn[154..154]), (sel[128..128] # DenominatorIn[153..153]), (sel[127..127] # DenominatorIn[152..152]), (sel[126..126] # DenominatorIn[151..151]), gnd_wire, (sel[124..124] # DenominatorIn[148..148]), (sel[123..123] # DenominatorIn[147..147]), (sel[122..122] # DenominatorIn[146..146]), (sel[121..121] # DenominatorIn[145..145]), gnd_wire, (sel[119..119] # DenominatorIn[142..142]), (sel[118..118] # DenominatorIn[141..141]), (sel[117..117] # DenominatorIn[140..140]), (sel[116..116] # DenominatorIn[139..139]), gnd_wire, (sel[114..114] # DenominatorIn[136..136]), (sel[113..113] # DenominatorIn[135..135]), (sel[112..112] # DenominatorIn[134..134]), (sel[111..111] # DenominatorIn[133..133]), gnd_wire, (sel[109..109] # DenominatorIn[130..130]), (sel[108..108] # DenominatorIn[129..129]), (sel[107..107] # DenominatorIn[128..128]), (sel[106..106] # DenominatorIn[127..127]), gnd_wire, (sel[104..104] # DenominatorIn[124..124]), (sel[103..103] # DenominatorIn[123..123]), (sel[102..102] # DenominatorIn[122..122]), (sel[101..101] # DenominatorIn[121..121]), gnd_wire, (sel[99..99] # DenominatorIn[118..118]), (sel[98..98] # DenominatorIn[117..117]), (sel[97..97] # DenominatorIn[116..116]), (sel[96..96] # DenominatorIn[115..115]), gnd_wire, (sel[94..94] # DenominatorIn[112..112]), (sel[93..93] # DenominatorIn[111..111]), (sel[92..92] # DenominatorIn[110..110]), (sel[91..91] # DenominatorIn[109..109]), gnd_wire, (sel[89..89] # DenominatorIn[106..106]), (sel[88..88] # DenominatorIn[105..105]), (sel[87..87] # DenominatorIn[104..104]), (sel[86..86] # DenominatorIn[103..103]), gnd_wire, (sel[84..84] # DenominatorIn[100..100]), (sel[83..83] # DenominatorIn[99..99]), (sel[82..82] # DenominatorIn[98..98]), (sel[81..81] # DenominatorIn[97..97]), gnd_wire, (sel[79..79] # DenominatorIn[94..94]), (sel[78..78] # DenominatorIn[93..93]), (sel[77..77] # DenominatorIn[92..92]), (sel[76..76] # DenominatorIn[91..91]), gnd_wire, (sel[74..74] # DenominatorIn[88..88]), (sel[73..73] # DenominatorIn[87..87]), (sel[72..72] # DenominatorIn[86..86]), (sel[71..71] # DenominatorIn[85..85]), gnd_wire, (sel[69..69] # DenominatorIn[82..82]), (sel[68..68] # DenominatorIn[81..81]), (sel[67..67] # DenominatorIn[80..80]), (sel[66..66] # DenominatorIn[79..79]), gnd_wire, (sel[64..64] # DenominatorIn[76..76]), (sel[63..63] # DenominatorIn[75..75]), (sel[62..62] # DenominatorIn[74..74]), (sel[61..61] # DenominatorIn[73..73]), gnd_wire, (sel[59..59] # DenominatorIn[70..70]), (sel[58..58] # DenominatorIn[69..69]), (sel[57..57] # DenominatorIn[68..68]), (sel[56..56] # DenominatorIn[67..67]), gnd_wire, (sel[54..54] # DenominatorIn[64..64]), (sel[53..53] # DenominatorIn[63..63]), (sel[52..52] # DenominatorIn[62..62]), (sel[51..51] # DenominatorIn[61..61]), gnd_wire, (sel[49..49] # DenominatorIn[58..58]), (sel[48..48] # DenominatorIn[57..57]), (sel[47..47] # DenominatorIn[56..56]), (sel[46..46] # DenominatorIn[55..55]), gnd_wire, (sel[44..44] # DenominatorIn[52..52]), (sel[43..43] # DenominatorIn[51..51]), (sel[42..42] # DenominatorIn[50..50]), (sel[41..41] # DenominatorIn[49..49]), gnd_wire, (sel[39..39] # DenominatorIn[46..46]), (sel[38..38] # DenominatorIn[45..45]), (sel[37..37] # DenominatorIn[44..44]), (sel[36..36] # DenominatorIn[43..43]), gnd_wire, (sel[34..34] # DenominatorIn[40..40]), (sel[33..33] # DenominatorIn[39..39]), (sel[32..32] # DenominatorIn[38..38]), (sel[31..31] # DenominatorIn[37..37]), gnd_wire, (sel[29..29] # DenominatorIn[34..34]), (sel[28..28] # DenominatorIn[33..33]), (sel[27..27] # DenominatorIn[32..32]), (sel[26..26] # DenominatorIn[31..31]), gnd_wire, (sel[24..24] # DenominatorIn[28..28]), (sel[23..23] # DenominatorIn[27..27]), (sel[22..22] # DenominatorIn[26..26]), (sel[21..21] # DenominatorIn[25..25]), gnd_wire, (sel[19..19] # DenominatorIn[22..22]), (sel[18..18] # DenominatorIn[21..21]), (sel[17..17] # DenominatorIn[20..20]), (sel[16..16] # DenominatorIn[19..19]), gnd_wire, (sel[14..14] # DenominatorIn[16..16]), (sel[13..13] # DenominatorIn[15..15]), (sel[12..12] # DenominatorIn[14..14]), (sel[11..11] # DenominatorIn[13..13]), gnd_wire, (sel[9..9] # DenominatorIn[10..10]), (sel[8..8] # DenominatorIn[9..9]), (sel[7..7] # DenominatorIn[8..8]), (sel[6..6] # DenominatorIn[7..7]), gnd_wire, (sel[4..4] # DenominatorIn[4..4]), (sel[3..3] # DenominatorIn[3..3]), (sel[2..2] # DenominatorIn[2..2]), (sel[1..1] # DenominatorIn[1..1]));
+ selnose[] = ( (! nose[1055..1055]), (! nose[1054..1054]), (! nose[1053..1053]), (! nose[1052..1052]), (! nose[1051..1051]), (! nose[1050..1050]), (! nose[1049..1049]), (! nose[1048..1048]), (! nose[1047..1047]), (! nose[1046..1046]), (! nose[1045..1045]), (! nose[1044..1044]), (! nose[1043..1043]), (! nose[1042..1042]), (! nose[1041..1041]), (! nose[1040..1040]), (! nose[1039..1039]), (! nose[1038..1038]), (! nose[1037..1037]), (! nose[1036..1036]), (! nose[1035..1035]), (! nose[1034..1034]), (! nose[1033..1033]), (! nose[1032..1032]), (! nose[1031..1031]), (! nose[1030..1030]), (! nose[1029..1029]), ((! nose[1028..1028]) # sel[164..164]), ((! nose[1027..1027]) # sel[163..163]), ((! nose[1026..1026]) # sel[162..162]), ((! nose[1025..1025]) # sel[161..161]), ((! nose[1024..1024]) # sel[160..160]), (! nose[1023..1023]), (! nose[1022..1022]), (! nose[1021..1021]), (! nose[1020..1020]), (! nose[1019..1019]), (! nose[1018..1018]), (! nose[1017..1017]), (! nose[1016..1016]), (! nose[1015..1015]), (! nose[1014..1014]), (! nose[1013..1013]), (! nose[1012..1012]), (! nose[1011..1011]), (! nose[1010..1010]), (! nose[1009..1009]), (! nose[1008..1008]), (! nose[1007..1007]), (! nose[1006..1006]), (! nose[1005..1005]), (! nose[1004..1004]), (! nose[1003..1003]), (! nose[1002..1002]), (! nose[1001..1001]), (! nose[1000..1000]), (! nose[999..999]), (! nose[998..998]), (! nose[997..997]), ((! nose[996..996]) # sel[159..159]), ((! nose[995..995]) # sel[158..158]), ((! nose[994..994]) # sel[157..157]), ((! nose[993..993]) # sel[156..156]), ((! nose[992..992]) # sel[155..155]), (! nose[991..991]), (! nose[990..990]), (! nose[989..989]), (! nose[988..988]), (! nose[987..987]), (! nose[986..986]), (! nose[985..985]), (! nose[984..984]), (! nose[983..983]), (! nose[982..982]), (! nose[981..981]), (! nose[980..980]), (! nose[979..979]), (! nose[978..978]), (! nose[977..977]), (! nose[976..976]), (! nose[975..975]), (! nose[974..974]), (! nose[973..973]), (! nose[972..972]), (! nose[971..971]), (! nose[970..970]), (! nose[969..969]), (! nose[968..968]), (! nose[967..967]), (! nose[966..966]), (! nose[965..965]), ((! nose[964..964]) # sel[154..154]), ((! nose[963..963]) # sel[153..153]), ((! nose[962..962]) # sel[152..152]), ((! nose[961..961]) # sel[151..151]), ((! nose[960..960]) # sel[150..150]), (! nose[959..959]), (! nose[958..958]), (! nose[957..957]), (! nose[956..956]), (! nose[955..955]), (! nose[954..954]), (! nose[953..953]), (! nose[952..952]), (! nose[951..951]), (! nose[950..950]), (! nose[949..949]), (! nose[948..948]), (! nose[947..947]), (! nose[946..946]), (! nose[945..945]), (! nose[944..944]), (! nose[943..943]), (! nose[942..942]), (! nose[941..941]), (! nose[940..940]), (! nose[939..939]), (! nose[938..938]), (! nose[937..937]), (! nose[936..936]), (! nose[935..935]), (! nose[934..934]), (! nose[933..933]), ((! nose[932..932]) # sel[149..149]), ((! nose[931..931]) # sel[148..148]), ((! nose[930..930]) # sel[147..147]), ((! nose[929..929]) # sel[146..146]), ((! nose[928..928]) # sel[145..145]), (! nose[927..927]), (! nose[926..926]), (! nose[925..925]), (! nose[924..924]), (! nose[923..923]), (! nose[922..922]), (! nose[921..921]), (! nose[920..920]), (! nose[919..919]), (! nose[918..918]), (! nose[917..917]), (! nose[916..916]), (! nose[915..915]), (! nose[914..914]), (! nose[913..913]), (! nose[912..912]), (! nose[911..911]), (! nose[910..910]), (! nose[909..909]), (! nose[908..908]), (! nose[907..907]), (! nose[906..906]), (! nose[905..905]), (! nose[904..904]), (! nose[903..903]), (! nose[902..902]), (! nose[901..901]), ((! nose[900..900]) # sel[144..144]), ((! nose[899..899]) # sel[143..143]), ((! nose[898..898]) # sel[142..142]), ((! nose[897..897]) # sel[141..141]), ((! nose[896..896]) # sel[140..140]), (! nose[895..895]), (! nose[894..894]), (! nose[893..893]), (! nose[892..892]), (! nose[891..891]), (! nose[890..890]), (! nose[889..889]), (! nose[888..888]), (! nose[887..887]), (! nose[886..886]), (! nose[885..885]), (! nose[884..884]), (! nose[883..883]), (! nose[882..882]), (! nose[881..881]), (! nose[880..880]), (! nose[879..879]), (! nose[878..878]), (! nose[877..877]), (! nose[876..876]), (! nose[875..875]), (! nose[874..874]), (! nose[873..873]), (! nose[872..872]), (! nose[871..871]), (! nose[870..870]), (! nose[869..869]), ((! nose[868..868]) # sel[139..139]), ((! nose[867..867]) # sel[138..138]), ((! nose[866..866]) # sel[137..137]), ((! nose[865..865]) # sel[136..136]), ((! nose[864..864]) # sel[135..135]), (! nose[863..863]), (! nose[862..862]), (! nose[861..861]), (! nose[860..860]), (! nose[859..859]), (! nose[858..858]), (! nose[857..857]), (! nose[856..856]), (! nose[855..855]), (! nose[854..854]), (! nose[853..853]), (! nose[852..852]), (! nose[851..851]), (! nose[850..850]), (! nose[849..849]), (! nose[848..848]), (! nose[847..847]), (! nose[846..846]), (! nose[845..845]), (! nose[844..844]), (! nose[843..843]), (! nose[842..842]), (! nose[841..841]), (! nose[840..840]), (! nose[839..839]), (! nose[838..838]), (! nose[837..837]), ((! nose[836..836]) # sel[134..134]), ((! nose[835..835]) # sel[133..133]), ((! nose[834..834]) # sel[132..132]), ((! nose[833..833]) # sel[131..131]), ((! nose[832..832]) # sel[130..130]), (! nose[831..831]), (! nose[830..830]), (! nose[829..829]), (! nose[828..828]), (! nose[827..827]), (! nose[826..826]), (! nose[825..825]), (! nose[824..824]), (! nose[823..823]), (! nose[822..822]), (! nose[821..821]), (! nose[820..820]), (! nose[819..819]), (! nose[818..818]), (! nose[817..817]), (! nose[816..816]), (! nose[815..815]), (! nose[814..814]), (! nose[813..813]), (! nose[812..812]), (! nose[811..811]), (! nose[810..810]), (! nose[809..809]), (! nose[808..808]), (! nose[807..807]), (! nose[806..806]), (! nose[805..805]), ((! nose[804..804]) # sel[129..129]), ((! nose[803..803]) # sel[128..128]), ((! nose[802..802]) # sel[127..127]), ((! nose[801..801]) # sel[126..126]), ((! nose[800..800]) # sel[125..125]), (! nose[799..799]), (! nose[798..798]), (! nose[797..797]), (! nose[796..796]), (! nose[795..795]), (! nose[794..794]), (! nose[793..793]), (! nose[792..792]), (! nose[791..791]), (! nose[790..790]), (! nose[789..789]), (! nose[788..788]), (! nose[787..787]), (! nose[786..786]), (! nose[785..785]), (! nose[784..784]), (! nose[783..783]), (! nose[782..782]), (! nose[781..781]), (! nose[780..780]), (! nose[779..779]), (! nose[778..778]), (! nose[777..777]), (! nose[776..776]), (! nose[775..775]), (! nose[774..774]), (! nose[773..773]), ((! nose[772..772]) # sel[124..124]), ((! nose[771..771]) # sel[123..123]), ((! nose[770..770]) # sel[122..122]), ((! nose[769..769]) # sel[121..121]), ((! nose[768..768]) # sel[120..120]), (! nose[767..767]), (! nose[766..766]), (! nose[765..765]), (! nose[764..764]), (! nose[763..763]), (! nose[762..762]), (! nose[761..761]), (! nose[760..760]), (! nose[759..759]), (! nose[758..758]), (! nose[757..757]), (! nose[756..756]), (! nose[755..755]), (! nose[754..754]), (! nose[753..753]), (! nose[752..752]), (! nose[751..751]), (! nose[750..750]), (! nose[749..749]), (! nose[748..748]), (! nose[747..747]), (! nose[746..746]), (! nose[745..745]), (! nose[744..744]), (! nose[743..743]), (! nose[742..742]), (! nose[741..741]), ((! nose[740..740]) # sel[119..119]), ((! nose[739..739]) # sel[118..118]), ((! nose[738..738]) # sel[117..117]), ((! nose[737..737]) # sel[116..116]), ((! nose[736..736]) # sel[115..115]), (! nose[735..735]), (! nose[734..734]), (! nose[733..733]), (! nose[732..732]), (! nose[731..731]), (! nose[730..730]), (! nose[729..729]), (! nose[728..728]), (! nose[727..727]), (! nose[726..726]), (! nose[725..725]), (! nose[724..724]), (! nose[723..723]), (! nose[722..722]), (! nose[721..721]), (! nose[720..720]), (! nose[719..719]), (! nose[718..718]), (! nose[717..717]), (! nose[716..716]), (! nose[715..715]), (! nose[714..714]), (! nose[713..713]), (! nose[712..712]), (! nose[711..711]), (! nose[710..710]), (! nose[709..709]), ((! nose[708..708]) # sel[114..114]), ((! nose[707..707]) # sel[113..113]), ((! nose[706..706]) # sel[112..112]), ((! nose[705..705]) # sel[111..111]), ((! nose[704..704]) # sel[110..110]), (! nose[703..703]), (! nose[702..702]), (! nose[701..701]), (! nose[700..700]), (! nose[699..699]), (! nose[698..698]), (! nose[697..697]), (! nose[696..696]), (! nose[695..695]), (! nose[694..694]), (! nose[693..693]), (! nose[692..692]), (! nose[691..691]), (! nose[690..690]), (! nose[689..689]), (! nose[688..688]), (! nose[687..687]), (! nose[686..686]), (! nose[685..685]), (! nose[684..684]), (! nose[683..683]), (! nose[682..682]), (! nose[681..681]), (! nose[680..680]), (! nose[679..679]), (! nose[678..678]), (! nose[677..677]), ((! nose[676..676]) # sel[109..109]), ((! nose[675..675]) # sel[108..108]), ((! nose[674..674]) # sel[107..107]), ((! nose[673..673]) # sel[106..106]), ((! nose[672..672]) # sel[105..105]), (! nose[671..671]), (! nose[670..670]), (! nose[669..669]), (! nose[668..668]), (! nose[667..667]), (! nose[666..666]), (! nose[665..665]), (! nose[664..664]), (! nose[663..663]), (! nose[662..662]), (! nose[661..661]), (! nose[660..660]), (! nose[659..659]), (! nose[658..658]), (! nose[657..657]), (! nose[656..656]), (! nose[655..655]), (! nose[654..654]), (! nose[653..653]), (! nose[652..652]), (! nose[651..651]), (! nose[650..650]), (! nose[649..649]), (! nose[648..648]), (! nose[647..647]), (! nose[646..646]), (! nose[645..645]), ((! nose[644..644]) # sel[104..104]), ((! nose[643..643]) # sel[103..103]), ((! nose[642..642]) # sel[102..102]), ((! nose[641..641]) # sel[101..101]), ((! nose[640..640]) # sel[100..100]), (! nose[639..639]), (! nose[638..638]), (! nose[637..637]), (! nose[636..636]), (! nose[635..635]), (! nose[634..634]), (! nose[633..633]), (! nose[632..632]), (! nose[631..631]), (! nose[630..630]), (! nose[629..629]), (! nose[628..628]), (! nose[627..627]), (! nose[626..626]), (! nose[625..625]), (! nose[624..624]), (! nose[623..623]), (! nose[622..622]), (! nose[621..621]), (! nose[620..620]), (! nose[619..619]), (! nose[618..618]), (! nose[617..617]), (! nose[616..616]), (! nose[615..615]), (! nose[614..614]), (! nose[613..613]), ((! nose[612..612]) # sel[99..99]), ((! nose[611..611]) # sel[98..98]), ((! nose[610..610]) # sel[97..97]), ((! nose[609..609]) # sel[96..96]), ((! nose[608..608]) # sel[95..95]), (! nose[607..607]), (! nose[606..606]), (! nose[605..605]), (! nose[604..604]), (! nose[603..603]), (! nose[602..602]), (! nose[601..601]), (! nose[600..600]), (! nose[599..599]), (! nose[598..598]), (! nose[597..597]), (! nose[596..596]), (! nose[595..595]), (! nose[594..594]), (! nose[593..593]), (! nose[592..592]), (! nose[591..591]), (! nose[590..590]), (! nose[589..589]), (! nose[588..588]), (! nose[587..587]), (! nose[586..586]), (! nose[585..585]), (! nose[584..584]), (! nose[583..583]), (! nose[582..582]), (! nose[581..581]), ((! nose[580..580]) # sel[94..94]), ((! nose[579..579]) # sel[93..93]), ((! nose[578..578]) # sel[92..92]), ((! nose[577..577]) # sel[91..91]), ((! nose[576..576]) # sel[90..90]), (! nose[575..575]), (! nose[574..574]), (! nose[573..573]), (! nose[572..572]), (! nose[571..571]), (! nose[570..570]), (! nose[569..569]), (! nose[568..568]), (! nose[567..567]), (! nose[566..566]), (! nose[565..565]), (! nose[564..564]), (! nose[563..563]), (! nose[562..562]), (! nose[561..561]), (! nose[560..560]), (! nose[559..559]), (! nose[558..558]), (! nose[557..557]), (! nose[556..556]), (! nose[555..555]), (! nose[554..554]), (! nose[553..553]), (! nose[552..552]), (! nose[551..551]), (! nose[550..550]), (! nose[549..549]), ((! nose[548..548]) # sel[89..89]), ((! nose[547..547]) # sel[88..88]), ((! nose[546..546]) # sel[87..87]), ((! nose[545..545]) # sel[86..86]), ((! nose[544..544]) # sel[85..85]), (! nose[543..543]), (! nose[542..542]), (! nose[541..541]), (! nose[540..540]), (! nose[539..539]), (! nose[538..538]), (! nose[537..537]), (! nose[536..536]), (! nose[535..535]), (! nose[534..534]), (! nose[533..533]), (! nose[532..532]), (! nose[531..531]), (! nose[530..530]), (! nose[529..529]), (! nose[528..528]), (! nose[527..527]), (! nose[526..526]), (! nose[525..525]), (! nose[524..524]), (! nose[523..523]), (! nose[522..522]), (! nose[521..521]), (! nose[520..520]), (! nose[519..519]), (! nose[518..518]), (! nose[517..517]), ((! nose[516..516]) # sel[84..84]), ((! nose[515..515]) # sel[83..83]), ((! nose[514..514]) # sel[82..82]), ((! nose[513..513]) # sel[81..81]), ((! nose[512..512]) # sel[80..80]), (! nose[511..511]), (! nose[510..510]), (! nose[509..509]), (! nose[508..508]), (! nose[507..507]), (! nose[506..506]), (! nose[505..505]), (! nose[504..504]), (! nose[503..503]), (! nose[502..502]), (! nose[501..501]), (! nose[500..500]), (! nose[499..499]), (! nose[498..498]), (! nose[497..497]), (! nose[496..496]), (! nose[495..495]), (! nose[494..494]), (! nose[493..493]), (! nose[492..492]), (! nose[491..491]), (! nose[490..490]), (! nose[489..489]), (! nose[488..488]), (! nose[487..487]), (! nose[486..486]), (! nose[485..485]), ((! nose[484..484]) # sel[79..79]), ((! nose[483..483]) # sel[78..78]), ((! nose[482..482]) # sel[77..77]), ((! nose[481..481]) # sel[76..76]), ((! nose[480..480]) # sel[75..75]), (! nose[479..479]), (! nose[478..478]), (! nose[477..477]), (! nose[476..476]), (! nose[475..475]), (! nose[474..474]), (! nose[473..473]), (! nose[472..472]), (! nose[471..471]), (! nose[470..470]), (! nose[469..469]), (! nose[468..468]), (! nose[467..467]), (! nose[466..466]), (! nose[465..465]), (! nose[464..464]), (! nose[463..463]), (! nose[462..462]), (! nose[461..461]), (! nose[460..460]), (! nose[459..459]), (! nose[458..458]), (! nose[457..457]), (! nose[456..456]), (! nose[455..455]), (! nose[454..454]), (! nose[453..453]), ((! nose[452..452]) # sel[74..74]), ((! nose[451..451]) # sel[73..73]), ((! nose[450..450]) # sel[72..72]), ((! nose[449..449]) # sel[71..71]), ((! nose[448..448]) # sel[70..70]), (! nose[447..447]), (! nose[446..446]), (! nose[445..445]), (! nose[444..444]), (! nose[443..443]), (! nose[442..442]), (! nose[441..441]), (! nose[440..440]), (! nose[439..439]), (! nose[438..438]), (! nose[437..437]), (! nose[436..436]), (! nose[435..435]), (! nose[434..434]), (! nose[433..433]), (! nose[432..432]), (! nose[431..431]), (! nose[430..430]), (! nose[429..429]), (! nose[428..428]), (! nose[427..427]), (! nose[426..426]), (! nose[425..425]), (! nose[424..424]), (! nose[423..423]), (! nose[422..422]), (! nose[421..421]), ((! nose[420..420]) # sel[69..69]), ((! nose[419..419]) # sel[68..68]), ((! nose[418..418]) # sel[67..67]), ((! nose[417..417]) # sel[66..66]), ((! nose[416..416]) # sel[65..65]), (! nose[415..415]), (! nose[414..414]), (! nose[413..413]), (! nose[412..412]), (! nose[411..411]), (! nose[410..410]), (! nose[409..409]), (! nose[408..408]), (! nose[407..407]), (! nose[406..406]), (! nose[405..405]), (! nose[404..404]), (! nose[403..403]), (! nose[402..402]), (! nose[401..401]), (! nose[400..400]), (! nose[399..399]), (! nose[398..398]), (! nose[397..397]), (! nose[396..396]), (! nose[395..395]), (! nose[394..394]), (! nose[393..393]), (! nose[392..392]), (! nose[391..391]), (! nose[390..390]), (! nose[389..389]), ((! nose[388..388]) # sel[64..64]), ((! nose[387..387]) # sel[63..63]), ((! nose[386..386]) # sel[62..62]), ((! nose[385..385]) # sel[61..61]), ((! nose[384..384]) # sel[60..60]), (! nose[383..383]), (! nose[382..382]), (! nose[381..381]), (! nose[380..380]), (! nose[379..379]), (! nose[378..378]), (! nose[377..377]), (! nose[376..376]), (! nose[375..375]), (! nose[374..374]), (! nose[373..373]), (! nose[372..372]), (! nose[371..371]), (! nose[370..370]), (! nose[369..369]), (! nose[368..368]), (! nose[367..367]), (! nose[366..366]), (! nose[365..365]), (! nose[364..364]), (! nose[363..363]), (! nose[362..362]), (! nose[361..361]), (! nose[360..360]), (! nose[359..359]), (! nose[358..358]), (! nose[357..357]), ((! nose[356..356]) # sel[59..59]), ((! nose[355..355]) # sel[58..58]), ((! nose[354..354]) # sel[57..57]), ((! nose[353..353]) # sel[56..56]), ((! nose[352..352]) # sel[55..55]), (! nose[351..351]), (! nose[350..350]), (! nose[349..349]), (! nose[348..348]), (! nose[347..347]), (! nose[346..346]), (! nose[345..345]), (! nose[344..344]), (! nose[343..343]), (! nose[342..342]), (! nose[341..341]), (! nose[340..340]), (! nose[339..339]), (! nose[338..338]), (! nose[337..337]), (! nose[336..336]), (! nose[335..335]), (! nose[334..334]), (! nose[333..333]), (! nose[332..332]), (! nose[331..331]), (! nose[330..330]), (! nose[329..329]), (! nose[328..328]), (! nose[327..327]), (! nose[326..326]), (! nose[325..325]), ((! nose[324..324]) # sel[54..54]), ((! nose[323..323]) # sel[53..53]), ((! nose[322..322]) # sel[52..52]), ((! nose[321..321]) # sel[51..51]), ((! nose[320..320]) # sel[50..50]), (! nose[319..319]), (! nose[318..318]), (! nose[317..317]), (! nose[316..316]), (! nose[315..315]), (! nose[314..314]), (! nose[313..313]), (! nose[312..312]), (! nose[311..311]), (! nose[310..310]), (! nose[309..309]), (! nose[308..308]), (! nose[307..307]), (! nose[306..306]), (! nose[305..305]), (! nose[304..304]), (! nose[303..303]), (! nose[302..302]), (! nose[301..301]), (! nose[300..300]), (! nose[299..299]), (! nose[298..298]), (! nose[297..297]), (! nose[296..296]), (! nose[295..295]), (! nose[294..294]), (! nose[293..293]), ((! nose[292..292]) # sel[49..49]), ((! nose[291..291]) # sel[48..48]), ((! nose[290..290]) # sel[47..47]), ((! nose[289..289]) # sel[46..46]), ((! nose[288..288]) # sel[45..45]), (! nose[287..287]), (! nose[286..286]), (! nose[285..285]), (! nose[284..284]), (! nose[283..283]), (! nose[282..282]), (! nose[281..281]), (! nose[280..280]), (! nose[279..279]), (! nose[278..278]), (! nose[277..277]), (! nose[276..276]), (! nose[275..275]), (! nose[274..274]), (! nose[273..273]), (! nose[272..272]), (! nose[271..271]), (! nose[270..270]), (! nose[269..269]), (! nose[268..268]), (! nose[267..267]), (! nose[266..266]), (! nose[265..265]), (! nose[264..264]), (! nose[263..263]), (! nose[262..262]), (! nose[261..261]), ((! nose[260..260]) # sel[44..44]), ((! nose[259..259]) # sel[43..43]), ((! nose[258..258]) # sel[42..42]), ((! nose[257..257]) # sel[41..41]), ((! nose[256..256]) # sel[40..40]), (! nose[255..255]), (! nose[254..254]), (! nose[253..253]), (! nose[252..252]), (! nose[251..251]), (! nose[250..250]), (! nose[249..249]), (! nose[248..248]), (! nose[247..247]), (! nose[246..246]), (! nose[245..245]), (! nose[244..244]), (! nose[243..243]), (! nose[242..242]), (! nose[241..241]), (! nose[240..240]), (! nose[239..239]), (! nose[238..238]), (! nose[237..237]), (! nose[236..236]), (! nose[235..235]), (! nose[234..234]), (! nose[233..233]), (! nose[232..232]), (! nose[231..231]), (! nose[230..230]), (! nose[229..229]), ((! nose[228..228]) # sel[39..39]), ((! nose[227..227]) # sel[38..38]), ((! nose[226..226]) # sel[37..37]), ((! nose[225..225]) # sel[36..36]), ((! nose[224..224]) # sel[35..35]), (! nose[223..223]), (! nose[222..222]), (! nose[221..221]), (! nose[220..220]), (! nose[219..219]), (! nose[218..218]), (! nose[217..217]), (! nose[216..216]), (! nose[215..215]), (! nose[214..214]), (! nose[213..213]), (! nose[212..212]), (! nose[211..211]), (! nose[210..210]), (! nose[209..209]), (! nose[208..208]), (! nose[207..207]), (! nose[206..206]), (! nose[205..205]), (! nose[204..204]), (! nose[203..203]), (! nose[202..202]), (! nose[201..201]), (! nose[200..200]), (! nose[199..199]), (! nose[198..198]), (! nose[197..197]), ((! nose[196..196]) # sel[34..34]), ((! nose[195..195]) # sel[33..33]), ((! nose[194..194]) # sel[32..32]), ((! nose[193..193]) # sel[31..31]), ((! nose[192..192]) # sel[30..30]), (! nose[191..191]), (! nose[190..190]), (! nose[189..189]), (! nose[188..188]), (! nose[187..187]), (! nose[186..186]), (! nose[185..185]), (! nose[184..184]), (! nose[183..183]), (! nose[182..182]), (! nose[181..181]), (! nose[180..180]), (! nose[179..179]), (! nose[178..178]), (! nose[177..177]), (! nose[176..176]), (! nose[175..175]), (! nose[174..174]), (! nose[173..173]), (! nose[172..172]), (! nose[171..171]), (! nose[170..170]), (! nose[169..169]), (! nose[168..168]), (! nose[167..167]), (! nose[166..166]), (! nose[165..165]), ((! nose[164..164]) # sel[29..29]), ((! nose[163..163]) # sel[28..28]), ((! nose[162..162]) # sel[27..27]), ((! nose[161..161]) # sel[26..26]), ((! nose[160..160]) # sel[25..25]), (! nose[159..159]), (! nose[158..158]), (! nose[157..157]), (! nose[156..156]), (! nose[155..155]), (! nose[154..154]), (! nose[153..153]), (! nose[152..152]), (! nose[151..151]), (! nose[150..150]), (! nose[149..149]), (! nose[148..148]), (! nose[147..147]), (! nose[146..146]), (! nose[145..145]), (! nose[144..144]), (! nose[143..143]), (! nose[142..142]), (! nose[141..141]), (! nose[140..140]), (! nose[139..139]), (! nose[138..138]), (! nose[137..137]), (! nose[136..136]), (! nose[135..135]), (! nose[134..134]), (! nose[133..133]), ((! nose[132..132]) # sel[24..24]), ((! nose[131..131]) # sel[23..23]), ((! nose[130..130]) # sel[22..22]), ((! nose[129..129]) # sel[21..21]), ((! nose[128..128]) # sel[20..20]), (! nose[127..127]), (! nose[126..126]), (! nose[125..125]), (! nose[124..124]), (! nose[123..123]), (! nose[122..122]), (! nose[121..121]), (! nose[120..120]), (! nose[119..119]), (! nose[118..118]), (! nose[117..117]), (! nose[116..116]), (! nose[115..115]), (! nose[114..114]), (! nose[113..113]), (! nose[112..112]), (! nose[111..111]), (! nose[110..110]), (! nose[109..109]), (! nose[108..108]), (! nose[107..107]), (! nose[106..106]), (! nose[105..105]), (! nose[104..104]), (! nose[103..103]), (! nose[102..102]), (! nose[101..101]), ((! nose[100..100]) # sel[19..19]), ((! nose[99..99]) # sel[18..18]), ((! nose[98..98]) # sel[17..17]), ((! nose[97..97]) # sel[16..16]), ((! nose[96..96]) # sel[15..15]), (! nose[95..95]), (! nose[94..94]), (! nose[93..93]), (! nose[92..92]), (! nose[91..91]), (! nose[90..90]), (! nose[89..89]), (! nose[88..88]), (! nose[87..87]), (! nose[86..86]), (! nose[85..85]), (! nose[84..84]), (! nose[83..83]), (! nose[82..82]), (! nose[81..81]), (! nose[80..80]), (! nose[79..79]), (! nose[78..78]), (! nose[77..77]), (! nose[76..76]), (! nose[75..75]), (! nose[74..74]), (! nose[73..73]), (! nose[72..72]), (! nose[71..71]), (! nose[70..70]), (! nose[69..69]), ((! nose[68..68]) # sel[14..14]), ((! nose[67..67]) # sel[13..13]), ((! nose[66..66]) # sel[12..12]), ((! nose[65..65]) # sel[11..11]), ((! nose[64..64]) # sel[10..10]), (! nose[63..63]), (! nose[62..62]), (! nose[61..61]), (! nose[60..60]), (! nose[59..59]), (! nose[58..58]), (! nose[57..57]), (! nose[56..56]), (! nose[55..55]), (! nose[54..54]), (! nose[53..53]), (! nose[52..52]), (! nose[51..51]), (! nose[50..50]), (! nose[49..49]), (! nose[48..48]), (! nose[47..47]), (! nose[46..46]), (! nose[45..45]), (! nose[44..44]), (! nose[43..43]), (! nose[42..42]), (! nose[41..41]), (! nose[40..40]), (! nose[39..39]), (! nose[38..38]), (! nose[37..37]), ((! nose[36..36]) # sel[9..9]), ((! nose[35..35]) # sel[8..8]), ((! nose[34..34]) # sel[7..7]), ((! nose[33..33]) # sel[6..6]), ((! nose[32..32]) # sel[5..5]), (! nose[31..31]), (! nose[30..30]), (! nose[29..29]), (! nose[28..28]), (! nose[27..27]), (! nose[26..26]), (! nose[25..25]), (! nose[24..24]), (! nose[23..23]), (! nose[22..22]), (! nose[21..21]), (! nose[20..20]), (! nose[19..19]), (! nose[18..18]), (! nose[17..17]), (! nose[16..16]), (! nose[15..15]), (! nose[14..14]), (! nose[13..13]), (! nose[12..12]), (! nose[11..11]), (! nose[10..10]), (! nose[9..9]), (! nose[8..8]), (! nose[7..7]), (! nose[6..6]), (! nose[5..5]), ((! nose[4..4]) # sel[4..4]), ((! nose[3..3]) # sel[3..3]), ((! nose[2..2]) # sel[2..2]), ((! nose[1..1]) # sel[1..1]), ((! nose[0..0]) # sel[0..0]));
+ StageIn[] = StageIn_tmp[];
+ StageIn_tmp[] = ( StageOut[191..0], B"000000");
+ StageOut[] = ( ((( StageIn[190..186], NumeratorIn[992..992]) & selnose[1023..1023]) # (prestg[191..186] & (! selnose[1023..1023]))), ((( StageIn[184..180], NumeratorIn[961..961]) & selnose[990..990]) # (prestg[185..180] & (! selnose[990..990]))), ((( StageIn[178..174], NumeratorIn[930..930]) & selnose[957..957]) # (prestg[179..174] & (! selnose[957..957]))), ((( StageIn[172..168], NumeratorIn[899..899]) & selnose[924..924]) # (prestg[173..168] & (! selnose[924..924]))), ((( StageIn[166..162], NumeratorIn[868..868]) & selnose[891..891]) # (prestg[167..162] & (! selnose[891..891]))), ((( StageIn[160..156], NumeratorIn[837..837]) & selnose[858..858]) # (prestg[161..156] & (! selnose[858..858]))), ((( StageIn[154..150], NumeratorIn[806..806]) & selnose[825..825]) # (prestg[155..150] & (! selnose[825..825]))), ((( StageIn[148..144], NumeratorIn[775..775]) & selnose[792..792]) # (prestg[149..144] & (! selnose[792..792]))), ((( StageIn[142..138], NumeratorIn[744..744]) & selnose[759..759]) # (prestg[143..138] & (! selnose[759..759]))), ((( StageIn[136..132], NumeratorIn[713..713]) & selnose[726..726]) # (prestg[137..132] & (! selnose[726..726]))), ((( StageIn[130..126], NumeratorIn[682..682]) & selnose[693..693]) # (prestg[131..126] & (! selnose[693..693]))), ((( StageIn[124..120], NumeratorIn[651..651]) & selnose[660..660]) # (prestg[125..120] & (! selnose[660..660]))), ((( StageIn[118..114], NumeratorIn[620..620]) & selnose[627..627]) # (prestg[119..114] & (! selnose[627..627]))), ((( StageIn[112..108], NumeratorIn[589..589]) & selnose[594..594]) # (prestg[113..108] & (! selnose[594..594]))), ((( StageIn[106..102], NumeratorIn[558..558]) & selnose[561..561]) # (prestg[107..102] & (! selnose[561..561]))), ((( StageIn[100..96], NumeratorIn[527..527]) & selnose[528..528]) # (prestg[101..96] & (! selnose[528..528]))), ((( StageIn[94..90], NumeratorIn[496..496]) & selnose[495..495]) # (prestg[95..90] & (! selnose[495..495]))), ((( StageIn[88..84], NumeratorIn[465..465]) & selnose[462..462]) # (prestg[89..84] & (! selnose[462..462]))), ((( StageIn[82..78], NumeratorIn[434..434]) & selnose[429..429]) # (prestg[83..78] & (! selnose[429..429]))), ((( StageIn[76..72], NumeratorIn[403..403]) & selnose[396..396]) # (prestg[77..72] & (! selnose[396..396]))), ((( StageIn[70..66], NumeratorIn[372..372]) & selnose[363..363]) # (prestg[71..66] & (! selnose[363..363]))), ((( StageIn[64..60], NumeratorIn[341..341]) & selnose[330..330]) # (prestg[65..60] & (! selnose[330..330]))), ((( StageIn[58..54], NumeratorIn[310..310]) & selnose[297..297]) # (prestg[59..54] & (! selnose[297..297]))), ((( StageIn[52..48], NumeratorIn[279..279]) & selnose[264..264]) # (prestg[53..48] & (! selnose[264..264]))), ((( StageIn[46..42], NumeratorIn[248..248]) & selnose[231..231]) # (prestg[47..42] & (! selnose[231..231]))), ((( StageIn[40..36], NumeratorIn[217..217]) & selnose[198..198]) # (prestg[41..36] & (! selnose[198..198]))), ((( StageIn[34..30], NumeratorIn[186..186]) & selnose[165..165]) # (prestg[35..30] & (! selnose[165..165]))), ((( StageIn[28..24], NumeratorIn[155..155]) & selnose[132..132]) # (prestg[29..24] & (! selnose[132..132]))), ((( StageIn[22..18], NumeratorIn[124..124]) & selnose[99..99]) # (prestg[23..18] & (! selnose[99..99]))), ((( StageIn[16..12], NumeratorIn[93..93]) & selnose[66..66]) # (prestg[17..12] & (! selnose[66..66]))), ((( StageIn[10..6], NumeratorIn[62..62]) & selnose[33..33]) # (prestg[11..6] & (! selnose[33..33]))), ((( StageIn[4..0], NumeratorIn[31..31]) & selnose[0..0]) # (prestg[5..0] & (! selnose[0..0]))));
+END;
+--VALID FILE
diff --git a/db/alt_u_div_m2f.tdf b/db/alt_u_div_m2f.tdf
new file mode 100644
index 0000000..083e7a1
--- /dev/null
+++ b/db/alt_u_div_m2f.tdf
@@ -0,0 +1,371 @@
+--alt_u_div DEVICE_FAMILY="Cyclone II" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=6 WIDTH_N=32 WIDTH_Q=32 WIDTH_R=6 denominator numerator quotient remainder
+--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_lpm_divide 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2009 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+
+FUNCTION add_sub_lkc (dataa[0..0], datab[0..0])
+RETURNS ( cout, result[0..0]);
+FUNCTION add_sub_mkc (dataa[1..0], datab[1..0])
+RETURNS ( cout, result[1..0]);
+
+--synthesis_resources = lut 230
+SUBDESIGN alt_u_div_m2f
+(
+ denominator[5..0] : input;
+ numerator[31..0] : input;
+ quotient[31..0] : output;
+ remainder[5..0] : output;
+)
+VARIABLE
+ add_sub_0 : add_sub_lkc;
+ add_sub_1 : add_sub_mkc;
+ add_sub_10_result_int[7..0] : WIRE;
+ add_sub_10_cout : WIRE;
+ add_sub_10_dataa[6..0] : WIRE;
+ add_sub_10_datab[6..0] : WIRE;
+ add_sub_10_result[6..0] : WIRE;
+ add_sub_11_result_int[7..0] : WIRE;
+ add_sub_11_cout : WIRE;
+ add_sub_11_dataa[6..0] : WIRE;
+ add_sub_11_datab[6..0] : WIRE;
+ add_sub_11_result[6..0] : WIRE;
+ add_sub_12_result_int[7..0] : WIRE;
+ add_sub_12_cout : WIRE;
+ add_sub_12_dataa[6..0] : WIRE;
+ add_sub_12_datab[6..0] : WIRE;
+ add_sub_12_result[6..0] : WIRE;
+ add_sub_13_result_int[7..0] : WIRE;
+ add_sub_13_cout : WIRE;
+ add_sub_13_dataa[6..0] : WIRE;
+ add_sub_13_datab[6..0] : WIRE;
+ add_sub_13_result[6..0] : WIRE;
+ add_sub_14_result_int[7..0] : WIRE;
+ add_sub_14_cout : WIRE;
+ add_sub_14_dataa[6..0] : WIRE;
+ add_sub_14_datab[6..0] : WIRE;
+ add_sub_14_result[6..0] : WIRE;
+ add_sub_15_result_int[7..0] : WIRE;
+ add_sub_15_cout : WIRE;
+ add_sub_15_dataa[6..0] : WIRE;
+ add_sub_15_datab[6..0] : WIRE;
+ add_sub_15_result[6..0] : WIRE;
+ add_sub_16_result_int[7..0] : WIRE;
+ add_sub_16_cout : WIRE;
+ add_sub_16_dataa[6..0] : WIRE;
+ add_sub_16_datab[6..0] : WIRE;
+ add_sub_16_result[6..0] : WIRE;
+ add_sub_17_result_int[7..0] : WIRE;
+ add_sub_17_cout : WIRE;
+ add_sub_17_dataa[6..0] : WIRE;
+ add_sub_17_datab[6..0] : WIRE;
+ add_sub_17_result[6..0] : WIRE;
+ add_sub_18_result_int[7..0] : WIRE;
+ add_sub_18_cout : WIRE;
+ add_sub_18_dataa[6..0] : WIRE;
+ add_sub_18_datab[6..0] : WIRE;
+ add_sub_18_result[6..0] : WIRE;
+ add_sub_19_result_int[7..0] : WIRE;
+ add_sub_19_cout : WIRE;
+ add_sub_19_dataa[6..0] : WIRE;
+ add_sub_19_datab[6..0] : WIRE;
+ add_sub_19_result[6..0] : WIRE;
+ add_sub_2_result_int[3..0] : WIRE;
+ add_sub_2_cout : WIRE;
+ add_sub_2_dataa[2..0] : WIRE;
+ add_sub_2_datab[2..0] : WIRE;
+ add_sub_2_result[2..0] : WIRE;
+ add_sub_20_result_int[7..0] : WIRE;
+ add_sub_20_cout : WIRE;
+ add_sub_20_dataa[6..0] : WIRE;
+ add_sub_20_datab[6..0] : WIRE;
+ add_sub_20_result[6..0] : WIRE;
+ add_sub_21_result_int[7..0] : WIRE;
+ add_sub_21_cout : WIRE;
+ add_sub_21_dataa[6..0] : WIRE;
+ add_sub_21_datab[6..0] : WIRE;
+ add_sub_21_result[6..0] : WIRE;
+ add_sub_22_result_int[7..0] : WIRE;
+ add_sub_22_cout : WIRE;
+ add_sub_22_dataa[6..0] : WIRE;
+ add_sub_22_datab[6..0] : WIRE;
+ add_sub_22_result[6..0] : WIRE;
+ add_sub_23_result_int[7..0] : WIRE;
+ add_sub_23_cout : WIRE;
+ add_sub_23_dataa[6..0] : WIRE;
+ add_sub_23_datab[6..0] : WIRE;
+ add_sub_23_result[6..0] : WIRE;
+ add_sub_24_result_int[7..0] : WIRE;
+ add_sub_24_cout : WIRE;
+ add_sub_24_dataa[6..0] : WIRE;
+ add_sub_24_datab[6..0] : WIRE;
+ add_sub_24_result[6..0] : WIRE;
+ add_sub_25_result_int[7..0] : WIRE;
+ add_sub_25_cout : WIRE;
+ add_sub_25_dataa[6..0] : WIRE;
+ add_sub_25_datab[6..0] : WIRE;
+ add_sub_25_result[6..0] : WIRE;
+ add_sub_26_result_int[7..0] : WIRE;
+ add_sub_26_cout : WIRE;
+ add_sub_26_dataa[6..0] : WIRE;
+ add_sub_26_datab[6..0] : WIRE;
+ add_sub_26_result[6..0] : WIRE;
+ add_sub_27_result_int[7..0] : WIRE;
+ add_sub_27_cout : WIRE;
+ add_sub_27_dataa[6..0] : WIRE;
+ add_sub_27_datab[6..0] : WIRE;
+ add_sub_27_result[6..0] : WIRE;
+ add_sub_28_result_int[7..0] : WIRE;
+ add_sub_28_cout : WIRE;
+ add_sub_28_dataa[6..0] : WIRE;
+ add_sub_28_datab[6..0] : WIRE;
+ add_sub_28_result[6..0] : WIRE;
+ add_sub_29_result_int[7..0] : WIRE;
+ add_sub_29_cout : WIRE;
+ add_sub_29_dataa[6..0] : WIRE;
+ add_sub_29_datab[6..0] : WIRE;
+ add_sub_29_result[6..0] : WIRE;
+ add_sub_3_result_int[4..0] : WIRE;
+ add_sub_3_cout : WIRE;
+ add_sub_3_dataa[3..0] : WIRE;
+ add_sub_3_datab[3..0] : WIRE;
+ add_sub_3_result[3..0] : WIRE;
+ add_sub_30_result_int[7..0] : WIRE;
+ add_sub_30_cout : WIRE;
+ add_sub_30_dataa[6..0] : WIRE;
+ add_sub_30_datab[6..0] : WIRE;
+ add_sub_30_result[6..0] : WIRE;
+ add_sub_31_result_int[7..0] : WIRE;
+ add_sub_31_cout : WIRE;
+ add_sub_31_dataa[6..0] : WIRE;
+ add_sub_31_datab[6..0] : WIRE;
+ add_sub_31_result[6..0] : WIRE;
+ add_sub_4_result_int[5..0] : WIRE;
+ add_sub_4_cout : WIRE;
+ add_sub_4_dataa[4..0] : WIRE;
+ add_sub_4_datab[4..0] : WIRE;
+ add_sub_4_result[4..0] : WIRE;
+ add_sub_5_result_int[6..0] : WIRE;
+ add_sub_5_cout : WIRE;
+ add_sub_5_dataa[5..0] : WIRE;
+ add_sub_5_datab[5..0] : WIRE;
+ add_sub_5_result[5..0] : WIRE;
+ add_sub_6_result_int[7..0] : WIRE;
+ add_sub_6_cout : WIRE;
+ add_sub_6_dataa[6..0] : WIRE;
+ add_sub_6_datab[6..0] : WIRE;
+ add_sub_6_result[6..0] : WIRE;
+ add_sub_7_result_int[7..0] : WIRE;
+ add_sub_7_cout : WIRE;
+ add_sub_7_dataa[6..0] : WIRE;
+ add_sub_7_datab[6..0] : WIRE;
+ add_sub_7_result[6..0] : WIRE;
+ add_sub_8_result_int[7..0] : WIRE;
+ add_sub_8_cout : WIRE;
+ add_sub_8_dataa[6..0] : WIRE;
+ add_sub_8_datab[6..0] : WIRE;
+ add_sub_8_result[6..0] : WIRE;
+ add_sub_9_result_int[7..0] : WIRE;
+ add_sub_9_cout : WIRE;
+ add_sub_9_dataa[6..0] : WIRE;
+ add_sub_9_datab[6..0] : WIRE;
+ add_sub_9_result[6..0] : WIRE;
+ DenominatorIn[230..0] : WIRE;
+ DenominatorIn_tmp[230..0] : WIRE;
+ gnd_wire : WIRE;
+ nose[1055..0] : WIRE;
+ NumeratorIn[1055..0] : WIRE;
+ NumeratorIn_tmp[1055..0] : WIRE;
+ prestg[223..0] : WIRE;
+ quotient_tmp[31..0] : WIRE;
+ sel[197..0] : WIRE;
+ selnose[1055..0] : WIRE;
+ StageIn[230..0] : WIRE;
+ StageIn_tmp[230..0] : WIRE;
+ StageOut[223..0] : WIRE;
+
+BEGIN
+ add_sub_0.dataa[0..0] = NumeratorIn[31..31];
+ add_sub_0.datab[0..0] = DenominatorIn[0..0];
+ add_sub_1.dataa[] = ( StageIn[7..7], NumeratorIn[62..62]);
+ add_sub_1.datab[1..0] = DenominatorIn[8..7];
+ add_sub_10_result_int[] = (0, add_sub_10_dataa[]) - (0, add_sub_10_datab[]);
+ add_sub_10_result[] = add_sub_10_result_int[6..0];
+ add_sub_10_cout = !add_sub_10_result_int[7];
+ add_sub_10_dataa[] = ( StageIn[75..70], NumeratorIn[341..341]);
+ add_sub_10_datab[] = DenominatorIn[76..70];
+ add_sub_11_result_int[] = (0, add_sub_11_dataa[]) - (0, add_sub_11_datab[]);
+ add_sub_11_result[] = add_sub_11_result_int[6..0];
+ add_sub_11_cout = !add_sub_11_result_int[7];
+ add_sub_11_dataa[] = ( StageIn[82..77], NumeratorIn[372..372]);
+ add_sub_11_datab[] = DenominatorIn[83..77];
+ add_sub_12_result_int[] = (0, add_sub_12_dataa[]) - (0, add_sub_12_datab[]);
+ add_sub_12_result[] = add_sub_12_result_int[6..0];
+ add_sub_12_cout = !add_sub_12_result_int[7];
+ add_sub_12_dataa[] = ( StageIn[89..84], NumeratorIn[403..403]);
+ add_sub_12_datab[] = DenominatorIn[90..84];
+ add_sub_13_result_int[] = (0, add_sub_13_dataa[]) - (0, add_sub_13_datab[]);
+ add_sub_13_result[] = add_sub_13_result_int[6..0];
+ add_sub_13_cout = !add_sub_13_result_int[7];
+ add_sub_13_dataa[] = ( StageIn[96..91], NumeratorIn[434..434]);
+ add_sub_13_datab[] = DenominatorIn[97..91];
+ add_sub_14_result_int[] = (0, add_sub_14_dataa[]) - (0, add_sub_14_datab[]);
+ add_sub_14_result[] = add_sub_14_result_int[6..0];
+ add_sub_14_cout = !add_sub_14_result_int[7];
+ add_sub_14_dataa[] = ( StageIn[103..98], NumeratorIn[465..465]);
+ add_sub_14_datab[] = DenominatorIn[104..98];
+ add_sub_15_result_int[] = (0, add_sub_15_dataa[]) - (0, add_sub_15_datab[]);
+ add_sub_15_result[] = add_sub_15_result_int[6..0];
+ add_sub_15_cout = !add_sub_15_result_int[7];
+ add_sub_15_dataa[] = ( StageIn[110..105], NumeratorIn[496..496]);
+ add_sub_15_datab[] = DenominatorIn[111..105];
+ add_sub_16_result_int[] = (0, add_sub_16_dataa[]) - (0, add_sub_16_datab[]);
+ add_sub_16_result[] = add_sub_16_result_int[6..0];
+ add_sub_16_cout = !add_sub_16_result_int[7];
+ add_sub_16_dataa[] = ( StageIn[117..112], NumeratorIn[527..527]);
+ add_sub_16_datab[] = DenominatorIn[118..112];
+ add_sub_17_result_int[] = (0, add_sub_17_dataa[]) - (0, add_sub_17_datab[]);
+ add_sub_17_result[] = add_sub_17_result_int[6..0];
+ add_sub_17_cout = !add_sub_17_result_int[7];
+ add_sub_17_dataa[] = ( StageIn[124..119], NumeratorIn[558..558]);
+ add_sub_17_datab[] = DenominatorIn[125..119];
+ add_sub_18_result_int[] = (0, add_sub_18_dataa[]) - (0, add_sub_18_datab[]);
+ add_sub_18_result[] = add_sub_18_result_int[6..0];
+ add_sub_18_cout = !add_sub_18_result_int[7];
+ add_sub_18_dataa[] = ( StageIn[131..126], NumeratorIn[589..589]);
+ add_sub_18_datab[] = DenominatorIn[132..126];
+ add_sub_19_result_int[] = (0, add_sub_19_dataa[]) - (0, add_sub_19_datab[]);
+ add_sub_19_result[] = add_sub_19_result_int[6..0];
+ add_sub_19_cout = !add_sub_19_result_int[7];
+ add_sub_19_dataa[] = ( StageIn[138..133], NumeratorIn[620..620]);
+ add_sub_19_datab[] = DenominatorIn[139..133];
+ add_sub_2_result_int[] = (0, add_sub_2_dataa[]) - (0, add_sub_2_datab[]);
+ add_sub_2_result[] = add_sub_2_result_int[2..0];
+ add_sub_2_cout = !add_sub_2_result_int[3];
+ add_sub_2_dataa[] = ( StageIn[15..14], NumeratorIn[93..93]);
+ add_sub_2_datab[] = DenominatorIn[16..14];
+ add_sub_20_result_int[] = (0, add_sub_20_dataa[]) - (0, add_sub_20_datab[]);
+ add_sub_20_result[] = add_sub_20_result_int[6..0];
+ add_sub_20_cout = !add_sub_20_result_int[7];
+ add_sub_20_dataa[] = ( StageIn[145..140], NumeratorIn[651..651]);
+ add_sub_20_datab[] = DenominatorIn[146..140];
+ add_sub_21_result_int[] = (0, add_sub_21_dataa[]) - (0, add_sub_21_datab[]);
+ add_sub_21_result[] = add_sub_21_result_int[6..0];
+ add_sub_21_cout = !add_sub_21_result_int[7];
+ add_sub_21_dataa[] = ( StageIn[152..147], NumeratorIn[682..682]);
+ add_sub_21_datab[] = DenominatorIn[153..147];
+ add_sub_22_result_int[] = (0, add_sub_22_dataa[]) - (0, add_sub_22_datab[]);
+ add_sub_22_result[] = add_sub_22_result_int[6..0];
+ add_sub_22_cout = !add_sub_22_result_int[7];
+ add_sub_22_dataa[] = ( StageIn[159..154], NumeratorIn[713..713]);
+ add_sub_22_datab[] = DenominatorIn[160..154];
+ add_sub_23_result_int[] = (0, add_sub_23_dataa[]) - (0, add_sub_23_datab[]);
+ add_sub_23_result[] = add_sub_23_result_int[6..0];
+ add_sub_23_cout = !add_sub_23_result_int[7];
+ add_sub_23_dataa[] = ( StageIn[166..161], NumeratorIn[744..744]);
+ add_sub_23_datab[] = DenominatorIn[167..161];
+ add_sub_24_result_int[] = (0, add_sub_24_dataa[]) - (0, add_sub_24_datab[]);
+ add_sub_24_result[] = add_sub_24_result_int[6..0];
+ add_sub_24_cout = !add_sub_24_result_int[7];
+ add_sub_24_dataa[] = ( StageIn[173..168], NumeratorIn[775..775]);
+ add_sub_24_datab[] = DenominatorIn[174..168];
+ add_sub_25_result_int[] = (0, add_sub_25_dataa[]) - (0, add_sub_25_datab[]);
+ add_sub_25_result[] = add_sub_25_result_int[6..0];
+ add_sub_25_cout = !add_sub_25_result_int[7];
+ add_sub_25_dataa[] = ( StageIn[180..175], NumeratorIn[806..806]);
+ add_sub_25_datab[] = DenominatorIn[181..175];
+ add_sub_26_result_int[] = (0, add_sub_26_dataa[]) - (0, add_sub_26_datab[]);
+ add_sub_26_result[] = add_sub_26_result_int[6..0];
+ add_sub_26_cout = !add_sub_26_result_int[7];
+ add_sub_26_dataa[] = ( StageIn[187..182], NumeratorIn[837..837]);
+ add_sub_26_datab[] = DenominatorIn[188..182];
+ add_sub_27_result_int[] = (0, add_sub_27_dataa[]) - (0, add_sub_27_datab[]);
+ add_sub_27_result[] = add_sub_27_result_int[6..0];
+ add_sub_27_cout = !add_sub_27_result_int[7];
+ add_sub_27_dataa[] = ( StageIn[194..189], NumeratorIn[868..868]);
+ add_sub_27_datab[] = DenominatorIn[195..189];
+ add_sub_28_result_int[] = (0, add_sub_28_dataa[]) - (0, add_sub_28_datab[]);
+ add_sub_28_result[] = add_sub_28_result_int[6..0];
+ add_sub_28_cout = !add_sub_28_result_int[7];
+ add_sub_28_dataa[] = ( StageIn[201..196], NumeratorIn[899..899]);
+ add_sub_28_datab[] = DenominatorIn[202..196];
+ add_sub_29_result_int[] = (0, add_sub_29_dataa[]) - (0, add_sub_29_datab[]);
+ add_sub_29_result[] = add_sub_29_result_int[6..0];
+ add_sub_29_cout = !add_sub_29_result_int[7];
+ add_sub_29_dataa[] = ( StageIn[208..203], NumeratorIn[930..930]);
+ add_sub_29_datab[] = DenominatorIn[209..203];
+ add_sub_3_result_int[] = (0, add_sub_3_dataa[]) - (0, add_sub_3_datab[]);
+ add_sub_3_result[] = add_sub_3_result_int[3..0];
+ add_sub_3_cout = !add_sub_3_result_int[4];
+ add_sub_3_dataa[] = ( StageIn[23..21], NumeratorIn[124..124]);
+ add_sub_3_datab[] = DenominatorIn[24..21];
+ add_sub_30_result_int[] = (0, add_sub_30_dataa[]) - (0, add_sub_30_datab[]);
+ add_sub_30_result[] = add_sub_30_result_int[6..0];
+ add_sub_30_cout = !add_sub_30_result_int[7];
+ add_sub_30_dataa[] = ( StageIn[215..210], NumeratorIn[961..961]);
+ add_sub_30_datab[] = DenominatorIn[216..210];
+ add_sub_31_result_int[] = (0, add_sub_31_dataa[]) - (0, add_sub_31_datab[]);
+ add_sub_31_result[] = add_sub_31_result_int[6..0];
+ add_sub_31_cout = !add_sub_31_result_int[7];
+ add_sub_31_dataa[] = ( StageIn[222..217], NumeratorIn[992..992]);
+ add_sub_31_datab[] = DenominatorIn[223..217];
+ add_sub_4_result_int[] = (0, add_sub_4_dataa[]) - (0, add_sub_4_datab[]);
+ add_sub_4_result[] = add_sub_4_result_int[4..0];
+ add_sub_4_cout = !add_sub_4_result_int[5];
+ add_sub_4_dataa[] = ( StageIn[31..28], NumeratorIn[155..155]);
+ add_sub_4_datab[] = DenominatorIn[32..28];
+ add_sub_5_result_int[] = (0, add_sub_5_dataa[]) - (0, add_sub_5_datab[]);
+ add_sub_5_result[] = add_sub_5_result_int[5..0];
+ add_sub_5_cout = !add_sub_5_result_int[6];
+ add_sub_5_dataa[] = ( StageIn[39..35], NumeratorIn[186..186]);
+ add_sub_5_datab[] = DenominatorIn[40..35];
+ add_sub_6_result_int[] = (0, add_sub_6_dataa[]) - (0, add_sub_6_datab[]);
+ add_sub_6_result[] = add_sub_6_result_int[6..0];
+ add_sub_6_cout = !add_sub_6_result_int[7];
+ add_sub_6_dataa[] = ( StageIn[47..42], NumeratorIn[217..217]);
+ add_sub_6_datab[] = DenominatorIn[48..42];
+ add_sub_7_result_int[] = (0, add_sub_7_dataa[]) - (0, add_sub_7_datab[]);
+ add_sub_7_result[] = add_sub_7_result_int[6..0];
+ add_sub_7_cout = !add_sub_7_result_int[7];
+ add_sub_7_dataa[] = ( StageIn[54..49], NumeratorIn[248..248]);
+ add_sub_7_datab[] = DenominatorIn[55..49];
+ add_sub_8_result_int[] = (0, add_sub_8_dataa[]) - (0, add_sub_8_datab[]);
+ add_sub_8_result[] = add_sub_8_result_int[6..0];
+ add_sub_8_cout = !add_sub_8_result_int[7];
+ add_sub_8_dataa[] = ( StageIn[61..56], NumeratorIn[279..279]);
+ add_sub_8_datab[] = DenominatorIn[62..56];
+ add_sub_9_result_int[] = (0, add_sub_9_dataa[]) - (0, add_sub_9_datab[]);
+ add_sub_9_result[] = add_sub_9_result_int[6..0];
+ add_sub_9_cout = !add_sub_9_result_int[7];
+ add_sub_9_dataa[] = ( StageIn[68..63], NumeratorIn[310..310]);
+ add_sub_9_datab[] = DenominatorIn[69..63];
+ DenominatorIn[] = DenominatorIn_tmp[];
+ DenominatorIn_tmp[] = ( DenominatorIn[223..0], ( gnd_wire, denominator[]));
+ gnd_wire = B"0";
+ nose[] = ( B"00000000000000000000000000000000", add_sub_31_cout, B"00000000000000000000000000000000", add_sub_30_cout, B"00000000000000000000000000000000", add_sub_29_cout, B"00000000000000000000000000000000", add_sub_28_cout, B"00000000000000000000000000000000", add_sub_27_cout, B"00000000000000000000000000000000", add_sub_26_cout, B"00000000000000000000000000000000", add_sub_25_cout, B"00000000000000000000000000000000", add_sub_24_cout, B"00000000000000000000000000000000", add_sub_23_cout, B"00000000000000000000000000000000", add_sub_22_cout, B"00000000000000000000000000000000", add_sub_21_cout, B"00000000000000000000000000000000", add_sub_20_cout, B"00000000000000000000000000000000", add_sub_19_cout, B"00000000000000000000000000000000", add_sub_18_cout, B"00000000000000000000000000000000", add_sub_17_cout, B"00000000000000000000000000000000", add_sub_16_cout, B"00000000000000000000000000000000", add_sub_15_cout, B"00000000000000000000000000000000", add_sub_14_cout, B"00000000000000000000000000000000", add_sub_13_cout, B"00000000000000000000000000000000", add_sub_12_cout, B"00000000000000000000000000000000", add_sub_11_cout, B"00000000000000000000000000000000", add_sub_10_cout, B"00000000000000000000000000000000", add_sub_9_cout, B"00000000000000000000000000000000", add_sub_8_cout, B"00000000000000000000000000000000", add_sub_7_cout, B"00000000000000000000000000000000", add_sub_6_cout, B"00000000000000000000000000000000", add_sub_5_cout, B"00000000000000000000000000000000", add_sub_4_cout, B"00000000000000000000000000000000", add_sub_3_cout, B"00000000000000000000000000000000", add_sub_2_cout, B"00000000000000000000000000000000", add_sub_1.cout, B"00000000000000000000000000000000", add_sub_0.cout);
+ NumeratorIn[] = NumeratorIn_tmp[];
+ NumeratorIn_tmp[] = ( NumeratorIn[1023..0], numerator[]);
+ prestg[] = ( add_sub_31_result[], add_sub_30_result[], add_sub_29_result[], add_sub_28_result[], add_sub_27_result[], add_sub_26_result[], add_sub_25_result[], add_sub_24_result[], add_sub_23_result[], add_sub_22_result[], add_sub_21_result[], add_sub_20_result[], add_sub_19_result[], add_sub_18_result[], add_sub_17_result[], add_sub_16_result[], add_sub_15_result[], add_sub_14_result[], add_sub_13_result[], add_sub_12_result[], add_sub_11_result[], add_sub_10_result[], add_sub_9_result[], add_sub_8_result[], add_sub_7_result[], add_sub_6_result[], GND, add_sub_5_result[], B"00", add_sub_4_result[], B"000", add_sub_3_result[], B"0000", add_sub_2_result[], B"00000", add_sub_1.result[], B"000000", add_sub_0.result[]);
+ quotient[] = quotient_tmp[];
+ quotient_tmp[] = ( (! selnose[0..0]), (! selnose[33..33]), (! selnose[66..66]), (! selnose[99..99]), (! selnose[132..132]), (! selnose[165..165]), (! selnose[198..198]), (! selnose[231..231]), (! selnose[264..264]), (! selnose[297..297]), (! selnose[330..330]), (! selnose[363..363]), (! selnose[396..396]), (! selnose[429..429]), (! selnose[462..462]), (! selnose[495..495]), (! selnose[528..528]), (! selnose[561..561]), (! selnose[594..594]), (! selnose[627..627]), (! selnose[660..660]), (! selnose[693..693]), (! selnose[726..726]), (! selnose[759..759]), (! selnose[792..792]), (! selnose[825..825]), (! selnose[858..858]), (! selnose[891..891]), (! selnose[924..924]), (! selnose[957..957]), (! selnose[990..990]), (! selnose[1023..1023]));
+ remainder[5..0] = StageIn[229..224];
+ sel[] = ( gnd_wire, (sel[197..197] # DenominatorIn[229..229]), (sel[196..196] # DenominatorIn[228..228]), (sel[195..195] # DenominatorIn[227..227]), (sel[194..194] # DenominatorIn[226..226]), (sel[193..193] # DenominatorIn[225..225]), gnd_wire, (sel[191..191] # DenominatorIn[222..222]), (sel[190..190] # DenominatorIn[221..221]), (sel[189..189] # DenominatorIn[220..220]), (sel[188..188] # DenominatorIn[219..219]), (sel[187..187] # DenominatorIn[218..218]), gnd_wire, (sel[185..185] # DenominatorIn[215..215]), (sel[184..184] # DenominatorIn[214..214]), (sel[183..183] # DenominatorIn[213..213]), (sel[182..182] # DenominatorIn[212..212]), (sel[181..181] # DenominatorIn[211..211]), gnd_wire, (sel[179..179] # DenominatorIn[208..208]), (sel[178..178] # DenominatorIn[207..207]), (sel[177..177] # DenominatorIn[206..206]), (sel[176..176] # DenominatorIn[205..205]), (sel[175..175] # DenominatorIn[204..204]), gnd_wire, (sel[173..173] # DenominatorIn[201..201]), (sel[172..172] # DenominatorIn[200..200]), (sel[171..171] # DenominatorIn[199..199]), (sel[170..170] # DenominatorIn[198..198]), (sel[169..169] # DenominatorIn[197..197]), gnd_wire, (sel[167..167] # DenominatorIn[194..194]), (sel[166..166] # DenominatorIn[193..193]), (sel[165..165] # DenominatorIn[192..192]), (sel[164..164] # DenominatorIn[191..191]), (sel[163..163] # DenominatorIn[190..190]), gnd_wire, (sel[161..161] # DenominatorIn[187..187]), (sel[160..160] # DenominatorIn[186..186]), (sel[159..159] # DenominatorIn[185..185]), (sel[158..158] # DenominatorIn[184..184]), (sel[157..157] # DenominatorIn[183..183]), gnd_wire, (sel[155..155] # DenominatorIn[180..180]), (sel[154..154] # DenominatorIn[179..179]), (sel[153..153] # DenominatorIn[178..178]), (sel[152..152] # DenominatorIn[177..177]), (sel[151..151] # DenominatorIn[176..176]), gnd_wire, (sel[149..149] # DenominatorIn[173..173]), (sel[148..148] # DenominatorIn[172..172]), (sel[147..147] # DenominatorIn[171..171]), (sel[146..146] # DenominatorIn[170..170]), (sel[145..145] # DenominatorIn[169..169]), gnd_wire, (sel[143..143] # DenominatorIn[166..166]), (sel[142..142] # DenominatorIn[165..165]), (sel[141..141] # DenominatorIn[164..164]), (sel[140..140] # DenominatorIn[163..163]), (sel[139..139] # DenominatorIn[162..162]), gnd_wire, (sel[137..137] # DenominatorIn[159..159]), (sel[136..136] # DenominatorIn[158..158]), (sel[135..135] # DenominatorIn[157..157]), (sel[134..134] # DenominatorIn[156..156]), (sel[133..133] # DenominatorIn[155..155]), gnd_wire, (sel[131..131] # DenominatorIn[152..152]), (sel[130..130] # DenominatorIn[151..151]), (sel[129..129] # DenominatorIn[150..150]), (sel[128..128] # DenominatorIn[149..149]), (sel[127..127] # DenominatorIn[148..148]), gnd_wire, (sel[125..125] # DenominatorIn[145..145]), (sel[124..124] # DenominatorIn[144..144]), (sel[123..123] # DenominatorIn[143..143]), (sel[122..122] # DenominatorIn[142..142]), (sel[121..121] # DenominatorIn[141..141]), gnd_wire, (sel[119..119] # DenominatorIn[138..138]), (sel[118..118] # DenominatorIn[137..137]), (sel[117..117] # DenominatorIn[136..136]), (sel[116..116] # DenominatorIn[135..135]), (sel[115..115] # DenominatorIn[134..134]), gnd_wire, (sel[113..113] # DenominatorIn[131..131]), (sel[112..112] # DenominatorIn[130..130]), (sel[111..111] # DenominatorIn[129..129]), (sel[110..110] # DenominatorIn[128..128]), (sel[109..109] # DenominatorIn[127..127]), gnd_wire, (sel[107..107] # DenominatorIn[124..124]), (sel[106..106] # DenominatorIn[123..123]), (sel[105..105] # DenominatorIn[122..122]), (sel[104..104] # DenominatorIn[121..121]), (sel[103..103] # DenominatorIn[120..120]), gnd_wire, (sel[101..101] # DenominatorIn[117..117]), (sel[100..100] # DenominatorIn[116..116]), (sel[99..99] # DenominatorIn[115..115]), (sel[98..98] # DenominatorIn[114..114]), (sel[97..97] # DenominatorIn[113..113]), gnd_wire, (sel[95..95] # DenominatorIn[110..110]), (sel[94..94] # DenominatorIn[109..109]), (sel[93..93] # DenominatorIn[108..108]), (sel[92..92] # DenominatorIn[107..107]), (sel[91..91] # DenominatorIn[106..106]), gnd_wire, (sel[89..89] # DenominatorIn[103..103]), (sel[88..88] # DenominatorIn[102..102]), (sel[87..87] # DenominatorIn[101..101]), (sel[86..86] # DenominatorIn[100..100]), (sel[85..85] # DenominatorIn[99..99]), gnd_wire, (sel[83..83] # DenominatorIn[96..96]), (sel[82..82] # DenominatorIn[95..95]), (sel[81..81] # DenominatorIn[94..94]), (sel[80..80] # DenominatorIn[93..93]), (sel[79..79] # DenominatorIn[92..92]), gnd_wire, (sel[77..77] # DenominatorIn[89..89]), (sel[76..76] # DenominatorIn[88..88]), (sel[75..75] # DenominatorIn[87..87]), (sel[74..74] # DenominatorIn[86..86]), (sel[73..73] # DenominatorIn[85..85]), gnd_wire, (sel[71..71] # DenominatorIn[82..82]), (sel[70..70] # DenominatorIn[81..81]), (sel[69..69] # DenominatorIn[80..80]), (sel[68..68] # DenominatorIn[79..79]), (sel[67..67] # DenominatorIn[78..78]), gnd_wire, (sel[65..65] # DenominatorIn[75..75]), (sel[64..64] # DenominatorIn[74..74]), (sel[63..63] # DenominatorIn[73..73]), (sel[62..62] # DenominatorIn[72..72]), (sel[61..61] # DenominatorIn[71..71]), gnd_wire, (sel[59..59] # DenominatorIn[68..68]), (sel[58..58] # DenominatorIn[67..67]), (sel[57..57] # DenominatorIn[66..66]), (sel[56..56] # DenominatorIn[65..65]), (sel[55..55] # DenominatorIn[64..64]), gnd_wire, (sel[53..53] # DenominatorIn[61..61]), (sel[52..52] # DenominatorIn[60..60]), (sel[51..51] # DenominatorIn[59..59]), (sel[50..50] # DenominatorIn[58..58]), (sel[49..49] # DenominatorIn[57..57]), gnd_wire, (sel[47..47] # DenominatorIn[54..54]), (sel[46..46] # DenominatorIn[53..53]), (sel[45..45] # DenominatorIn[52..52]), (sel[44..44] # DenominatorIn[51..51]), (sel[43..43] # DenominatorIn[50..50]), gnd_wire, (sel[41..41] # DenominatorIn[47..47]), (sel[40..40] # DenominatorIn[46..46]), (sel[39..39] # DenominatorIn[45..45]), (sel[38..38] # DenominatorIn[44..44]), (sel[37..37] # DenominatorIn[43..43]), gnd_wire, (sel[35..35] # DenominatorIn[40..40]), (sel[34..34] # DenominatorIn[39..39]), (sel[33..33] # DenominatorIn[38..38]), (sel[32..32] # DenominatorIn[37..37]), (sel[31..31] # DenominatorIn[36..36]), gnd_wire, (sel[29..29] # DenominatorIn[33..33]), (sel[28..28] # DenominatorIn[32..32]), (sel[27..27] # DenominatorIn[31..31]), (sel[26..26] # DenominatorIn[30..30]), (sel[25..25] # DenominatorIn[29..29]), gnd_wire, (sel[23..23] # DenominatorIn[26..26]), (sel[22..22] # DenominatorIn[25..25]), (sel[21..21] # DenominatorIn[24..24]), (sel[20..20] # DenominatorIn[23..23]), (sel[19..19] # DenominatorIn[22..22]), gnd_wire, (sel[17..17] # DenominatorIn[19..19]), (sel[16..16] # DenominatorIn[18..18]), (sel[15..15] # DenominatorIn[17..17]), (sel[14..14] # DenominatorIn[16..16]), (sel[13..13] # DenominatorIn[15..15]), gnd_wire, (sel[11..11] # DenominatorIn[12..12]), (sel[10..10] # DenominatorIn[11..11]), (sel[9..9] # DenominatorIn[10..10]), (sel[8..8] # DenominatorIn[9..9]), (sel[7..7] # DenominatorIn[8..8]), gnd_wire, (sel[5..5] # DenominatorIn[5..5]), (sel[4..4] # DenominatorIn[4..4]), (sel[3..3] # DenominatorIn[3..3]), (sel[2..2] # DenominatorIn[2..2]), (sel[1..1] # DenominatorIn[1..1]));
+ selnose[] = ( (! nose[1055..1055]), (! nose[1054..1054]), (! nose[1053..1053]), (! nose[1052..1052]), (! nose[1051..1051]), (! nose[1050..1050]), (! nose[1049..1049]), (! nose[1048..1048]), (! nose[1047..1047]), (! nose[1046..1046]), (! nose[1045..1045]), (! nose[1044..1044]), (! nose[1043..1043]), (! nose[1042..1042]), (! nose[1041..1041]), (! nose[1040..1040]), (! nose[1039..1039]), (! nose[1038..1038]), (! nose[1037..1037]), (! nose[1036..1036]), (! nose[1035..1035]), (! nose[1034..1034]), (! nose[1033..1033]), (! nose[1032..1032]), (! nose[1031..1031]), (! nose[1030..1030]), ((! nose[1029..1029]) # sel[197..197]), ((! nose[1028..1028]) # sel[196..196]), ((! nose[1027..1027]) # sel[195..195]), ((! nose[1026..1026]) # sel[194..194]), ((! nose[1025..1025]) # sel[193..193]), ((! nose[1024..1024]) # sel[192..192]), (! nose[1023..1023]), (! nose[1022..1022]), (! nose[1021..1021]), (! nose[1020..1020]), (! nose[1019..1019]), (! nose[1018..1018]), (! nose[1017..1017]), (! nose[1016..1016]), (! nose[1015..1015]), (! nose[1014..1014]), (! nose[1013..1013]), (! nose[1012..1012]), (! nose[1011..1011]), (! nose[1010..1010]), (! nose[1009..1009]), (! nose[1008..1008]), (! nose[1007..1007]), (! nose[1006..1006]), (! nose[1005..1005]), (! nose[1004..1004]), (! nose[1003..1003]), (! nose[1002..1002]), (! nose[1001..1001]), (! nose[1000..1000]), (! nose[999..999]), (! nose[998..998]), ((! nose[997..997]) # sel[191..191]), ((! nose[996..996]) # sel[190..190]), ((! nose[995..995]) # sel[189..189]), ((! nose[994..994]) # sel[188..188]), ((! nose[993..993]) # sel[187..187]), ((! nose[992..992]) # sel[186..186]), (! nose[991..991]), (! nose[990..990]), (! nose[989..989]), (! nose[988..988]), (! nose[987..987]), (! nose[986..986]), (! nose[985..985]), (! nose[984..984]), (! nose[983..983]), (! nose[982..982]), (! nose[981..981]), (! nose[980..980]), (! nose[979..979]), (! nose[978..978]), (! nose[977..977]), (! nose[976..976]), (! nose[975..975]), (! nose[974..974]), (! nose[973..973]), (! nose[972..972]), (! nose[971..971]), (! nose[970..970]), (! nose[969..969]), (! nose[968..968]), (! nose[967..967]), (! nose[966..966]), ((! nose[965..965]) # sel[185..185]), ((! nose[964..964]) # sel[184..184]), ((! nose[963..963]) # sel[183..183]), ((! nose[962..962]) # sel[182..182]), ((! nose[961..961]) # sel[181..181]), ((! nose[960..960]) # sel[180..180]), (! nose[959..959]), (! nose[958..958]), (! nose[957..957]), (! nose[956..956]), (! nose[955..955]), (! nose[954..954]), (! nose[953..953]), (! nose[952..952]), (! nose[951..951]), (! nose[950..950]), (! nose[949..949]), (! nose[948..948]), (! nose[947..947]), (! nose[946..946]), (! nose[945..945]), (! nose[944..944]), (! nose[943..943]), (! nose[942..942]), (! nose[941..941]), (! nose[940..940]), (! nose[939..939]), (! nose[938..938]), (! nose[937..937]), (! nose[936..936]), (! nose[935..935]), (! nose[934..934]), ((! nose[933..933]) # sel[179..179]), ((! nose[932..932]) # sel[178..178]), ((! nose[931..931]) # sel[177..177]), ((! nose[930..930]) # sel[176..176]), ((! nose[929..929]) # sel[175..175]), ((! nose[928..928]) # sel[174..174]), (! nose[927..927]), (! nose[926..926]), (! nose[925..925]), (! nose[924..924]), (! nose[923..923]), (! nose[922..922]), (! nose[921..921]), (! nose[920..920]), (! nose[919..919]), (! nose[918..918]), (! nose[917..917]), (! nose[916..916]), (! nose[915..915]), (! nose[914..914]), (! nose[913..913]), (! nose[912..912]), (! nose[911..911]), (! nose[910..910]), (! nose[909..909]), (! nose[908..908]), (! nose[907..907]), (! nose[906..906]), (! nose[905..905]), (! nose[904..904]), (! nose[903..903]), (! nose[902..902]), ((! nose[901..901]) # sel[173..173]), ((! nose[900..900]) # sel[172..172]), ((! nose[899..899]) # sel[171..171]), ((! nose[898..898]) # sel[170..170]), ((! nose[897..897]) # sel[169..169]), ((! nose[896..896]) # sel[168..168]), (! nose[895..895]), (! nose[894..894]), (! nose[893..893]), (! nose[892..892]), (! nose[891..891]), (! nose[890..890]), (! nose[889..889]), (! nose[888..888]), (! nose[887..887]), (! nose[886..886]), (! nose[885..885]), (! nose[884..884]), (! nose[883..883]), (! nose[882..882]), (! nose[881..881]), (! nose[880..880]), (! nose[879..879]), (! nose[878..878]), (! nose[877..877]), (! nose[876..876]), (! nose[875..875]), (! nose[874..874]), (! nose[873..873]), (! nose[872..872]), (! nose[871..871]), (! nose[870..870]), ((! nose[869..869]) # sel[167..167]), ((! nose[868..868]) # sel[166..166]), ((! nose[867..867]) # sel[165..165]), ((! nose[866..866]) # sel[164..164]), ((! nose[865..865]) # sel[163..163]), ((! nose[864..864]) # sel[162..162]), (! nose[863..863]), (! nose[862..862]), (! nose[861..861]), (! nose[860..860]), (! nose[859..859]), (! nose[858..858]), (! nose[857..857]), (! nose[856..856]), (! nose[855..855]), (! nose[854..854]), (! nose[853..853]), (! nose[852..852]), (! nose[851..851]), (! nose[850..850]), (! nose[849..849]), (! nose[848..848]), (! nose[847..847]), (! nose[846..846]), (! nose[845..845]), (! nose[844..844]), (! nose[843..843]), (! nose[842..842]), (! nose[841..841]), (! nose[840..840]), (! nose[839..839]), (! nose[838..838]), ((! nose[837..837]) # sel[161..161]), ((! nose[836..836]) # sel[160..160]), ((! nose[835..835]) # sel[159..159]), ((! nose[834..834]) # sel[158..158]), ((! nose[833..833]) # sel[157..157]), ((! nose[832..832]) # sel[156..156]), (! nose[831..831]), (! nose[830..830]), (! nose[829..829]), (! nose[828..828]), (! nose[827..827]), (! nose[826..826]), (! nose[825..825]), (! nose[824..824]), (! nose[823..823]), (! nose[822..822]), (! nose[821..821]), (! nose[820..820]), (! nose[819..819]), (! nose[818..818]), (! nose[817..817]), (! nose[816..816]), (! nose[815..815]), (! nose[814..814]), (! nose[813..813]), (! nose[812..812]), (! nose[811..811]), (! nose[810..810]), (! nose[809..809]), (! nose[808..808]), (! nose[807..807]), (! nose[806..806]), ((! nose[805..805]) # sel[155..155]), ((! nose[804..804]) # sel[154..154]), ((! nose[803..803]) # sel[153..153]), ((! nose[802..802]) # sel[152..152]), ((! nose[801..801]) # sel[151..151]), ((! nose[800..800]) # sel[150..150]), (! nose[799..799]), (! nose[798..798]), (! nose[797..797]), (! nose[796..796]), (! nose[795..795]), (! nose[794..794]), (! nose[793..793]), (! nose[792..792]), (! nose[791..791]), (! nose[790..790]), (! nose[789..789]), (! nose[788..788]), (! nose[787..787]), (! nose[786..786]), (! nose[785..785]), (! nose[784..784]), (! nose[783..783]), (! nose[782..782]), (! nose[781..781]), (! nose[780..780]), (! nose[779..779]), (! nose[778..778]), (! nose[777..777]), (! nose[776..776]), (! nose[775..775]), (! nose[774..774]), ((! nose[773..773]) # sel[149..149]), ((! nose[772..772]) # sel[148..148]), ((! nose[771..771]) # sel[147..147]), ((! nose[770..770]) # sel[146..146]), ((! nose[769..769]) # sel[145..145]), ((! nose[768..768]) # sel[144..144]), (! nose[767..767]), (! nose[766..766]), (! nose[765..765]), (! nose[764..764]), (! nose[763..763]), (! nose[762..762]), (! nose[761..761]), (! nose[760..760]), (! nose[759..759]), (! nose[758..758]), (! nose[757..757]), (! nose[756..756]), (! nose[755..755]), (! nose[754..754]), (! nose[753..753]), (! nose[752..752]), (! nose[751..751]), (! nose[750..750]), (! nose[749..749]), (! nose[748..748]), (! nose[747..747]), (! nose[746..746]), (! nose[745..745]), (! nose[744..744]), (! nose[743..743]), (! nose[742..742]), ((! nose[741..741]) # sel[143..143]), ((! nose[740..740]) # sel[142..142]), ((! nose[739..739]) # sel[141..141]), ((! nose[738..738]) # sel[140..140]), ((! nose[737..737]) # sel[139..139]), ((! nose[736..736]) # sel[138..138]), (! nose[735..735]), (! nose[734..734]), (! nose[733..733]), (! nose[732..732]), (! nose[731..731]), (! nose[730..730]), (! nose[729..729]), (! nose[728..728]), (! nose[727..727]), (! nose[726..726]), (! nose[725..725]), (! nose[724..724]), (! nose[723..723]), (! nose[722..722]), (! nose[721..721]), (! nose[720..720]), (! nose[719..719]), (! nose[718..718]), (! nose[717..717]), (! nose[716..716]), (! nose[715..715]), (! nose[714..714]), (! nose[713..713]), (! nose[712..712]), (! nose[711..711]), (! nose[710..710]), ((! nose[709..709]) # sel[137..137]), ((! nose[708..708]) # sel[136..136]), ((! nose[707..707]) # sel[135..135]), ((! nose[706..706]) # sel[134..134]), ((! nose[705..705]) # sel[133..133]), ((! nose[704..704]) # sel[132..132]), (! nose[703..703]), (! nose[702..702]), (! nose[701..701]), (! nose[700..700]), (! nose[699..699]), (! nose[698..698]), (! nose[697..697]), (! nose[696..696]), (! nose[695..695]), (! nose[694..694]), (! nose[693..693]), (! nose[692..692]), (! nose[691..691]), (! nose[690..690]), (! nose[689..689]), (! nose[688..688]), (! nose[687..687]), (! nose[686..686]), (! nose[685..685]), (! nose[684..684]), (! nose[683..683]), (! nose[682..682]), (! nose[681..681]), (! nose[680..680]), (! nose[679..679]), (! nose[678..678]), ((! nose[677..677]) # sel[131..131]), ((! nose[676..676]) # sel[130..130]), ((! nose[675..675]) # sel[129..129]), ((! nose[674..674]) # sel[128..128]), ((! nose[673..673]) # sel[127..127]), ((! nose[672..672]) # sel[126..126]), (! nose[671..671]), (! nose[670..670]), (! nose[669..669]), (! nose[668..668]), (! nose[667..667]), (! nose[666..666]), (! nose[665..665]), (! nose[664..664]), (! nose[663..663]), (! nose[662..662]), (! nose[661..661]), (! nose[660..660]), (! nose[659..659]), (! nose[658..658]), (! nose[657..657]), (! nose[656..656]), (! nose[655..655]), (! nose[654..654]), (! nose[653..653]), (! nose[652..652]), (! nose[651..651]), (! nose[650..650]), (! nose[649..649]), (! nose[648..648]), (! nose[647..647]), (! nose[646..646]), ((! nose[645..645]) # sel[125..125]), ((! nose[644..644]) # sel[124..124]), ((! nose[643..643]) # sel[123..123]), ((! nose[642..642]) # sel[122..122]), ((! nose[641..641]) # sel[121..121]), ((! nose[640..640]) # sel[120..120]), (! nose[639..639]), (! nose[638..638]), (! nose[637..637]), (! nose[636..636]), (! nose[635..635]), (! nose[634..634]), (! nose[633..633]), (! nose[632..632]), (! nose[631..631]), (! nose[630..630]), (! nose[629..629]), (! nose[628..628]), (! nose[627..627]), (! nose[626..626]), (! nose[625..625]), (! nose[624..624]), (! nose[623..623]), (! nose[622..622]), (! nose[621..621]), (! nose[620..620]), (! nose[619..619]), (! nose[618..618]), (! nose[617..617]), (! nose[616..616]), (! nose[615..615]), (! nose[614..614]), ((! nose[613..613]) # sel[119..119]), ((! nose[612..612]) # sel[118..118]), ((! nose[611..611]) # sel[117..117]), ((! nose[610..610]) # sel[116..116]), ((! nose[609..609]) # sel[115..115]), ((! nose[608..608]) # sel[114..114]), (! nose[607..607]), (! nose[606..606]), (! nose[605..605]), (! nose[604..604]), (! nose[603..603]), (! nose[602..602]), (! nose[601..601]), (! nose[600..600]), (! nose[599..599]), (! nose[598..598]), (! nose[597..597]), (! nose[596..596]), (! nose[595..595]), (! nose[594..594]), (! nose[593..593]), (! nose[592..592]), (! nose[591..591]), (! nose[590..590]), (! nose[589..589]), (! nose[588..588]), (! nose[587..587]), (! nose[586..586]), (! nose[585..585]), (! nose[584..584]), (! nose[583..583]), (! nose[582..582]), ((! nose[581..581]) # sel[113..113]), ((! nose[580..580]) # sel[112..112]), ((! nose[579..579]) # sel[111..111]), ((! nose[578..578]) # sel[110..110]), ((! nose[577..577]) # sel[109..109]), ((! nose[576..576]) # sel[108..108]), (! nose[575..575]), (! nose[574..574]), (! nose[573..573]), (! nose[572..572]), (! nose[571..571]), (! nose[570..570]), (! nose[569..569]), (! nose[568..568]), (! nose[567..567]), (! nose[566..566]), (! nose[565..565]), (! nose[564..564]), (! nose[563..563]), (! nose[562..562]), (! nose[561..561]), (! nose[560..560]), (! nose[559..559]), (! nose[558..558]), (! nose[557..557]), (! nose[556..556]), (! nose[555..555]), (! nose[554..554]), (! nose[553..553]), (! nose[552..552]), (! nose[551..551]), (! nose[550..550]), ((! nose[549..549]) # sel[107..107]), ((! nose[548..548]) # sel[106..106]), ((! nose[547..547]) # sel[105..105]), ((! nose[546..546]) # sel[104..104]), ((! nose[545..545]) # sel[103..103]), ((! nose[544..544]) # sel[102..102]), (! nose[543..543]), (! nose[542..542]), (! nose[541..541]), (! nose[540..540]), (! nose[539..539]), (! nose[538..538]), (! nose[537..537]), (! nose[536..536]), (! nose[535..535]), (! nose[534..534]), (! nose[533..533]), (! nose[532..532]), (! nose[531..531]), (! nose[530..530]), (! nose[529..529]), (! nose[528..528]), (! nose[527..527]), (! nose[526..526]), (! nose[525..525]), (! nose[524..524]), (! nose[523..523]), (! nose[522..522]), (! nose[521..521]), (! nose[520..520]), (! nose[519..519]), (! nose[518..518]), ((! nose[517..517]) # sel[101..101]), ((! nose[516..516]) # sel[100..100]), ((! nose[515..515]) # sel[99..99]), ((! nose[514..514]) # sel[98..98]), ((! nose[513..513]) # sel[97..97]), ((! nose[512..512]) # sel[96..96]), (! nose[511..511]), (! nose[510..510]), (! nose[509..509]), (! nose[508..508]), (! nose[507..507]), (! nose[506..506]), (! nose[505..505]), (! nose[504..504]), (! nose[503..503]), (! nose[502..502]), (! nose[501..501]), (! nose[500..500]), (! nose[499..499]), (! nose[498..498]), (! nose[497..497]), (! nose[496..496]), (! nose[495..495]), (! nose[494..494]), (! nose[493..493]), (! nose[492..492]), (! nose[491..491]), (! nose[490..490]), (! nose[489..489]), (! nose[488..488]), (! nose[487..487]), (! nose[486..486]), ((! nose[485..485]) # sel[95..95]), ((! nose[484..484]) # sel[94..94]), ((! nose[483..483]) # sel[93..93]), ((! nose[482..482]) # sel[92..92]), ((! nose[481..481]) # sel[91..91]), ((! nose[480..480]) # sel[90..90]), (! nose[479..479]), (! nose[478..478]), (! nose[477..477]), (! nose[476..476]), (! nose[475..475]), (! nose[474..474]), (! nose[473..473]), (! nose[472..472]), (! nose[471..471]), (! nose[470..470]), (! nose[469..469]), (! nose[468..468]), (! nose[467..467]), (! nose[466..466]), (! nose[465..465]), (! nose[464..464]), (! nose[463..463]), (! nose[462..462]), (! nose[461..461]), (! nose[460..460]), (! nose[459..459]), (! nose[458..458]), (! nose[457..457]), (! nose[456..456]), (! nose[455..455]), (! nose[454..454]), ((! nose[453..453]) # sel[89..89]), ((! nose[452..452]) # sel[88..88]), ((! nose[451..451]) # sel[87..87]), ((! nose[450..450]) # sel[86..86]), ((! nose[449..449]) # sel[85..85]), ((! nose[448..448]) # sel[84..84]), (! nose[447..447]), (! nose[446..446]), (! nose[445..445]), (! nose[444..444]), (! nose[443..443]), (! nose[442..442]), (! nose[441..441]), (! nose[440..440]), (! nose[439..439]), (! nose[438..438]), (! nose[437..437]), (! nose[436..436]), (! nose[435..435]), (! nose[434..434]), (! nose[433..433]), (! nose[432..432]), (! nose[431..431]), (! nose[430..430]), (! nose[429..429]), (! nose[428..428]), (! nose[427..427]), (! nose[426..426]), (! nose[425..425]), (! nose[424..424]), (! nose[423..423]), (! nose[422..422]), ((! nose[421..421]) # sel[83..83]), ((! nose[420..420]) # sel[82..82]), ((! nose[419..419]) # sel[81..81]), ((! nose[418..418]) # sel[80..80]), ((! nose[417..417]) # sel[79..79]), ((! nose[416..416]) # sel[78..78]), (! nose[415..415]), (! nose[414..414]), (! nose[413..413]), (! nose[412..412]), (! nose[411..411]), (! nose[410..410]), (! nose[409..409]), (! nose[408..408]), (! nose[407..407]), (! nose[406..406]), (! nose[405..405]), (! nose[404..404]), (! nose[403..403]), (! nose[402..402]), (! nose[401..401]), (! nose[400..400]), (! nose[399..399]), (! nose[398..398]), (! nose[397..397]), (! nose[396..396]), (! nose[395..395]), (! nose[394..394]), (! nose[393..393]), (! nose[392..392]), (! nose[391..391]), (! nose[390..390]), ((! nose[389..389]) # sel[77..77]), ((! nose[388..388]) # sel[76..76]), ((! nose[387..387]) # sel[75..75]), ((! nose[386..386]) # sel[74..74]), ((! nose[385..385]) # sel[73..73]), ((! nose[384..384]) # sel[72..72]), (! nose[383..383]), (! nose[382..382]), (! nose[381..381]), (! nose[380..380]), (! nose[379..379]), (! nose[378..378]), (! nose[377..377]), (! nose[376..376]), (! nose[375..375]), (! nose[374..374]), (! nose[373..373]), (! nose[372..372]), (! nose[371..371]), (! nose[370..370]), (! nose[369..369]), (! nose[368..368]), (! nose[367..367]), (! nose[366..366]), (! nose[365..365]), (! nose[364..364]), (! nose[363..363]), (! nose[362..362]), (! nose[361..361]), (! nose[360..360]), (! nose[359..359]), (! nose[358..358]), ((! nose[357..357]) # sel[71..71]), ((! nose[356..356]) # sel[70..70]), ((! nose[355..355]) # sel[69..69]), ((! nose[354..354]) # sel[68..68]), ((! nose[353..353]) # sel[67..67]), ((! nose[352..352]) # sel[66..66]), (! nose[351..351]), (! nose[350..350]), (! nose[349..349]), (! nose[348..348]), (! nose[347..347]), (! nose[346..346]), (! nose[345..345]), (! nose[344..344]), (! nose[343..343]), (! nose[342..342]), (! nose[341..341]), (! nose[340..340]), (! nose[339..339]), (! nose[338..338]), (! nose[337..337]), (! nose[336..336]), (! nose[335..335]), (! nose[334..334]), (! nose[333..333]), (! nose[332..332]), (! nose[331..331]), (! nose[330..330]), (! nose[329..329]), (! nose[328..328]), (! nose[327..327]), (! nose[326..326]), ((! nose[325..325]) # sel[65..65]), ((! nose[324..324]) # sel[64..64]), ((! nose[323..323]) # sel[63..63]), ((! nose[322..322]) # sel[62..62]), ((! nose[321..321]) # sel[61..61]), ((! nose[320..320]) # sel[60..60]), (! nose[319..319]), (! nose[318..318]), (! nose[317..317]), (! nose[316..316]), (! nose[315..315]), (! nose[314..314]), (! nose[313..313]), (! nose[312..312]), (! nose[311..311]), (! nose[310..310]), (! nose[309..309]), (! nose[308..308]), (! nose[307..307]), (! nose[306..306]), (! nose[305..305]), (! nose[304..304]), (! nose[303..303]), (! nose[302..302]), (! nose[301..301]), (! nose[300..300]), (! nose[299..299]), (! nose[298..298]), (! nose[297..297]), (! nose[296..296]), (! nose[295..295]), (! nose[294..294]), ((! nose[293..293]) # sel[59..59]), ((! nose[292..292]) # sel[58..58]), ((! nose[291..291]) # sel[57..57]), ((! nose[290..290]) # sel[56..56]), ((! nose[289..289]) # sel[55..55]), ((! nose[288..288]) # sel[54..54]), (! nose[287..287]), (! nose[286..286]), (! nose[285..285]), (! nose[284..284]), (! nose[283..283]), (! nose[282..282]), (! nose[281..281]), (! nose[280..280]), (! nose[279..279]), (! nose[278..278]), (! nose[277..277]), (! nose[276..276]), (! nose[275..275]), (! nose[274..274]), (! nose[273..273]), (! nose[272..272]), (! nose[271..271]), (! nose[270..270]), (! nose[269..269]), (! nose[268..268]), (! nose[267..267]), (! nose[266..266]), (! nose[265..265]), (! nose[264..264]), (! nose[263..263]), (! nose[262..262]), ((! nose[261..261]) # sel[53..53]), ((! nose[260..260]) # sel[52..52]), ((! nose[259..259]) # sel[51..51]), ((! nose[258..258]) # sel[50..50]), ((! nose[257..257]) # sel[49..49]), ((! nose[256..256]) # sel[48..48]), (! nose[255..255]), (! nose[254..254]), (! nose[253..253]), (! nose[252..252]), (! nose[251..251]), (! nose[250..250]), (! nose[249..249]), (! nose[248..248]), (! nose[247..247]), (! nose[246..246]), (! nose[245..245]), (! nose[244..244]), (! nose[243..243]), (! nose[242..242]), (! nose[241..241]), (! nose[240..240]), (! nose[239..239]), (! nose[238..238]), (! nose[237..237]), (! nose[236..236]), (! nose[235..235]), (! nose[234..234]), (! nose[233..233]), (! nose[232..232]), (! nose[231..231]), (! nose[230..230]), ((! nose[229..229]) # sel[47..47]), ((! nose[228..228]) # sel[46..46]), ((! nose[227..227]) # sel[45..45]), ((! nose[226..226]) # sel[44..44]), ((! nose[225..225]) # sel[43..43]), ((! nose[224..224]) # sel[42..42]), (! nose[223..223]), (! nose[222..222]), (! nose[221..221]), (! nose[220..220]), (! nose[219..219]), (! nose[218..218]), (! nose[217..217]), (! nose[216..216]), (! nose[215..215]), (! nose[214..214]), (! nose[213..213]), (! nose[212..212]), (! nose[211..211]), (! nose[210..210]), (! nose[209..209]), (! nose[208..208]), (! nose[207..207]), (! nose[206..206]), (! nose[205..205]), (! nose[204..204]), (! nose[203..203]), (! nose[202..202]), (! nose[201..201]), (! nose[200..200]), (! nose[199..199]), (! nose[198..198]), ((! nose[197..197]) # sel[41..41]), ((! nose[196..196]) # sel[40..40]), ((! nose[195..195]) # sel[39..39]), ((! nose[194..194]) # sel[38..38]), ((! nose[193..193]) # sel[37..37]), ((! nose[192..192]) # sel[36..36]), (! nose[191..191]), (! nose[190..190]), (! nose[189..189]), (! nose[188..188]), (! nose[187..187]), (! nose[186..186]), (! nose[185..185]), (! nose[184..184]), (! nose[183..183]), (! nose[182..182]), (! nose[181..181]), (! nose[180..180]), (! nose[179..179]), (! nose[178..178]), (! nose[177..177]), (! nose[176..176]), (! nose[175..175]), (! nose[174..174]), (! nose[173..173]), (! nose[172..172]), (! nose[171..171]), (! nose[170..170]), (! nose[169..169]), (! nose[168..168]), (! nose[167..167]), (! nose[166..166]), ((! nose[165..165]) # sel[35..35]), ((! nose[164..164]) # sel[34..34]), ((! nose[163..163]) # sel[33..33]), ((! nose[162..162]) # sel[32..32]), ((! nose[161..161]) # sel[31..31]), ((! nose[160..160]) # sel[30..30]), (! nose[159..159]), (! nose[158..158]), (! nose[157..157]), (! nose[156..156]), (! nose[155..155]), (! nose[154..154]), (! nose[153..153]), (! nose[152..152]), (! nose[151..151]), (! nose[150..150]), (! nose[149..149]), (! nose[148..148]), (! nose[147..147]), (! nose[146..146]), (! nose[145..145]), (! nose[144..144]), (! nose[143..143]), (! nose[142..142]), (! nose[141..141]), (! nose[140..140]), (! nose[139..139]), (! nose[138..138]), (! nose[137..137]), (! nose[136..136]), (! nose[135..135]), (! nose[134..134]), ((! nose[133..133]) # sel[29..29]), ((! nose[132..132]) # sel[28..28]), ((! nose[131..131]) # sel[27..27]), ((! nose[130..130]) # sel[26..26]), ((! nose[129..129]) # sel[25..25]), ((! nose[128..128]) # sel[24..24]), (! nose[127..127]), (! nose[126..126]), (! nose[125..125]), (! nose[124..124]), (! nose[123..123]), (! nose[122..122]), (! nose[121..121]), (! nose[120..120]), (! nose[119..119]), (! nose[118..118]), (! nose[117..117]), (! nose[116..116]), (! nose[115..115]), (! nose[114..114]), (! nose[113..113]), (! nose[112..112]), (! nose[111..111]), (! nose[110..110]), (! nose[109..109]), (! nose[108..108]), (! nose[107..107]), (! nose[106..106]), (! nose[105..105]), (! nose[104..104]), (! nose[103..103]), (! nose[102..102]), ((! nose[101..101]) # sel[23..23]), ((! nose[100..100]) # sel[22..22]), ((! nose[99..99]) # sel[21..21]), ((! nose[98..98]) # sel[20..20]), ((! nose[97..97]) # sel[19..19]), ((! nose[96..96]) # sel[18..18]), (! nose[95..95]), (! nose[94..94]), (! nose[93..93]), (! nose[92..92]), (! nose[91..91]), (! nose[90..90]), (! nose[89..89]), (! nose[88..88]), (! nose[87..87]), (! nose[86..86]), (! nose[85..85]), (! nose[84..84]), (! nose[83..83]), (! nose[82..82]), (! nose[81..81]), (! nose[80..80]), (! nose[79..79]), (! nose[78..78]), (! nose[77..77]), (! nose[76..76]), (! nose[75..75]), (! nose[74..74]), (! nose[73..73]), (! nose[72..72]), (! nose[71..71]), (! nose[70..70]), ((! nose[69..69]) # sel[17..17]), ((! nose[68..68]) # sel[16..16]), ((! nose[67..67]) # sel[15..15]), ((! nose[66..66]) # sel[14..14]), ((! nose[65..65]) # sel[13..13]), ((! nose[64..64]) # sel[12..12]), (! nose[63..63]), (! nose[62..62]), (! nose[61..61]), (! nose[60..60]), (! nose[59..59]), (! nose[58..58]), (! nose[57..57]), (! nose[56..56]), (! nose[55..55]), (! nose[54..54]), (! nose[53..53]), (! nose[52..52]), (! nose[51..51]), (! nose[50..50]), (! nose[49..49]), (! nose[48..48]), (! nose[47..47]), (! nose[46..46]), (! nose[45..45]), (! nose[44..44]), (! nose[43..43]), (! nose[42..42]), (! nose[41..41]), (! nose[40..40]), (! nose[39..39]), (! nose[38..38]), ((! nose[37..37]) # sel[11..11]), ((! nose[36..36]) # sel[10..10]), ((! nose[35..35]) # sel[9..9]), ((! nose[34..34]) # sel[8..8]), ((! nose[33..33]) # sel[7..7]), ((! nose[32..32]) # sel[6..6]), (! nose[31..31]), (! nose[30..30]), (! nose[29..29]), (! nose[28..28]), (! nose[27..27]), (! nose[26..26]), (! nose[25..25]), (! nose[24..24]), (! nose[23..23]), (! nose[22..22]), (! nose[21..21]), (! nose[20..20]), (! nose[19..19]), (! nose[18..18]), (! nose[17..17]), (! nose[16..16]), (! nose[15..15]), (! nose[14..14]), (! nose[13..13]), (! nose[12..12]), (! nose[11..11]), (! nose[10..10]), (! nose[9..9]), (! nose[8..8]), (! nose[7..7]), (! nose[6..6]), ((! nose[5..5]) # sel[5..5]), ((! nose[4..4]) # sel[4..4]), ((! nose[3..3]) # sel[3..3]), ((! nose[2..2]) # sel[2..2]), ((! nose[1..1]) # sel[1..1]), ((! nose[0..0]) # sel[0..0]));
+ StageIn[] = StageIn_tmp[];
+ StageIn_tmp[] = ( StageOut[223..0], B"0000000");
+ StageOut[] = ( ((( StageIn[222..217], NumeratorIn[992..992]) & selnose[1023..1023]) # (prestg[223..217] & (! selnose[1023..1023]))), ((( StageIn[215..210], NumeratorIn[961..961]) & selnose[990..990]) # (prestg[216..210] & (! selnose[990..990]))), ((( StageIn[208..203], NumeratorIn[930..930]) & selnose[957..957]) # (prestg[209..203] & (! selnose[957..957]))), ((( StageIn[201..196], NumeratorIn[899..899]) & selnose[924..924]) # (prestg[202..196] & (! selnose[924..924]))), ((( StageIn[194..189], NumeratorIn[868..868]) & selnose[891..891]) # (prestg[195..189] & (! selnose[891..891]))), ((( StageIn[187..182], NumeratorIn[837..837]) & selnose[858..858]) # (prestg[188..182] & (! selnose[858..858]))), ((( StageIn[180..175], NumeratorIn[806..806]) & selnose[825..825]) # (prestg[181..175] & (! selnose[825..825]))), ((( StageIn[173..168], NumeratorIn[775..775]) & selnose[792..792]) # (prestg[174..168] & (! selnose[792..792]))), ((( StageIn[166..161], NumeratorIn[744..744]) & selnose[759..759]) # (prestg[167..161] & (! selnose[759..759]))), ((( StageIn[159..154], NumeratorIn[713..713]) & selnose[726..726]) # (prestg[160..154] & (! selnose[726..726]))), ((( StageIn[152..147], NumeratorIn[682..682]) & selnose[693..693]) # (prestg[153..147] & (! selnose[693..693]))), ((( StageIn[145..140], NumeratorIn[651..651]) & selnose[660..660]) # (prestg[146..140] & (! selnose[660..660]))), ((( StageIn[138..133], NumeratorIn[620..620]) & selnose[627..627]) # (prestg[139..133] & (! selnose[627..627]))), ((( StageIn[131..126], NumeratorIn[589..589]) & selnose[594..594]) # (prestg[132..126] & (! selnose[594..594]))), ((( StageIn[124..119], NumeratorIn[558..558]) & selnose[561..561]) # (prestg[125..119] & (! selnose[561..561]))), ((( StageIn[117..112], NumeratorIn[527..527]) & selnose[528..528]) # (prestg[118..112] & (! selnose[528..528]))), ((( StageIn[110..105], NumeratorIn[496..496]) & selnose[495..495]) # (prestg[111..105] & (! selnose[495..495]))), ((( StageIn[103..98], NumeratorIn[465..465]) & selnose[462..462]) # (prestg[104..98] & (! selnose[462..462]))), ((( StageIn[96..91], NumeratorIn[434..434]) & selnose[429..429]) # (prestg[97..91] & (! selnose[429..429]))), ((( StageIn[89..84], NumeratorIn[403..403]) & selnose[396..396]) # (prestg[90..84] & (! selnose[396..396]))), ((( StageIn[82..77], NumeratorIn[372..372]) & selnose[363..363]) # (prestg[83..77] & (! selnose[363..363]))), ((( StageIn[75..70], NumeratorIn[341..341]) & selnose[330..330]) # (prestg[76..70] & (! selnose[330..330]))), ((( StageIn[68..63], NumeratorIn[310..310]) & selnose[297..297]) # (prestg[69..63] & (! selnose[297..297]))), ((( StageIn[61..56], NumeratorIn[279..279]) & selnose[264..264]) # (prestg[62..56] & (! selnose[264..264]))), ((( StageIn[54..49], NumeratorIn[248..248]) & selnose[231..231]) # (prestg[55..49] & (! selnose[231..231]))), ((( StageIn[47..42], NumeratorIn[217..217]) & selnose[198..198]) # (prestg[48..42] & (! selnose[198..198]))), ((( StageIn[40..35], NumeratorIn[186..186]) & selnose[165..165]) # (prestg[41..35] & (! selnose[165..165]))), ((( StageIn[33..28], NumeratorIn[155..155]) & selnose[132..132]) # (prestg[34..28] & (! selnose[132..132]))), ((( StageIn[26..21], NumeratorIn[124..124]) & selnose[99..99]) # (prestg[27..21] & (! selnose[99..99]))), ((( StageIn[19..14], NumeratorIn[93..93]) & selnose[66..66]) # (prestg[20..14] & (! selnose[66..66]))), ((( StageIn[12..7], NumeratorIn[62..62]) & selnose[33..33]) # (prestg[13..7] & (! selnose[33..33]))), ((( StageIn[5..0], NumeratorIn[31..31]) & selnose[0..0]) # (prestg[6..0] & (! selnose[0..0]))));
+END;
+--VALID FILE
diff --git a/db/logic_util_heursitic.dat b/db/logic_util_heursitic.dat
new file mode 100644
index 0000000..e6824aa
Binary files /dev/null and b/db/logic_util_heursitic.dat differ
diff --git a/db/lpm_abs_0s9.tdf b/db/lpm_abs_0s9.tdf
new file mode 100644
index 0000000..e9632a5
--- /dev/null
+++ b/db/lpm_abs_0s9.tdf
@@ -0,0 +1,41 @@
+--lpm_abs CARRY_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone II" IGNORE_CARRY_BUFFERS="OFF" LPM_WIDTH=32 data result
+--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2009 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+
+FUNCTION carry_sum (cin, sin)
+RETURNS ( cout, sout);
+
+--synthesis_resources = lut 32
+SUBDESIGN lpm_abs_0s9
+(
+ data[31..0] : input;
+ overflow : output;
+ result[31..0] : output;
+)
+VARIABLE
+ cs2a[31..0] : carry_sum;
+ result_tmp[31..0] : WIRE;
+
+BEGIN
+ cs2a[].cin = ( ((data[31..31] $ data[31..1]) & cs2a[30..0].cout), ((! data[0..0]) & data[31..31]));
+ cs2a[].sin = ( ((data[31..31] $ data[31..1]) $ cs2a[30..0].cout), data[0..0]);
+ overflow = (result_tmp[31..31] & data[31..31]);
+ result[] = result_tmp[];
+ result_tmp[] = ( cs2a[31..1].sout, data[0..0]);
+END;
+--VALID FILE
diff --git a/db/lpm_abs_gq9.tdf b/db/lpm_abs_gq9.tdf
new file mode 100644
index 0000000..db4c9bc
--- /dev/null
+++ b/db/lpm_abs_gq9.tdf
@@ -0,0 +1,41 @@
+--lpm_abs CARRY_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone II" IGNORE_CARRY_BUFFERS="OFF" LPM_WIDTH=5 data result
+--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2009 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+
+FUNCTION carry_sum (cin, sin)
+RETURNS ( cout, sout);
+
+--synthesis_resources = lut 5
+SUBDESIGN lpm_abs_gq9
+(
+ data[4..0] : input;
+ overflow : output;
+ result[4..0] : output;
+)
+VARIABLE
+ cs1a[4..0] : carry_sum;
+ result_tmp[4..0] : WIRE;
+
+BEGIN
+ cs1a[].cin = ( ((data[4..4] $ data[4..1]) & cs1a[3..0].cout), ((! data[0..0]) & data[4..4]));
+ cs1a[].sin = ( ((data[4..4] $ data[4..1]) $ cs1a[3..0].cout), data[0..0]);
+ overflow = (result_tmp[4..4] & data[4..4]);
+ result[] = result_tmp[];
+ result_tmp[] = ( cs1a[4..1].sout, data[0..0]);
+END;
+--VALID FILE
diff --git a/db/lpm_abs_hq9.tdf b/db/lpm_abs_hq9.tdf
new file mode 100644
index 0000000..aa4f21b
--- /dev/null
+++ b/db/lpm_abs_hq9.tdf
@@ -0,0 +1,41 @@
+--lpm_abs CARRY_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone II" IGNORE_CARRY_BUFFERS="OFF" LPM_WIDTH=6 data result
+--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2009 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+
+FUNCTION carry_sum (cin, sin)
+RETURNS ( cout, sout);
+
+--synthesis_resources = lut 6
+SUBDESIGN lpm_abs_hq9
+(
+ data[5..0] : input;
+ overflow : output;
+ result[5..0] : output;
+)
+VARIABLE
+ cs1a[5..0] : carry_sum;
+ result_tmp[5..0] : WIRE;
+
+BEGIN
+ cs1a[].cin = ( ((data[5..5] $ data[5..1]) & cs1a[4..0].cout), ((! data[0..0]) & data[5..5]));
+ cs1a[].sin = ( ((data[5..5] $ data[5..1]) $ cs1a[4..0].cout), data[0..0]);
+ overflow = (result_tmp[5..5] & data[5..5]);
+ result[] = result_tmp[];
+ result_tmp[] = ( cs1a[5..1].sout, data[0..0]);
+END;
+--VALID FILE
diff --git a/db/lpm_divide_7so.tdf b/db/lpm_divide_7so.tdf
new file mode 100644
index 0000000..01872c3
--- /dev/null
+++ b/db/lpm_divide_7so.tdf
@@ -0,0 +1,42 @@
+--lpm_divide DEVICE_FAMILY="Cyclone II" LPM_DREPRESENTATION="SIGNED" LPM_NREPRESENTATION="SIGNED" LPM_REMAINDERPOSITIVE="FALSE" LPM_WIDTHD=5 LPM_WIDTHN=32 OPTIMIZE_FOR_SPEED=5 denom numer quotient CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
+--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_lpm_divide 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2009 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+
+FUNCTION abs_divider_kbg (denominator[4..0], numerator[31..0])
+RETURNS ( quotient[31..0], remainder[4..0]);
+
+--synthesis_resources =
+SUBDESIGN lpm_divide_7so
+(
+ denom[4..0] : input;
+ numer[31..0] : input;
+ quotient[31..0] : output;
+ remain[4..0] : output;
+)
+VARIABLE
+ divider : abs_divider_kbg;
+ numer_tmp[31..0] : WIRE;
+
+BEGIN
+ divider.denominator[] = denom[];
+ divider.numerator[] = numer_tmp[];
+ numer_tmp[] = numer[];
+ quotient[] = divider.quotient[];
+ remain[] = divider.remainder[];
+END;
+--VALID FILE
diff --git a/db/lpm_divide_8so.tdf b/db/lpm_divide_8so.tdf
new file mode 100644
index 0000000..635e21e
--- /dev/null
+++ b/db/lpm_divide_8so.tdf
@@ -0,0 +1,42 @@
+--lpm_divide DEVICE_FAMILY="Cyclone II" LPM_DREPRESENTATION="SIGNED" LPM_NREPRESENTATION="SIGNED" LPM_REMAINDERPOSITIVE="FALSE" LPM_WIDTHD=6 LPM_WIDTHN=32 OPTIMIZE_FOR_SPEED=5 denom numer quotient CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
+--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_lpm_divide 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2009 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+
+FUNCTION abs_divider_lbg (denominator[5..0], numerator[31..0])
+RETURNS ( quotient[31..0], remainder[5..0]);
+
+--synthesis_resources = lut 306
+SUBDESIGN lpm_divide_8so
+(
+ denom[5..0] : input;
+ numer[31..0] : input;
+ quotient[31..0] : output;
+ remain[5..0] : output;
+)
+VARIABLE
+ divider : abs_divider_lbg;
+ numer_tmp[31..0] : WIRE;
+
+BEGIN
+ divider.denominator[] = denom[];
+ divider.numerator[] = numer_tmp[];
+ numer_tmp[] = numer[];
+ quotient[] = divider.quotient[];
+ remain[] = divider.remainder[];
+END;
+--VALID FILE
diff --git a/db/lpm_divide_ako.tdf b/db/lpm_divide_ako.tdf
new file mode 100644
index 0000000..f97a384
--- /dev/null
+++ b/db/lpm_divide_ako.tdf
@@ -0,0 +1,42 @@
+--lpm_divide DEVICE_FAMILY="Cyclone II" LPM_DREPRESENTATION="SIGNED" LPM_NREPRESENTATION="SIGNED" LPM_REMAINDERPOSITIVE="FALSE" LPM_WIDTHD=5 LPM_WIDTHN=32 OPTIMIZE_FOR_SPEED=5 denom numer remain CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
+--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_lpm_divide 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2009 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+
+FUNCTION abs_divider_kbg (denominator[4..0], numerator[31..0])
+RETURNS ( quotient[31..0], remainder[4..0]);
+
+--synthesis_resources = lut 246
+SUBDESIGN lpm_divide_ako
+(
+ denom[4..0] : input;
+ numer[31..0] : input;
+ quotient[31..0] : output;
+ remain[4..0] : output;
+)
+VARIABLE
+ divider : abs_divider_kbg;
+ numer_tmp[31..0] : WIRE;
+
+BEGIN
+ divider.denominator[] = denom[];
+ divider.numerator[] = numer_tmp[];
+ numer_tmp[] = numer[];
+ quotient[] = divider.quotient[];
+ remain[] = divider.remainder[];
+END;
+--VALID FILE
diff --git a/db/myArkanoid.(0).cnf.cdb b/db/myArkanoid.(0).cnf.cdb
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diff --git a/db/myArkanoid.(4).cnf.cdb b/db/myArkanoid.(4).cnf.cdb
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diff --git a/db/myArkanoid.(6).cnf.cdb b/db/myArkanoid.(6).cnf.cdb
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diff --git a/db/myArkanoid.analyze_file.qmsg b/db/myArkanoid.analyze_file.qmsg
new file mode 100644
index 0000000..7da24b5
--- /dev/null
+++ b/db/myArkanoid.analyze_file.qmsg
@@ -0,0 +1,5 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus II " "Info: Running Quartus II Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 27 20:01:25 2012 " "Info: Processing started: Sun May 27 20:01:25 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid --analyze_file=TotalScheme.bdf " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid --analyze_file=TotalScheme.bdf" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 0 s Quartus II " "Info: Quartus II Analyze Current File was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "188 " "Info: Peak virtual memory: 188 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 27 20:01:25 2012 " "Info: Processing ended: Sun May 27 20:01:25 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/db/myArkanoid.asm.qmsg b/db/myArkanoid.asm.qmsg
new file mode 100644
index 0000000..4cb387d
--- /dev/null
+++ b/db/myArkanoid.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 28 14:22:29 2012 " "Info: Processing started: Mon May 28 14:22:29 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "219 " "Info: Peak virtual memory: 219 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 28 14:22:31 2012 " "Info: Processing ended: Mon May 28 14:22:31 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/db/myArkanoid.asm.rdb b/db/myArkanoid.asm.rdb
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diff --git a/db/myArkanoid.asm_labs.ddb b/db/myArkanoid.asm_labs.ddb
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index 0000000..f9142cd
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diff --git a/db/myArkanoid.cbx.xml b/db/myArkanoid.cbx.xml
new file mode 100644
index 0000000..d0abf6b
--- /dev/null
+++ b/db/myArkanoid.cbx.xml
@@ -0,0 +1,11 @@
+
+
+
+
+
+
+
+
+
+
+
diff --git a/db/myArkanoid.cmp.bpm b/db/myArkanoid.cmp.bpm
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diff --git a/db/myArkanoid.cmp.cdb b/db/myArkanoid.cmp.cdb
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diff --git a/db/myArkanoid.cmp.ecobp b/db/myArkanoid.cmp.ecobp
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diff --git a/db/myArkanoid.cmp.hdb b/db/myArkanoid.cmp.hdb
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diff --git a/db/myArkanoid.cmp.kpt b/db/myArkanoid.cmp.kpt
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diff --git a/db/myArkanoid.cmp.logdb b/db/myArkanoid.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/db/myArkanoid.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/db/myArkanoid.cmp.rdb b/db/myArkanoid.cmp.rdb
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diff --git a/db/myArkanoid.cmp.tdb b/db/myArkanoid.cmp.tdb
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diff --git a/db/myArkanoid.cmp0.ddb b/db/myArkanoid.cmp0.ddb
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diff --git a/db/myArkanoid.cmp2.ddb b/db/myArkanoid.cmp2.ddb
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diff --git a/db/myArkanoid.cmp_merge.kpt b/db/myArkanoid.cmp_merge.kpt
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index 0000000..f4d2124
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diff --git a/db/myArkanoid.db_info b/db/myArkanoid.db_info
new file mode 100644
index 0000000..8395150
--- /dev/null
+++ b/db/myArkanoid.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 9.1 Build 222 10/21/2009 SJ Full Version
+Version_Index = 184606208
+Creation_Time = Tue May 22 14:45:50 2012
diff --git a/db/myArkanoid.eco.cdb b/db/myArkanoid.eco.cdb
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index 0000000..888c5b6
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diff --git a/db/myArkanoid.fit.qmsg b/db/myArkanoid.fit.qmsg
new file mode 100644
index 0000000..3693689
--- /dev/null
+++ b/db/myArkanoid.fit.qmsg
@@ -0,0 +1,38 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 28 14:21:59 2012 " "Info: Processing started: Mon May 28 14:21:59 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "IMPP_MPP_USER_DEVICE" "myArkanoid EP2C20F484C7 " "Info: Selected device EP2C20F484C7 for design \"myArkanoid\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C15AF484C7 " "Info: Device EP2C15AF484C7 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484C7 " "Info: Device EP2C35F484C7 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C7 " "Info: Device EP2C50F484C7 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ C4 " "Info: Pin ~ASDO~ is reserved at location C4" { } { { "c:/quartus/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/quartus/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/Verilog/Arkanoid2PDE1/" 0 { } { { 0 { 0 ""} 0 12665 3016 4146 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ C3 " "Info: Pin ~nCSO~ is reserved at location C3" { } { { "c:/quartus/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/quartus/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/Verilog/Arkanoid2PDE1/" 0 { } { { 0 { 0 ""} 0 12666 3016 4146 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS91p/nCEO~ W20 " "Info: Pin ~LVDS91p/nCEO~ is reserved at location W20" { } { { "c:/quartus/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/quartus/quartus/bin/pin_planner.ppl" { ~LVDS91p/nCEO~ } } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS91p/nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/Verilog/Arkanoid2PDE1/" 0 { } { { 0 { 0 ""} 0 12667 3016 4146 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
+{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Timing-driven compilation is using the Classic Timing Analyzer" { } { } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
+{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ClockDivider:inst1\|clk25MHz_ " "Info: Automatically promoted node ClockDivider:inst1\|clk25MHz_ " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ClockDivider:inst1\|clk25MHz_~0 " "Info: Destination node ClockDivider:inst1\|clk25MHz_~0" { } { { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { ClockDivider:inst1|clk25MHz_~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/Verilog/Arkanoid2PDE1/" 0 { } { { 0 { 0 ""} 0 12659 3016 4146 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1} } { { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { ClockDivider:inst1|clk25MHz_ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/Verilog/Arkanoid2PDE1/" 0 { } { { 0 { 0 ""} 0 19 3016 4146 0} } } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Info: Fitter preparation operations ending: elapsed time is 00:00:03" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Info: Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "139.129 ns register register " "Info: Estimated most critical path is register to register delay of 139.129 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Arkanoid:inst\|button2_state 1 REG LAB_X32_Y11 36 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X32_Y11; Fanout = 36; REG Node = 'Arkanoid:inst\|button2_state'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { Arkanoid:inst|button2_state } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 108 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.779 ns) + CELL(0.544 ns) 1.323 ns Arkanoid:inst\|platform2_position~4 2 COMB LAB_X33_Y13 73 " "Info: 2: + IC(0.779 ns) + CELL(0.544 ns) = 1.323 ns; Loc. = LAB_X33_Y13; Fanout = 73; COMB Node = 'Arkanoid:inst\|platform2_position~4'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.323 ns" { Arkanoid:inst|button2_state Arkanoid:inst|platform2_position~4 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.740 ns) + CELL(0.521 ns) 2.584 ns Arkanoid:inst\|platform2_position~5 3 COMB LAB_X33_Y15 63 " "Info: 3: + IC(0.740 ns) + CELL(0.521 ns) = 2.584 ns; Loc. = LAB_X33_Y15; Fanout = 63; COMB Node = 'Arkanoid:inst\|platform2_position~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.261 ns" { Arkanoid:inst|platform2_position~4 Arkanoid:inst|platform2_position~5 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.495 ns) 4.152 ns Arkanoid:inst\|Add4~1 4 COMB LAB_X32_Y16 2 " "Info: 4: + IC(1.073 ns) + CELL(0.495 ns) = 4.152 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.568 ns" { Arkanoid:inst|platform2_position~5 Arkanoid:inst|Add4~1 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.232 ns Arkanoid:inst\|Add4~3 5 COMB LAB_X32_Y16 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 4.232 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~1 Arkanoid:inst|Add4~3 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.312 ns Arkanoid:inst\|Add4~5 6 COMB LAB_X32_Y16 2 " "Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 4.312 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~3 Arkanoid:inst|Add4~5 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.392 ns Arkanoid:inst\|Add4~7 7 COMB LAB_X32_Y16 2 " "Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 4.392 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~5 Arkanoid:inst|Add4~7 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.472 ns Arkanoid:inst\|Add4~9 8 COMB LAB_X32_Y16 2 " "Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 4.472 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~7 Arkanoid:inst|Add4~9 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.552 ns Arkanoid:inst\|Add4~11 9 COMB LAB_X32_Y16 2 " "Info: 9: + IC(0.000 ns) + CELL(0.080 ns) = 4.552 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~9 Arkanoid:inst|Add4~11 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.632 ns Arkanoid:inst\|Add4~13 10 COMB LAB_X32_Y16 2 " "Info: 10: + IC(0.000 ns) + CELL(0.080 ns) = 4.632 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~11 Arkanoid:inst|Add4~13 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.712 ns Arkanoid:inst\|Add4~15 11 COMB LAB_X32_Y16 2 " "Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 4.712 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~13 Arkanoid:inst|Add4~15 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.792 ns Arkanoid:inst\|Add4~17 12 COMB LAB_X32_Y16 2 " "Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 4.792 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~15 Arkanoid:inst|Add4~17 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.872 ns Arkanoid:inst\|Add4~19 13 COMB LAB_X32_Y16 2 " "Info: 13: + IC(0.000 ns) + CELL(0.080 ns) = 4.872 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~17 Arkanoid:inst|Add4~19 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.952 ns Arkanoid:inst\|Add4~21 14 COMB LAB_X32_Y16 2 " "Info: 14: + IC(0.000 ns) + CELL(0.080 ns) = 4.952 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~19 Arkanoid:inst|Add4~21 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.032 ns Arkanoid:inst\|Add4~23 15 COMB LAB_X32_Y16 2 " "Info: 15: + IC(0.000 ns) + CELL(0.080 ns) = 5.032 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~21 Arkanoid:inst|Add4~23 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.112 ns Arkanoid:inst\|Add4~25 16 COMB LAB_X32_Y16 2 " "Info: 16: + IC(0.000 ns) + CELL(0.080 ns) = 5.112 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~23 Arkanoid:inst|Add4~25 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.192 ns Arkanoid:inst\|Add4~27 17 COMB LAB_X32_Y16 2 " "Info: 17: + IC(0.000 ns) + CELL(0.080 ns) = 5.192 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~25 Arkanoid:inst|Add4~27 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.272 ns Arkanoid:inst\|Add4~29 18 COMB LAB_X32_Y16 2 " "Info: 18: + IC(0.000 ns) + CELL(0.080 ns) = 5.272 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~27 Arkanoid:inst|Add4~29 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.352 ns Arkanoid:inst\|Add4~31 19 COMB LAB_X32_Y16 2 " "Info: 19: + IC(0.000 ns) + CELL(0.080 ns) = 5.352 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~29 Arkanoid:inst|Add4~31 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.098 ns) + CELL(0.080 ns) 5.530 ns Arkanoid:inst\|Add4~33 20 COMB LAB_X32_Y15 2 " "Info: 20: + IC(0.098 ns) + CELL(0.080 ns) = 5.530 ns; Loc. = LAB_X32_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { Arkanoid:inst|Add4~31 Arkanoid:inst|Add4~33 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.610 ns Arkanoid:inst\|Add4~35 21 COMB LAB_X32_Y15 2 " "Info: 21: + IC(0.000 ns) + CELL(0.080 ns) = 5.610 ns; Loc. = LAB_X32_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~33 Arkanoid:inst|Add4~35 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.690 ns Arkanoid:inst\|Add4~37 22 COMB LAB_X32_Y15 2 " "Info: 22: + IC(0.000 ns) + CELL(0.080 ns) = 5.690 ns; Loc. = LAB_X32_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~35 Arkanoid:inst|Add4~37 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.770 ns Arkanoid:inst\|Add4~39 23 COMB LAB_X32_Y15 2 " "Info: 23: + IC(0.000 ns) + CELL(0.080 ns) = 5.770 ns; Loc. = LAB_X32_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~37 Arkanoid:inst|Add4~39 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.850 ns Arkanoid:inst\|Add4~41 24 COMB LAB_X32_Y15 2 " "Info: 24: + IC(0.000 ns) + CELL(0.080 ns) = 5.850 ns; Loc. = LAB_X32_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~39 Arkanoid:inst|Add4~41 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.930 ns Arkanoid:inst\|Add4~43 25 COMB LAB_X32_Y15 2 " "Info: 25: + IC(0.000 ns) + CELL(0.080 ns) = 5.930 ns; Loc. = LAB_X32_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~41 Arkanoid:inst|Add4~43 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 6.010 ns Arkanoid:inst\|Add4~45 26 COMB LAB_X32_Y15 2 " "Info: 26: + IC(0.000 ns) + CELL(0.080 ns) = 6.010 ns; Loc. = LAB_X32_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~43 Arkanoid:inst|Add4~45 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 6.090 ns Arkanoid:inst\|Add4~47 27 COMB LAB_X32_Y15 2 " "Info: 27: + IC(0.000 ns) + CELL(0.080 ns) = 6.090 ns; Loc. = LAB_X32_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~45 Arkanoid:inst|Add4~47 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 6.170 ns Arkanoid:inst\|Add4~49 28 COMB LAB_X32_Y15 2 " "Info: 28: + IC(0.000 ns) + CELL(0.080 ns) = 6.170 ns; Loc. = LAB_X32_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~47 Arkanoid:inst|Add4~49 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 6.250 ns Arkanoid:inst\|Add4~51 29 COMB LAB_X32_Y15 2 " "Info: 29: + IC(0.000 ns) + CELL(0.080 ns) = 6.250 ns; Loc. = LAB_X32_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~51'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~49 Arkanoid:inst|Add4~51 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 6.330 ns Arkanoid:inst\|Add4~53 30 COMB LAB_X32_Y15 2 " "Info: 30: + IC(0.000 ns) + CELL(0.080 ns) = 6.330 ns; Loc. = LAB_X32_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~53'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~51 Arkanoid:inst|Add4~53 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 6.788 ns Arkanoid:inst\|Add4~54 31 COMB LAB_X32_Y15 1 " "Info: 31: + IC(0.000 ns) + CELL(0.458 ns) = 6.788 ns; Loc. = LAB_X32_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|Add4~54'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|Add4~53 Arkanoid:inst|Add4~54 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.388 ns) + CELL(0.521 ns) 7.697 ns Arkanoid:inst\|platform2_position~29 32 COMB LAB_X33_Y15 4 " "Info: 32: + IC(0.388 ns) + CELL(0.521 ns) = 7.697 ns; Loc. = LAB_X33_Y15; Fanout = 4; COMB Node = 'Arkanoid:inst\|platform2_position~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|Add4~54 Arkanoid:inst|platform2_position~29 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.177 ns) 8.372 ns Arkanoid:inst\|LessThan3~3 33 COMB LAB_X33_Y15 1 " "Info: 33: + IC(0.498 ns) + CELL(0.177 ns) = 8.372 ns; Loc. = LAB_X33_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan3~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.675 ns" { Arkanoid:inst|platform2_position~29 Arkanoid:inst|LessThan3~3 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.178 ns) 9.048 ns Arkanoid:inst\|LessThan3~4 34 COMB LAB_X33_Y15 1 " "Info: 34: + IC(0.498 ns) + CELL(0.178 ns) = 9.048 ns; Loc. = LAB_X33_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan3~4'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { Arkanoid:inst|LessThan3~3 Arkanoid:inst|LessThan3~4 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.237 ns) + CELL(0.322 ns) 10.607 ns Arkanoid:inst\|LessThan3~10 35 COMB LAB_X31_Y16 2 " "Info: 35: + IC(1.237 ns) + CELL(0.322 ns) = 10.607 ns; Loc. = LAB_X31_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|LessThan3~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.559 ns" { Arkanoid:inst|LessThan3~4 Arkanoid:inst|LessThan3~10 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.495 ns) 11.834 ns Arkanoid:inst\|Add5~1 36 COMB LAB_X30_Y16 2 " "Info: 36: + IC(0.732 ns) + CELL(0.495 ns) = 11.834 ns; Loc. = LAB_X30_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.227 ns" { Arkanoid:inst|LessThan3~10 Arkanoid:inst|Add5~1 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 12.292 ns Arkanoid:inst\|Add5~2 37 COMB LAB_X30_Y16 1 " "Info: 37: + IC(0.000 ns) + CELL(0.458 ns) = 12.292 ns; Loc. = LAB_X30_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst\|Add5~2'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|Add5~1 Arkanoid:inst|Add5~2 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.521 ns) 13.558 ns Arkanoid:inst\|platform2_position~48 38 COMB LAB_X31_Y13 16 " "Info: 38: + IC(0.745 ns) + CELL(0.521 ns) = 13.558 ns; Loc. = LAB_X31_Y13; Fanout = 16; COMB Node = 'Arkanoid:inst\|platform2_position~48'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.266 ns" { Arkanoid:inst|Add5~2 Arkanoid:inst|platform2_position~48 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.362 ns) + CELL(0.517 ns) 15.437 ns Arkanoid:inst\|Add7~3 39 COMB LAB_X27_Y14 2 " "Info: 39: + IC(1.362 ns) + CELL(0.517 ns) = 15.437 ns; Loc. = LAB_X27_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add7~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.879 ns" { Arkanoid:inst|platform2_position~48 Arkanoid:inst|Add7~3 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 15.895 ns Arkanoid:inst\|Add7~4 40 COMB LAB_X27_Y14 15 " "Info: 40: + IC(0.000 ns) + CELL(0.458 ns) = 15.895 ns; Loc. = LAB_X27_Y14; Fanout = 15; COMB Node = 'Arkanoid:inst\|Add7~4'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|Add7~3 Arkanoid:inst|Add7~4 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.709 ns) + CELL(0.517 ns) 17.121 ns Arkanoid:inst\|LessThan139~5 41 COMB LAB_X26_Y14 1 " "Info: 41: + IC(0.709 ns) + CELL(0.517 ns) = 17.121 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.226 ns" { Arkanoid:inst|Add7~4 Arkanoid:inst|LessThan139~5 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.201 ns Arkanoid:inst\|LessThan139~7 42 COMB LAB_X26_Y14 1 " "Info: 42: + IC(0.000 ns) + CELL(0.080 ns) = 17.201 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~5 Arkanoid:inst|LessThan139~7 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.281 ns Arkanoid:inst\|LessThan139~9 43 COMB LAB_X26_Y14 1 " "Info: 43: + IC(0.000 ns) + CELL(0.080 ns) = 17.281 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~7 Arkanoid:inst|LessThan139~9 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.361 ns Arkanoid:inst\|LessThan139~11 44 COMB LAB_X26_Y14 1 " "Info: 44: + IC(0.000 ns) + CELL(0.080 ns) = 17.361 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~9 Arkanoid:inst|LessThan139~11 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.441 ns Arkanoid:inst\|LessThan139~13 45 COMB LAB_X26_Y14 1 " "Info: 45: + IC(0.000 ns) + CELL(0.080 ns) = 17.441 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~11 Arkanoid:inst|LessThan139~13 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.521 ns Arkanoid:inst\|LessThan139~15 46 COMB LAB_X26_Y14 1 " "Info: 46: + IC(0.000 ns) + CELL(0.080 ns) = 17.521 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~13 Arkanoid:inst|LessThan139~15 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.601 ns Arkanoid:inst\|LessThan139~17 47 COMB LAB_X26_Y14 1 " "Info: 47: + IC(0.000 ns) + CELL(0.080 ns) = 17.601 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~15 Arkanoid:inst|LessThan139~17 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.681 ns Arkanoid:inst\|LessThan139~19 48 COMB LAB_X26_Y14 1 " "Info: 48: + IC(0.000 ns) + CELL(0.080 ns) = 17.681 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~17 Arkanoid:inst|LessThan139~19 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.761 ns Arkanoid:inst\|LessThan139~21 49 COMB LAB_X26_Y14 1 " "Info: 49: + IC(0.000 ns) + CELL(0.080 ns) = 17.761 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~19 Arkanoid:inst|LessThan139~21 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.841 ns Arkanoid:inst\|LessThan139~23 50 COMB LAB_X26_Y14 1 " "Info: 50: + IC(0.000 ns) + CELL(0.080 ns) = 17.841 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~21 Arkanoid:inst|LessThan139~23 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.921 ns Arkanoid:inst\|LessThan139~25 51 COMB LAB_X26_Y14 1 " "Info: 51: + IC(0.000 ns) + CELL(0.080 ns) = 17.921 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~23 Arkanoid:inst|LessThan139~25 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.001 ns Arkanoid:inst\|LessThan139~27 52 COMB LAB_X26_Y14 1 " "Info: 52: + IC(0.000 ns) + CELL(0.080 ns) = 18.001 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~25 Arkanoid:inst|LessThan139~27 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.081 ns Arkanoid:inst\|LessThan139~29 53 COMB LAB_X26_Y14 1 " "Info: 53: + IC(0.000 ns) + CELL(0.080 ns) = 18.081 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~27 Arkanoid:inst|LessThan139~29 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.161 ns Arkanoid:inst\|LessThan139~31 54 COMB LAB_X26_Y14 1 " "Info: 54: + IC(0.000 ns) + CELL(0.080 ns) = 18.161 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~29 Arkanoid:inst|LessThan139~31 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.098 ns) + CELL(0.080 ns) 18.339 ns Arkanoid:inst\|LessThan139~33 55 COMB LAB_X26_Y13 1 " "Info: 55: + IC(0.098 ns) + CELL(0.080 ns) = 18.339 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { Arkanoid:inst|LessThan139~31 Arkanoid:inst|LessThan139~33 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.419 ns Arkanoid:inst\|LessThan139~35 56 COMB LAB_X26_Y13 1 " "Info: 56: + IC(0.000 ns) + CELL(0.080 ns) = 18.419 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~33 Arkanoid:inst|LessThan139~35 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.499 ns Arkanoid:inst\|LessThan139~37 57 COMB LAB_X26_Y13 1 " "Info: 57: + IC(0.000 ns) + CELL(0.080 ns) = 18.499 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~35 Arkanoid:inst|LessThan139~37 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.579 ns Arkanoid:inst\|LessThan139~39 58 COMB LAB_X26_Y13 1 " "Info: 58: + IC(0.000 ns) + CELL(0.080 ns) = 18.579 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~37 Arkanoid:inst|LessThan139~39 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.659 ns Arkanoid:inst\|LessThan139~41 59 COMB LAB_X26_Y13 1 " "Info: 59: + IC(0.000 ns) + CELL(0.080 ns) = 18.659 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~39 Arkanoid:inst|LessThan139~41 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.739 ns Arkanoid:inst\|LessThan139~43 60 COMB LAB_X26_Y13 1 " "Info: 60: + IC(0.000 ns) + CELL(0.080 ns) = 18.739 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~41 Arkanoid:inst|LessThan139~43 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.819 ns Arkanoid:inst\|LessThan139~45 61 COMB LAB_X26_Y13 1 " "Info: 61: + IC(0.000 ns) + CELL(0.080 ns) = 18.819 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~43 Arkanoid:inst|LessThan139~45 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.899 ns Arkanoid:inst\|LessThan139~47 62 COMB LAB_X26_Y13 1 " "Info: 62: + IC(0.000 ns) + CELL(0.080 ns) = 18.899 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~45 Arkanoid:inst|LessThan139~47 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.979 ns Arkanoid:inst\|LessThan139~49 63 COMB LAB_X26_Y13 1 " "Info: 63: + IC(0.000 ns) + CELL(0.080 ns) = 18.979 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~47 Arkanoid:inst|LessThan139~49 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.059 ns Arkanoid:inst\|LessThan139~51 64 COMB LAB_X26_Y13 1 " "Info: 64: + IC(0.000 ns) + CELL(0.080 ns) = 19.059 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~51'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~49 Arkanoid:inst|LessThan139~51 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.139 ns Arkanoid:inst\|LessThan139~53 65 COMB LAB_X26_Y13 1 " "Info: 65: + IC(0.000 ns) + CELL(0.080 ns) = 19.139 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~53'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~51 Arkanoid:inst|LessThan139~53 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.219 ns Arkanoid:inst\|LessThan139~55 66 COMB LAB_X26_Y13 1 " "Info: 66: + IC(0.000 ns) + CELL(0.080 ns) = 19.219 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~55'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~53 Arkanoid:inst|LessThan139~55 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.299 ns Arkanoid:inst\|LessThan139~57 67 COMB LAB_X26_Y13 1 " "Info: 67: + IC(0.000 ns) + CELL(0.080 ns) = 19.299 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~57'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~55 Arkanoid:inst|LessThan139~57 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.379 ns Arkanoid:inst\|LessThan139~59 68 COMB LAB_X26_Y13 1 " "Info: 68: + IC(0.000 ns) + CELL(0.080 ns) = 19.379 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~59'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~57 Arkanoid:inst|LessThan139~59 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.459 ns Arkanoid:inst\|LessThan139~61 69 COMB LAB_X26_Y13 1 " "Info: 69: + IC(0.000 ns) + CELL(0.080 ns) = 19.459 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~61'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~59 Arkanoid:inst|LessThan139~61 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 19.917 ns Arkanoid:inst\|LessThan139~62 70 COMB LAB_X26_Y13 3 " "Info: 70: + IC(0.000 ns) + CELL(0.458 ns) = 19.917 ns; Loc. = LAB_X26_Y13; Fanout = 3; COMB Node = 'Arkanoid:inst\|LessThan139~62'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|LessThan139~61 Arkanoid:inst|LessThan139~62 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 141 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.763 ns) + CELL(0.521 ns) 21.201 ns Arkanoid:inst\|always2~5 71 COMB LAB_X26_Y11 9 " "Info: 71: + IC(0.763 ns) + CELL(0.521 ns) = 21.201 ns; Loc. = LAB_X26_Y11; Fanout = 9; COMB Node = 'Arkanoid:inst\|always2~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.284 ns" { Arkanoid:inst|LessThan139~62 Arkanoid:inst|always2~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.739 ns) + CELL(0.495 ns) 23.435 ns Arkanoid:inst\|Add9~1 72 COMB LAB_X13_Y11 2 " "Info: 72: + IC(1.739 ns) + CELL(0.495 ns) = 23.435 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.234 ns" { Arkanoid:inst|always2~5 Arkanoid:inst|Add9~1 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.515 ns Arkanoid:inst\|Add9~3 73 COMB LAB_X13_Y11 2 " "Info: 73: + IC(0.000 ns) + CELL(0.080 ns) = 23.515 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~1 Arkanoid:inst|Add9~3 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.595 ns Arkanoid:inst\|Add9~5 74 COMB LAB_X13_Y11 2 " "Info: 74: + IC(0.000 ns) + CELL(0.080 ns) = 23.595 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~3 Arkanoid:inst|Add9~5 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.675 ns Arkanoid:inst\|Add9~7 75 COMB LAB_X13_Y11 2 " "Info: 75: + IC(0.000 ns) + CELL(0.080 ns) = 23.675 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~5 Arkanoid:inst|Add9~7 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.755 ns Arkanoid:inst\|Add9~9 76 COMB LAB_X13_Y11 2 " "Info: 76: + IC(0.000 ns) + CELL(0.080 ns) = 23.755 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~7 Arkanoid:inst|Add9~9 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.835 ns Arkanoid:inst\|Add9~11 77 COMB LAB_X13_Y11 2 " "Info: 77: + IC(0.000 ns) + CELL(0.080 ns) = 23.835 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~9 Arkanoid:inst|Add9~11 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.915 ns Arkanoid:inst\|Add9~13 78 COMB LAB_X13_Y11 2 " "Info: 78: + IC(0.000 ns) + CELL(0.080 ns) = 23.915 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~11 Arkanoid:inst|Add9~13 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.995 ns Arkanoid:inst\|Add9~15 79 COMB LAB_X13_Y11 2 " "Info: 79: + IC(0.000 ns) + CELL(0.080 ns) = 23.995 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~13 Arkanoid:inst|Add9~15 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.075 ns Arkanoid:inst\|Add9~17 80 COMB LAB_X13_Y11 2 " "Info: 80: + IC(0.000 ns) + CELL(0.080 ns) = 24.075 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~15 Arkanoid:inst|Add9~17 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.155 ns Arkanoid:inst\|Add9~19 81 COMB LAB_X13_Y11 2 " "Info: 81: + IC(0.000 ns) + CELL(0.080 ns) = 24.155 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~17 Arkanoid:inst|Add9~19 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.235 ns Arkanoid:inst\|Add9~21 82 COMB LAB_X13_Y11 2 " "Info: 82: + IC(0.000 ns) + CELL(0.080 ns) = 24.235 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~19 Arkanoid:inst|Add9~21 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.315 ns Arkanoid:inst\|Add9~23 83 COMB LAB_X13_Y11 2 " "Info: 83: + IC(0.000 ns) + CELL(0.080 ns) = 24.315 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~21 Arkanoid:inst|Add9~23 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.395 ns Arkanoid:inst\|Add9~25 84 COMB LAB_X13_Y11 2 " "Info: 84: + IC(0.000 ns) + CELL(0.080 ns) = 24.395 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~23 Arkanoid:inst|Add9~25 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.475 ns Arkanoid:inst\|Add9~27 85 COMB LAB_X13_Y11 2 " "Info: 85: + IC(0.000 ns) + CELL(0.080 ns) = 24.475 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~25 Arkanoid:inst|Add9~27 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.555 ns Arkanoid:inst\|Add9~29 86 COMB LAB_X13_Y11 2 " "Info: 86: + IC(0.000 ns) + CELL(0.080 ns) = 24.555 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~27 Arkanoid:inst|Add9~29 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.635 ns Arkanoid:inst\|Add9~31 87 COMB LAB_X13_Y11 2 " "Info: 87: + IC(0.000 ns) + CELL(0.080 ns) = 24.635 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~29 Arkanoid:inst|Add9~31 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.098 ns) + CELL(0.080 ns) 24.813 ns Arkanoid:inst\|Add9~33 88 COMB LAB_X13_Y10 2 " "Info: 88: + IC(0.098 ns) + CELL(0.080 ns) = 24.813 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { Arkanoid:inst|Add9~31 Arkanoid:inst|Add9~33 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.893 ns Arkanoid:inst\|Add9~35 89 COMB LAB_X13_Y10 2 " "Info: 89: + IC(0.000 ns) + CELL(0.080 ns) = 24.893 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~33 Arkanoid:inst|Add9~35 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.973 ns Arkanoid:inst\|Add9~37 90 COMB LAB_X13_Y10 2 " "Info: 90: + IC(0.000 ns) + CELL(0.080 ns) = 24.973 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~35 Arkanoid:inst|Add9~37 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.053 ns Arkanoid:inst\|Add9~39 91 COMB LAB_X13_Y10 2 " "Info: 91: + IC(0.000 ns) + CELL(0.080 ns) = 25.053 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~37 Arkanoid:inst|Add9~39 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.133 ns Arkanoid:inst\|Add9~41 92 COMB LAB_X13_Y10 2 " "Info: 92: + IC(0.000 ns) + CELL(0.080 ns) = 25.133 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~39 Arkanoid:inst|Add9~41 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.213 ns Arkanoid:inst\|Add9~43 93 COMB LAB_X13_Y10 2 " "Info: 93: + IC(0.000 ns) + CELL(0.080 ns) = 25.213 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~41 Arkanoid:inst|Add9~43 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.293 ns Arkanoid:inst\|Add9~45 94 COMB LAB_X13_Y10 2 " "Info: 94: + IC(0.000 ns) + CELL(0.080 ns) = 25.293 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~43 Arkanoid:inst|Add9~45 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.373 ns Arkanoid:inst\|Add9~47 95 COMB LAB_X13_Y10 2 " "Info: 95: + IC(0.000 ns) + CELL(0.080 ns) = 25.373 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~45 Arkanoid:inst|Add9~47 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.453 ns Arkanoid:inst\|Add9~49 96 COMB LAB_X13_Y10 2 " "Info: 96: + IC(0.000 ns) + CELL(0.080 ns) = 25.453 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~47 Arkanoid:inst|Add9~49 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.533 ns Arkanoid:inst\|Add9~51 97 COMB LAB_X13_Y10 2 " "Info: 97: + IC(0.000 ns) + CELL(0.080 ns) = 25.533 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~51'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~49 Arkanoid:inst|Add9~51 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.613 ns Arkanoid:inst\|Add9~53 98 COMB LAB_X13_Y10 2 " "Info: 98: + IC(0.000 ns) + CELL(0.080 ns) = 25.613 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~53'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~51 Arkanoid:inst|Add9~53 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.693 ns Arkanoid:inst\|Add9~55 99 COMB LAB_X13_Y10 2 " "Info: 99: + IC(0.000 ns) + CELL(0.080 ns) = 25.693 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~55'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~53 Arkanoid:inst|Add9~55 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.773 ns Arkanoid:inst\|Add9~57 100 COMB LAB_X13_Y10 2 " "Info: 100: + IC(0.000 ns) + CELL(0.080 ns) = 25.773 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~57'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~55 Arkanoid:inst|Add9~57 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.853 ns Arkanoid:inst\|Add9~59 101 COMB LAB_X13_Y10 2 " "Info: 101: + IC(0.000 ns) + CELL(0.080 ns) = 25.853 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~59'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~57 Arkanoid:inst|Add9~59 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.933 ns Arkanoid:inst\|Add9~61 102 COMB LAB_X13_Y10 1 " "Info: 102: + IC(0.000 ns) + CELL(0.080 ns) = 25.933 ns; Loc. = LAB_X13_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|Add9~61'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~59 Arkanoid:inst|Add9~61 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 26.391 ns Arkanoid:inst\|Add9~63 103 COMB LAB_X13_Y10 3 " "Info: 103: + IC(0.000 ns) + CELL(0.458 ns) = 26.391 ns; Loc. = LAB_X13_Y10; Fanout = 3; COMB Node = 'Arkanoid:inst\|Add9~63'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|Add9~61 Arkanoid:inst|Add9~63 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.521 ns) 27.657 ns Arkanoid:inst\|lpm_divide:Mod0\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[0\]~0 104 COMB LAB_X12_Y13 4 " "Info: 104: + IC(0.745 ns) + CELL(0.521 ns) = 27.657 ns; Loc. = LAB_X12_Y13; Fanout = 4; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod0\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[0\]~0'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.266 ns" { Arkanoid:inst|Add9~63 Arkanoid:inst|lpm_divide:Mod0|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[0]~0 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.381 ns) + CELL(0.495 ns) 29.533 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~1 105 COMB LAB_X14_Y14 2 " "Info: 105: + IC(1.381 ns) + CELL(0.495 ns) = 29.533 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.876 ns" { Arkanoid:inst|lpm_divide:Mod0|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[0]~0 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~1 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 29.613 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~3 106 COMB LAB_X14_Y14 2 " "Info: 106: + IC(0.000 ns) + CELL(0.080 ns) = 29.613 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 29.693 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~5 107 COMB LAB_X14_Y14 2 " "Info: 107: + IC(0.000 ns) + CELL(0.080 ns) = 29.693 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 29.773 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~7 108 COMB LAB_X14_Y14 2 " "Info: 108: + IC(0.000 ns) + CELL(0.080 ns) = 29.773 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 29.853 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~9 109 COMB LAB_X14_Y14 2 " "Info: 109: + IC(0.000 ns) + CELL(0.080 ns) = 29.853 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 29.933 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~11 110 COMB LAB_X14_Y14 2 " "Info: 110: + IC(0.000 ns) + CELL(0.080 ns) = 29.933 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.013 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~13 111 COMB LAB_X14_Y14 2 " "Info: 111: + IC(0.000 ns) + CELL(0.080 ns) = 30.013 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.093 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~15 112 COMB LAB_X14_Y14 2 " "Info: 112: + IC(0.000 ns) + CELL(0.080 ns) = 30.093 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.173 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~17 113 COMB LAB_X14_Y14 2 " "Info: 113: + IC(0.000 ns) + CELL(0.080 ns) = 30.173 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.253 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~19 114 COMB LAB_X14_Y14 2 " "Info: 114: + IC(0.000 ns) + CELL(0.080 ns) = 30.253 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.333 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~21 115 COMB LAB_X14_Y14 2 " "Info: 115: + IC(0.000 ns) + CELL(0.080 ns) = 30.333 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.413 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~23 116 COMB LAB_X14_Y14 2 " "Info: 116: + IC(0.000 ns) + CELL(0.080 ns) = 30.413 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.493 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~25 117 COMB LAB_X14_Y14 2 " "Info: 117: + IC(0.000 ns) + CELL(0.080 ns) = 30.493 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.573 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~27 118 COMB LAB_X14_Y14 2 " "Info: 118: + IC(0.000 ns) + CELL(0.080 ns) = 30.573 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.653 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~29 119 COMB LAB_X14_Y14 2 " "Info: 119: + IC(0.000 ns) + CELL(0.080 ns) = 30.653 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.098 ns) + CELL(0.080 ns) 30.831 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~31 120 COMB LAB_X14_Y13 2 " "Info: 120: + IC(0.098 ns) + CELL(0.080 ns) = 30.831 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.911 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~33 121 COMB LAB_X14_Y13 2 " "Info: 121: + IC(0.000 ns) + CELL(0.080 ns) = 30.911 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.991 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~35 122 COMB LAB_X14_Y13 2 " "Info: 122: + IC(0.000 ns) + CELL(0.080 ns) = 30.991 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.071 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~37 123 COMB LAB_X14_Y13 2 " "Info: 123: + IC(0.000 ns) + CELL(0.080 ns) = 31.071 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.151 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~39 124 COMB LAB_X14_Y13 2 " "Info: 124: + IC(0.000 ns) + CELL(0.080 ns) = 31.151 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.231 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~41 125 COMB LAB_X14_Y13 2 " "Info: 125: + IC(0.000 ns) + CELL(0.080 ns) = 31.231 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.311 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~43 126 COMB LAB_X14_Y13 2 " "Info: 126: + IC(0.000 ns) + CELL(0.080 ns) = 31.311 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.391 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~45 127 COMB LAB_X14_Y13 2 " "Info: 127: + IC(0.000 ns) + CELL(0.080 ns) = 31.391 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.471 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~47 128 COMB LAB_X14_Y13 2 " "Info: 128: + IC(0.000 ns) + CELL(0.080 ns) = 31.471 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.551 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~49 129 COMB LAB_X14_Y13 2 " "Info: 129: + IC(0.000 ns) + CELL(0.080 ns) = 31.551 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.631 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~51 130 COMB LAB_X14_Y13 2 " "Info: 130: + IC(0.000 ns) + CELL(0.080 ns) = 31.631 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~51'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.711 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~53 131 COMB LAB_X14_Y13 2 " "Info: 131: + IC(0.000 ns) + CELL(0.080 ns) = 31.711 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~53'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.791 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~55 132 COMB LAB_X14_Y13 2 " "Info: 132: + IC(0.000 ns) + CELL(0.080 ns) = 31.791 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~55'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 32.249 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~56 133 COMB LAB_X14_Y13 4 " "Info: 133: + IC(0.000 ns) + CELL(0.458 ns) = 32.249 ns; Loc. = LAB_X14_Y13; Fanout = 4; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~56'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~56 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.984 ns) + CELL(0.517 ns) 34.750 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[1\]~1 134 COMB LAB_X21_Y21 2 " "Info: 134: + IC(1.984 ns) + CELL(0.517 ns) = 34.750 ns; Loc. = LAB_X21_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.501 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~56 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 141 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 34.830 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[2\]~3 135 COMB LAB_X21_Y21 2 " "Info: 135: + IC(0.000 ns) + CELL(0.080 ns) = 34.830 ns; Loc. = LAB_X21_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 141 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 34.910 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[3\]~5 136 COMB LAB_X21_Y21 1 " "Info: 136: + IC(0.000 ns) + CELL(0.080 ns) = 34.910 ns; Loc. = LAB_X21_Y21; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 141 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 35.368 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[4\]~6 137 COMB LAB_X21_Y21 14 " "Info: 137: + IC(0.000 ns) + CELL(0.458 ns) = 35.368 ns; Loc. = LAB_X21_Y21; Fanout = 14; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[4\]~6'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 141 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.177 ns) 36.277 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[18\]~111 138 COMB LAB_X22_Y21 2 " "Info: 138: + IC(0.732 ns) + CELL(0.177 ns) = 36.277 ns; Loc. = LAB_X22_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[18\]~111'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[18]~111 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.495 ns) 37.270 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[1\]~1 139 COMB LAB_X22_Y21 2 " "Info: 139: + IC(0.498 ns) + CELL(0.495 ns) = 37.270 ns; Loc. = LAB_X22_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.993 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[18]~111 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 37.350 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[2\]~3 140 COMB LAB_X22_Y21 2 " "Info: 140: + IC(0.000 ns) + CELL(0.080 ns) = 37.350 ns; Loc. = LAB_X22_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 37.430 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[3\]~5 141 COMB LAB_X22_Y21 2 " "Info: 141: + IC(0.000 ns) + CELL(0.080 ns) = 37.430 ns; Loc. = LAB_X22_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 37.510 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[4\]~7 142 COMB LAB_X22_Y21 1 " "Info: 142: + IC(0.000 ns) + CELL(0.080 ns) = 37.510 ns; Loc. = LAB_X22_Y21; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 37.968 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[5\]~8 143 COMB LAB_X22_Y21 17 " "Info: 143: + IC(0.000 ns) + CELL(0.458 ns) = 37.968 ns; Loc. = LAB_X22_Y21; Fanout = 17; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[5\]~8'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.177 ns) 39.234 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[24\]~121 144 COMB LAB_X21_Y17 2 " "Info: 144: + IC(1.089 ns) + CELL(0.177 ns) = 39.234 ns; Loc. = LAB_X21_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[24\]~121'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.266 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[24]~121 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.495 ns) 40.818 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[1\]~1 145 COMB LAB_X22_Y21 2 " "Info: 145: + IC(1.089 ns) + CELL(0.495 ns) = 40.818 ns; Loc. = LAB_X22_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.584 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[24]~121 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 40.898 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[2\]~3 146 COMB LAB_X22_Y21 2 " "Info: 146: + IC(0.000 ns) + CELL(0.080 ns) = 40.898 ns; Loc. = LAB_X22_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 40.978 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[3\]~5 147 COMB LAB_X22_Y21 2 " "Info: 147: + IC(0.000 ns) + CELL(0.080 ns) = 40.978 ns; Loc. = LAB_X22_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 41.058 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[4\]~7 148 COMB LAB_X22_Y21 1 " "Info: 148: + IC(0.000 ns) + CELL(0.080 ns) = 41.058 ns; Loc. = LAB_X22_Y21; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 41.138 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[5\]~9 149 COMB LAB_X22_Y21 1 " "Info: 149: + IC(0.000 ns) + CELL(0.080 ns) = 41.138 ns; Loc. = LAB_X22_Y21; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 41.596 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[6\]~10 150 COMB LAB_X22_Y21 16 " "Info: 150: + IC(0.000 ns) + CELL(0.458 ns) = 41.596 ns; Loc. = LAB_X22_Y21; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.397 ns) + CELL(0.177 ns) 43.170 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[30\]~129 151 COMB LAB_X20_Y17 2 " "Info: 151: + IC(1.397 ns) + CELL(0.177 ns) = 43.170 ns; Loc. = LAB_X20_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[30\]~129'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.574 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[30]~129 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.495 ns) 44.397 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[1\]~1 152 COMB LAB_X21_Y17 2 " "Info: 152: + IC(0.732 ns) + CELL(0.495 ns) = 44.397 ns; Loc. = LAB_X21_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.227 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[30]~129 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 44.477 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[2\]~3 153 COMB LAB_X21_Y17 2 " "Info: 153: + IC(0.000 ns) + CELL(0.080 ns) = 44.477 ns; Loc. = LAB_X21_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 44.557 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[3\]~5 154 COMB LAB_X21_Y17 2 " "Info: 154: + IC(0.000 ns) + CELL(0.080 ns) = 44.557 ns; Loc. = LAB_X21_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 44.637 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[4\]~7 155 COMB LAB_X21_Y17 1 " "Info: 155: + IC(0.000 ns) + CELL(0.080 ns) = 44.637 ns; Loc. = LAB_X21_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 44.717 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[5\]~9 156 COMB LAB_X21_Y17 1 " "Info: 156: + IC(0.000 ns) + CELL(0.080 ns) = 44.717 ns; Loc. = LAB_X21_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 45.175 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[6\]~10 157 COMB LAB_X21_Y17 16 " "Info: 157: + IC(0.000 ns) + CELL(0.458 ns) = 45.175 ns; Loc. = LAB_X21_Y17; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.058 ns) + CELL(0.177 ns) 46.410 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[36\]~137 158 COMB LAB_X16_Y17 2 " "Info: 158: + IC(1.058 ns) + CELL(0.177 ns) = 46.410 ns; Loc. = LAB_X16_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[36\]~137'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.235 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~137 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.039 ns) + CELL(0.495 ns) 47.944 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[1\]~1 159 COMB LAB_X20_Y17 2 " "Info: 159: + IC(1.039 ns) + CELL(0.495 ns) = 47.944 ns; Loc. = LAB_X20_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.534 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~137 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 48.024 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[2\]~3 160 COMB LAB_X20_Y17 2 " "Info: 160: + IC(0.000 ns) + CELL(0.080 ns) = 48.024 ns; Loc. = LAB_X20_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 48.104 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[3\]~5 161 COMB LAB_X20_Y17 2 " "Info: 161: + IC(0.000 ns) + CELL(0.080 ns) = 48.104 ns; Loc. = LAB_X20_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 48.184 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[4\]~7 162 COMB LAB_X20_Y17 1 " "Info: 162: + IC(0.000 ns) + CELL(0.080 ns) = 48.184 ns; Loc. = LAB_X20_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 48.264 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[5\]~9 163 COMB LAB_X20_Y17 1 " "Info: 163: + IC(0.000 ns) + CELL(0.080 ns) = 48.264 ns; Loc. = LAB_X20_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 48.722 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[6\]~10 164 COMB LAB_X20_Y17 16 " "Info: 164: + IC(0.000 ns) + CELL(0.458 ns) = 48.722 ns; Loc. = LAB_X20_Y17; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.396 ns) + CELL(0.177 ns) 50.295 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[42\]~145 165 COMB LAB_X16_Y15 2 " "Info: 165: + IC(1.396 ns) + CELL(0.177 ns) = 50.295 ns; Loc. = LAB_X16_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[42\]~145'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[42]~145 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.084 ns) + CELL(0.495 ns) 51.874 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[1\]~1 166 COMB LAB_X16_Y17 2 " "Info: 166: + IC(1.084 ns) + CELL(0.495 ns) = 51.874 ns; Loc. = LAB_X16_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.579 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[42]~145 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 51.954 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[2\]~3 167 COMB LAB_X16_Y17 2 " "Info: 167: + IC(0.000 ns) + CELL(0.080 ns) = 51.954 ns; Loc. = LAB_X16_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 52.034 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[3\]~5 168 COMB LAB_X16_Y17 2 " "Info: 168: + IC(0.000 ns) + CELL(0.080 ns) = 52.034 ns; Loc. = LAB_X16_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 52.114 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[4\]~7 169 COMB LAB_X16_Y17 1 " "Info: 169: + IC(0.000 ns) + CELL(0.080 ns) = 52.114 ns; Loc. = LAB_X16_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 52.194 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[5\]~9 170 COMB LAB_X16_Y17 1 " "Info: 170: + IC(0.000 ns) + CELL(0.080 ns) = 52.194 ns; Loc. = LAB_X16_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 52.652 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[6\]~10 171 COMB LAB_X16_Y17 16 " "Info: 171: + IC(0.000 ns) + CELL(0.458 ns) = 52.652 ns; Loc. = LAB_X16_Y17; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.393 ns) + CELL(0.177 ns) 54.222 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[48\]~153 172 COMB LAB_X13_Y15 2 " "Info: 172: + IC(1.393 ns) + CELL(0.177 ns) = 54.222 ns; Loc. = LAB_X13_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[48\]~153'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.570 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[48]~153 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.039 ns) + CELL(0.495 ns) 55.756 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[1\]~1 173 COMB LAB_X16_Y15 2 " "Info: 173: + IC(1.039 ns) + CELL(0.495 ns) = 55.756 ns; Loc. = LAB_X16_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.534 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[48]~153 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 55.836 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[2\]~3 174 COMB LAB_X16_Y15 2 " "Info: 174: + IC(0.000 ns) + CELL(0.080 ns) = 55.836 ns; Loc. = LAB_X16_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 55.916 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[3\]~5 175 COMB LAB_X16_Y15 2 " "Info: 175: + IC(0.000 ns) + CELL(0.080 ns) = 55.916 ns; Loc. = LAB_X16_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 55.996 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[4\]~7 176 COMB LAB_X16_Y15 1 " "Info: 176: + IC(0.000 ns) + CELL(0.080 ns) = 55.996 ns; Loc. = LAB_X16_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 56.076 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[5\]~9 177 COMB LAB_X16_Y15 1 " "Info: 177: + IC(0.000 ns) + CELL(0.080 ns) = 56.076 ns; Loc. = LAB_X16_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 56.534 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[6\]~10 178 COMB LAB_X16_Y15 16 " "Info: 178: + IC(0.000 ns) + CELL(0.458 ns) = 56.534 ns; Loc. = LAB_X16_Y15; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.940 ns) + CELL(0.319 ns) 57.793 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[57\]~339 179 COMB LAB_X16_Y17 3 " "Info: 179: + IC(0.940 ns) + CELL(0.319 ns) = 57.793 ns; Loc. = LAB_X16_Y17; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[57\]~339'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.259 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[57]~339 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.680 ns) + CELL(0.517 ns) 59.990 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[4\]~7 180 COMB LAB_X11_Y15 1 " "Info: 180: + IC(1.680 ns) + CELL(0.517 ns) = 59.990 ns; Loc. = LAB_X11_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.197 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[57]~339 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 36 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 60.070 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[5\]~9 181 COMB LAB_X11_Y15 1 " "Info: 181: + IC(0.000 ns) + CELL(0.080 ns) = 60.070 ns; Loc. = LAB_X11_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 36 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 60.528 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[6\]~10 182 COMB LAB_X11_Y15 16 " "Info: 182: + IC(0.000 ns) + CELL(0.458 ns) = 60.528 ns; Loc. = LAB_X11_Y15; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 36 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.914 ns) + CELL(0.319 ns) 61.761 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[63\]~341 183 COMB LAB_X16_Y15 3 " "Info: 183: + IC(0.914 ns) + CELL(0.319 ns) = 61.761 ns; Loc. = LAB_X16_Y15; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[63\]~341'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.233 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[63]~341 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.015 ns) + CELL(0.517 ns) 63.293 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[4\]~7 184 COMB LAB_X13_Y15 1 " "Info: 184: + IC(1.015 ns) + CELL(0.517 ns) = 63.293 ns; Loc. = LAB_X13_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.532 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[63]~341 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 63.373 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[5\]~9 185 COMB LAB_X13_Y15 1 " "Info: 185: + IC(0.000 ns) + CELL(0.080 ns) = 63.373 ns; Loc. = LAB_X13_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 63.831 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[6\]~10 186 COMB LAB_X13_Y15 16 " "Info: 186: + IC(0.000 ns) + CELL(0.458 ns) = 63.831 ns; Loc. = LAB_X13_Y15; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.040 ns) + CELL(0.177 ns) 65.048 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[66\]~177 187 COMB LAB_X9_Y15 2 " "Info: 187: + IC(1.040 ns) + CELL(0.177 ns) = 65.048 ns; Loc. = LAB_X9_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[66\]~177'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.217 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[66]~177 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.495 ns) 66.581 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[1\]~1 188 COMB LAB_X11_Y15 2 " "Info: 188: + IC(1.038 ns) + CELL(0.495 ns) = 66.581 ns; Loc. = LAB_X11_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.533 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[66]~177 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 66.661 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[2\]~3 189 COMB LAB_X11_Y15 2 " "Info: 189: + IC(0.000 ns) + CELL(0.080 ns) = 66.661 ns; Loc. = LAB_X11_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 66.741 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[3\]~5 190 COMB LAB_X11_Y15 2 " "Info: 190: + IC(0.000 ns) + CELL(0.080 ns) = 66.741 ns; Loc. = LAB_X11_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 66.821 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[4\]~7 191 COMB LAB_X11_Y15 1 " "Info: 191: + IC(0.000 ns) + CELL(0.080 ns) = 66.821 ns; Loc. = LAB_X11_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 66.901 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[5\]~9 192 COMB LAB_X11_Y15 1 " "Info: 192: + IC(0.000 ns) + CELL(0.080 ns) = 66.901 ns; Loc. = LAB_X11_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 67.359 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[6\]~10 193 COMB LAB_X11_Y15 16 " "Info: 193: + IC(0.000 ns) + CELL(0.458 ns) = 67.359 ns; Loc. = LAB_X11_Y15; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.894 ns) + CELL(0.319 ns) 68.572 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[76\]~344 194 COMB LAB_X13_Y15 1 " "Info: 194: + IC(0.894 ns) + CELL(0.319 ns) = 68.572 ns; Loc. = LAB_X13_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[76\]~344'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.213 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[76]~344 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.016 ns) + CELL(0.517 ns) 70.105 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[5\]~9 195 COMB LAB_X10_Y15 1 " "Info: 195: + IC(1.016 ns) + CELL(0.517 ns) = 70.105 ns; Loc. = LAB_X10_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.533 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[76]~344 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 51 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 70.563 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[6\]~10 196 COMB LAB_X10_Y15 16 " "Info: 196: + IC(0.000 ns) + CELL(0.458 ns) = 70.563 ns; Loc. = LAB_X10_Y15; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 51 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.177 ns) 71.778 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[82\]~186 197 COMB LAB_X12_Y15 1 " "Info: 197: + IC(1.038 ns) + CELL(0.177 ns) = 71.778 ns; Loc. = LAB_X12_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[82\]~186'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.215 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[82]~186 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.039 ns) + CELL(0.495 ns) 73.312 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[5\]~9 198 COMB LAB_X9_Y15 1 " "Info: 198: + IC(1.039 ns) + CELL(0.495 ns) = 73.312 ns; Loc. = LAB_X9_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.534 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[82]~186 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 56 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 73.770 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[6\]~10 199 COMB LAB_X9_Y15 16 " "Info: 199: + IC(0.000 ns) + CELL(0.458 ns) = 73.770 ns; Loc. = LAB_X9_Y15; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 56 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.039 ns) + CELL(0.177 ns) 74.986 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[88\]~194 200 COMB LAB_X12_Y15 1 " "Info: 200: + IC(1.039 ns) + CELL(0.177 ns) = 74.986 ns; Loc. = LAB_X12_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[88\]~194'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.216 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[88]~194 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.382 ns) + CELL(0.495 ns) 76.863 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[5\]~9 201 COMB LAB_X9_Y14 1 " "Info: 201: + IC(1.382 ns) + CELL(0.495 ns) = 76.863 ns; Loc. = LAB_X9_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.877 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[88]~194 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 61 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 77.321 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[6\]~10 202 COMB LAB_X9_Y14 16 " "Info: 202: + IC(0.000 ns) + CELL(0.458 ns) = 77.321 ns; Loc. = LAB_X9_Y14; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 61 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.177 ns) 78.587 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[90\]~209 203 COMB LAB_X9_Y10 2 " "Info: 203: + IC(1.089 ns) + CELL(0.177 ns) = 78.587 ns; Loc. = LAB_X9_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[90\]~209'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.266 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[90]~209 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.495 ns) 79.580 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[1\]~1 204 COMB LAB_X9_Y10 2 " "Info: 204: + IC(0.498 ns) + CELL(0.495 ns) = 79.580 ns; Loc. = LAB_X9_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.993 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[90]~209 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 79.660 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[2\]~3 205 COMB LAB_X9_Y10 2 " "Info: 205: + IC(0.000 ns) + CELL(0.080 ns) = 79.660 ns; Loc. = LAB_X9_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 79.740 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[3\]~5 206 COMB LAB_X9_Y10 2 " "Info: 206: + IC(0.000 ns) + CELL(0.080 ns) = 79.740 ns; Loc. = LAB_X9_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 79.820 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[4\]~7 207 COMB LAB_X9_Y10 1 " "Info: 207: + IC(0.000 ns) + CELL(0.080 ns) = 79.820 ns; Loc. = LAB_X9_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 79.900 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[5\]~9 208 COMB LAB_X9_Y10 1 " "Info: 208: + IC(0.000 ns) + CELL(0.080 ns) = 79.900 ns; Loc. = LAB_X9_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 80.358 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[6\]~10 209 COMB LAB_X9_Y10 16 " "Info: 209: + IC(0.000 ns) + CELL(0.458 ns) = 80.358 ns; Loc. = LAB_X9_Y10; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.177 ns) 81.267 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[96\]~217 210 COMB LAB_X10_Y10 2 " "Info: 210: + IC(0.732 ns) + CELL(0.177 ns) = 81.267 ns; Loc. = LAB_X10_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[96\]~217'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[96]~217 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.495 ns) 82.260 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[1\]~1 211 COMB LAB_X10_Y10 2 " "Info: 211: + IC(0.498 ns) + CELL(0.495 ns) = 82.260 ns; Loc. = LAB_X10_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.993 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[96]~217 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 82.340 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[2\]~3 212 COMB LAB_X10_Y10 2 " "Info: 212: + IC(0.000 ns) + CELL(0.080 ns) = 82.340 ns; Loc. = LAB_X10_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 82.420 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[3\]~5 213 COMB LAB_X10_Y10 2 " "Info: 213: + IC(0.000 ns) + CELL(0.080 ns) = 82.420 ns; Loc. = LAB_X10_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 82.500 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[4\]~7 214 COMB LAB_X10_Y10 1 " "Info: 214: + IC(0.000 ns) + CELL(0.080 ns) = 82.500 ns; Loc. = LAB_X10_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 82.580 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[5\]~9 215 COMB LAB_X10_Y10 1 " "Info: 215: + IC(0.000 ns) + CELL(0.080 ns) = 82.580 ns; Loc. = LAB_X10_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 83.038 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[6\]~10 216 COMB LAB_X10_Y10 16 " "Info: 216: + IC(0.000 ns) + CELL(0.458 ns) = 83.038 ns; Loc. = LAB_X10_Y10; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.084 ns) + CELL(0.177 ns) 84.299 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[102\]~225 217 COMB LAB_X9_Y12 2 " "Info: 217: + IC(1.084 ns) + CELL(0.177 ns) = 84.299 ns; Loc. = LAB_X9_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[102\]~225'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.261 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~225 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.495 ns) 85.292 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[1\]~1 218 COMB LAB_X9_Y12 2 " "Info: 218: + IC(0.498 ns) + CELL(0.495 ns) = 85.292 ns; Loc. = LAB_X9_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.993 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~225 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 85.372 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[2\]~3 219 COMB LAB_X9_Y12 2 " "Info: 219: + IC(0.000 ns) + CELL(0.080 ns) = 85.372 ns; Loc. = LAB_X9_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 85.452 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[3\]~5 220 COMB LAB_X9_Y12 2 " "Info: 220: + IC(0.000 ns) + CELL(0.080 ns) = 85.452 ns; Loc. = LAB_X9_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 85.532 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[4\]~7 221 COMB LAB_X9_Y12 1 " "Info: 221: + IC(0.000 ns) + CELL(0.080 ns) = 85.532 ns; Loc. = LAB_X9_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 85.612 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[5\]~9 222 COMB LAB_X9_Y12 1 " "Info: 222: + IC(0.000 ns) + CELL(0.080 ns) = 85.612 ns; Loc. = LAB_X9_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 86.070 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[6\]~10 223 COMB LAB_X9_Y12 16 " "Info: 223: + IC(0.000 ns) + CELL(0.458 ns) = 86.070 ns; Loc. = LAB_X9_Y12; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.177 ns) 87.285 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[108\]~233 224 COMB LAB_X11_Y12 2 " "Info: 224: + IC(1.038 ns) + CELL(0.177 ns) = 87.285 ns; Loc. = LAB_X11_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[108\]~233'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.215 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[108]~233 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.495 ns) 88.278 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[1\]~1 225 COMB LAB_X11_Y12 2 " "Info: 225: + IC(0.498 ns) + CELL(0.495 ns) = 88.278 ns; Loc. = LAB_X11_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.993 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[108]~233 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 88.358 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[2\]~3 226 COMB LAB_X11_Y12 2 " "Info: 226: + IC(0.000 ns) + CELL(0.080 ns) = 88.358 ns; Loc. = LAB_X11_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 88.438 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[3\]~5 227 COMB LAB_X11_Y12 2 " "Info: 227: + IC(0.000 ns) + CELL(0.080 ns) = 88.438 ns; Loc. = LAB_X11_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 88.518 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[4\]~7 228 COMB LAB_X11_Y12 1 " "Info: 228: + IC(0.000 ns) + CELL(0.080 ns) = 88.518 ns; Loc. = LAB_X11_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 88.598 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[5\]~9 229 COMB LAB_X11_Y12 1 " "Info: 229: + IC(0.000 ns) + CELL(0.080 ns) = 88.598 ns; Loc. = LAB_X11_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 89.056 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[6\]~10 230 COMB LAB_X11_Y12 16 " "Info: 230: + IC(0.000 ns) + CELL(0.458 ns) = 89.056 ns; Loc. = LAB_X11_Y12; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.177 ns) 90.322 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[114\]~241 231 COMB LAB_X10_Y9 2 " "Info: 231: + IC(1.089 ns) + CELL(0.177 ns) = 90.322 ns; Loc. = LAB_X10_Y9; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[114\]~241'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.266 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[114]~241 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.495 ns) 91.315 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[1\]~1 232 COMB LAB_X10_Y9 2 " "Info: 232: + IC(0.498 ns) + CELL(0.495 ns) = 91.315 ns; Loc. = LAB_X10_Y9; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.993 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[114]~241 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 91 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 91.395 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[2\]~3 233 COMB LAB_X10_Y9 2 " "Info: 233: + IC(0.000 ns) + CELL(0.080 ns) = 91.395 ns; Loc. = LAB_X10_Y9; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 91 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 91.475 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[3\]~5 234 COMB LAB_X10_Y9 2 " "Info: 234: + IC(0.000 ns) + CELL(0.080 ns) = 91.475 ns; Loc. = LAB_X10_Y9; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 91 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 91.555 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[4\]~7 235 COMB LAB_X10_Y9 1 " "Info: 235: + IC(0.000 ns) + CELL(0.080 ns) = 91.555 ns; Loc. = LAB_X10_Y9; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 91 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 91.635 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[5\]~9 236 COMB LAB_X10_Y9 1 " "Info: 236: + IC(0.000 ns) + CELL(0.080 ns) = 91.635 ns; Loc. = LAB_X10_Y9; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 91 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 92.093 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[6\]~10 237 COMB LAB_X10_Y9 16 " "Info: 237: + IC(0.000 ns) + CELL(0.458 ns) = 92.093 ns; Loc. = LAB_X10_Y9; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 91 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.544 ns) 93.359 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[122\]~244 238 COMB LAB_X11_Y12 3 " "Info: 238: + IC(0.722 ns) + CELL(0.544 ns) = 93.359 ns; Loc. = LAB_X11_Y12; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[122\]~244'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.266 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~244 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.517 ns) 94.942 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[3\]~5 239 COMB LAB_X11_Y9 2 " "Info: 239: + IC(1.066 ns) + CELL(0.517 ns) = 94.942 ns; Loc. = LAB_X11_Y9; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.583 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~244 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 95.022 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[4\]~7 240 COMB LAB_X11_Y9 1 " "Info: 240: + IC(0.000 ns) + CELL(0.080 ns) = 95.022 ns; Loc. = LAB_X11_Y9; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 95.102 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[5\]~9 241 COMB LAB_X11_Y9 1 " "Info: 241: + IC(0.000 ns) + CELL(0.080 ns) = 95.102 ns; Loc. = LAB_X11_Y9; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 95.560 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[6\]~10 242 COMB LAB_X11_Y9 16 " "Info: 242: + IC(0.000 ns) + CELL(0.458 ns) = 95.560 ns; Loc. = LAB_X11_Y9; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.544 ns) 96.469 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[128\]~252 243 COMB LAB_X10_Y9 3 " "Info: 243: + IC(0.365 ns) + CELL(0.544 ns) = 96.469 ns; Loc. = LAB_X10_Y9; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[128\]~252'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[128]~252 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.017 ns) + CELL(0.517 ns) 98.003 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[3\]~5 244 COMB LAB_X14_Y9 2 " "Info: 244: + IC(1.017 ns) + CELL(0.517 ns) = 98.003 ns; Loc. = LAB_X14_Y9; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.534 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[128]~252 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 98.083 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[4\]~7 245 COMB LAB_X14_Y9 1 " "Info: 245: + IC(0.000 ns) + CELL(0.080 ns) = 98.083 ns; Loc. = LAB_X14_Y9; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 98.163 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[5\]~9 246 COMB LAB_X14_Y9 1 " "Info: 246: + IC(0.000 ns) + CELL(0.080 ns) = 98.163 ns; Loc. = LAB_X14_Y9; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 98.621 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[6\]~10 247 COMB LAB_X14_Y9 16 " "Info: 247: + IC(0.000 ns) + CELL(0.458 ns) = 98.621 ns; Loc. = LAB_X14_Y9; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.681 ns) + CELL(0.544 ns) 99.846 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[134\]~260 248 COMB LAB_X11_Y9 3 " "Info: 248: + IC(0.681 ns) + CELL(0.544 ns) = 99.846 ns; Loc. = LAB_X11_Y9; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[134\]~260'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.225 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[134]~260 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.017 ns) + CELL(0.517 ns) 101.380 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[3\]~5 249 COMB LAB_X15_Y9 2 " "Info: 249: + IC(1.017 ns) + CELL(0.517 ns) = 101.380 ns; Loc. = LAB_X15_Y9; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.534 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[134]~260 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 101.460 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[4\]~7 250 COMB LAB_X15_Y9 1 " "Info: 250: + IC(0.000 ns) + CELL(0.080 ns) = 101.460 ns; Loc. = LAB_X15_Y9; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 101.540 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[5\]~9 251 COMB LAB_X15_Y9 1 " "Info: 251: + IC(0.000 ns) + CELL(0.080 ns) = 101.540 ns; Loc. = LAB_X15_Y9; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 101.998 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[6\]~10 252 COMB LAB_X15_Y9 16 " "Info: 252: + IC(0.000 ns) + CELL(0.458 ns) = 101.998 ns; Loc. = LAB_X15_Y9; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.375 ns) + CELL(0.544 ns) 102.917 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[140\]~268 253 COMB LAB_X14_Y9 3 " "Info: 253: + IC(0.375 ns) + CELL(0.544 ns) = 102.917 ns; Loc. = LAB_X14_Y9; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[140\]~268'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.919 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[140]~268 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.060 ns) + CELL(0.517 ns) 104.494 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[3\]~5 254 COMB LAB_X15_Y10 2 " "Info: 254: + IC(1.060 ns) + CELL(0.517 ns) = 104.494 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.577 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[140]~268 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 104.574 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[4\]~7 255 COMB LAB_X15_Y10 1 " "Info: 255: + IC(0.000 ns) + CELL(0.080 ns) = 104.574 ns; Loc. = LAB_X15_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 104.654 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[5\]~9 256 COMB LAB_X15_Y10 1 " "Info: 256: + IC(0.000 ns) + CELL(0.080 ns) = 104.654 ns; Loc. = LAB_X15_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 105.112 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[6\]~10 257 COMB LAB_X15_Y10 16 " "Info: 257: + IC(0.000 ns) + CELL(0.458 ns) = 105.112 ns; Loc. = LAB_X15_Y10; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.716 ns) + CELL(0.544 ns) 106.372 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[146\]~276 258 COMB LAB_X15_Y9 3 " "Info: 258: + IC(0.716 ns) + CELL(0.544 ns) = 106.372 ns; Loc. = LAB_X15_Y9; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[146\]~276'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.260 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~276 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.060 ns) + CELL(0.517 ns) 107.949 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[3\]~5 259 COMB LAB_X16_Y10 2 " "Info: 259: + IC(1.060 ns) + CELL(0.517 ns) = 107.949 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.577 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~276 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 108.029 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[4\]~7 260 COMB LAB_X16_Y10 1 " "Info: 260: + IC(0.000 ns) + CELL(0.080 ns) = 108.029 ns; Loc. = LAB_X16_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 108.109 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[5\]~9 261 COMB LAB_X16_Y10 1 " "Info: 261: + IC(0.000 ns) + CELL(0.080 ns) = 108.109 ns; Loc. = LAB_X16_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 108.567 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[6\]~10 262 COMB LAB_X16_Y10 16 " "Info: 262: + IC(0.000 ns) + CELL(0.458 ns) = 108.567 ns; Loc. = LAB_X16_Y10; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.544 ns) 109.476 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[152\]~284 263 COMB LAB_X15_Y10 3 " "Info: 263: + IC(0.365 ns) + CELL(0.544 ns) = 109.476 ns; Loc. = LAB_X15_Y10; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[152\]~284'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[152]~284 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.060 ns) + CELL(0.517 ns) 111.053 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[3\]~5 264 COMB LAB_X16_Y11 2 " "Info: 264: + IC(1.060 ns) + CELL(0.517 ns) = 111.053 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.577 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[152]~284 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 111.133 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[4\]~7 265 COMB LAB_X16_Y11 1 " "Info: 265: + IC(0.000 ns) + CELL(0.080 ns) = 111.133 ns; Loc. = LAB_X16_Y11; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 111.213 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[5\]~9 266 COMB LAB_X16_Y11 1 " "Info: 266: + IC(0.000 ns) + CELL(0.080 ns) = 111.213 ns; Loc. = LAB_X16_Y11; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 111.671 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[6\]~10 267 COMB LAB_X16_Y11 16 " "Info: 267: + IC(0.000 ns) + CELL(0.458 ns) = 111.671 ns; Loc. = LAB_X16_Y11; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.706 ns) + CELL(0.544 ns) 112.921 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[158\]~292 268 COMB LAB_X16_Y10 3 " "Info: 268: + IC(0.706 ns) + CELL(0.544 ns) = 112.921 ns; Loc. = LAB_X16_Y10; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[158\]~292'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.250 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[158]~292 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.050 ns) + CELL(0.517 ns) 114.488 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[3\]~5 269 COMB LAB_X15_Y11 2 " "Info: 269: + IC(1.050 ns) + CELL(0.517 ns) = 114.488 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.567 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[158]~292 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 114.568 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[4\]~7 270 COMB LAB_X15_Y11 1 " "Info: 270: + IC(0.000 ns) + CELL(0.080 ns) = 114.568 ns; Loc. = LAB_X15_Y11; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 114.648 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[5\]~9 271 COMB LAB_X15_Y11 1 " "Info: 271: + IC(0.000 ns) + CELL(0.080 ns) = 114.648 ns; Loc. = LAB_X15_Y11; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 115.106 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[6\]~10 272 COMB LAB_X15_Y11 16 " "Info: 272: + IC(0.000 ns) + CELL(0.458 ns) = 115.106 ns; Loc. = LAB_X15_Y11; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.375 ns) + CELL(0.544 ns) 116.025 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[164\]~300 273 COMB LAB_X16_Y11 3 " "Info: 273: + IC(0.375 ns) + CELL(0.544 ns) = 116.025 ns; Loc. = LAB_X16_Y11; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[164\]~300'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.919 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[164]~300 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.358 ns) + CELL(0.517 ns) 117.900 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[3\]~5 274 COMB LAB_X14_Y12 2 " "Info: 274: + IC(1.358 ns) + CELL(0.517 ns) = 117.900 ns; Loc. = LAB_X14_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.875 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[164]~300 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 117.980 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[4\]~7 275 COMB LAB_X14_Y12 1 " "Info: 275: + IC(0.000 ns) + CELL(0.080 ns) = 117.980 ns; Loc. = LAB_X14_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 118.060 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[5\]~9 276 COMB LAB_X14_Y12 1 " "Info: 276: + IC(0.000 ns) + CELL(0.080 ns) = 118.060 ns; Loc. = LAB_X14_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 118.518 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[6\]~10 277 COMB LAB_X14_Y12 16 " "Info: 277: + IC(0.000 ns) + CELL(0.458 ns) = 118.518 ns; Loc. = LAB_X14_Y12; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.716 ns) + CELL(0.544 ns) 119.778 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[170\]~308 278 COMB LAB_X15_Y11 3 " "Info: 278: + IC(0.716 ns) + CELL(0.544 ns) = 119.778 ns; Loc. = LAB_X15_Y11; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[170\]~308'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.260 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[170]~308 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.060 ns) + CELL(0.517 ns) 121.355 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[3\]~5 279 COMB LAB_X15_Y12 2 " "Info: 279: + IC(1.060 ns) + CELL(0.517 ns) = 121.355 ns; Loc. = LAB_X15_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.577 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[170]~308 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 121.435 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[4\]~7 280 COMB LAB_X15_Y12 1 " "Info: 280: + IC(0.000 ns) + CELL(0.080 ns) = 121.435 ns; Loc. = LAB_X15_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 121.515 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[5\]~9 281 COMB LAB_X15_Y12 1 " "Info: 281: + IC(0.000 ns) + CELL(0.080 ns) = 121.515 ns; Loc. = LAB_X15_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 121.973 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[6\]~10 282 COMB LAB_X15_Y12 17 " "Info: 282: + IC(0.000 ns) + CELL(0.458 ns) = 121.973 ns; Loc. = LAB_X15_Y12; Fanout = 17; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.375 ns) + CELL(0.544 ns) 122.892 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[176\]~316 283 COMB LAB_X14_Y12 3 " "Info: 283: + IC(0.375 ns) + CELL(0.544 ns) = 122.892 ns; Loc. = LAB_X14_Y12; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[176\]~316'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.919 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~316 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.024 ns) + CELL(0.517 ns) 124.433 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[3\]~5 284 COMB LAB_X16_Y12 2 " "Info: 284: + IC(1.024 ns) + CELL(0.517 ns) = 124.433 ns; Loc. = LAB_X16_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.541 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~316 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 124.513 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[4\]~7 285 COMB LAB_X16_Y12 1 " "Info: 285: + IC(0.000 ns) + CELL(0.080 ns) = 124.513 ns; Loc. = LAB_X16_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 124.593 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[5\]~9 286 COMB LAB_X16_Y12 1 " "Info: 286: + IC(0.000 ns) + CELL(0.080 ns) = 124.593 ns; Loc. = LAB_X16_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 125.051 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[6\]~10 287 COMB LAB_X16_Y12 13 " "Info: 287: + IC(0.000 ns) + CELL(0.458 ns) = 125.051 ns; Loc. = LAB_X16_Y12; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.544 ns) 125.960 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[182\]~324 288 COMB LAB_X15_Y12 1 " "Info: 288: + IC(0.365 ns) + CELL(0.544 ns) = 125.960 ns; Loc. = LAB_X15_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[182\]~324'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[182]~324 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.060 ns) + CELL(0.517 ns) 127.537 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[3\]~5 289 COMB LAB_X16_Y13 1 " "Info: 289: + IC(1.060 ns) + CELL(0.517 ns) = 127.537 ns; Loc. = LAB_X16_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.577 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[182]~324 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 127.617 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[4\]~7 290 COMB LAB_X16_Y13 1 " "Info: 290: + IC(0.000 ns) + CELL(0.080 ns) = 127.617 ns; Loc. = LAB_X16_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 127.697 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[5\]~9 291 COMB LAB_X16_Y13 1 " "Info: 291: + IC(0.000 ns) + CELL(0.080 ns) = 127.697 ns; Loc. = LAB_X16_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 128.155 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[6\]~10 292 COMB LAB_X16_Y13 3 " "Info: 292: + IC(0.000 ns) + CELL(0.458 ns) = 128.155 ns; Loc. = LAB_X16_Y13; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.369 ns) + CELL(0.517 ns) 130.041 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~1 293 COMB LAB_X18_Y11 2 " "Info: 293: + IC(1.369 ns) + CELL(0.517 ns) = 130.041 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.886 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~1 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 130.121 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~3 294 COMB LAB_X18_Y11 2 " "Info: 294: + IC(0.000 ns) + CELL(0.080 ns) = 130.121 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~3 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 130.201 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~5 295 COMB LAB_X18_Y11 2 " "Info: 295: + IC(0.000 ns) + CELL(0.080 ns) = 130.201 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 130.281 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~7 296 COMB LAB_X18_Y11 2 " "Info: 296: + IC(0.000 ns) + CELL(0.080 ns) = 130.281 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~7 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 130.361 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~9 297 COMB LAB_X18_Y11 2 " "Info: 297: + IC(0.000 ns) + CELL(0.080 ns) = 130.361 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~9 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 130.441 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~11 298 COMB LAB_X18_Y11 2 " "Info: 298: + IC(0.000 ns) + CELL(0.080 ns) = 130.441 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~11 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 130.521 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~13 299 COMB LAB_X18_Y11 2 " "Info: 299: + IC(0.000 ns) + CELL(0.080 ns) = 130.521 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~13 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 130.601 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~15 300 COMB LAB_X18_Y11 2 " "Info: 300: + IC(0.000 ns) + CELL(0.080 ns) = 130.601 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~15 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 130.681 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~17 301 COMB LAB_X18_Y11 2 " "Info: 301: + IC(0.000 ns) + CELL(0.080 ns) = 130.681 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~17 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 130.761 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~19 302 COMB LAB_X18_Y11 2 " "Info: 302: + IC(0.000 ns) + CELL(0.080 ns) = 130.761 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~19 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 130.841 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~21 303 COMB LAB_X18_Y11 2 " "Info: 303: + IC(0.000 ns) + CELL(0.080 ns) = 130.841 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~21 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 130.921 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~23 304 COMB LAB_X18_Y11 2 " "Info: 304: + IC(0.000 ns) + CELL(0.080 ns) = 130.921 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~23 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.001 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~25 305 COMB LAB_X18_Y11 2 " "Info: 305: + IC(0.000 ns) + CELL(0.080 ns) = 131.001 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~25 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.081 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~27 306 COMB LAB_X18_Y11 2 " "Info: 306: + IC(0.000 ns) + CELL(0.080 ns) = 131.081 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~27 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.161 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~29 307 COMB LAB_X18_Y11 2 " "Info: 307: + IC(0.000 ns) + CELL(0.080 ns) = 131.161 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~29 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.098 ns) + CELL(0.080 ns) 131.339 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~31 308 COMB LAB_X18_Y10 2 " "Info: 308: + IC(0.098 ns) + CELL(0.080 ns) = 131.339 ns; Loc. = LAB_X18_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~31 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.419 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~33 309 COMB LAB_X18_Y10 2 " "Info: 309: + IC(0.000 ns) + CELL(0.080 ns) = 131.419 ns; Loc. = LAB_X18_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~33 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.499 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~35 310 COMB LAB_X18_Y10 2 " "Info: 310: + IC(0.000 ns) + CELL(0.080 ns) = 131.499 ns; Loc. = LAB_X18_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~33 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~35 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.579 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~37 311 COMB LAB_X18_Y10 2 " "Info: 311: + IC(0.000 ns) + CELL(0.080 ns) = 131.579 ns; Loc. = LAB_X18_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~35 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~37 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.659 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~39 312 COMB LAB_X18_Y10 2 " "Info: 312: + IC(0.000 ns) + CELL(0.080 ns) = 131.659 ns; Loc. = LAB_X18_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~37 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~39 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.739 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~41 313 COMB LAB_X18_Y10 2 " "Info: 313: + IC(0.000 ns) + CELL(0.080 ns) = 131.739 ns; Loc. = LAB_X18_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~39 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~41 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.819 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~43 314 COMB LAB_X18_Y10 2 " "Info: 314: + IC(0.000 ns) + CELL(0.080 ns) = 131.819 ns; Loc. = LAB_X18_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~41 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~43 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.899 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~45 315 COMB LAB_X18_Y10 2 " "Info: 315: + IC(0.000 ns) + CELL(0.080 ns) = 131.899 ns; Loc. = LAB_X18_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~43 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~45 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.979 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~47 316 COMB LAB_X18_Y10 2 " "Info: 316: + IC(0.000 ns) + CELL(0.080 ns) = 131.979 ns; Loc. = LAB_X18_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~45 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~47 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 132.059 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~49 317 COMB LAB_X18_Y10 2 " "Info: 317: + IC(0.000 ns) + CELL(0.080 ns) = 132.059 ns; Loc. = LAB_X18_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~47 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~49 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 132.139 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~51 318 COMB LAB_X18_Y10 2 " "Info: 318: + IC(0.000 ns) + CELL(0.080 ns) = 132.139 ns; Loc. = LAB_X18_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~51'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~49 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~51 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 132.597 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~52 319 COMB LAB_X18_Y10 1 " "Info: 319: + IC(0.000 ns) + CELL(0.458 ns) = 132.597 ns; Loc. = LAB_X18_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~52'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~51 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~52 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.178 ns) 133.507 ns Arkanoid:inst\|Equal6~2 320 COMB LAB_X19_Y10 2 " "Info: 320: + IC(0.732 ns) + CELL(0.178 ns) = 133.507 ns; Loc. = LAB_X19_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Equal6~2'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.910 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~52 Arkanoid:inst|Equal6~2 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.131 ns) + CELL(0.545 ns) 134.183 ns Arkanoid:inst\|Equal6~3 321 COMB LAB_X19_Y10 1 " "Info: 321: + IC(0.131 ns) + CELL(0.545 ns) = 134.183 ns; Loc. = LAB_X19_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|Equal6~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { Arkanoid:inst|Equal6~2 Arkanoid:inst|Equal6~3 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.354 ns) + CELL(0.322 ns) 134.859 ns Arkanoid:inst\|Equal6~7 322 COMB LAB_X19_Y10 1 " "Info: 322: + IC(0.354 ns) + CELL(0.322 ns) = 134.859 ns; Loc. = LAB_X19_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|Equal6~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { Arkanoid:inst|Equal6~3 Arkanoid:inst|Equal6~7 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.034 ns) + CELL(0.544 ns) 136.437 ns Arkanoid:inst\|Equal6~24 323 COMB LAB_X15_Y13 5 " "Info: 323: + IC(1.034 ns) + CELL(0.544 ns) = 136.437 ns; Loc. = LAB_X15_Y13; Fanout = 5; COMB Node = 'Arkanoid:inst\|Equal6~24'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.578 ns" { Arkanoid:inst|Equal6~7 Arkanoid:inst|Equal6~24 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.131 ns) + CELL(0.545 ns) 137.113 ns Arkanoid:inst\|WideNor0~4 324 COMB LAB_X15_Y13 4 " "Info: 324: + IC(0.131 ns) + CELL(0.545 ns) = 137.113 ns; Loc. = LAB_X15_Y13; Fanout = 4; COMB Node = 'Arkanoid:inst\|WideNor0~4'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { Arkanoid:inst|Equal6~24 Arkanoid:inst|WideNor0~4 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.131 ns) + CELL(0.545 ns) 137.789 ns Arkanoid:inst\|WideOr0~0 325 COMB LAB_X15_Y13 3 " "Info: 325: + IC(0.131 ns) + CELL(0.545 ns) = 137.789 ns; Loc. = LAB_X15_Y13; Fanout = 3; COMB Node = 'Arkanoid:inst\|WideOr0~0'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { Arkanoid:inst|WideNor0~4 Arkanoid:inst|WideOr0~0 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.521 ns) 139.033 ns Arkanoid:inst\|high~8 326 COMB LAB_X10_Y13 1 " "Info: 326: + IC(0.723 ns) + CELL(0.521 ns) = 139.033 ns; Loc. = LAB_X10_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|high~8'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.244 ns" { Arkanoid:inst|WideOr0~0 Arkanoid:inst|high~8 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 139.129 ns Arkanoid:inst\|hex3_\[5\] 327 REG LAB_X10_Y13 1 " "Info: 327: + IC(0.000 ns) + CELL(0.096 ns) = 139.129 ns; Loc. = LAB_X10_Y13; Fanout = 1; REG Node = 'Arkanoid:inst\|hex3_\[5\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { Arkanoid:inst|high~8 Arkanoid:inst|hex3_[5] } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "67.965 ns ( 48.85 % ) " "Info: Total cell delay = 67.965 ns ( 48.85 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "71.164 ns ( 51.15 % ) " "Info: Total interconnect delay = 71.164 ns ( 51.15 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "139.129 ns" { Arkanoid:inst|button2_state Arkanoid:inst|platform2_position~4 Arkanoid:inst|platform2_position~5 Arkanoid:inst|Add4~1 Arkanoid:inst|Add4~3 Arkanoid:inst|Add4~5 Arkanoid:inst|Add4~7 Arkanoid:inst|Add4~9 Arkanoid:inst|Add4~11 Arkanoid:inst|Add4~13 Arkanoid:inst|Add4~15 Arkanoid:inst|Add4~17 Arkanoid:inst|Add4~19 Arkanoid:inst|Add4~21 Arkanoid:inst|Add4~23 Arkanoid:inst|Add4~25 Arkanoid:inst|Add4~27 Arkanoid:inst|Add4~29 Arkanoid:inst|Add4~31 Arkanoid:inst|Add4~33 Arkanoid:inst|Add4~35 Arkanoid:inst|Add4~37 Arkanoid:inst|Add4~39 Arkanoid:inst|Add4~41 Arkanoid:inst|Add4~43 Arkanoid:inst|Add4~45 Arkanoid:inst|Add4~47 Arkanoid:inst|Add4~49 Arkanoid:inst|Add4~51 Arkanoid:inst|Add4~53 Arkanoid:inst|Add4~54 Arkanoid:inst|platform2_position~29 Arkanoid:inst|LessThan3~3 Arkanoid:inst|LessThan3~4 Arkanoid:inst|LessThan3~10 Arkanoid:inst|Add5~1 Arkanoid:inst|Add5~2 Arkanoid:inst|platform2_position~48 Arkanoid:inst|Add7~3 Arkanoid:inst|Add7~4 Arkanoid:inst|LessThan139~5 Arkanoid:inst|LessThan139~7 Arkanoid:inst|LessThan139~9 Arkanoid:inst|LessThan139~11 Arkanoid:inst|LessThan139~13 Arkanoid:inst|LessThan139~15 Arkanoid:inst|LessThan139~17 Arkanoid:inst|LessThan139~19 Arkanoid:inst|LessThan139~21 Arkanoid:inst|LessThan139~23 Arkanoid:inst|LessThan139~25 Arkanoid:inst|LessThan139~27 Arkanoid:inst|LessThan139~29 Arkanoid:inst|LessThan139~31 Arkanoid:inst|LessThan139~33 Arkanoid:inst|LessThan139~35 Arkanoid:inst|LessThan139~37 Arkanoid:inst|LessThan139~39 Arkanoid:inst|LessThan139~41 Arkanoid:inst|LessThan139~43 Arkanoid:inst|LessThan139~45 Arkanoid:inst|LessThan139~47 Arkanoid:inst|LessThan139~49 Arkanoid:inst|LessThan139~51 Arkanoid:inst|LessThan139~53 Arkanoid:inst|LessThan139~55 Arkanoid:inst|LessThan139~57 Arkanoid:inst|LessThan139~59 Arkanoid:inst|LessThan139~61 Arkanoid:inst|LessThan139~62 Arkanoid:inst|always2~5 Arkanoid:inst|Add9~1 Arkanoid:inst|Add9~3 Arkanoid:inst|Add9~5 Arkanoid:inst|Add9~7 Arkanoid:inst|Add9~9 Arkanoid:inst|Add9~11 Arkanoid:inst|Add9~13 Arkanoid:inst|Add9~15 Arkanoid:inst|Add9~17 Arkanoid:inst|Add9~19 Arkanoid:inst|Add9~21 Arkanoid:inst|Add9~23 Arkanoid:inst|Add9~25 Arkanoid:inst|Add9~27 Arkanoid:inst|Add9~29 Arkanoid:inst|Add9~31 Arkanoid:inst|Add9~33 Arkanoid:inst|Add9~35 Arkanoid:inst|Add9~37 Arkanoid:inst|Add9~39 Arkanoid:inst|Add9~41 Arkanoid:inst|Add9~43 Arkanoid:inst|Add9~45 Arkanoid:inst|Add9~47 Arkanoid:inst|Add9~49 Arkanoid:inst|Add9~51 Arkanoid:inst|Add9~53 Arkanoid:inst|Add9~55 Arkanoid:inst|Add9~57 Arkanoid:inst|Add9~59 Arkanoid:inst|Add9~61 Arkanoid:inst|Add9~63 Arkanoid:inst|lpm_divide:Mod0|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[0]~0 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~56 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[18]~111 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[24]~121 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[30]~129 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~137 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[42]~145 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[48]~153 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[57]~339 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[63]~341 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[66]~177 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[76]~344 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[82]~186 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[88]~194 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[90]~209 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[96]~217 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~225 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[108]~233 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[114]~241 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~244 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[128]~252 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[134]~260 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[140]~268 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~276 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[152]~284 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[158]~292 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[164]~300 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[170]~308 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~316 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[182]~324 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~33 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~35 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~37 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~39 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~41 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~43 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~45 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~47 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~49 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~51 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~52 Arkanoid:inst|Equal6~2 Arkanoid:inst|Equal6~3 Arkanoid:inst|Equal6~7 Arkanoid:inst|Equal6~24 Arkanoid:inst|WideNor0~4 Arkanoid:inst|WideOr0~0 Arkanoid:inst|high~8 Arkanoid:inst|hex3_[5] } "NODE_NAME" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "13 " "Info: Average interconnect usage is 13% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "26 X25_Y14 X37_Y27 " "Info: Peak interconnect usage is 26% of the available device resources in the region that extends from location X25_Y14 to location X37_Y27" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:08 " "Info: Fitter routing operations ending: elapsed time is 00:00:08" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
+{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "50 " "Warning: Found 50 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "h_sync 0 " "Info: Pin \"h_sync\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "v_sync 0 " "Info: Pin \"v_sync\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "blue\[3\] 0 " "Info: Pin \"blue\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "blue\[2\] 0 " "Info: Pin \"blue\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "blue\[1\] 0 " "Info: Pin \"blue\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "blue\[0\] 0 " "Info: Pin \"blue\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "green\[3\] 0 " "Info: Pin \"green\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "green\[2\] 0 " "Info: Pin \"green\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "green\[1\] 0 " "Info: Pin \"green\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "green\[0\] 0 " "Info: Pin \"green\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[6\] 0 " "Info: Pin \"hex0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[5\] 0 " "Info: Pin \"hex0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[4\] 0 " "Info: Pin \"hex0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[3\] 0 " "Info: Pin \"hex0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[2\] 0 " "Info: Pin \"hex0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[1\] 0 " "Info: Pin \"hex0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[0\] 0 " "Info: Pin \"hex0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[6\] 0 " "Info: Pin \"hex1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[5\] 0 " "Info: Pin \"hex1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[4\] 0 " "Info: Pin \"hex1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[3\] 0 " "Info: Pin \"hex1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[2\] 0 " "Info: Pin \"hex1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[1\] 0 " "Info: Pin \"hex1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[0\] 0 " "Info: Pin \"hex1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex2\[6\] 0 " "Info: Pin \"hex2\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex2\[5\] 0 " "Info: Pin \"hex2\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex2\[4\] 0 " "Info: Pin \"hex2\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex2\[3\] 0 " "Info: Pin \"hex2\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex2\[2\] 0 " "Info: Pin \"hex2\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex2\[1\] 0 " "Info: Pin \"hex2\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex2\[0\] 0 " "Info: Pin \"hex2\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex3\[6\] 0 " "Info: Pin \"hex3\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex3\[5\] 0 " "Info: Pin \"hex3\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex3\[4\] 0 " "Info: Pin \"hex3\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex3\[3\] 0 " "Info: Pin \"hex3\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex3\[2\] 0 " "Info: Pin \"hex3\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex3\[1\] 0 " "Info: Pin \"hex3\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex3\[0\] 0 " "Info: Pin \"hex3\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[7\] 0 " "Info: Pin \"led\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[6\] 0 " "Info: Pin \"led\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[5\] 0 " "Info: Pin \"led\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[4\] 0 " "Info: Pin \"led\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[3\] 0 " "Info: Pin \"led\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[2\] 0 " "Info: Pin \"led\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[1\] 0 " "Info: Pin \"led\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[0\] 0 " "Info: Pin \"led\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "red\[3\] 0 " "Info: Pin \"red\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "red\[2\] 0 " "Info: Pin \"red\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "red\[1\] 0 " "Info: Pin \"red\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "red\[0\] 0 " "Info: Pin \"red\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "G:/Verilog/Arkanoid2PDE1/myArkanoid.fit.smsg " "Info: Generated suppressed messages file G:/Verilog/Arkanoid2PDE1/myArkanoid.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "266 " "Info: Peak virtual memory: 266 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 28 14:22:27 2012 " "Info: Processing ended: Mon May 28 14:22:27 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Info: Elapsed time: 00:00:28" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:31 " "Info: Total CPU time (on all processors): 00:00:31" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/db/myArkanoid.hier_info b/db/myArkanoid.hier_info
new file mode 100644
index 0000000..659f6cf
--- /dev/null
+++ b/db/myArkanoid.hier_info
@@ -0,0 +1,2470 @@
+|TotalScheme
+h_sync <= Arkanoid:inst.h_sync
+clk_50MHz => ClockDivider:inst1.clk50MHz
+button1 => Debouncer:inst2.noisy
+button2 => Debouncer:inst3.noisy
+button3 => Debouncer:inst4.noisy
+button4 => Debouncer:inst5.noisy
+v_sync <= Arkanoid:inst.v_sync
+blue[0] <= Arkanoid:inst.blue[0]
+blue[1] <= Arkanoid:inst.blue[1]
+blue[2] <= Arkanoid:inst.blue[2]
+blue[3] <= Arkanoid:inst.blue[3]
+green[0] <= Arkanoid:inst.green[0]
+green[1] <= Arkanoid:inst.green[1]
+green[2] <= Arkanoid:inst.green[2]
+green[3] <= Arkanoid:inst.green[3]
+hex0[0] <= Arkanoid:inst.hex0[0]
+hex0[1] <= Arkanoid:inst.hex0[1]
+hex0[2] <= Arkanoid:inst.hex0[2]
+hex0[3] <= Arkanoid:inst.hex0[3]
+hex0[4] <= Arkanoid:inst.hex0[4]
+hex0[5] <= Arkanoid:inst.hex0[5]
+hex0[6] <= Arkanoid:inst.hex0[6]
+hex1[0] <= Arkanoid:inst.hex1[0]
+hex1[1] <= Arkanoid:inst.hex1[1]
+hex1[2] <= Arkanoid:inst.hex1[2]
+hex1[3] <= Arkanoid:inst.hex1[3]
+hex1[4] <= Arkanoid:inst.hex1[4]
+hex1[5] <= Arkanoid:inst.hex1[5]
+hex1[6] <= Arkanoid:inst.hex1[6]
+hex2[0] <= Arkanoid:inst.hex2[0]
+hex2[1] <= Arkanoid:inst.hex2[1]
+hex2[2] <= Arkanoid:inst.hex2[2]
+hex2[3] <= Arkanoid:inst.hex2[3]
+hex2[4] <= Arkanoid:inst.hex2[4]
+hex2[5] <= Arkanoid:inst.hex2[5]
+hex2[6] <= Arkanoid:inst.hex2[6]
+hex3[0] <= Arkanoid:inst.hex3[0]
+hex3[1] <= Arkanoid:inst.hex3[1]
+hex3[2] <= Arkanoid:inst.hex3[2]
+hex3[3] <= Arkanoid:inst.hex3[3]
+hex3[4] <= Arkanoid:inst.hex3[4]
+hex3[5] <= Arkanoid:inst.hex3[5]
+hex3[6] <= Arkanoid:inst.hex3[6]
+led[0] <= Arkanoid:inst.led[0]
+led[1] <= Arkanoid:inst.led[1]
+led[2] <= Arkanoid:inst.led[2]
+led[3] <= Arkanoid:inst.led[3]
+led[4] <= Arkanoid:inst.led[4]
+led[5] <= Arkanoid:inst.led[5]
+led[6] <= Arkanoid:inst.led[6]
+led[7] <= Arkanoid:inst.led[7]
+red[0] <= Arkanoid:inst.red[0]
+red[1] <= Arkanoid:inst.red[1]
+red[2] <= Arkanoid:inst.red[2]
+red[3] <= Arkanoid:inst.red[3]
+
+
+|TotalScheme|Arkanoid:inst
+clk25MHz => blue_[0].CLK
+clk25MHz => blue_[1].CLK
+clk25MHz => blue_[2].CLK
+clk25MHz => blue_[3].CLK
+clk25MHz => green_[0].CLK
+clk25MHz => green_[1].CLK
+clk25MHz => green_[2].CLK
+clk25MHz => green_[3].CLK
+clk25MHz => red_[0].CLK
+clk25MHz => red_[1].CLK
+clk25MHz => red_[2].CLK
+clk25MHz => red_[3].CLK
+clk25MHz => hex0_[0].CLK
+clk25MHz => hex0_[1].CLK
+clk25MHz => hex0_[2].CLK
+clk25MHz => hex0_[3].CLK
+clk25MHz => hex0_[4].CLK
+clk25MHz => hex0_[5].CLK
+clk25MHz => hex0_[6].CLK
+clk25MHz => hex1_[0].CLK
+clk25MHz => hex1_[1].CLK
+clk25MHz => hex1_[2].CLK
+clk25MHz => hex1_[3].CLK
+clk25MHz => hex1_[4].CLK
+clk25MHz => hex1_[5].CLK
+clk25MHz => hex1_[6].CLK
+clk25MHz => hex2_[0].CLK
+clk25MHz => hex2_[1].CLK
+clk25MHz => hex2_[2].CLK
+clk25MHz => hex2_[3].CLK
+clk25MHz => hex2_[4].CLK
+clk25MHz => hex2_[5].CLK
+clk25MHz => hex2_[6].CLK
+clk25MHz => hex3_[0].CLK
+clk25MHz => hex3_[1].CLK
+clk25MHz => hex3_[2].CLK
+clk25MHz => hex3_[3].CLK
+clk25MHz => hex3_[4].CLK
+clk25MHz => hex3_[5].CLK
+clk25MHz => hex3_[6].CLK
+clk25MHz => player2_score[0].CLK
+clk25MHz => player2_score[1].CLK
+clk25MHz => player2_score[2].CLK
+clk25MHz => player2_score[3].CLK
+clk25MHz => player2_score[4].CLK
+clk25MHz => player2_score[5].CLK
+clk25MHz => player2_score[6].CLK
+clk25MHz => player2_score[7].CLK
+clk25MHz => player2_score[8].CLK
+clk25MHz => player2_score[9].CLK
+clk25MHz => player2_score[10].CLK
+clk25MHz => player2_score[11].CLK
+clk25MHz => player2_score[12].CLK
+clk25MHz => player2_score[13].CLK
+clk25MHz => player2_score[14].CLK
+clk25MHz => player2_score[15].CLK
+clk25MHz => player2_score[16].CLK
+clk25MHz => player2_score[17].CLK
+clk25MHz => player2_score[18].CLK
+clk25MHz => player2_score[19].CLK
+clk25MHz => player2_score[20].CLK
+clk25MHz => player2_score[21].CLK
+clk25MHz => player2_score[22].CLK
+clk25MHz => player2_score[23].CLK
+clk25MHz => player2_score[24].CLK
+clk25MHz => player2_score[25].CLK
+clk25MHz => player2_score[26].CLK
+clk25MHz => player2_score[27].CLK
+clk25MHz => player2_score[28].CLK
+clk25MHz => player2_score[29].CLK
+clk25MHz => player2_score[30].CLK
+clk25MHz => player2_score[31].CLK
+clk25MHz => player1_score[0].CLK
+clk25MHz => player1_score[1].CLK
+clk25MHz => player1_score[2].CLK
+clk25MHz => player1_score[3].CLK
+clk25MHz => player1_score[4].CLK
+clk25MHz => player1_score[5].CLK
+clk25MHz => player1_score[6].CLK
+clk25MHz => player1_score[7].CLK
+clk25MHz => player1_score[8].CLK
+clk25MHz => player1_score[9].CLK
+clk25MHz => player1_score[10].CLK
+clk25MHz => player1_score[11].CLK
+clk25MHz => player1_score[12].CLK
+clk25MHz => player1_score[13].CLK
+clk25MHz => player1_score[14].CLK
+clk25MHz => player1_score[15].CLK
+clk25MHz => player1_score[16].CLK
+clk25MHz => player1_score[17].CLK
+clk25MHz => player1_score[18].CLK
+clk25MHz => player1_score[19].CLK
+clk25MHz => player1_score[20].CLK
+clk25MHz => player1_score[21].CLK
+clk25MHz => player1_score[22].CLK
+clk25MHz => player1_score[23].CLK
+clk25MHz => player1_score[24].CLK
+clk25MHz => player1_score[25].CLK
+clk25MHz => player1_score[26].CLK
+clk25MHz => player1_score[27].CLK
+clk25MHz => player1_score[28].CLK
+clk25MHz => player1_score[29].CLK
+clk25MHz => player1_score[30].CLK
+clk25MHz => player1_score[31].CLK
+clk25MHz => ball_clock_counter[0].CLK
+clk25MHz => ball_clock_counter[1].CLK
+clk25MHz => ball_clock_counter[2].CLK
+clk25MHz => ball_clock_counter[3].CLK
+clk25MHz => ball_clock_counter[4].CLK
+clk25MHz => ball_clock_counter[5].CLK
+clk25MHz => ball_clock_counter[6].CLK
+clk25MHz => ball_clock_counter[7].CLK
+clk25MHz => ball_clock_counter[8].CLK
+clk25MHz => ball_clock_counter[9].CLK
+clk25MHz => ball_clock_counter[10].CLK
+clk25MHz => ball_clock_counter[11].CLK
+clk25MHz => ball_clock_counter[12].CLK
+clk25MHz => ball_clock_counter[13].CLK
+clk25MHz => ball_clock_counter[14].CLK
+clk25MHz => ball_clock_counter[15].CLK
+clk25MHz => ball_clock_counter[16].CLK
+clk25MHz => ball_clock_counter[17].CLK
+clk25MHz => ball_clock_counter[18].CLK
+clk25MHz => ball_clock_counter[19].CLK
+clk25MHz => ball_clock_counter[20].CLK
+clk25MHz => ball_clock_counter[21].CLK
+clk25MHz => ball_clock_counter[22].CLK
+clk25MHz => ball_clock_counter[23].CLK
+clk25MHz => ball_clock_counter[24].CLK
+clk25MHz => ball_clock_counter[25].CLK
+clk25MHz => ball_clock_counter[26].CLK
+clk25MHz => ball_clock_counter[27].CLK
+clk25MHz => ball_clock_counter[28].CLK
+clk25MHz => ball_clock_counter[29].CLK
+clk25MHz => ball_clock_counter[30].CLK
+clk25MHz => ball_clock_counter[31].CLK
+clk25MHz => field[22][31][0].CLK
+clk25MHz => field[22][31][1].CLK
+clk25MHz => field[22][30][0].CLK
+clk25MHz => field[22][30][1].CLK
+clk25MHz => field[22][29][0].CLK
+clk25MHz => field[22][29][1].CLK
+clk25MHz => field[22][28][0].CLK
+clk25MHz => field[22][28][1].CLK
+clk25MHz => field[22][27][0].CLK
+clk25MHz => field[22][27][1].CLK
+clk25MHz => field[22][26][0].CLK
+clk25MHz => field[22][26][1].CLK
+clk25MHz => field[22][25][0].CLK
+clk25MHz => field[22][25][1].CLK
+clk25MHz => field[22][24][0].CLK
+clk25MHz => field[22][24][1].CLK
+clk25MHz => field[22][23][0].CLK
+clk25MHz => field[22][23][1].CLK
+clk25MHz => field[22][22][0].CLK
+clk25MHz => field[22][22][1].CLK
+clk25MHz => field[22][21][0].CLK
+clk25MHz => field[22][21][1].CLK
+clk25MHz => field[22][20][0].CLK
+clk25MHz => field[22][20][1].CLK
+clk25MHz => field[22][19][0].CLK
+clk25MHz => field[22][19][1].CLK
+clk25MHz => field[22][18][0].CLK
+clk25MHz => field[22][18][1].CLK
+clk25MHz => field[22][17][0].CLK
+clk25MHz => field[22][17][1].CLK
+clk25MHz => field[22][16][0].CLK
+clk25MHz => field[22][16][1].CLK
+clk25MHz => field[22][15][0].CLK
+clk25MHz => field[22][15][1].CLK
+clk25MHz => field[22][14][0].CLK
+clk25MHz => field[22][14][1].CLK
+clk25MHz => field[22][13][0].CLK
+clk25MHz => field[22][13][1].CLK
+clk25MHz => field[22][12][0].CLK
+clk25MHz => field[22][12][1].CLK
+clk25MHz => field[22][11][0].CLK
+clk25MHz => field[22][11][1].CLK
+clk25MHz => field[22][10][0].CLK
+clk25MHz => field[22][10][1].CLK
+clk25MHz => field[22][9][0].CLK
+clk25MHz => field[22][9][1].CLK
+clk25MHz => field[22][8][0].CLK
+clk25MHz => field[22][8][1].CLK
+clk25MHz => field[22][7][0].CLK
+clk25MHz => field[22][7][1].CLK
+clk25MHz => field[22][6][0].CLK
+clk25MHz => field[22][6][1].CLK
+clk25MHz => field[22][5][0].CLK
+clk25MHz => field[22][5][1].CLK
+clk25MHz => field[22][4][0].CLK
+clk25MHz => field[22][4][1].CLK
+clk25MHz => field[22][3][0].CLK
+clk25MHz => field[22][3][1].CLK
+clk25MHz => field[22][2][0].CLK
+clk25MHz => field[22][2][1].CLK
+clk25MHz => field[22][1][0].CLK
+clk25MHz => field[22][1][1].CLK
+clk25MHz => field[22][0][0].CLK
+clk25MHz => field[22][0][1].CLK
+clk25MHz => field[21][31][0].CLK
+clk25MHz => field[21][31][1].CLK
+clk25MHz => field[21][30][0].CLK
+clk25MHz => field[21][30][1].CLK
+clk25MHz => field[21][29][0].CLK
+clk25MHz => field[21][29][1].CLK
+clk25MHz => field[21][28][0].CLK
+clk25MHz => field[21][28][1].CLK
+clk25MHz => field[21][27][0].CLK
+clk25MHz => field[21][27][1].CLK
+clk25MHz => field[21][26][0].CLK
+clk25MHz => field[21][26][1].CLK
+clk25MHz => field[21][25][0].CLK
+clk25MHz => field[21][25][1].CLK
+clk25MHz => field[21][24][0].CLK
+clk25MHz => field[21][24][1].CLK
+clk25MHz => field[21][23][0].CLK
+clk25MHz => field[21][23][1].CLK
+clk25MHz => field[21][22][0].CLK
+clk25MHz => field[21][22][1].CLK
+clk25MHz => field[21][21][0].CLK
+clk25MHz => field[21][21][1].CLK
+clk25MHz => field[21][20][0].CLK
+clk25MHz => field[21][20][1].CLK
+clk25MHz => field[21][19][0].CLK
+clk25MHz => field[21][19][1].CLK
+clk25MHz => field[21][18][0].CLK
+clk25MHz => field[21][18][1].CLK
+clk25MHz => field[21][17][0].CLK
+clk25MHz => field[21][17][1].CLK
+clk25MHz => field[21][16][0].CLK
+clk25MHz => field[21][16][1].CLK
+clk25MHz => field[21][15][0].CLK
+clk25MHz => field[21][15][1].CLK
+clk25MHz => field[21][14][0].CLK
+clk25MHz => field[21][14][1].CLK
+clk25MHz => field[21][13][0].CLK
+clk25MHz => field[21][13][1].CLK
+clk25MHz => field[21][12][0].CLK
+clk25MHz => field[21][12][1].CLK
+clk25MHz => field[21][11][0].CLK
+clk25MHz => field[21][11][1].CLK
+clk25MHz => field[21][10][0].CLK
+clk25MHz => field[21][10][1].CLK
+clk25MHz => field[21][9][0].CLK
+clk25MHz => field[21][9][1].CLK
+clk25MHz => field[21][8][0].CLK
+clk25MHz => field[21][8][1].CLK
+clk25MHz => field[21][7][0].CLK
+clk25MHz => field[21][7][1].CLK
+clk25MHz => field[21][6][0].CLK
+clk25MHz => field[21][6][1].CLK
+clk25MHz => field[21][5][0].CLK
+clk25MHz => field[21][5][1].CLK
+clk25MHz => field[21][4][0].CLK
+clk25MHz => field[21][4][1].CLK
+clk25MHz => field[21][3][0].CLK
+clk25MHz => field[21][3][1].CLK
+clk25MHz => field[21][2][0].CLK
+clk25MHz => field[21][2][1].CLK
+clk25MHz => field[21][1][0].CLK
+clk25MHz => field[21][1][1].CLK
+clk25MHz => field[21][0][0].CLK
+clk25MHz => field[21][0][1].CLK
+clk25MHz => field[20][31][0].CLK
+clk25MHz => field[20][31][1].CLK
+clk25MHz => field[20][30][0].CLK
+clk25MHz => field[20][30][1].CLK
+clk25MHz => field[20][29][0].CLK
+clk25MHz => field[20][29][1].CLK
+clk25MHz => field[20][28][0].CLK
+clk25MHz => field[20][28][1].CLK
+clk25MHz => field[20][27][0].CLK
+clk25MHz => field[20][27][1].CLK
+clk25MHz => field[20][26][0].CLK
+clk25MHz => field[20][26][1].CLK
+clk25MHz => field[20][25][0].CLK
+clk25MHz => field[20][25][1].CLK
+clk25MHz => field[20][24][0].CLK
+clk25MHz => field[20][24][1].CLK
+clk25MHz => field[20][23][0].CLK
+clk25MHz => field[20][23][1].CLK
+clk25MHz => field[20][22][0].CLK
+clk25MHz => field[20][22][1].CLK
+clk25MHz => field[20][21][0].CLK
+clk25MHz => field[20][21][1].CLK
+clk25MHz => field[20][20][0].CLK
+clk25MHz => field[20][20][1].CLK
+clk25MHz => field[20][19][0].CLK
+clk25MHz => field[20][19][1].CLK
+clk25MHz => field[20][18][0].CLK
+clk25MHz => field[20][18][1].CLK
+clk25MHz => field[20][17][0].CLK
+clk25MHz => field[20][17][1].CLK
+clk25MHz => field[20][16][0].CLK
+clk25MHz => field[20][16][1].CLK
+clk25MHz => field[20][15][0].CLK
+clk25MHz => field[20][15][1].CLK
+clk25MHz => field[20][14][0].CLK
+clk25MHz => field[20][14][1].CLK
+clk25MHz => field[20][13][0].CLK
+clk25MHz => field[20][13][1].CLK
+clk25MHz => field[20][12][0].CLK
+clk25MHz => field[20][12][1].CLK
+clk25MHz => field[20][11][0].CLK
+clk25MHz => field[20][11][1].CLK
+clk25MHz => field[20][10][0].CLK
+clk25MHz => field[20][10][1].CLK
+clk25MHz => field[20][9][0].CLK
+clk25MHz => field[20][9][1].CLK
+clk25MHz => field[20][8][0].CLK
+clk25MHz => field[20][8][1].CLK
+clk25MHz => field[20][7][0].CLK
+clk25MHz => field[20][7][1].CLK
+clk25MHz => field[20][6][0].CLK
+clk25MHz => field[20][6][1].CLK
+clk25MHz => field[20][5][0].CLK
+clk25MHz => field[20][5][1].CLK
+clk25MHz => field[20][4][0].CLK
+clk25MHz => field[20][4][1].CLK
+clk25MHz => field[20][3][0].CLK
+clk25MHz => field[20][3][1].CLK
+clk25MHz => field[20][2][0].CLK
+clk25MHz => field[20][2][1].CLK
+clk25MHz => field[20][1][0].CLK
+clk25MHz => field[20][1][1].CLK
+clk25MHz => field[20][0][0].CLK
+clk25MHz => field[20][0][1].CLK
+clk25MHz => field[19][31][0].CLK
+clk25MHz => field[19][31][1].CLK
+clk25MHz => field[19][30][0].CLK
+clk25MHz => field[19][30][1].CLK
+clk25MHz => field[19][29][0].CLK
+clk25MHz => field[19][29][1].CLK
+clk25MHz => field[19][28][0].CLK
+clk25MHz => field[19][28][1].CLK
+clk25MHz => field[19][27][0].CLK
+clk25MHz => field[19][27][1].CLK
+clk25MHz => field[19][26][0].CLK
+clk25MHz => field[19][26][1].CLK
+clk25MHz => field[19][25][0].CLK
+clk25MHz => field[19][25][1].CLK
+clk25MHz => field[19][24][0].CLK
+clk25MHz => field[19][24][1].CLK
+clk25MHz => field[19][23][0].CLK
+clk25MHz => field[19][23][1].CLK
+clk25MHz => field[19][22][0].CLK
+clk25MHz => field[19][22][1].CLK
+clk25MHz => field[19][21][0].CLK
+clk25MHz => field[19][21][1].CLK
+clk25MHz => field[19][20][0].CLK
+clk25MHz => field[19][20][1].CLK
+clk25MHz => field[19][19][0].CLK
+clk25MHz => field[19][19][1].CLK
+clk25MHz => field[19][18][0].CLK
+clk25MHz => field[19][18][1].CLK
+clk25MHz => field[19][17][0].CLK
+clk25MHz => field[19][17][1].CLK
+clk25MHz => field[19][16][0].CLK
+clk25MHz => field[19][16][1].CLK
+clk25MHz => field[19][15][0].CLK
+clk25MHz => field[19][15][1].CLK
+clk25MHz => field[19][14][0].CLK
+clk25MHz => field[19][14][1].CLK
+clk25MHz => field[19][13][0].CLK
+clk25MHz => field[19][13][1].CLK
+clk25MHz => field[19][12][0].CLK
+clk25MHz => field[19][12][1].CLK
+clk25MHz => field[19][11][0].CLK
+clk25MHz => field[19][11][1].CLK
+clk25MHz => field[19][10][0].CLK
+clk25MHz => field[19][10][1].CLK
+clk25MHz => field[19][9][0].CLK
+clk25MHz => field[19][9][1].CLK
+clk25MHz => field[19][8][0].CLK
+clk25MHz => field[19][8][1].CLK
+clk25MHz => field[19][7][0].CLK
+clk25MHz => field[19][7][1].CLK
+clk25MHz => field[19][6][0].CLK
+clk25MHz => field[19][6][1].CLK
+clk25MHz => field[19][5][0].CLK
+clk25MHz => field[19][5][1].CLK
+clk25MHz => field[19][4][0].CLK
+clk25MHz => field[19][4][1].CLK
+clk25MHz => field[19][3][0].CLK
+clk25MHz => field[19][3][1].CLK
+clk25MHz => field[19][2][0].CLK
+clk25MHz => field[19][2][1].CLK
+clk25MHz => field[19][1][0].CLK
+clk25MHz => field[19][1][1].CLK
+clk25MHz => field[19][0][0].CLK
+clk25MHz => field[19][0][1].CLK
+clk25MHz => field[18][31][0].CLK
+clk25MHz => field[18][31][1].CLK
+clk25MHz => field[18][30][0].CLK
+clk25MHz => field[18][30][1].CLK
+clk25MHz => field[18][29][0].CLK
+clk25MHz => field[18][29][1].CLK
+clk25MHz => field[18][28][0].CLK
+clk25MHz => field[18][28][1].CLK
+clk25MHz => field[18][27][0].CLK
+clk25MHz => field[18][27][1].CLK
+clk25MHz => field[18][26][0].CLK
+clk25MHz => field[18][26][1].CLK
+clk25MHz => field[18][25][0].CLK
+clk25MHz => field[18][25][1].CLK
+clk25MHz => field[18][24][0].CLK
+clk25MHz => field[18][24][1].CLK
+clk25MHz => field[18][23][0].CLK
+clk25MHz => field[18][23][1].CLK
+clk25MHz => field[18][22][0].CLK
+clk25MHz => field[18][22][1].CLK
+clk25MHz => field[18][21][0].CLK
+clk25MHz => field[18][21][1].CLK
+clk25MHz => field[18][20][0].CLK
+clk25MHz => field[18][20][1].CLK
+clk25MHz => field[18][19][0].CLK
+clk25MHz => field[18][19][1].CLK
+clk25MHz => field[18][18][0].CLK
+clk25MHz => field[18][18][1].CLK
+clk25MHz => field[18][17][0].CLK
+clk25MHz => field[18][17][1].CLK
+clk25MHz => field[18][16][0].CLK
+clk25MHz => field[18][16][1].CLK
+clk25MHz => field[18][15][0].CLK
+clk25MHz => field[18][15][1].CLK
+clk25MHz => field[18][14][0].CLK
+clk25MHz => field[18][14][1].CLK
+clk25MHz => field[18][13][0].CLK
+clk25MHz => field[18][13][1].CLK
+clk25MHz => field[18][12][0].CLK
+clk25MHz => field[18][12][1].CLK
+clk25MHz => field[18][11][0].CLK
+clk25MHz => field[18][11][1].CLK
+clk25MHz => field[18][10][0].CLK
+clk25MHz => field[18][10][1].CLK
+clk25MHz => field[18][9][0].CLK
+clk25MHz => field[18][9][1].CLK
+clk25MHz => field[18][8][0].CLK
+clk25MHz => field[18][8][1].CLK
+clk25MHz => field[18][7][0].CLK
+clk25MHz => field[18][7][1].CLK
+clk25MHz => field[18][6][0].CLK
+clk25MHz => field[18][6][1].CLK
+clk25MHz => field[18][5][0].CLK
+clk25MHz => field[18][5][1].CLK
+clk25MHz => field[18][4][0].CLK
+clk25MHz => field[18][4][1].CLK
+clk25MHz => field[18][3][0].CLK
+clk25MHz => field[18][3][1].CLK
+clk25MHz => field[18][2][0].CLK
+clk25MHz => field[18][2][1].CLK
+clk25MHz => field[18][1][0].CLK
+clk25MHz => field[18][1][1].CLK
+clk25MHz => field[18][0][0].CLK
+clk25MHz => field[18][0][1].CLK
+clk25MHz => field[17][31][0].CLK
+clk25MHz => field[17][31][1].CLK
+clk25MHz => field[17][30][0].CLK
+clk25MHz => field[17][30][1].CLK
+clk25MHz => field[17][29][0].CLK
+clk25MHz => field[17][29][1].CLK
+clk25MHz => field[17][28][0].CLK
+clk25MHz => field[17][28][1].CLK
+clk25MHz => field[17][27][0].CLK
+clk25MHz => field[17][27][1].CLK
+clk25MHz => field[17][26][0].CLK
+clk25MHz => field[17][26][1].CLK
+clk25MHz => field[17][25][0].CLK
+clk25MHz => field[17][25][1].CLK
+clk25MHz => field[17][24][0].CLK
+clk25MHz => field[17][24][1].CLK
+clk25MHz => field[17][23][0].CLK
+clk25MHz => field[17][23][1].CLK
+clk25MHz => field[17][22][0].CLK
+clk25MHz => field[17][22][1].CLK
+clk25MHz => field[17][21][0].CLK
+clk25MHz => field[17][21][1].CLK
+clk25MHz => field[17][20][0].CLK
+clk25MHz => field[17][20][1].CLK
+clk25MHz => field[17][19][0].CLK
+clk25MHz => field[17][19][1].CLK
+clk25MHz => field[17][18][0].CLK
+clk25MHz => field[17][18][1].CLK
+clk25MHz => field[17][17][0].CLK
+clk25MHz => field[17][17][1].CLK
+clk25MHz => field[17][16][0].CLK
+clk25MHz => field[17][16][1].CLK
+clk25MHz => field[17][15][0].CLK
+clk25MHz => field[17][15][1].CLK
+clk25MHz => field[17][14][0].CLK
+clk25MHz => field[17][14][1].CLK
+clk25MHz => field[17][13][0].CLK
+clk25MHz => field[17][13][1].CLK
+clk25MHz => field[17][12][0].CLK
+clk25MHz => field[17][12][1].CLK
+clk25MHz => field[17][11][0].CLK
+clk25MHz => field[17][11][1].CLK
+clk25MHz => field[17][10][0].CLK
+clk25MHz => field[17][10][1].CLK
+clk25MHz => field[17][9][0].CLK
+clk25MHz => field[17][9][1].CLK
+clk25MHz => field[17][8][0].CLK
+clk25MHz => field[17][8][1].CLK
+clk25MHz => field[17][7][0].CLK
+clk25MHz => field[17][7][1].CLK
+clk25MHz => field[17][6][0].CLK
+clk25MHz => field[17][6][1].CLK
+clk25MHz => field[17][5][0].CLK
+clk25MHz => field[17][5][1].CLK
+clk25MHz => field[17][4][0].CLK
+clk25MHz => field[17][4][1].CLK
+clk25MHz => field[17][3][0].CLK
+clk25MHz => field[17][3][1].CLK
+clk25MHz => field[17][2][0].CLK
+clk25MHz => field[17][2][1].CLK
+clk25MHz => field[17][1][0].CLK
+clk25MHz => field[17][1][1].CLK
+clk25MHz => field[17][0][0].CLK
+clk25MHz => field[17][0][1].CLK
+clk25MHz => field[16][31][0].CLK
+clk25MHz => field[16][31][1].CLK
+clk25MHz => field[16][30][0].CLK
+clk25MHz => field[16][30][1].CLK
+clk25MHz => field[16][29][0].CLK
+clk25MHz => field[16][29][1].CLK
+clk25MHz => field[16][28][0].CLK
+clk25MHz => field[16][28][1].CLK
+clk25MHz => field[16][27][0].CLK
+clk25MHz => field[16][27][1].CLK
+clk25MHz => field[16][26][0].CLK
+clk25MHz => field[16][26][1].CLK
+clk25MHz => field[16][25][0].CLK
+clk25MHz => field[16][25][1].CLK
+clk25MHz => field[16][24][0].CLK
+clk25MHz => field[16][24][1].CLK
+clk25MHz => field[16][23][0].CLK
+clk25MHz => field[16][23][1].CLK
+clk25MHz => field[16][22][0].CLK
+clk25MHz => field[16][22][1].CLK
+clk25MHz => field[16][21][0].CLK
+clk25MHz => field[16][21][1].CLK
+clk25MHz => field[16][20][0].CLK
+clk25MHz => field[16][20][1].CLK
+clk25MHz => field[16][19][0].CLK
+clk25MHz => field[16][19][1].CLK
+clk25MHz => field[16][18][0].CLK
+clk25MHz => field[16][18][1].CLK
+clk25MHz => field[16][17][0].CLK
+clk25MHz => field[16][17][1].CLK
+clk25MHz => field[16][16][0].CLK
+clk25MHz => field[16][16][1].CLK
+clk25MHz => field[16][15][0].CLK
+clk25MHz => field[16][15][1].CLK
+clk25MHz => field[16][14][0].CLK
+clk25MHz => field[16][14][1].CLK
+clk25MHz => field[16][13][0].CLK
+clk25MHz => field[16][13][1].CLK
+clk25MHz => field[16][12][0].CLK
+clk25MHz => field[16][12][1].CLK
+clk25MHz => field[16][11][0].CLK
+clk25MHz => field[16][11][1].CLK
+clk25MHz => field[16][10][0].CLK
+clk25MHz => field[16][10][1].CLK
+clk25MHz => field[16][9][0].CLK
+clk25MHz => field[16][9][1].CLK
+clk25MHz => field[16][8][0].CLK
+clk25MHz => field[16][8][1].CLK
+clk25MHz => field[16][7][0].CLK
+clk25MHz => field[16][7][1].CLK
+clk25MHz => field[16][6][0].CLK
+clk25MHz => field[16][6][1].CLK
+clk25MHz => field[16][5][0].CLK
+clk25MHz => field[16][5][1].CLK
+clk25MHz => field[16][4][0].CLK
+clk25MHz => field[16][4][1].CLK
+clk25MHz => field[16][3][0].CLK
+clk25MHz => field[16][3][1].CLK
+clk25MHz => field[16][2][0].CLK
+clk25MHz => field[16][2][1].CLK
+clk25MHz => field[16][1][0].CLK
+clk25MHz => field[16][1][1].CLK
+clk25MHz => field[16][0][0].CLK
+clk25MHz => field[16][0][1].CLK
+clk25MHz => field[15][31][0].CLK
+clk25MHz => field[15][31][1].CLK
+clk25MHz => field[15][30][0].CLK
+clk25MHz => field[15][30][1].CLK
+clk25MHz => field[15][29][0].CLK
+clk25MHz => field[15][29][1].CLK
+clk25MHz => field[15][28][0].CLK
+clk25MHz => field[15][28][1].CLK
+clk25MHz => field[15][27][0].CLK
+clk25MHz => field[15][27][1].CLK
+clk25MHz => field[15][26][0].CLK
+clk25MHz => field[15][26][1].CLK
+clk25MHz => field[15][25][0].CLK
+clk25MHz => field[15][25][1].CLK
+clk25MHz => field[15][24][0].CLK
+clk25MHz => field[15][24][1].CLK
+clk25MHz => field[15][23][0].CLK
+clk25MHz => field[15][23][1].CLK
+clk25MHz => field[15][22][0].CLK
+clk25MHz => field[15][22][1].CLK
+clk25MHz => field[15][21][0].CLK
+clk25MHz => field[15][21][1].CLK
+clk25MHz => field[15][20][0].CLK
+clk25MHz => field[15][20][1].CLK
+clk25MHz => field[15][19][0].CLK
+clk25MHz => field[15][19][1].CLK
+clk25MHz => field[15][18][0].CLK
+clk25MHz => field[15][18][1].CLK
+clk25MHz => field[15][17][0].CLK
+clk25MHz => field[15][17][1].CLK
+clk25MHz => field[15][16][0].CLK
+clk25MHz => field[15][16][1].CLK
+clk25MHz => field[15][15][0].CLK
+clk25MHz => field[15][15][1].CLK
+clk25MHz => field[15][14][0].CLK
+clk25MHz => field[15][14][1].CLK
+clk25MHz => field[15][13][0].CLK
+clk25MHz => field[15][13][1].CLK
+clk25MHz => field[15][12][0].CLK
+clk25MHz => field[15][12][1].CLK
+clk25MHz => field[15][11][0].CLK
+clk25MHz => field[15][11][1].CLK
+clk25MHz => field[15][10][0].CLK
+clk25MHz => field[15][10][1].CLK
+clk25MHz => field[15][9][0].CLK
+clk25MHz => field[15][9][1].CLK
+clk25MHz => field[15][8][0].CLK
+clk25MHz => field[15][8][1].CLK
+clk25MHz => field[15][7][0].CLK
+clk25MHz => field[15][7][1].CLK
+clk25MHz => field[15][6][0].CLK
+clk25MHz => field[15][6][1].CLK
+clk25MHz => field[15][5][0].CLK
+clk25MHz => field[15][5][1].CLK
+clk25MHz => field[15][4][0].CLK
+clk25MHz => field[15][4][1].CLK
+clk25MHz => field[15][3][0].CLK
+clk25MHz => field[15][3][1].CLK
+clk25MHz => field[15][2][0].CLK
+clk25MHz => field[15][2][1].CLK
+clk25MHz => field[15][1][0].CLK
+clk25MHz => field[15][1][1].CLK
+clk25MHz => field[15][0][0].CLK
+clk25MHz => field[15][0][1].CLK
+clk25MHz => field[14][31][0].CLK
+clk25MHz => field[14][31][1].CLK
+clk25MHz => field[14][30][0].CLK
+clk25MHz => field[14][30][1].CLK
+clk25MHz => field[14][29][0].CLK
+clk25MHz => field[14][29][1].CLK
+clk25MHz => field[14][28][0].CLK
+clk25MHz => field[14][28][1].CLK
+clk25MHz => field[14][27][0].CLK
+clk25MHz => field[14][27][1].CLK
+clk25MHz => field[14][26][0].CLK
+clk25MHz => field[14][26][1].CLK
+clk25MHz => field[14][25][0].CLK
+clk25MHz => field[14][25][1].CLK
+clk25MHz => field[14][24][0].CLK
+clk25MHz => field[14][24][1].CLK
+clk25MHz => field[14][23][0].CLK
+clk25MHz => field[14][23][1].CLK
+clk25MHz => field[14][22][0].CLK
+clk25MHz => field[14][22][1].CLK
+clk25MHz => field[14][21][0].CLK
+clk25MHz => field[14][21][1].CLK
+clk25MHz => field[14][20][0].CLK
+clk25MHz => field[14][20][1].CLK
+clk25MHz => field[14][19][0].CLK
+clk25MHz => field[14][19][1].CLK
+clk25MHz => field[14][18][0].CLK
+clk25MHz => field[14][18][1].CLK
+clk25MHz => field[14][17][0].CLK
+clk25MHz => field[14][17][1].CLK
+clk25MHz => field[14][16][0].CLK
+clk25MHz => field[14][16][1].CLK
+clk25MHz => field[14][15][0].CLK
+clk25MHz => field[14][15][1].CLK
+clk25MHz => field[14][14][0].CLK
+clk25MHz => field[14][14][1].CLK
+clk25MHz => field[14][13][0].CLK
+clk25MHz => field[14][13][1].CLK
+clk25MHz => field[14][12][0].CLK
+clk25MHz => field[14][12][1].CLK
+clk25MHz => field[14][11][0].CLK
+clk25MHz => field[14][11][1].CLK
+clk25MHz => field[14][10][0].CLK
+clk25MHz => field[14][10][1].CLK
+clk25MHz => field[14][9][0].CLK
+clk25MHz => field[14][9][1].CLK
+clk25MHz => field[14][8][0].CLK
+clk25MHz => field[14][8][1].CLK
+clk25MHz => field[14][7][0].CLK
+clk25MHz => field[14][7][1].CLK
+clk25MHz => field[14][6][0].CLK
+clk25MHz => field[14][6][1].CLK
+clk25MHz => field[14][5][0].CLK
+clk25MHz => field[14][5][1].CLK
+clk25MHz => field[14][4][0].CLK
+clk25MHz => field[14][4][1].CLK
+clk25MHz => field[14][3][0].CLK
+clk25MHz => field[14][3][1].CLK
+clk25MHz => field[14][2][0].CLK
+clk25MHz => field[14][2][1].CLK
+clk25MHz => field[14][1][0].CLK
+clk25MHz => field[14][1][1].CLK
+clk25MHz => field[14][0][0].CLK
+clk25MHz => field[14][0][1].CLK
+clk25MHz => field[13][31][0].CLK
+clk25MHz => field[13][31][1].CLK
+clk25MHz => field[13][30][0].CLK
+clk25MHz => field[13][30][1].CLK
+clk25MHz => field[13][29][0].CLK
+clk25MHz => field[13][29][1].CLK
+clk25MHz => field[13][28][0].CLK
+clk25MHz => field[13][28][1].CLK
+clk25MHz => field[13][27][0].CLK
+clk25MHz => field[13][27][1].CLK
+clk25MHz => field[13][26][0].CLK
+clk25MHz => field[13][26][1].CLK
+clk25MHz => field[13][25][0].CLK
+clk25MHz => field[13][25][1].CLK
+clk25MHz => field[13][24][0].CLK
+clk25MHz => field[13][24][1].CLK
+clk25MHz => field[13][23][0].CLK
+clk25MHz => field[13][23][1].CLK
+clk25MHz => field[13][22][0].CLK
+clk25MHz => field[13][22][1].CLK
+clk25MHz => field[13][21][0].CLK
+clk25MHz => field[13][21][1].CLK
+clk25MHz => field[13][20][0].CLK
+clk25MHz => field[13][20][1].CLK
+clk25MHz => field[13][19][0].CLK
+clk25MHz => field[13][19][1].CLK
+clk25MHz => field[13][18][0].CLK
+clk25MHz => field[13][18][1].CLK
+clk25MHz => field[13][17][0].CLK
+clk25MHz => field[13][17][1].CLK
+clk25MHz => field[13][16][0].CLK
+clk25MHz => field[13][16][1].CLK
+clk25MHz => field[13][15][0].CLK
+clk25MHz => field[13][15][1].CLK
+clk25MHz => field[13][14][0].CLK
+clk25MHz => field[13][14][1].CLK
+clk25MHz => field[13][13][0].CLK
+clk25MHz => field[13][13][1].CLK
+clk25MHz => field[13][12][0].CLK
+clk25MHz => field[13][12][1].CLK
+clk25MHz => field[13][11][0].CLK
+clk25MHz => field[13][11][1].CLK
+clk25MHz => field[13][10][0].CLK
+clk25MHz => field[13][10][1].CLK
+clk25MHz => field[13][9][0].CLK
+clk25MHz => field[13][9][1].CLK
+clk25MHz => field[13][8][0].CLK
+clk25MHz => field[13][8][1].CLK
+clk25MHz => field[13][7][0].CLK
+clk25MHz => field[13][7][1].CLK
+clk25MHz => field[13][6][0].CLK
+clk25MHz => field[13][6][1].CLK
+clk25MHz => field[13][5][0].CLK
+clk25MHz => field[13][5][1].CLK
+clk25MHz => field[13][4][0].CLK
+clk25MHz => field[13][4][1].CLK
+clk25MHz => field[13][3][0].CLK
+clk25MHz => field[13][3][1].CLK
+clk25MHz => field[13][2][0].CLK
+clk25MHz => field[13][2][1].CLK
+clk25MHz => field[13][1][0].CLK
+clk25MHz => field[13][1][1].CLK
+clk25MHz => field[13][0][0].CLK
+clk25MHz => field[13][0][1].CLK
+clk25MHz => field[12][31][0].CLK
+clk25MHz => field[12][31][1].CLK
+clk25MHz => field[12][30][0].CLK
+clk25MHz => field[12][30][1].CLK
+clk25MHz => field[12][29][0].CLK
+clk25MHz => field[12][29][1].CLK
+clk25MHz => field[12][28][0].CLK
+clk25MHz => field[12][28][1].CLK
+clk25MHz => field[12][27][0].CLK
+clk25MHz => field[12][27][1].CLK
+clk25MHz => field[12][26][0].CLK
+clk25MHz => field[12][26][1].CLK
+clk25MHz => field[12][25][0].CLK
+clk25MHz => field[12][25][1].CLK
+clk25MHz => field[12][24][0].CLK
+clk25MHz => field[12][24][1].CLK
+clk25MHz => field[12][23][0].CLK
+clk25MHz => field[12][23][1].CLK
+clk25MHz => field[12][22][0].CLK
+clk25MHz => field[12][22][1].CLK
+clk25MHz => field[12][21][0].CLK
+clk25MHz => field[12][21][1].CLK
+clk25MHz => field[12][20][0].CLK
+clk25MHz => field[12][20][1].CLK
+clk25MHz => field[12][19][0].CLK
+clk25MHz => field[12][19][1].CLK
+clk25MHz => field[12][18][0].CLK
+clk25MHz => field[12][18][1].CLK
+clk25MHz => field[12][17][0].CLK
+clk25MHz => field[12][17][1].CLK
+clk25MHz => field[12][16][0].CLK
+clk25MHz => field[12][16][1].CLK
+clk25MHz => field[12][15][0].CLK
+clk25MHz => field[12][15][1].CLK
+clk25MHz => field[12][14][0].CLK
+clk25MHz => field[12][14][1].CLK
+clk25MHz => field[12][13][0].CLK
+clk25MHz => field[12][13][1].CLK
+clk25MHz => field[12][12][0].CLK
+clk25MHz => field[12][12][1].CLK
+clk25MHz => field[12][11][0].CLK
+clk25MHz => field[12][11][1].CLK
+clk25MHz => field[12][10][0].CLK
+clk25MHz => field[12][10][1].CLK
+clk25MHz => field[12][9][0].CLK
+clk25MHz => field[12][9][1].CLK
+clk25MHz => field[12][8][0].CLK
+clk25MHz => field[12][8][1].CLK
+clk25MHz => field[12][7][0].CLK
+clk25MHz => field[12][7][1].CLK
+clk25MHz => field[12][6][0].CLK
+clk25MHz => field[12][6][1].CLK
+clk25MHz => field[12][5][0].CLK
+clk25MHz => field[12][5][1].CLK
+clk25MHz => field[12][4][0].CLK
+clk25MHz => field[12][4][1].CLK
+clk25MHz => field[12][3][0].CLK
+clk25MHz => field[12][3][1].CLK
+clk25MHz => field[12][2][0].CLK
+clk25MHz => field[12][2][1].CLK
+clk25MHz => field[12][1][0].CLK
+clk25MHz => field[12][1][1].CLK
+clk25MHz => field[12][0][0].CLK
+clk25MHz => field[12][0][1].CLK
+clk25MHz => field[11][31][0].CLK
+clk25MHz => field[11][31][1].CLK
+clk25MHz => field[11][30][0].CLK
+clk25MHz => field[11][30][1].CLK
+clk25MHz => field[11][29][0].CLK
+clk25MHz => field[11][29][1].CLK
+clk25MHz => field[11][28][0].CLK
+clk25MHz => field[11][28][1].CLK
+clk25MHz => field[11][27][0].CLK
+clk25MHz => field[11][27][1].CLK
+clk25MHz => field[11][26][0].CLK
+clk25MHz => field[11][26][1].CLK
+clk25MHz => field[11][25][0].CLK
+clk25MHz => field[11][25][1].CLK
+clk25MHz => field[11][24][0].CLK
+clk25MHz => field[11][24][1].CLK
+clk25MHz => field[11][23][0].CLK
+clk25MHz => field[11][23][1].CLK
+clk25MHz => field[11][22][0].CLK
+clk25MHz => field[11][22][1].CLK
+clk25MHz => field[11][21][0].CLK
+clk25MHz => field[11][21][1].CLK
+clk25MHz => field[11][20][0].CLK
+clk25MHz => field[11][20][1].CLK
+clk25MHz => field[11][19][0].CLK
+clk25MHz => field[11][19][1].CLK
+clk25MHz => field[11][18][0].CLK
+clk25MHz => field[11][18][1].CLK
+clk25MHz => field[11][17][0].CLK
+clk25MHz => field[11][17][1].CLK
+clk25MHz => field[11][16][0].CLK
+clk25MHz => field[11][16][1].CLK
+clk25MHz => field[11][15][0].CLK
+clk25MHz => field[11][15][1].CLK
+clk25MHz => field[11][14][0].CLK
+clk25MHz => field[11][14][1].CLK
+clk25MHz => field[11][13][0].CLK
+clk25MHz => field[11][13][1].CLK
+clk25MHz => field[11][12][0].CLK
+clk25MHz => field[11][12][1].CLK
+clk25MHz => field[11][11][0].CLK
+clk25MHz => field[11][11][1].CLK
+clk25MHz => field[11][10][0].CLK
+clk25MHz => field[11][10][1].CLK
+clk25MHz => field[11][9][0].CLK
+clk25MHz => field[11][9][1].CLK
+clk25MHz => field[11][8][0].CLK
+clk25MHz => field[11][8][1].CLK
+clk25MHz => field[11][7][0].CLK
+clk25MHz => field[11][7][1].CLK
+clk25MHz => field[11][6][0].CLK
+clk25MHz => field[11][6][1].CLK
+clk25MHz => field[11][5][0].CLK
+clk25MHz => field[11][5][1].CLK
+clk25MHz => field[11][4][0].CLK
+clk25MHz => field[11][4][1].CLK
+clk25MHz => field[11][3][0].CLK
+clk25MHz => field[11][3][1].CLK
+clk25MHz => field[11][2][0].CLK
+clk25MHz => field[11][2][1].CLK
+clk25MHz => field[11][1][0].CLK
+clk25MHz => field[11][1][1].CLK
+clk25MHz => field[11][0][0].CLK
+clk25MHz => field[11][0][1].CLK
+clk25MHz => field[10][31][0].CLK
+clk25MHz => field[10][31][1].CLK
+clk25MHz => field[10][30][0].CLK
+clk25MHz => field[10][30][1].CLK
+clk25MHz => field[10][29][0].CLK
+clk25MHz => field[10][29][1].CLK
+clk25MHz => field[10][28][0].CLK
+clk25MHz => field[10][28][1].CLK
+clk25MHz => field[10][27][0].CLK
+clk25MHz => field[10][27][1].CLK
+clk25MHz => field[10][26][0].CLK
+clk25MHz => field[10][26][1].CLK
+clk25MHz => field[10][25][0].CLK
+clk25MHz => field[10][25][1].CLK
+clk25MHz => field[10][24][0].CLK
+clk25MHz => field[10][24][1].CLK
+clk25MHz => field[10][23][0].CLK
+clk25MHz => field[10][23][1].CLK
+clk25MHz => field[10][22][0].CLK
+clk25MHz => field[10][22][1].CLK
+clk25MHz => field[10][21][0].CLK
+clk25MHz => field[10][21][1].CLK
+clk25MHz => field[10][20][0].CLK
+clk25MHz => field[10][20][1].CLK
+clk25MHz => field[10][19][0].CLK
+clk25MHz => field[10][19][1].CLK
+clk25MHz => field[10][18][0].CLK
+clk25MHz => field[10][18][1].CLK
+clk25MHz => field[10][17][0].CLK
+clk25MHz => field[10][17][1].CLK
+clk25MHz => field[10][16][0].CLK
+clk25MHz => field[10][16][1].CLK
+clk25MHz => field[10][15][0].CLK
+clk25MHz => field[10][15][1].CLK
+clk25MHz => field[10][14][0].CLK
+clk25MHz => field[10][14][1].CLK
+clk25MHz => field[10][13][0].CLK
+clk25MHz => field[10][13][1].CLK
+clk25MHz => field[10][12][0].CLK
+clk25MHz => field[10][12][1].CLK
+clk25MHz => field[10][11][0].CLK
+clk25MHz => field[10][11][1].CLK
+clk25MHz => field[10][10][0].CLK
+clk25MHz => field[10][10][1].CLK
+clk25MHz => field[10][9][0].CLK
+clk25MHz => field[10][9][1].CLK
+clk25MHz => field[10][8][0].CLK
+clk25MHz => field[10][8][1].CLK
+clk25MHz => field[10][7][0].CLK
+clk25MHz => field[10][7][1].CLK
+clk25MHz => field[10][6][0].CLK
+clk25MHz => field[10][6][1].CLK
+clk25MHz => field[10][5][0].CLK
+clk25MHz => field[10][5][1].CLK
+clk25MHz => field[10][4][0].CLK
+clk25MHz => field[10][4][1].CLK
+clk25MHz => field[10][3][0].CLK
+clk25MHz => field[10][3][1].CLK
+clk25MHz => field[10][2][0].CLK
+clk25MHz => field[10][2][1].CLK
+clk25MHz => field[10][1][0].CLK
+clk25MHz => field[10][1][1].CLK
+clk25MHz => field[10][0][0].CLK
+clk25MHz => field[10][0][1].CLK
+clk25MHz => field[9][31][0].CLK
+clk25MHz => field[9][31][1].CLK
+clk25MHz => field[9][30][0].CLK
+clk25MHz => field[9][30][1].CLK
+clk25MHz => field[9][29][0].CLK
+clk25MHz => field[9][29][1].CLK
+clk25MHz => field[9][28][0].CLK
+clk25MHz => field[9][28][1].CLK
+clk25MHz => field[9][27][0].CLK
+clk25MHz => field[9][27][1].CLK
+clk25MHz => field[9][26][0].CLK
+clk25MHz => field[9][26][1].CLK
+clk25MHz => field[9][25][0].CLK
+clk25MHz => field[9][25][1].CLK
+clk25MHz => field[9][24][0].CLK
+clk25MHz => field[9][24][1].CLK
+clk25MHz => field[9][23][0].CLK
+clk25MHz => field[9][23][1].CLK
+clk25MHz => field[9][22][0].CLK
+clk25MHz => field[9][22][1].CLK
+clk25MHz => field[9][21][0].CLK
+clk25MHz => field[9][21][1].CLK
+clk25MHz => field[9][20][0].CLK
+clk25MHz => field[9][20][1].CLK
+clk25MHz => field[9][19][0].CLK
+clk25MHz => field[9][19][1].CLK
+clk25MHz => field[9][18][0].CLK
+clk25MHz => field[9][18][1].CLK
+clk25MHz => field[9][17][0].CLK
+clk25MHz => field[9][17][1].CLK
+clk25MHz => field[9][16][0].CLK
+clk25MHz => field[9][16][1].CLK
+clk25MHz => field[9][15][0].CLK
+clk25MHz => field[9][15][1].CLK
+clk25MHz => field[9][14][0].CLK
+clk25MHz => field[9][14][1].CLK
+clk25MHz => field[9][13][0].CLK
+clk25MHz => field[9][13][1].CLK
+clk25MHz => field[9][12][0].CLK
+clk25MHz => field[9][12][1].CLK
+clk25MHz => field[9][11][0].CLK
+clk25MHz => field[9][11][1].CLK
+clk25MHz => field[9][10][0].CLK
+clk25MHz => field[9][10][1].CLK
+clk25MHz => field[9][9][0].CLK
+clk25MHz => field[9][9][1].CLK
+clk25MHz => field[9][8][0].CLK
+clk25MHz => field[9][8][1].CLK
+clk25MHz => field[9][7][0].CLK
+clk25MHz => field[9][7][1].CLK
+clk25MHz => field[9][6][0].CLK
+clk25MHz => field[9][6][1].CLK
+clk25MHz => field[9][5][0].CLK
+clk25MHz => field[9][5][1].CLK
+clk25MHz => field[9][4][0].CLK
+clk25MHz => field[9][4][1].CLK
+clk25MHz => field[9][3][0].CLK
+clk25MHz => field[9][3][1].CLK
+clk25MHz => field[9][2][0].CLK
+clk25MHz => field[9][2][1].CLK
+clk25MHz => field[9][1][0].CLK
+clk25MHz => field[9][1][1].CLK
+clk25MHz => field[9][0][0].CLK
+clk25MHz => field[9][0][1].CLK
+clk25MHz => field[8][31][0].CLK
+clk25MHz => field[8][31][1].CLK
+clk25MHz => field[8][30][0].CLK
+clk25MHz => field[8][30][1].CLK
+clk25MHz => field[8][29][0].CLK
+clk25MHz => field[8][29][1].CLK
+clk25MHz => field[8][28][0].CLK
+clk25MHz => field[8][28][1].CLK
+clk25MHz => field[8][27][0].CLK
+clk25MHz => field[8][27][1].CLK
+clk25MHz => field[8][26][0].CLK
+clk25MHz => field[8][26][1].CLK
+clk25MHz => field[8][25][0].CLK
+clk25MHz => field[8][25][1].CLK
+clk25MHz => field[8][24][0].CLK
+clk25MHz => field[8][24][1].CLK
+clk25MHz => field[8][23][0].CLK
+clk25MHz => field[8][23][1].CLK
+clk25MHz => field[8][22][0].CLK
+clk25MHz => field[8][22][1].CLK
+clk25MHz => field[8][21][0].CLK
+clk25MHz => field[8][21][1].CLK
+clk25MHz => field[8][20][0].CLK
+clk25MHz => field[8][20][1].CLK
+clk25MHz => field[8][19][0].CLK
+clk25MHz => field[8][19][1].CLK
+clk25MHz => field[8][18][0].CLK
+clk25MHz => field[8][18][1].CLK
+clk25MHz => field[8][17][0].CLK
+clk25MHz => field[8][17][1].CLK
+clk25MHz => field[8][16][0].CLK
+clk25MHz => field[8][16][1].CLK
+clk25MHz => field[8][15][0].CLK
+clk25MHz => field[8][15][1].CLK
+clk25MHz => field[8][14][0].CLK
+clk25MHz => field[8][14][1].CLK
+clk25MHz => field[8][13][0].CLK
+clk25MHz => field[8][13][1].CLK
+clk25MHz => field[8][12][0].CLK
+clk25MHz => field[8][12][1].CLK
+clk25MHz => field[8][11][0].CLK
+clk25MHz => field[8][11][1].CLK
+clk25MHz => field[8][10][0].CLK
+clk25MHz => field[8][10][1].CLK
+clk25MHz => field[8][9][0].CLK
+clk25MHz => field[8][9][1].CLK
+clk25MHz => field[8][8][0].CLK
+clk25MHz => field[8][8][1].CLK
+clk25MHz => field[8][7][0].CLK
+clk25MHz => field[8][7][1].CLK
+clk25MHz => field[8][6][0].CLK
+clk25MHz => field[8][6][1].CLK
+clk25MHz => field[8][5][0].CLK
+clk25MHz => field[8][5][1].CLK
+clk25MHz => field[8][4][0].CLK
+clk25MHz => field[8][4][1].CLK
+clk25MHz => field[8][3][0].CLK
+clk25MHz => field[8][3][1].CLK
+clk25MHz => field[8][2][0].CLK
+clk25MHz => field[8][2][1].CLK
+clk25MHz => field[8][1][0].CLK
+clk25MHz => field[8][1][1].CLK
+clk25MHz => field[8][0][0].CLK
+clk25MHz => field[8][0][1].CLK
+clk25MHz => field[7][31][0].CLK
+clk25MHz => field[7][31][1].CLK
+clk25MHz => field[7][30][0].CLK
+clk25MHz => field[7][30][1].CLK
+clk25MHz => field[7][29][0].CLK
+clk25MHz => field[7][29][1].CLK
+clk25MHz => field[7][28][0].CLK
+clk25MHz => field[7][28][1].CLK
+clk25MHz => field[7][27][0].CLK
+clk25MHz => field[7][27][1].CLK
+clk25MHz => field[7][26][0].CLK
+clk25MHz => field[7][26][1].CLK
+clk25MHz => field[7][25][0].CLK
+clk25MHz => field[7][25][1].CLK
+clk25MHz => field[7][24][0].CLK
+clk25MHz => field[7][24][1].CLK
+clk25MHz => field[7][23][0].CLK
+clk25MHz => field[7][23][1].CLK
+clk25MHz => field[7][22][0].CLK
+clk25MHz => field[7][22][1].CLK
+clk25MHz => field[7][21][0].CLK
+clk25MHz => field[7][21][1].CLK
+clk25MHz => field[7][20][0].CLK
+clk25MHz => field[7][20][1].CLK
+clk25MHz => field[7][19][0].CLK
+clk25MHz => field[7][19][1].CLK
+clk25MHz => field[7][18][0].CLK
+clk25MHz => field[7][18][1].CLK
+clk25MHz => field[7][17][0].CLK
+clk25MHz => field[7][17][1].CLK
+clk25MHz => field[7][16][0].CLK
+clk25MHz => field[7][16][1].CLK
+clk25MHz => field[7][15][0].CLK
+clk25MHz => field[7][15][1].CLK
+clk25MHz => field[7][14][0].CLK
+clk25MHz => field[7][14][1].CLK
+clk25MHz => field[7][13][0].CLK
+clk25MHz => field[7][13][1].CLK
+clk25MHz => field[7][12][0].CLK
+clk25MHz => field[7][12][1].CLK
+clk25MHz => field[7][11][0].CLK
+clk25MHz => field[7][11][1].CLK
+clk25MHz => field[7][10][0].CLK
+clk25MHz => field[7][10][1].CLK
+clk25MHz => field[7][9][0].CLK
+clk25MHz => field[7][9][1].CLK
+clk25MHz => field[7][8][0].CLK
+clk25MHz => field[7][8][1].CLK
+clk25MHz => field[7][7][0].CLK
+clk25MHz => field[7][7][1].CLK
+clk25MHz => field[7][6][0].CLK
+clk25MHz => field[7][6][1].CLK
+clk25MHz => field[7][5][0].CLK
+clk25MHz => field[7][5][1].CLK
+clk25MHz => field[7][4][0].CLK
+clk25MHz => field[7][4][1].CLK
+clk25MHz => field[7][3][0].CLK
+clk25MHz => field[7][3][1].CLK
+clk25MHz => field[7][2][0].CLK
+clk25MHz => field[7][2][1].CLK
+clk25MHz => field[7][1][0].CLK
+clk25MHz => field[7][1][1].CLK
+clk25MHz => field[7][0][0].CLK
+clk25MHz => field[7][0][1].CLK
+clk25MHz => field[6][31][0].CLK
+clk25MHz => field[6][31][1].CLK
+clk25MHz => field[6][30][0].CLK
+clk25MHz => field[6][30][1].CLK
+clk25MHz => field[6][29][0].CLK
+clk25MHz => field[6][29][1].CLK
+clk25MHz => field[6][28][0].CLK
+clk25MHz => field[6][28][1].CLK
+clk25MHz => field[6][27][0].CLK
+clk25MHz => field[6][27][1].CLK
+clk25MHz => field[6][26][0].CLK
+clk25MHz => field[6][26][1].CLK
+clk25MHz => field[6][25][0].CLK
+clk25MHz => field[6][25][1].CLK
+clk25MHz => field[6][24][0].CLK
+clk25MHz => field[6][24][1].CLK
+clk25MHz => field[6][23][0].CLK
+clk25MHz => field[6][23][1].CLK
+clk25MHz => field[6][22][0].CLK
+clk25MHz => field[6][22][1].CLK
+clk25MHz => field[6][21][0].CLK
+clk25MHz => field[6][21][1].CLK
+clk25MHz => field[6][20][0].CLK
+clk25MHz => field[6][20][1].CLK
+clk25MHz => field[6][19][0].CLK
+clk25MHz => field[6][19][1].CLK
+clk25MHz => field[6][18][0].CLK
+clk25MHz => field[6][18][1].CLK
+clk25MHz => field[6][17][0].CLK
+clk25MHz => field[6][17][1].CLK
+clk25MHz => field[6][16][0].CLK
+clk25MHz => field[6][16][1].CLK
+clk25MHz => field[6][15][0].CLK
+clk25MHz => field[6][15][1].CLK
+clk25MHz => field[6][14][0].CLK
+clk25MHz => field[6][14][1].CLK
+clk25MHz => field[6][13][0].CLK
+clk25MHz => field[6][13][1].CLK
+clk25MHz => field[6][12][0].CLK
+clk25MHz => field[6][12][1].CLK
+clk25MHz => field[6][11][0].CLK
+clk25MHz => field[6][11][1].CLK
+clk25MHz => field[6][10][0].CLK
+clk25MHz => field[6][10][1].CLK
+clk25MHz => field[6][9][0].CLK
+clk25MHz => field[6][9][1].CLK
+clk25MHz => field[6][8][0].CLK
+clk25MHz => field[6][8][1].CLK
+clk25MHz => field[6][7][0].CLK
+clk25MHz => field[6][7][1].CLK
+clk25MHz => field[6][6][0].CLK
+clk25MHz => field[6][6][1].CLK
+clk25MHz => field[6][5][0].CLK
+clk25MHz => field[6][5][1].CLK
+clk25MHz => field[6][4][0].CLK
+clk25MHz => field[6][4][1].CLK
+clk25MHz => field[6][3][0].CLK
+clk25MHz => field[6][3][1].CLK
+clk25MHz => field[6][2][0].CLK
+clk25MHz => field[6][2][1].CLK
+clk25MHz => field[6][1][0].CLK
+clk25MHz => field[6][1][1].CLK
+clk25MHz => field[6][0][0].CLK
+clk25MHz => field[6][0][1].CLK
+clk25MHz => field[5][31][0].CLK
+clk25MHz => field[5][31][1].CLK
+clk25MHz => field[5][30][0].CLK
+clk25MHz => field[5][30][1].CLK
+clk25MHz => field[5][29][0].CLK
+clk25MHz => field[5][29][1].CLK
+clk25MHz => field[5][28][0].CLK
+clk25MHz => field[5][28][1].CLK
+clk25MHz => field[5][27][0].CLK
+clk25MHz => field[5][27][1].CLK
+clk25MHz => field[5][26][0].CLK
+clk25MHz => field[5][26][1].CLK
+clk25MHz => field[5][25][0].CLK
+clk25MHz => field[5][25][1].CLK
+clk25MHz => field[5][24][0].CLK
+clk25MHz => field[5][24][1].CLK
+clk25MHz => field[5][23][0].CLK
+clk25MHz => field[5][23][1].CLK
+clk25MHz => field[5][22][0].CLK
+clk25MHz => field[5][22][1].CLK
+clk25MHz => field[5][21][0].CLK
+clk25MHz => field[5][21][1].CLK
+clk25MHz => field[5][20][0].CLK
+clk25MHz => field[5][20][1].CLK
+clk25MHz => field[5][19][0].CLK
+clk25MHz => field[5][19][1].CLK
+clk25MHz => field[5][18][0].CLK
+clk25MHz => field[5][18][1].CLK
+clk25MHz => field[5][17][0].CLK
+clk25MHz => field[5][17][1].CLK
+clk25MHz => field[5][16][0].CLK
+clk25MHz => field[5][16][1].CLK
+clk25MHz => field[5][15][0].CLK
+clk25MHz => field[5][15][1].CLK
+clk25MHz => field[5][14][0].CLK
+clk25MHz => field[5][14][1].CLK
+clk25MHz => field[5][13][0].CLK
+clk25MHz => field[5][13][1].CLK
+clk25MHz => field[5][12][0].CLK
+clk25MHz => field[5][12][1].CLK
+clk25MHz => field[5][11][0].CLK
+clk25MHz => field[5][11][1].CLK
+clk25MHz => field[5][10][0].CLK
+clk25MHz => field[5][10][1].CLK
+clk25MHz => field[5][9][0].CLK
+clk25MHz => field[5][9][1].CLK
+clk25MHz => field[5][8][0].CLK
+clk25MHz => field[5][8][1].CLK
+clk25MHz => field[5][7][0].CLK
+clk25MHz => field[5][7][1].CLK
+clk25MHz => field[5][6][0].CLK
+clk25MHz => field[5][6][1].CLK
+clk25MHz => field[5][5][0].CLK
+clk25MHz => field[5][5][1].CLK
+clk25MHz => field[5][4][0].CLK
+clk25MHz => field[5][4][1].CLK
+clk25MHz => field[5][3][0].CLK
+clk25MHz => field[5][3][1].CLK
+clk25MHz => field[5][2][0].CLK
+clk25MHz => field[5][2][1].CLK
+clk25MHz => field[5][1][0].CLK
+clk25MHz => field[5][1][1].CLK
+clk25MHz => field[5][0][0].CLK
+clk25MHz => field[5][0][1].CLK
+clk25MHz => field[4][31][0].CLK
+clk25MHz => field[4][31][1].CLK
+clk25MHz => field[4][30][0].CLK
+clk25MHz => field[4][30][1].CLK
+clk25MHz => field[4][29][0].CLK
+clk25MHz => field[4][29][1].CLK
+clk25MHz => field[4][28][0].CLK
+clk25MHz => field[4][28][1].CLK
+clk25MHz => field[4][27][0].CLK
+clk25MHz => field[4][27][1].CLK
+clk25MHz => field[4][26][0].CLK
+clk25MHz => field[4][26][1].CLK
+clk25MHz => field[4][25][0].CLK
+clk25MHz => field[4][25][1].CLK
+clk25MHz => field[4][24][0].CLK
+clk25MHz => field[4][24][1].CLK
+clk25MHz => field[4][23][0].CLK
+clk25MHz => field[4][23][1].CLK
+clk25MHz => field[4][22][0].CLK
+clk25MHz => field[4][22][1].CLK
+clk25MHz => field[4][21][0].CLK
+clk25MHz => field[4][21][1].CLK
+clk25MHz => field[4][20][0].CLK
+clk25MHz => field[4][20][1].CLK
+clk25MHz => field[4][19][0].CLK
+clk25MHz => field[4][19][1].CLK
+clk25MHz => field[4][18][0].CLK
+clk25MHz => field[4][18][1].CLK
+clk25MHz => field[4][17][0].CLK
+clk25MHz => field[4][17][1].CLK
+clk25MHz => field[4][16][0].CLK
+clk25MHz => field[4][16][1].CLK
+clk25MHz => field[4][15][0].CLK
+clk25MHz => field[4][15][1].CLK
+clk25MHz => field[4][14][0].CLK
+clk25MHz => field[4][14][1].CLK
+clk25MHz => field[4][13][0].CLK
+clk25MHz => field[4][13][1].CLK
+clk25MHz => field[4][12][0].CLK
+clk25MHz => field[4][12][1].CLK
+clk25MHz => field[4][11][0].CLK
+clk25MHz => field[4][11][1].CLK
+clk25MHz => field[4][10][0].CLK
+clk25MHz => field[4][10][1].CLK
+clk25MHz => field[4][9][0].CLK
+clk25MHz => field[4][9][1].CLK
+clk25MHz => field[4][8][0].CLK
+clk25MHz => field[4][8][1].CLK
+clk25MHz => field[4][7][0].CLK
+clk25MHz => field[4][7][1].CLK
+clk25MHz => field[4][6][0].CLK
+clk25MHz => field[4][6][1].CLK
+clk25MHz => field[4][5][0].CLK
+clk25MHz => field[4][5][1].CLK
+clk25MHz => field[4][4][0].CLK
+clk25MHz => field[4][4][1].CLK
+clk25MHz => field[4][3][0].CLK
+clk25MHz => field[4][3][1].CLK
+clk25MHz => field[4][2][0].CLK
+clk25MHz => field[4][2][1].CLK
+clk25MHz => field[4][1][0].CLK
+clk25MHz => field[4][1][1].CLK
+clk25MHz => field[4][0][0].CLK
+clk25MHz => field[4][0][1].CLK
+clk25MHz => field[3][31][0].CLK
+clk25MHz => field[3][31][1].CLK
+clk25MHz => field[3][30][0].CLK
+clk25MHz => field[3][30][1].CLK
+clk25MHz => field[3][29][0].CLK
+clk25MHz => field[3][29][1].CLK
+clk25MHz => field[3][28][0].CLK
+clk25MHz => field[3][28][1].CLK
+clk25MHz => field[3][27][0].CLK
+clk25MHz => field[3][27][1].CLK
+clk25MHz => field[3][26][0].CLK
+clk25MHz => field[3][26][1].CLK
+clk25MHz => field[3][25][0].CLK
+clk25MHz => field[3][25][1].CLK
+clk25MHz => field[3][24][0].CLK
+clk25MHz => field[3][24][1].CLK
+clk25MHz => field[3][23][0].CLK
+clk25MHz => field[3][23][1].CLK
+clk25MHz => field[3][22][0].CLK
+clk25MHz => field[3][22][1].CLK
+clk25MHz => field[3][21][0].CLK
+clk25MHz => field[3][21][1].CLK
+clk25MHz => field[3][20][0].CLK
+clk25MHz => field[3][20][1].CLK
+clk25MHz => field[3][19][0].CLK
+clk25MHz => field[3][19][1].CLK
+clk25MHz => field[3][18][0].CLK
+clk25MHz => field[3][18][1].CLK
+clk25MHz => field[3][17][0].CLK
+clk25MHz => field[3][17][1].CLK
+clk25MHz => field[3][16][0].CLK
+clk25MHz => field[3][16][1].CLK
+clk25MHz => field[3][15][0].CLK
+clk25MHz => field[3][15][1].CLK
+clk25MHz => field[3][14][0].CLK
+clk25MHz => field[3][14][1].CLK
+clk25MHz => field[3][13][0].CLK
+clk25MHz => field[3][13][1].CLK
+clk25MHz => field[3][12][0].CLK
+clk25MHz => field[3][12][1].CLK
+clk25MHz => field[3][11][0].CLK
+clk25MHz => field[3][11][1].CLK
+clk25MHz => field[3][10][0].CLK
+clk25MHz => field[3][10][1].CLK
+clk25MHz => field[3][9][0].CLK
+clk25MHz => field[3][9][1].CLK
+clk25MHz => field[3][8][0].CLK
+clk25MHz => field[3][8][1].CLK
+clk25MHz => field[3][7][0].CLK
+clk25MHz => field[3][7][1].CLK
+clk25MHz => field[3][6][0].CLK
+clk25MHz => field[3][6][1].CLK
+clk25MHz => field[3][5][0].CLK
+clk25MHz => field[3][5][1].CLK
+clk25MHz => field[3][4][0].CLK
+clk25MHz => field[3][4][1].CLK
+clk25MHz => field[3][3][0].CLK
+clk25MHz => field[3][3][1].CLK
+clk25MHz => field[3][2][0].CLK
+clk25MHz => field[3][2][1].CLK
+clk25MHz => field[3][1][0].CLK
+clk25MHz => field[3][1][1].CLK
+clk25MHz => field[3][0][0].CLK
+clk25MHz => field[3][0][1].CLK
+clk25MHz => field[2][31][0].CLK
+clk25MHz => field[2][31][1].CLK
+clk25MHz => field[2][30][0].CLK
+clk25MHz => field[2][30][1].CLK
+clk25MHz => field[2][29][0].CLK
+clk25MHz => field[2][29][1].CLK
+clk25MHz => field[2][28][0].CLK
+clk25MHz => field[2][28][1].CLK
+clk25MHz => field[2][27][0].CLK
+clk25MHz => field[2][27][1].CLK
+clk25MHz => field[2][26][0].CLK
+clk25MHz => field[2][26][1].CLK
+clk25MHz => field[2][25][0].CLK
+clk25MHz => field[2][25][1].CLK
+clk25MHz => field[2][24][0].CLK
+clk25MHz => field[2][24][1].CLK
+clk25MHz => field[2][23][0].CLK
+clk25MHz => field[2][23][1].CLK
+clk25MHz => field[2][22][0].CLK
+clk25MHz => field[2][22][1].CLK
+clk25MHz => field[2][21][0].CLK
+clk25MHz => field[2][21][1].CLK
+clk25MHz => field[2][20][0].CLK
+clk25MHz => field[2][20][1].CLK
+clk25MHz => field[2][19][0].CLK
+clk25MHz => field[2][19][1].CLK
+clk25MHz => field[2][18][0].CLK
+clk25MHz => field[2][18][1].CLK
+clk25MHz => field[2][17][0].CLK
+clk25MHz => field[2][17][1].CLK
+clk25MHz => field[2][16][0].CLK
+clk25MHz => field[2][16][1].CLK
+clk25MHz => field[2][15][0].CLK
+clk25MHz => field[2][15][1].CLK
+clk25MHz => field[2][14][0].CLK
+clk25MHz => field[2][14][1].CLK
+clk25MHz => field[2][13][0].CLK
+clk25MHz => field[2][13][1].CLK
+clk25MHz => field[2][12][0].CLK
+clk25MHz => field[2][12][1].CLK
+clk25MHz => field[2][11][0].CLK
+clk25MHz => field[2][11][1].CLK
+clk25MHz => field[2][10][0].CLK
+clk25MHz => field[2][10][1].CLK
+clk25MHz => field[2][9][0].CLK
+clk25MHz => field[2][9][1].CLK
+clk25MHz => field[2][8][0].CLK
+clk25MHz => field[2][8][1].CLK
+clk25MHz => field[2][7][0].CLK
+clk25MHz => field[2][7][1].CLK
+clk25MHz => field[2][6][0].CLK
+clk25MHz => field[2][6][1].CLK
+clk25MHz => field[2][5][0].CLK
+clk25MHz => field[2][5][1].CLK
+clk25MHz => field[2][4][0].CLK
+clk25MHz => field[2][4][1].CLK
+clk25MHz => field[2][3][0].CLK
+clk25MHz => field[2][3][1].CLK
+clk25MHz => field[2][2][0].CLK
+clk25MHz => field[2][2][1].CLK
+clk25MHz => field[2][1][0].CLK
+clk25MHz => field[2][1][1].CLK
+clk25MHz => field[2][0][0].CLK
+clk25MHz => field[2][0][1].CLK
+clk25MHz => field[1][31][0].CLK
+clk25MHz => field[1][31][1].CLK
+clk25MHz => field[1][30][0].CLK
+clk25MHz => field[1][30][1].CLK
+clk25MHz => field[1][29][0].CLK
+clk25MHz => field[1][29][1].CLK
+clk25MHz => field[1][28][0].CLK
+clk25MHz => field[1][28][1].CLK
+clk25MHz => field[1][27][0].CLK
+clk25MHz => field[1][27][1].CLK
+clk25MHz => field[1][26][0].CLK
+clk25MHz => field[1][26][1].CLK
+clk25MHz => field[1][25][0].CLK
+clk25MHz => field[1][25][1].CLK
+clk25MHz => field[1][24][0].CLK
+clk25MHz => field[1][24][1].CLK
+clk25MHz => field[1][23][0].CLK
+clk25MHz => field[1][23][1].CLK
+clk25MHz => field[1][22][0].CLK
+clk25MHz => field[1][22][1].CLK
+clk25MHz => field[1][21][0].CLK
+clk25MHz => field[1][21][1].CLK
+clk25MHz => field[1][20][0].CLK
+clk25MHz => field[1][20][1].CLK
+clk25MHz => field[1][19][0].CLK
+clk25MHz => field[1][19][1].CLK
+clk25MHz => field[1][18][0].CLK
+clk25MHz => field[1][18][1].CLK
+clk25MHz => field[1][17][0].CLK
+clk25MHz => field[1][17][1].CLK
+clk25MHz => field[1][16][0].CLK
+clk25MHz => field[1][16][1].CLK
+clk25MHz => field[1][15][0].CLK
+clk25MHz => field[1][15][1].CLK
+clk25MHz => field[1][14][0].CLK
+clk25MHz => field[1][14][1].CLK
+clk25MHz => field[1][13][0].CLK
+clk25MHz => field[1][13][1].CLK
+clk25MHz => field[1][12][0].CLK
+clk25MHz => field[1][12][1].CLK
+clk25MHz => field[1][11][0].CLK
+clk25MHz => field[1][11][1].CLK
+clk25MHz => field[1][10][0].CLK
+clk25MHz => field[1][10][1].CLK
+clk25MHz => field[1][9][0].CLK
+clk25MHz => field[1][9][1].CLK
+clk25MHz => field[1][8][0].CLK
+clk25MHz => field[1][8][1].CLK
+clk25MHz => field[1][7][0].CLK
+clk25MHz => field[1][7][1].CLK
+clk25MHz => field[1][6][0].CLK
+clk25MHz => field[1][6][1].CLK
+clk25MHz => field[1][5][0].CLK
+clk25MHz => field[1][5][1].CLK
+clk25MHz => field[1][4][0].CLK
+clk25MHz => field[1][4][1].CLK
+clk25MHz => field[1][3][0].CLK
+clk25MHz => field[1][3][1].CLK
+clk25MHz => field[1][2][0].CLK
+clk25MHz => field[1][2][1].CLK
+clk25MHz => field[1][1][0].CLK
+clk25MHz => field[1][1][1].CLK
+clk25MHz => field[1][0][0].CLK
+clk25MHz => field[1][0][1].CLK
+clk25MHz => button4_state.CLK
+clk25MHz => button3_state.CLK
+clk25MHz => button2_state.CLK
+clk25MHz => button1_state.CLK
+clk25MHz => game_state.CLK
+clk25MHz => platform2_position[0].CLK
+clk25MHz => platform2_position[1].CLK
+clk25MHz => platform2_position[2].CLK
+clk25MHz => platform2_position[3].CLK
+clk25MHz => platform2_position[4].CLK
+clk25MHz => platform2_position[5].CLK
+clk25MHz => platform2_position[6].CLK
+clk25MHz => platform2_position[7].CLK
+clk25MHz => platform2_position[8].CLK
+clk25MHz => platform2_position[9].CLK
+clk25MHz => platform2_position[10].CLK
+clk25MHz => platform2_position[11].CLK
+clk25MHz => platform2_position[12].CLK
+clk25MHz => platform2_position[13].CLK
+clk25MHz => platform2_position[14].CLK
+clk25MHz => platform2_position[15].CLK
+clk25MHz => platform2_position[16].CLK
+clk25MHz => platform2_position[17].CLK
+clk25MHz => platform2_position[18].CLK
+clk25MHz => platform2_position[19].CLK
+clk25MHz => platform2_position[20].CLK
+clk25MHz => platform2_position[21].CLK
+clk25MHz => platform2_position[22].CLK
+clk25MHz => platform2_position[23].CLK
+clk25MHz => platform2_position[24].CLK
+clk25MHz => platform2_position[25].CLK
+clk25MHz => platform2_position[26].CLK
+clk25MHz => platform2_position[27].CLK
+clk25MHz => platform2_position[28].CLK
+clk25MHz => platform2_position[29].CLK
+clk25MHz => platform2_position[30].CLK
+clk25MHz => platform2_position[31].CLK
+clk25MHz => platform1_position[0].CLK
+clk25MHz => platform1_position[1].CLK
+clk25MHz => platform1_position[2].CLK
+clk25MHz => platform1_position[3].CLK
+clk25MHz => platform1_position[4].CLK
+clk25MHz => platform1_position[5].CLK
+clk25MHz => platform1_position[6].CLK
+clk25MHz => platform1_position[7].CLK
+clk25MHz => platform1_position[8].CLK
+clk25MHz => platform1_position[9].CLK
+clk25MHz => platform1_position[10].CLK
+clk25MHz => platform1_position[11].CLK
+clk25MHz => platform1_position[12].CLK
+clk25MHz => platform1_position[13].CLK
+clk25MHz => platform1_position[14].CLK
+clk25MHz => platform1_position[15].CLK
+clk25MHz => platform1_position[16].CLK
+clk25MHz => platform1_position[17].CLK
+clk25MHz => platform1_position[18].CLK
+clk25MHz => platform1_position[19].CLK
+clk25MHz => platform1_position[20].CLK
+clk25MHz => platform1_position[21].CLK
+clk25MHz => platform1_position[22].CLK
+clk25MHz => platform1_position[23].CLK
+clk25MHz => platform1_position[24].CLK
+clk25MHz => platform1_position[25].CLK
+clk25MHz => platform1_position[26].CLK
+clk25MHz => platform1_position[27].CLK
+clk25MHz => platform1_position[28].CLK
+clk25MHz => platform1_position[29].CLK
+clk25MHz => platform1_position[30].CLK
+clk25MHz => platform1_position[31].CLK
+clk25MHz => ball_y[0].CLK
+clk25MHz => ball_y[1].CLK
+clk25MHz => ball_y[2].CLK
+clk25MHz => ball_y[3].CLK
+clk25MHz => ball_y[4].CLK
+clk25MHz => ball_y[5].CLK
+clk25MHz => ball_y[6].CLK
+clk25MHz => ball_y[7].CLK
+clk25MHz => ball_y[8].CLK
+clk25MHz => ball_y[9].CLK
+clk25MHz => ball_y[10].CLK
+clk25MHz => ball_y[11].CLK
+clk25MHz => ball_y[12].CLK
+clk25MHz => ball_y[13].CLK
+clk25MHz => ball_y[14].CLK
+clk25MHz => ball_y[15].CLK
+clk25MHz => ball_y[16].CLK
+clk25MHz => ball_y[17].CLK
+clk25MHz => ball_y[18].CLK
+clk25MHz => ball_y[19].CLK
+clk25MHz => ball_y[20].CLK
+clk25MHz => ball_y[21].CLK
+clk25MHz => ball_y[22].CLK
+clk25MHz => ball_y[23].CLK
+clk25MHz => ball_y[24].CLK
+clk25MHz => ball_y[25].CLK
+clk25MHz => ball_y[26].CLK
+clk25MHz => ball_y[27].CLK
+clk25MHz => ball_y[28].CLK
+clk25MHz => ball_y[29].CLK
+clk25MHz => ball_y[30].CLK
+clk25MHz => ball_y[31].CLK
+clk25MHz => ball_x[0].CLK
+clk25MHz => ball_x[1].CLK
+clk25MHz => ball_x[2].CLK
+clk25MHz => ball_x[3].CLK
+clk25MHz => ball_x[4].CLK
+clk25MHz => ball_x[5].CLK
+clk25MHz => ball_x[6].CLK
+clk25MHz => ball_x[7].CLK
+clk25MHz => ball_x[8].CLK
+clk25MHz => ball_x[9].CLK
+clk25MHz => ball_x[10].CLK
+clk25MHz => ball_x[11].CLK
+clk25MHz => ball_x[12].CLK
+clk25MHz => ball_x[13].CLK
+clk25MHz => ball_x[14].CLK
+clk25MHz => ball_x[15].CLK
+clk25MHz => ball_x[16].CLK
+clk25MHz => ball_x[17].CLK
+clk25MHz => ball_x[18].CLK
+clk25MHz => ball_x[19].CLK
+clk25MHz => ball_x[20].CLK
+clk25MHz => ball_x[21].CLK
+clk25MHz => ball_x[22].CLK
+clk25MHz => ball_x[23].CLK
+clk25MHz => ball_x[24].CLK
+clk25MHz => ball_x[25].CLK
+clk25MHz => ball_x[26].CLK
+clk25MHz => ball_x[27].CLK
+clk25MHz => ball_x[28].CLK
+clk25MHz => ball_x[29].CLK
+clk25MHz => ball_x[30].CLK
+clk25MHz => ball_x[31].CLK
+clk25MHz => led_[0].CLK
+clk25MHz => led_[1].CLK
+clk25MHz => led_[2].CLK
+clk25MHz => led_[3].CLK
+clk25MHz => led_[4].CLK
+clk25MHz => led_[5].CLK
+clk25MHz => led_[6].CLK
+clk25MHz => led_[7].CLK
+clk25MHz => v_counter[0].CLK
+clk25MHz => v_counter[1].CLK
+clk25MHz => v_counter[2].CLK
+clk25MHz => v_counter[3].CLK
+clk25MHz => v_counter[4].CLK
+clk25MHz => v_counter[5].CLK
+clk25MHz => v_counter[6].CLK
+clk25MHz => v_counter[7].CLK
+clk25MHz => v_counter[8].CLK
+clk25MHz => v_counter[9].CLK
+clk25MHz => v_counter[10].CLK
+clk25MHz => v_counter[11].CLK
+clk25MHz => v_counter[12].CLK
+clk25MHz => v_counter[13].CLK
+clk25MHz => v_counter[14].CLK
+clk25MHz => v_counter[15].CLK
+clk25MHz => v_counter[16].CLK
+clk25MHz => v_counter[17].CLK
+clk25MHz => v_counter[18].CLK
+clk25MHz => v_counter[19].CLK
+clk25MHz => v_counter[20].CLK
+clk25MHz => v_counter[21].CLK
+clk25MHz => v_counter[22].CLK
+clk25MHz => v_counter[23].CLK
+clk25MHz => v_counter[24].CLK
+clk25MHz => v_counter[25].CLK
+clk25MHz => v_counter[26].CLK
+clk25MHz => v_counter[27].CLK
+clk25MHz => v_counter[28].CLK
+clk25MHz => v_counter[29].CLK
+clk25MHz => v_counter[30].CLK
+clk25MHz => v_counter[31].CLK
+clk25MHz => h_counter[0].CLK
+clk25MHz => h_counter[1].CLK
+clk25MHz => h_counter[2].CLK
+clk25MHz => h_counter[3].CLK
+clk25MHz => h_counter[4].CLK
+clk25MHz => h_counter[5].CLK
+clk25MHz => h_counter[6].CLK
+clk25MHz => h_counter[7].CLK
+clk25MHz => h_counter[8].CLK
+clk25MHz => h_counter[9].CLK
+clk25MHz => h_counter[10].CLK
+clk25MHz => h_counter[11].CLK
+clk25MHz => h_counter[12].CLK
+clk25MHz => h_counter[13].CLK
+clk25MHz => h_counter[14].CLK
+clk25MHz => h_counter[15].CLK
+clk25MHz => h_counter[16].CLK
+clk25MHz => h_counter[17].CLK
+clk25MHz => h_counter[18].CLK
+clk25MHz => h_counter[19].CLK
+clk25MHz => h_counter[20].CLK
+clk25MHz => h_counter[21].CLK
+clk25MHz => h_counter[22].CLK
+clk25MHz => h_counter[23].CLK
+clk25MHz => h_counter[24].CLK
+clk25MHz => h_counter[25].CLK
+clk25MHz => h_counter[26].CLK
+clk25MHz => h_counter[27].CLK
+clk25MHz => h_counter[28].CLK
+clk25MHz => h_counter[29].CLK
+clk25MHz => h_counter[30].CLK
+clk25MHz => h_counter[31].CLK
+clk25MHz => ball_direction~5.DATAIN
+button1 => always2.IN1
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_x.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_y.OUTPUTSELECT
+button1 => ball_direction.OUTPUTSELECT
+button1 => ball_direction.OUTPUTSELECT
+button1 => ball_direction.OUTPUTSELECT
+button1 => ball_direction.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform1_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => platform2_position.OUTPUTSELECT
+button1 => game_state.OUTPUTSELECT
+button1 => button1_state.DATAIN
+button1 => led_[6].DATAIN
+button1 => led_[7].DATAIN
+button2 => always2.IN1
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_x.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_y.OUTPUTSELECT
+button2 => ball_direction.OUTPUTSELECT
+button2 => ball_direction.OUTPUTSELECT
+button2 => ball_direction.OUTPUTSELECT
+button2 => ball_direction.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform1_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => platform2_position.OUTPUTSELECT
+button2 => game_state.OUTPUTSELECT
+button2 => button2_state.DATAIN
+button2 => led_[4].DATAIN
+button2 => led_[5].DATAIN
+button3 => always2.IN1
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_x.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_y.OUTPUTSELECT
+button3 => ball_direction.OUTPUTSELECT
+button3 => ball_direction.OUTPUTSELECT
+button3 => ball_direction.OUTPUTSELECT
+button3 => ball_direction.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform1_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => platform2_position.OUTPUTSELECT
+button3 => game_state.OUTPUTSELECT
+button3 => button3_state.DATAIN
+button3 => led_[2].DATAIN
+button3 => led_[3].DATAIN
+button4 => always2.IN1
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_x.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_y.OUTPUTSELECT
+button4 => ball_direction.OUTPUTSELECT
+button4 => ball_direction.OUTPUTSELECT
+button4 => ball_direction.OUTPUTSELECT
+button4 => ball_direction.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform1_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => platform2_position.OUTPUTSELECT
+button4 => game_state.OUTPUTSELECT
+button4 => button4_state.DATAIN
+button4 => led_[0].DATAIN
+button4 => led_[1].DATAIN
+h_sync <= h_sync.DB_MAX_OUTPUT_PORT_TYPE
+v_sync <= v_sync.DB_MAX_OUTPUT_PORT_TYPE
+red[0] <= red_[0].DB_MAX_OUTPUT_PORT_TYPE
+red[1] <= red_[1].DB_MAX_OUTPUT_PORT_TYPE
+red[2] <= red_[2].DB_MAX_OUTPUT_PORT_TYPE
+red[3] <= red_[3].DB_MAX_OUTPUT_PORT_TYPE
+green[0] <= green_[0].DB_MAX_OUTPUT_PORT_TYPE
+green[1] <= green_[1].DB_MAX_OUTPUT_PORT_TYPE
+green[2] <= green_[2].DB_MAX_OUTPUT_PORT_TYPE
+green[3] <= green_[3].DB_MAX_OUTPUT_PORT_TYPE
+blue[0] <= blue_[0].DB_MAX_OUTPUT_PORT_TYPE
+blue[1] <= blue_[1].DB_MAX_OUTPUT_PORT_TYPE
+blue[2] <= blue_[2].DB_MAX_OUTPUT_PORT_TYPE
+blue[3] <= blue_[3].DB_MAX_OUTPUT_PORT_TYPE
+hex0[0] <= hex0_[0].DB_MAX_OUTPUT_PORT_TYPE
+hex0[1] <= hex0_[1].DB_MAX_OUTPUT_PORT_TYPE
+hex0[2] <= hex0_[2].DB_MAX_OUTPUT_PORT_TYPE
+hex0[3] <= hex0_[3].DB_MAX_OUTPUT_PORT_TYPE
+hex0[4] <= hex0_[4].DB_MAX_OUTPUT_PORT_TYPE
+hex0[5] <= hex0_[5].DB_MAX_OUTPUT_PORT_TYPE
+hex0[6] <= hex0_[6].DB_MAX_OUTPUT_PORT_TYPE
+hex1[0] <= hex1_[0].DB_MAX_OUTPUT_PORT_TYPE
+hex1[1] <= hex1_[1].DB_MAX_OUTPUT_PORT_TYPE
+hex1[2] <= hex1_[2].DB_MAX_OUTPUT_PORT_TYPE
+hex1[3] <= hex1_[3].DB_MAX_OUTPUT_PORT_TYPE
+hex1[4] <= hex1_[4].DB_MAX_OUTPUT_PORT_TYPE
+hex1[5] <= hex1_[5].DB_MAX_OUTPUT_PORT_TYPE
+hex1[6] <= hex1_[6].DB_MAX_OUTPUT_PORT_TYPE
+hex2[0] <= hex2_[0].DB_MAX_OUTPUT_PORT_TYPE
+hex2[1] <= hex2_[1].DB_MAX_OUTPUT_PORT_TYPE
+hex2[2] <= hex2_[2].DB_MAX_OUTPUT_PORT_TYPE
+hex2[3] <= hex2_[3].DB_MAX_OUTPUT_PORT_TYPE
+hex2[4] <= hex2_[4].DB_MAX_OUTPUT_PORT_TYPE
+hex2[5] <= hex2_[5].DB_MAX_OUTPUT_PORT_TYPE
+hex2[6] <= hex2_[6].DB_MAX_OUTPUT_PORT_TYPE
+hex3[0] <= hex3_[0].DB_MAX_OUTPUT_PORT_TYPE
+hex3[1] <= hex3_[1].DB_MAX_OUTPUT_PORT_TYPE
+hex3[2] <= hex3_[2].DB_MAX_OUTPUT_PORT_TYPE
+hex3[3] <= hex3_[3].DB_MAX_OUTPUT_PORT_TYPE
+hex3[4] <= hex3_[4].DB_MAX_OUTPUT_PORT_TYPE
+hex3[5] <= hex3_[5].DB_MAX_OUTPUT_PORT_TYPE
+hex3[6] <= hex3_[6].DB_MAX_OUTPUT_PORT_TYPE
+led[0] <= led_[0].DB_MAX_OUTPUT_PORT_TYPE
+led[1] <= led_[1].DB_MAX_OUTPUT_PORT_TYPE
+led[2] <= led_[2].DB_MAX_OUTPUT_PORT_TYPE
+led[3] <= led_[3].DB_MAX_OUTPUT_PORT_TYPE
+led[4] <= led_[4].DB_MAX_OUTPUT_PORT_TYPE
+led[5] <= led_[5].DB_MAX_OUTPUT_PORT_TYPE
+led[6] <= led_[6].DB_MAX_OUTPUT_PORT_TYPE
+led[7] <= led_[7].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TotalScheme|ClockDivider:inst1
+clk50MHz => clk25MHz_.CLK
+clk25MHz <= clk25MHz_.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TotalScheme|Debouncer:inst2
+noisy => button_reg[0].DATAIN
+clk => debounced~reg0.CLK
+clk => button_reg[0].CLK
+clk => button_reg[1].CLK
+clk => button_reg[2].CLK
+clk => button_reg[3].CLK
+clk => button_reg[4].CLK
+clk => button_reg[5].CLK
+clk => button_reg[6].CLK
+clk => button_reg[7].CLK
+debounced <= debounced~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TotalScheme|Debouncer:inst3
+noisy => button_reg[0].DATAIN
+clk => debounced~reg0.CLK
+clk => button_reg[0].CLK
+clk => button_reg[1].CLK
+clk => button_reg[2].CLK
+clk => button_reg[3].CLK
+clk => button_reg[4].CLK
+clk => button_reg[5].CLK
+clk => button_reg[6].CLK
+clk => button_reg[7].CLK
+debounced <= debounced~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TotalScheme|Debouncer:inst4
+noisy => button_reg[0].DATAIN
+clk => debounced~reg0.CLK
+clk => button_reg[0].CLK
+clk => button_reg[1].CLK
+clk => button_reg[2].CLK
+clk => button_reg[3].CLK
+clk => button_reg[4].CLK
+clk => button_reg[5].CLK
+clk => button_reg[6].CLK
+clk => button_reg[7].CLK
+debounced <= debounced~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TotalScheme|Debouncer:inst5
+noisy => button_reg[0].DATAIN
+clk => debounced~reg0.CLK
+clk => button_reg[0].CLK
+clk => button_reg[1].CLK
+clk => button_reg[2].CLK
+clk => button_reg[3].CLK
+clk => button_reg[4].CLK
+clk => button_reg[5].CLK
+clk => button_reg[6].CLK
+clk => button_reg[7].CLK
+debounced <= debounced~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
diff --git a/db/myArkanoid.hif b/db/myArkanoid.hif
new file mode 100644
index 0000000..a7c12d6
--- /dev/null
+++ b/db/myArkanoid.hif
@@ -0,0 +1,3022 @@
+Quartus II
+Version 9.1 Build 222 10/21/2009 SJ Full Version
+11
+980
+OFF
+OFF
+OFF
+ON
+ON
+ON
+FV_OFF
+Level2
+0
+0
+VRSM_ON
+VHSM_ON
+0
+-- Start Library Paths --
+-- End Library Paths --
+-- Start VHDL Libraries --
+-- End VHDL Libraries --
+# entity
+lpm_divide
+# storage
+db|myArkanoid.(2).cnf
+db|myArkanoid.(2).cnf
+# case_insensitive
+# source_file
+c:|quartus|quartus|libraries|megafunctions|lpm_divide.tdf
+7b2071c21e42b4a04d32c24dcdc565
+7
+# user_parameter {
+LPM_WIDTHN
+32
+PARAMETER_UNKNOWN
+USR
+LPM_WIDTHD
+6
+PARAMETER_UNKNOWN
+USR
+LPM_NREPRESENTATION
+SIGNED
+PARAMETER_UNKNOWN
+USR
+LPM_DREPRESENTATION
+SIGNED
+PARAMETER_UNKNOWN
+USR
+LPM_PIPELINE
+0
+PARAMETER_UNKNOWN
+DEF
+LPM_REMAINDERPOSITIVE
+FALSE
+PARAMETER_UNKNOWN
+USR
+MAXIMIZE_SPEED
+5
+PARAMETER_UNKNOWN
+DEF
+CBXI_PARAMETER
+lpm_divide_8so
+PARAMETER_UNKNOWN
+USR
+CARRY_CHAIN
+MANUAL
+PARAMETER_UNKNOWN
+USR
+OPTIMIZE_FOR_SPEED
+5
+PARAMETER_UNKNOWN
+USR
+AUTO_CARRY_CHAINS
+ON
+AUTO_CARRY
+USR
+IGNORE_CARRY_BUFFERS
+OFF
+IGNORE_CARRY
+USR
+AUTO_CASCADE_CHAINS
+ON
+AUTO_CASCADE
+USR
+IGNORE_CASCADE_BUFFERS
+OFF
+IGNORE_CASCADE
+USR
+}
+# used_port {
+quotient4
+-1
+3
+quotient3
+-1
+3
+quotient2
+-1
+3
+quotient1
+-1
+3
+quotient0
+-1
+3
+numer9
+-1
+3
+numer8
+-1
+3
+numer7
+-1
+3
+numer6
+-1
+3
+numer5
+-1
+3
+numer4
+-1
+3
+numer31
+-1
+3
+numer30
+-1
+3
+numer3
+-1
+3
+numer29
+-1
+3
+numer28
+-1
+3
+numer27
+-1
+3
+numer26
+-1
+3
+numer25
+-1
+3
+numer24
+-1
+3
+numer23
+-1
+3
+numer22
+-1
+3
+numer21
+-1
+3
+numer20
+-1
+3
+numer2
+-1
+3
+numer19
+-1
+3
+numer18
+-1
+3
+numer17
+-1
+3
+numer16
+-1
+3
+numer15
+-1
+3
+numer14
+-1
+3
+numer13
+-1
+3
+numer12
+-1
+3
+numer11
+-1
+3
+numer10
+-1
+3
+numer1
+-1
+3
+numer0
+-1
+3
+denom5
+-1
+1
+denom3
+-1
+1
+denom1
+-1
+1
+denom0
+-1
+1
+denom4
+-1
+2
+denom2
+-1
+2
+}
+# macro_sequence
+
+# end
+# entity
+lpm_divide_8so
+# storage
+db|myArkanoid.(3).cnf
+db|myArkanoid.(3).cnf
+# case_insensitive
+# source_file
+db|lpm_divide_8so.tdf
+ce24cf53c65694518cce943ee4bcf144
+7
+# used_port {
+quotient9
+-1
+3
+quotient8
+-1
+3
+quotient7
+-1
+3
+quotient6
+-1
+3
+quotient5
+-1
+3
+quotient4
+-1
+3
+quotient31
+-1
+3
+quotient30
+-1
+3
+quotient3
+-1
+3
+quotient29
+-1
+3
+quotient28
+-1
+3
+quotient27
+-1
+3
+quotient26
+-1
+3
+quotient25
+-1
+3
+quotient24
+-1
+3
+quotient23
+-1
+3
+quotient22
+-1
+3
+quotient21
+-1
+3
+quotient20
+-1
+3
+quotient2
+-1
+3
+quotient19
+-1
+3
+quotient18
+-1
+3
+quotient17
+-1
+3
+quotient16
+-1
+3
+quotient15
+-1
+3
+quotient14
+-1
+3
+quotient13
+-1
+3
+quotient12
+-1
+3
+quotient11
+-1
+3
+quotient10
+-1
+3
+quotient1
+-1
+3
+quotient0
+-1
+3
+numer9
+-1
+3
+numer8
+-1
+3
+numer7
+-1
+3
+numer6
+-1
+3
+numer5
+-1
+3
+numer4
+-1
+3
+numer31
+-1
+3
+numer30
+-1
+3
+numer3
+-1
+3
+numer29
+-1
+3
+numer28
+-1
+3
+numer27
+-1
+3
+numer26
+-1
+3
+numer25
+-1
+3
+numer24
+-1
+3
+numer23
+-1
+3
+numer22
+-1
+3
+numer21
+-1
+3
+numer20
+-1
+3
+numer2
+-1
+3
+numer19
+-1
+3
+numer18
+-1
+3
+numer17
+-1
+3
+numer16
+-1
+3
+numer15
+-1
+3
+numer14
+-1
+3
+numer13
+-1
+3
+numer12
+-1
+3
+numer11
+-1
+3
+numer10
+-1
+3
+numer1
+-1
+3
+numer0
+-1
+3
+denom5
+-1
+3
+denom4
+-1
+3
+denom3
+-1
+3
+denom2
+-1
+3
+denom1
+-1
+3
+denom0
+-1
+3
+}
+# macro_sequence
+
+# end
+# entity
+abs_divider_lbg
+# storage
+db|myArkanoid.(4).cnf
+db|myArkanoid.(4).cnf
+# case_insensitive
+# source_file
+db|abs_divider_lbg.tdf
+3d798e48dc5d9f4d69c6389ac9c1842
+7
+# used_port {
+remainder5
+-1
+3
+remainder4
+-1
+3
+remainder3
+-1
+3
+remainder2
+-1
+3
+remainder1
+-1
+3
+remainder0
+-1
+3
+quotient9
+-1
+3
+quotient8
+-1
+3
+quotient7
+-1
+3
+quotient6
+-1
+3
+quotient5
+-1
+3
+quotient4
+-1
+3
+quotient31
+-1
+3
+quotient30
+-1
+3
+quotient3
+-1
+3
+quotient29
+-1
+3
+quotient28
+-1
+3
+quotient27
+-1
+3
+quotient26
+-1
+3
+quotient25
+-1
+3
+quotient24
+-1
+3
+quotient23
+-1
+3
+quotient22
+-1
+3
+quotient21
+-1
+3
+quotient20
+-1
+3
+quotient2
+-1
+3
+quotient19
+-1
+3
+quotient18
+-1
+3
+quotient17
+-1
+3
+quotient16
+-1
+3
+quotient15
+-1
+3
+quotient14
+-1
+3
+quotient13
+-1
+3
+quotient12
+-1
+3
+quotient11
+-1
+3
+quotient10
+-1
+3
+quotient1
+-1
+3
+quotient0
+-1
+3
+numerator9
+-1
+3
+numerator8
+-1
+3
+numerator7
+-1
+3
+numerator6
+-1
+3
+numerator5
+-1
+3
+numerator4
+-1
+3
+numerator31
+-1
+3
+numerator30
+-1
+3
+numerator3
+-1
+3
+numerator29
+-1
+3
+numerator28
+-1
+3
+numerator27
+-1
+3
+numerator26
+-1
+3
+numerator25
+-1
+3
+numerator24
+-1
+3
+numerator23
+-1
+3
+numerator22
+-1
+3
+numerator21
+-1
+3
+numerator20
+-1
+3
+numerator2
+-1
+3
+numerator19
+-1
+3
+numerator18
+-1
+3
+numerator17
+-1
+3
+numerator16
+-1
+3
+numerator15
+-1
+3
+numerator14
+-1
+3
+numerator13
+-1
+3
+numerator12
+-1
+3
+numerator11
+-1
+3
+numerator10
+-1
+3
+numerator1
+-1
+3
+numerator0
+-1
+3
+denominator5
+-1
+3
+denominator4
+-1
+3
+denominator3
+-1
+3
+denominator2
+-1
+3
+denominator1
+-1
+3
+denominator0
+-1
+3
+}
+# macro_sequence
+
+# end
+# entity
+alt_u_div_m2f
+# storage
+db|myArkanoid.(5).cnf
+db|myArkanoid.(5).cnf
+# case_insensitive
+# source_file
+db|alt_u_div_m2f.tdf
+50fe3ce086f769933f9a3469a2b533f7
+7
+# used_port {
+remainder5
+-1
+3
+remainder4
+-1
+3
+remainder3
+-1
+3
+remainder2
+-1
+3
+remainder1
+-1
+3
+remainder0
+-1
+3
+quotient9
+-1
+3
+quotient8
+-1
+3
+quotient7
+-1
+3
+quotient6
+-1
+3
+quotient5
+-1
+3
+quotient4
+-1
+3
+quotient31
+-1
+3
+quotient30
+-1
+3
+quotient3
+-1
+3
+quotient29
+-1
+3
+quotient28
+-1
+3
+quotient27
+-1
+3
+quotient26
+-1
+3
+quotient25
+-1
+3
+quotient24
+-1
+3
+quotient23
+-1
+3
+quotient22
+-1
+3
+quotient21
+-1
+3
+quotient20
+-1
+3
+quotient2
+-1
+3
+quotient19
+-1
+3
+quotient18
+-1
+3
+quotient17
+-1
+3
+quotient16
+-1
+3
+quotient15
+-1
+3
+quotient14
+-1
+3
+quotient13
+-1
+3
+quotient12
+-1
+3
+quotient11
+-1
+3
+quotient10
+-1
+3
+quotient1
+-1
+3
+quotient0
+-1
+3
+numerator9
+-1
+3
+numerator8
+-1
+3
+numerator7
+-1
+3
+numerator6
+-1
+3
+numerator5
+-1
+3
+numerator4
+-1
+3
+numerator31
+-1
+3
+numerator30
+-1
+3
+numerator3
+-1
+3
+numerator29
+-1
+3
+numerator28
+-1
+3
+numerator27
+-1
+3
+numerator26
+-1
+3
+numerator25
+-1
+3
+numerator24
+-1
+3
+numerator23
+-1
+3
+numerator22
+-1
+3
+numerator21
+-1
+3
+numerator20
+-1
+3
+numerator2
+-1
+3
+numerator19
+-1
+3
+numerator18
+-1
+3
+numerator17
+-1
+3
+numerator16
+-1
+3
+numerator15
+-1
+3
+numerator14
+-1
+3
+numerator13
+-1
+3
+numerator12
+-1
+3
+numerator11
+-1
+3
+numerator10
+-1
+3
+numerator1
+-1
+3
+numerator0
+-1
+3
+denominator5
+-1
+3
+denominator4
+-1
+3
+denominator3
+-1
+3
+denominator2
+-1
+3
+denominator1
+-1
+3
+denominator0
+-1
+3
+}
+# macro_sequence
+
+# end
+# entity
+add_sub_lkc
+# storage
+db|myArkanoid.(6).cnf
+db|myArkanoid.(6).cnf
+# case_insensitive
+# source_file
+db|add_sub_lkc.tdf
+dc8f1ea28c24fd6ddac292e3ba4f034
+7
+# used_port {
+result0
+-1
+3
+datab0
+-1
+3
+dataa0
+-1
+3
+cout
+-1
+3
+}
+# macro_sequence
+
+# end
+# entity
+add_sub_mkc
+# storage
+db|myArkanoid.(7).cnf
+db|myArkanoid.(7).cnf
+# case_insensitive
+# source_file
+db|add_sub_mkc.tdf
+55db7a45907585935dd833819e1ca16c
+7
+# used_port {
+result1
+-1
+3
+result0
+-1
+3
+datab1
+-1
+3
+datab0
+-1
+3
+dataa1
+-1
+3
+dataa0
+-1
+3
+cout
+-1
+3
+}
+# macro_sequence
+
+# end
+# entity
+lpm_abs_hq9
+# storage
+db|myArkanoid.(8).cnf
+db|myArkanoid.(8).cnf
+# case_insensitive
+# source_file
+db|lpm_abs_hq9.tdf
+2947417121bcada45f352647f689df
+7
+# used_port {
+result5
+-1
+3
+result4
+-1
+3
+result3
+-1
+3
+result2
+-1
+3
+result1
+-1
+3
+result0
+-1
+3
+data5
+-1
+3
+data4
+-1
+3
+data3
+-1
+3
+data2
+-1
+3
+data1
+-1
+3
+data0
+-1
+3
+}
+# macro_sequence
+
+# end
+# entity
+lpm_abs_0s9
+# storage
+db|myArkanoid.(9).cnf
+db|myArkanoid.(9).cnf
+# case_insensitive
+# source_file
+db|lpm_abs_0s9.tdf
+7d7739b1d04342ae32a2f5776cc10ee
+7
+# used_port {
+result9
+-1
+3
+result8
+-1
+3
+result7
+-1
+3
+result6
+-1
+3
+result5
+-1
+3
+result4
+-1
+3
+result31
+-1
+3
+result30
+-1
+3
+result3
+-1
+3
+result29
+-1
+3
+result28
+-1
+3
+result27
+-1
+3
+result26
+-1
+3
+result25
+-1
+3
+result24
+-1
+3
+result23
+-1
+3
+result22
+-1
+3
+result21
+-1
+3
+result20
+-1
+3
+result2
+-1
+3
+result19
+-1
+3
+result18
+-1
+3
+result17
+-1
+3
+result16
+-1
+3
+result15
+-1
+3
+result14
+-1
+3
+result13
+-1
+3
+result12
+-1
+3
+result11
+-1
+3
+result10
+-1
+3
+result1
+-1
+3
+result0
+-1
+3
+data9
+-1
+3
+data8
+-1
+3
+data7
+-1
+3
+data6
+-1
+3
+data5
+-1
+3
+data4
+-1
+3
+data31
+-1
+3
+data30
+-1
+3
+data3
+-1
+3
+data29
+-1
+3
+data28
+-1
+3
+data27
+-1
+3
+data26
+-1
+3
+data25
+-1
+3
+data24
+-1
+3
+data23
+-1
+3
+data22
+-1
+3
+data21
+-1
+3
+data20
+-1
+3
+data2
+-1
+3
+data19
+-1
+3
+data18
+-1
+3
+data17
+-1
+3
+data16
+-1
+3
+data15
+-1
+3
+data14
+-1
+3
+data13
+-1
+3
+data12
+-1
+3
+data11
+-1
+3
+data10
+-1
+3
+data1
+-1
+3
+data0
+-1
+3
+}
+# macro_sequence
+
+# end
+# entity
+lpm_divide
+# storage
+db|myArkanoid.(10).cnf
+db|myArkanoid.(10).cnf
+# case_insensitive
+# source_file
+c:|quartus|quartus|libraries|megafunctions|lpm_divide.tdf
+7b2071c21e42b4a04d32c24dcdc565
+7
+# user_parameter {
+LPM_WIDTHN
+32
+PARAMETER_UNKNOWN
+USR
+LPM_WIDTHD
+5
+PARAMETER_UNKNOWN
+USR
+LPM_NREPRESENTATION
+SIGNED
+PARAMETER_UNKNOWN
+USR
+LPM_DREPRESENTATION
+SIGNED
+PARAMETER_UNKNOWN
+USR
+LPM_PIPELINE
+0
+PARAMETER_UNKNOWN
+DEF
+LPM_REMAINDERPOSITIVE
+FALSE
+PARAMETER_UNKNOWN
+USR
+MAXIMIZE_SPEED
+5
+PARAMETER_UNKNOWN
+DEF
+CBXI_PARAMETER
+lpm_divide_ako
+PARAMETER_UNKNOWN
+USR
+CARRY_CHAIN
+MANUAL
+PARAMETER_UNKNOWN
+USR
+OPTIMIZE_FOR_SPEED
+5
+PARAMETER_UNKNOWN
+USR
+AUTO_CARRY_CHAINS
+ON
+AUTO_CARRY
+USR
+IGNORE_CARRY_BUFFERS
+OFF
+IGNORE_CARRY
+USR
+AUTO_CASCADE_CHAINS
+ON
+AUTO_CASCADE
+USR
+IGNORE_CASCADE_BUFFERS
+OFF
+IGNORE_CASCADE
+USR
+}
+# used_port {
+remain4
+-1
+3
+remain3
+-1
+3
+remain2
+-1
+3
+remain1
+-1
+3
+remain0
+-1
+3
+numer9
+-1
+1
+numer8
+-1
+1
+numer7
+-1
+1
+numer6
+-1
+1
+numer5
+-1
+1
+numer4
+-1
+1
+numer31
+-1
+1
+numer30
+-1
+1
+numer3
+-1
+1
+numer29
+-1
+1
+numer28
+-1
+1
+numer27
+-1
+1
+numer26
+-1
+1
+numer25
+-1
+1
+numer24
+-1
+1
+numer23
+-1
+1
+numer22
+-1
+1
+numer21
+-1
+1
+numer20
+-1
+1
+numer2
+-1
+1
+numer19
+-1
+1
+numer18
+-1
+1
+numer17
+-1
+1
+numer16
+-1
+1
+numer15
+-1
+1
+numer14
+-1
+1
+numer13
+-1
+1
+numer12
+-1
+1
+numer11
+-1
+1
+numer10
+-1
+1
+numer1
+-1
+1
+numer0
+-1
+1
+denom4
+-1
+1
+denom2
+-1
+1
+denom0
+-1
+1
+denom3
+-1
+2
+denom1
+-1
+2
+}
+# macro_sequence
+
+# end
+# entity
+lpm_divide_ako
+# storage
+db|myArkanoid.(11).cnf
+db|myArkanoid.(11).cnf
+# case_insensitive
+# source_file
+db|lpm_divide_ako.tdf
+1f1b6a2685b2672329ad99fffdcf4098
+7
+# used_port {
+remain4
+-1
+3
+remain3
+-1
+3
+remain2
+-1
+3
+remain1
+-1
+3
+remain0
+-1
+3
+numer9
+-1
+3
+numer8
+-1
+3
+numer7
+-1
+3
+numer6
+-1
+3
+numer5
+-1
+3
+numer4
+-1
+3
+numer31
+-1
+3
+numer30
+-1
+3
+numer3
+-1
+3
+numer29
+-1
+3
+numer28
+-1
+3
+numer27
+-1
+3
+numer26
+-1
+3
+numer25
+-1
+3
+numer24
+-1
+3
+numer23
+-1
+3
+numer22
+-1
+3
+numer21
+-1
+3
+numer20
+-1
+3
+numer2
+-1
+3
+numer19
+-1
+3
+numer18
+-1
+3
+numer17
+-1
+3
+numer16
+-1
+3
+numer15
+-1
+3
+numer14
+-1
+3
+numer13
+-1
+3
+numer12
+-1
+3
+numer11
+-1
+3
+numer10
+-1
+3
+numer1
+-1
+3
+numer0
+-1
+3
+denom4
+-1
+3
+denom3
+-1
+3
+denom2
+-1
+3
+denom1
+-1
+3
+denom0
+-1
+3
+}
+# macro_sequence
+
+# end
+# entity
+abs_divider_kbg
+# storage
+db|myArkanoid.(12).cnf
+db|myArkanoid.(12).cnf
+# case_insensitive
+# source_file
+db|abs_divider_kbg.tdf
+4cf23e7a562d4a454c6ec938421ee61a
+7
+# used_port {
+remainder4
+-1
+3
+remainder3
+-1
+3
+remainder2
+-1
+3
+remainder1
+-1
+3
+remainder0
+-1
+3
+quotient9
+-1
+3
+quotient8
+-1
+3
+quotient7
+-1
+3
+quotient6
+-1
+3
+quotient5
+-1
+3
+quotient4
+-1
+3
+quotient31
+-1
+3
+quotient30
+-1
+3
+quotient3
+-1
+3
+quotient29
+-1
+3
+quotient28
+-1
+3
+quotient27
+-1
+3
+quotient26
+-1
+3
+quotient25
+-1
+3
+quotient24
+-1
+3
+quotient23
+-1
+3
+quotient22
+-1
+3
+quotient21
+-1
+3
+quotient20
+-1
+3
+quotient2
+-1
+3
+quotient19
+-1
+3
+quotient18
+-1
+3
+quotient17
+-1
+3
+quotient16
+-1
+3
+quotient15
+-1
+3
+quotient14
+-1
+3
+quotient13
+-1
+3
+quotient12
+-1
+3
+quotient11
+-1
+3
+quotient10
+-1
+3
+quotient1
+-1
+3
+quotient0
+-1
+3
+numerator9
+-1
+3
+numerator8
+-1
+3
+numerator7
+-1
+3
+numerator6
+-1
+3
+numerator5
+-1
+3
+numerator4
+-1
+3
+numerator31
+-1
+3
+numerator30
+-1
+3
+numerator3
+-1
+3
+numerator29
+-1
+3
+numerator28
+-1
+3
+numerator27
+-1
+3
+numerator26
+-1
+3
+numerator25
+-1
+3
+numerator24
+-1
+3
+numerator23
+-1
+3
+numerator22
+-1
+3
+numerator21
+-1
+3
+numerator20
+-1
+3
+numerator2
+-1
+3
+numerator19
+-1
+3
+numerator18
+-1
+3
+numerator17
+-1
+3
+numerator16
+-1
+3
+numerator15
+-1
+3
+numerator14
+-1
+3
+numerator13
+-1
+3
+numerator12
+-1
+3
+numerator11
+-1
+3
+numerator10
+-1
+3
+numerator1
+-1
+3
+numerator0
+-1
+3
+denominator4
+-1
+3
+denominator3
+-1
+3
+denominator2
+-1
+3
+denominator1
+-1
+3
+denominator0
+-1
+3
+}
+# macro_sequence
+
+# end
+# entity
+alt_u_div_k2f
+# storage
+db|myArkanoid.(13).cnf
+db|myArkanoid.(13).cnf
+# case_insensitive
+# source_file
+db|alt_u_div_k2f.tdf
+9de0661664a830cc7af7b4cc99e19c
+7
+# used_port {
+remainder4
+-1
+3
+remainder3
+-1
+3
+remainder2
+-1
+3
+remainder1
+-1
+3
+remainder0
+-1
+3
+quotient9
+-1
+3
+quotient8
+-1
+3
+quotient7
+-1
+3
+quotient6
+-1
+3
+quotient5
+-1
+3
+quotient4
+-1
+3
+quotient31
+-1
+3
+quotient30
+-1
+3
+quotient3
+-1
+3
+quotient29
+-1
+3
+quotient28
+-1
+3
+quotient27
+-1
+3
+quotient26
+-1
+3
+quotient25
+-1
+3
+quotient24
+-1
+3
+quotient23
+-1
+3
+quotient22
+-1
+3
+quotient21
+-1
+3
+quotient20
+-1
+3
+quotient2
+-1
+3
+quotient19
+-1
+3
+quotient18
+-1
+3
+quotient17
+-1
+3
+quotient16
+-1
+3
+quotient15
+-1
+3
+quotient14
+-1
+3
+quotient13
+-1
+3
+quotient12
+-1
+3
+quotient11
+-1
+3
+quotient10
+-1
+3
+quotient1
+-1
+3
+quotient0
+-1
+3
+numerator9
+-1
+3
+numerator8
+-1
+3
+numerator7
+-1
+3
+numerator6
+-1
+3
+numerator5
+-1
+3
+numerator4
+-1
+3
+numerator31
+-1
+3
+numerator30
+-1
+3
+numerator3
+-1
+3
+numerator29
+-1
+3
+numerator28
+-1
+3
+numerator27
+-1
+3
+numerator26
+-1
+3
+numerator25
+-1
+3
+numerator24
+-1
+3
+numerator23
+-1
+3
+numerator22
+-1
+3
+numerator21
+-1
+3
+numerator20
+-1
+3
+numerator2
+-1
+3
+numerator19
+-1
+3
+numerator18
+-1
+3
+numerator17
+-1
+3
+numerator16
+-1
+3
+numerator15
+-1
+3
+numerator14
+-1
+3
+numerator13
+-1
+3
+numerator12
+-1
+3
+numerator11
+-1
+3
+numerator10
+-1
+3
+numerator1
+-1
+3
+numerator0
+-1
+3
+denominator4
+-1
+3
+denominator3
+-1
+3
+denominator2
+-1
+3
+denominator1
+-1
+3
+denominator0
+-1
+3
+}
+# macro_sequence
+
+# end
+# entity
+lpm_abs_gq9
+# storage
+db|myArkanoid.(14).cnf
+db|myArkanoid.(14).cnf
+# case_insensitive
+# source_file
+db|lpm_abs_gq9.tdf
+ff9f2265fb1c2c2d56f34d4a49bfade4
+7
+# used_port {
+result4
+-1
+3
+result3
+-1
+3
+result2
+-1
+3
+result1
+-1
+3
+result0
+-1
+3
+data4
+-1
+3
+data3
+-1
+3
+data2
+-1
+3
+data1
+-1
+3
+data0
+-1
+3
+}
+# macro_sequence
+
+# end
+# entity
+lpm_divide
+# storage
+db|myArkanoid.(15).cnf
+db|myArkanoid.(15).cnf
+# case_insensitive
+# source_file
+c:|quartus|quartus|libraries|megafunctions|lpm_divide.tdf
+7b2071c21e42b4a04d32c24dcdc565
+7
+# user_parameter {
+LPM_WIDTHN
+32
+PARAMETER_UNKNOWN
+USR
+LPM_WIDTHD
+5
+PARAMETER_UNKNOWN
+USR
+LPM_NREPRESENTATION
+SIGNED
+PARAMETER_UNKNOWN
+USR
+LPM_DREPRESENTATION
+SIGNED
+PARAMETER_UNKNOWN
+USR
+LPM_PIPELINE
+0
+PARAMETER_UNKNOWN
+DEF
+LPM_REMAINDERPOSITIVE
+FALSE
+PARAMETER_UNKNOWN
+USR
+MAXIMIZE_SPEED
+5
+PARAMETER_UNKNOWN
+DEF
+CBXI_PARAMETER
+lpm_divide_ako
+PARAMETER_UNKNOWN
+USR
+CARRY_CHAIN
+MANUAL
+PARAMETER_UNKNOWN
+USR
+OPTIMIZE_FOR_SPEED
+5
+PARAMETER_UNKNOWN
+USR
+AUTO_CARRY_CHAINS
+ON
+AUTO_CARRY
+USR
+IGNORE_CARRY_BUFFERS
+OFF
+IGNORE_CARRY
+USR
+AUTO_CASCADE_CHAINS
+ON
+AUTO_CASCADE
+USR
+IGNORE_CASCADE_BUFFERS
+OFF
+IGNORE_CASCADE
+USR
+}
+# used_port {
+remain4
+-1
+3
+remain3
+-1
+3
+remain2
+-1
+3
+remain1
+-1
+3
+remain0
+-1
+3
+numer9
+-1
+3
+numer8
+-1
+3
+numer7
+-1
+3
+numer6
+-1
+3
+numer5
+-1
+3
+numer4
+-1
+3
+numer31
+-1
+3
+numer30
+-1
+3
+numer3
+-1
+3
+numer29
+-1
+3
+numer28
+-1
+3
+numer27
+-1
+3
+numer26
+-1
+3
+numer25
+-1
+3
+numer24
+-1
+3
+numer23
+-1
+3
+numer22
+-1
+3
+numer21
+-1
+3
+numer20
+-1
+3
+numer2
+-1
+3
+numer19
+-1
+3
+numer18
+-1
+3
+numer17
+-1
+3
+numer16
+-1
+3
+numer15
+-1
+3
+numer14
+-1
+3
+numer13
+-1
+3
+numer12
+-1
+3
+numer11
+-1
+3
+numer10
+-1
+3
+numer1
+-1
+3
+numer0
+-1
+3
+denom4
+-1
+1
+denom2
+-1
+1
+denom0
+-1
+1
+denom3
+-1
+2
+denom1
+-1
+2
+}
+# macro_sequence
+
+# end
+# entity
+lpm_divide
+# storage
+db|myArkanoid.(16).cnf
+db|myArkanoid.(16).cnf
+# case_insensitive
+# source_file
+c:|quartus|quartus|libraries|megafunctions|lpm_divide.tdf
+7b2071c21e42b4a04d32c24dcdc565
+7
+# user_parameter {
+LPM_WIDTHN
+32
+PARAMETER_UNKNOWN
+USR
+LPM_WIDTHD
+5
+PARAMETER_UNKNOWN
+USR
+LPM_NREPRESENTATION
+SIGNED
+PARAMETER_UNKNOWN
+USR
+LPM_DREPRESENTATION
+SIGNED
+PARAMETER_UNKNOWN
+USR
+LPM_PIPELINE
+0
+PARAMETER_UNKNOWN
+DEF
+LPM_REMAINDERPOSITIVE
+FALSE
+PARAMETER_UNKNOWN
+USR
+MAXIMIZE_SPEED
+5
+PARAMETER_UNKNOWN
+DEF
+CBXI_PARAMETER
+lpm_divide_7so
+PARAMETER_UNKNOWN
+USR
+CARRY_CHAIN
+MANUAL
+PARAMETER_UNKNOWN
+USR
+OPTIMIZE_FOR_SPEED
+5
+PARAMETER_UNKNOWN
+USR
+AUTO_CARRY_CHAINS
+ON
+AUTO_CARRY
+USR
+IGNORE_CARRY_BUFFERS
+OFF
+IGNORE_CARRY
+USR
+AUTO_CASCADE_CHAINS
+ON
+AUTO_CASCADE
+USR
+IGNORE_CASCADE_BUFFERS
+OFF
+IGNORE_CASCADE
+USR
+}
+# used_port {
+quotient9
+-1
+3
+quotient8
+-1
+3
+quotient7
+-1
+3
+quotient6
+-1
+3
+quotient5
+-1
+3
+quotient4
+-1
+3
+quotient31
+-1
+3
+quotient30
+-1
+3
+quotient3
+-1
+3
+quotient29
+-1
+3
+quotient28
+-1
+3
+quotient27
+-1
+3
+quotient26
+-1
+3
+quotient25
+-1
+3
+quotient24
+-1
+3
+quotient23
+-1
+3
+quotient22
+-1
+3
+quotient21
+-1
+3
+quotient20
+-1
+3
+quotient2
+-1
+3
+quotient19
+-1
+3
+quotient18
+-1
+3
+quotient17
+-1
+3
+quotient16
+-1
+3
+quotient15
+-1
+3
+quotient14
+-1
+3
+quotient13
+-1
+3
+quotient12
+-1
+3
+quotient11
+-1
+3
+quotient10
+-1
+3
+quotient1
+-1
+3
+quotient0
+-1
+3
+numer9
+-1
+3
+numer8
+-1
+3
+numer7
+-1
+3
+numer6
+-1
+3
+numer5
+-1
+3
+numer4
+-1
+3
+numer31
+-1
+3
+numer30
+-1
+3
+numer3
+-1
+3
+numer29
+-1
+3
+numer28
+-1
+3
+numer27
+-1
+3
+numer26
+-1
+3
+numer25
+-1
+3
+numer24
+-1
+3
+numer23
+-1
+3
+numer22
+-1
+3
+numer21
+-1
+3
+numer20
+-1
+3
+numer2
+-1
+3
+numer19
+-1
+3
+numer18
+-1
+3
+numer17
+-1
+3
+numer16
+-1
+3
+numer15
+-1
+3
+numer14
+-1
+3
+numer13
+-1
+3
+numer12
+-1
+3
+numer11
+-1
+3
+numer10
+-1
+3
+numer1
+-1
+3
+numer0
+-1
+3
+denom4
+-1
+1
+denom2
+-1
+1
+denom0
+-1
+1
+denom3
+-1
+2
+denom1
+-1
+2
+}
+# macro_sequence
+
+# end
+# entity
+lpm_divide_7so
+# storage
+db|myArkanoid.(17).cnf
+db|myArkanoid.(17).cnf
+# case_insensitive
+# source_file
+db|lpm_divide_7so.tdf
+f17b182bbdbd1c4275bccdea794ac39
+7
+# used_port {
+quotient9
+-1
+3
+quotient8
+-1
+3
+quotient7
+-1
+3
+quotient6
+-1
+3
+quotient5
+-1
+3
+quotient4
+-1
+3
+quotient31
+-1
+3
+quotient30
+-1
+3
+quotient3
+-1
+3
+quotient29
+-1
+3
+quotient28
+-1
+3
+quotient27
+-1
+3
+quotient26
+-1
+3
+quotient25
+-1
+3
+quotient24
+-1
+3
+quotient23
+-1
+3
+quotient22
+-1
+3
+quotient21
+-1
+3
+quotient20
+-1
+3
+quotient2
+-1
+3
+quotient19
+-1
+3
+quotient18
+-1
+3
+quotient17
+-1
+3
+quotient16
+-1
+3
+quotient15
+-1
+3
+quotient14
+-1
+3
+quotient13
+-1
+3
+quotient12
+-1
+3
+quotient11
+-1
+3
+quotient10
+-1
+3
+quotient1
+-1
+3
+quotient0
+-1
+3
+numer9
+-1
+3
+numer8
+-1
+3
+numer7
+-1
+3
+numer6
+-1
+3
+numer5
+-1
+3
+numer4
+-1
+3
+numer31
+-1
+3
+numer30
+-1
+3
+numer3
+-1
+3
+numer29
+-1
+3
+numer28
+-1
+3
+numer27
+-1
+3
+numer26
+-1
+3
+numer25
+-1
+3
+numer24
+-1
+3
+numer23
+-1
+3
+numer22
+-1
+3
+numer21
+-1
+3
+numer20
+-1
+3
+numer2
+-1
+3
+numer19
+-1
+3
+numer18
+-1
+3
+numer17
+-1
+3
+numer16
+-1
+3
+numer15
+-1
+3
+numer14
+-1
+3
+numer13
+-1
+3
+numer12
+-1
+3
+numer11
+-1
+3
+numer10
+-1
+3
+numer1
+-1
+3
+numer0
+-1
+3
+denom4
+-1
+3
+denom3
+-1
+3
+denom2
+-1
+3
+denom1
+-1
+3
+denom0
+-1
+3
+}
+# macro_sequence
+
+# end
+# entity
+ClockDivider
+# storage
+db|myArkanoid.(18).cnf
+db|myArkanoid.(18).cnf
+# logic_option {
+AUTO_RAM_RECOGNITION
+ON
+}
+# case_sensitive
+# source_file
+clockdivider.v
+a841afd85faaa4898873ca53f3881a3e
+8
+# internal_option {
+HDL_INITIAL_FANOUT_LIMIT
+OFF
+AUTO_RESOURCE_SHARING
+OFF
+AUTO_RAM_RECOGNITION
+ON
+AUTO_ROM_RECOGNITION
+ON
+IGNORE_VERILOG_INITIAL_CONSTRUCTS
+OFF
+VERILOG_CONSTANT_LOOP_LIMIT
+5000
+VERILOG_NON_CONSTANT_LOOP_LIMIT
+250
+}
+# hierarchies {
+ClockDivider:inst1
+}
+# macro_sequence
+_arkanoid_header__int_to_digital__vga_sync_
+# end
+# entity
+Debouncer
+# storage
+db|myArkanoid.(19).cnf
+db|myArkanoid.(19).cnf
+# logic_option {
+AUTO_RAM_RECOGNITION
+ON
+}
+# case_sensitive
+# source_file
+debouncer.v
+30abc2e7a4b218a294995468548d80
+8
+# internal_option {
+HDL_INITIAL_FANOUT_LIMIT
+OFF
+AUTO_RESOURCE_SHARING
+OFF
+AUTO_RAM_RECOGNITION
+ON
+AUTO_ROM_RECOGNITION
+ON
+IGNORE_VERILOG_INITIAL_CONSTRUCTS
+OFF
+VERILOG_CONSTANT_LOOP_LIMIT
+5000
+VERILOG_NON_CONSTANT_LOOP_LIMIT
+250
+}
+# hierarchies {
+Debouncer:inst2
+Debouncer:inst3
+Debouncer:inst4
+Debouncer:inst5
+}
+# macro_sequence
+_arkanoid_header__int_to_digital__vga_sync_
+# end
+# entity
+TotalScheme
+# storage
+db|myArkanoid.(0).cnf
+db|myArkanoid.(0).cnf
+# case_insensitive
+# source_file
+totalscheme.bdf
+8c0b58b10205cb7a79fb14d2a3546a2
+26
+# internal_option {
+BLOCK_DESIGN_NAMING
+AUTO
+}
+# hierarchies {
+|
+}
+# macro_sequence
+
+# end
+# entity
+Arkanoid
+# storage
+db|myArkanoid.(1).cnf
+db|myArkanoid.(1).cnf
+# logic_option {
+AUTO_RAM_RECOGNITION
+ON
+}
+# case_sensitive
+# source_file
+arkanoid.v
+3ee3915498764b76f5fd3cebc57479
+8
+# internal_option {
+HDL_INITIAL_FANOUT_LIMIT
+OFF
+AUTO_RESOURCE_SHARING
+OFF
+AUTO_RAM_RECOGNITION
+ON
+AUTO_ROM_RECOGNITION
+ON
+IGNORE_VERILOG_INITIAL_CONSTRUCTS
+OFF
+VERILOG_CONSTANT_LOOP_LIMIT
+5000
+VERILOG_NON_CONSTANT_LOOP_LIMIT
+250
+}
+# user_parameter {
+CELL_SIZE
+20
+PARAMETER_SIGNED_DEC
+USR
+BALL_SIZE
+1
+PARAMETER_SIGNED_DEC
+USR
+BALL_SPEED
+3
+PARAMETER_SIGNED_DEC
+USR
+PLATFORM_WIDTH
+7
+PARAMETER_SIGNED_DEC
+USR
+BK_COLOR_R
+1111
+PARAMETER_UNSIGNED_BIN
+USR
+BK_COLOR_G
+1111
+PARAMETER_UNSIGNED_BIN
+USR
+BK_COLOR_B
+1111
+PARAMETER_UNSIGNED_BIN
+USR
+STABLE_COLOR_R
+0011
+PARAMETER_UNSIGNED_BIN
+USR
+STABLE_COLOR_G
+1100
+PARAMETER_UNSIGNED_BIN
+USR
+STABLE_COLOR_B
+0110
+PARAMETER_UNSIGNED_BIN
+USR
+BALL_COLOR_R
+0000
+PARAMETER_UNSIGNED_BIN
+USR
+BALL_COLOR_G
+0000
+PARAMETER_UNSIGNED_BIN
+USR
+BALL_COLOR_B
+1111
+PARAMETER_UNSIGNED_BIN
+USR
+PLATFORM_COLOR_R
+1111
+PARAMETER_UNSIGNED_BIN
+USR
+PLATFORM_COLOR_G
+0000
+PARAMETER_UNSIGNED_BIN
+USR
+PLATFORM_COLOR_B
+0000
+PARAMETER_UNSIGNED_BIN
+USR
+}
+# include_file {
+vga_sync.v
+e4d6d191c41b45dd71332235369f23c
+arkanoid_header.v
+6afec8cf205492578e6cf615fb6732fe
+int_to_digital.v
+c797102e6d8cb4a6d9d64274fcb6a947
+}
+# hierarchies {
+Arkanoid:inst
+}
+# macro_sequence
+_arkanoid_header__int_to_digital__vga_sync_
+# end
+# complete
+
\ No newline at end of file
diff --git a/db/myArkanoid.lpc.html b/db/myArkanoid.lpc.html
new file mode 100644
index 0000000..43fbba3
--- /dev/null
+++ b/db/myArkanoid.lpc.html
@@ -0,0 +1,114 @@
+
+
+| Hierarchy |
+Input |
+Constant Input |
+Unused Input |
+Floating Input |
+Output |
+Constant Output |
+Unused Output |
+Floating Output |
+Bidir |
+Constant Bidir |
+Unused Bidir |
+Input only Bidir |
+Output only Bidir |
+
+
+| inst5 |
+2 |
+0 |
+0 |
+0 |
+1 |
+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
+
+
+| inst4 |
+2 |
+0 |
+0 |
+0 |
+1 |
+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
+
+
+| inst3 |
+2 |
+0 |
+0 |
+0 |
+1 |
+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
+
+
+| inst2 |
+2 |
+0 |
+0 |
+0 |
+1 |
+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
+
+
+| inst1 |
+1 |
+0 |
+0 |
+0 |
+1 |
+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
+
+
+| inst |
+5 |
+0 |
+0 |
+0 |
+50 |
+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
+
+
diff --git a/db/myArkanoid.lpc.rdb b/db/myArkanoid.lpc.rdb
new file mode 100644
index 0000000..03264e7
Binary files /dev/null and b/db/myArkanoid.lpc.rdb differ
diff --git a/db/myArkanoid.lpc.txt b/db/myArkanoid.lpc.txt
new file mode 100644
index 0000000..f94530b
--- /dev/null
+++ b/db/myArkanoid.lpc.txt
@@ -0,0 +1,12 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; inst5 ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; inst4 ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; inst3 ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; inst2 ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; inst1 ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; inst ; 5 ; 0 ; 0 ; 0 ; 50 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/db/myArkanoid.map.bpm b/db/myArkanoid.map.bpm
new file mode 100644
index 0000000..be328d4
Binary files /dev/null and b/db/myArkanoid.map.bpm differ
diff --git a/db/myArkanoid.map.cdb b/db/myArkanoid.map.cdb
new file mode 100644
index 0000000..35beca5
Binary files /dev/null and b/db/myArkanoid.map.cdb differ
diff --git a/db/myArkanoid.map.ecobp b/db/myArkanoid.map.ecobp
new file mode 100644
index 0000000..e05efff
Binary files /dev/null and b/db/myArkanoid.map.ecobp differ
diff --git a/db/myArkanoid.map.hdb b/db/myArkanoid.map.hdb
new file mode 100644
index 0000000..a30c8a7
Binary files /dev/null and b/db/myArkanoid.map.hdb differ
diff --git a/db/myArkanoid.map.kpt b/db/myArkanoid.map.kpt
new file mode 100644
index 0000000..80cdac0
Binary files /dev/null and b/db/myArkanoid.map.kpt differ
diff --git a/db/myArkanoid.map.logdb b/db/myArkanoid.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/db/myArkanoid.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/db/myArkanoid.map.qmsg b/db/myArkanoid.map.qmsg
new file mode 100644
index 0000000..62d5fcc
--- /dev/null
+++ b/db/myArkanoid.map.qmsg
@@ -0,0 +1,43 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 28 14:18:56 2012 " "Info: Processing started: Mon May 28 14:18:56 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "debouncer.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file debouncer.v" { { "Info" "ISGN_ENTITY_NAME" "1 Debouncer " "Info: Found entity 1: Debouncer" { } { { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "totalscheme.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file totalscheme.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 TotalScheme " "Info: Found entity 1: TotalScheme" { } { { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "arkanoid.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file arkanoid.v" { { "Info" "ISGN_ENTITY_NAME" "1 Arkanoid " "Info: Found entity 1: Arkanoid" { } { { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "arkanoid_header.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file arkanoid_header.v" { } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "int_to_digital.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file int_to_digital.v" { } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga_sync.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file vga_sync.v" { } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clockdivider.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clockdivider.v" { { "Info" "ISGN_ENTITY_NAME" "1 ClockDivider " "Info: Found entity 1: ClockDivider" { } { { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_TOP" "TotalScheme " "Info: Elaborating entity \"TotalScheme\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Arkanoid Arkanoid:inst " "Info: Elaborating entity \"Arkanoid\" for hierarchy \"Arkanoid:inst\"" { } { { "TotalScheme.bdf" "inst" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { 128 464 616 352 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VERI_CANT_ANALYZE_CASE_STATEMENT" "int_to_digital.v(21) " "Warning (10762): Verilog HDL Case Statement warning at int_to_digital.v(21): can't check case statement for completeness because the case expression has too many possible states" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 21 0 0 } } } 0 10762 "Verilog HDL Case Statement warning at %1!s!: can't check case statement for completeness because the case expression has too many possible states" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VERI_2104_UNCONVERTED" "n1 IntToDigital int_to_digital.v(10) " "Warning (10776): Verilog HDL warning at int_to_digital.v(10): variable n1 in static task or function IntToDigital may have unintended latch behavior" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 10 0 0 } } } 0 10776 "Verilog HDL warning at %3!s!: variable %1!s! in static task or function %2!s! may have unintended latch behavior" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VERI_2104_UNCONVERTED" "n0 IntToDigital int_to_digital.v(10) " "Warning (10776): Verilog HDL warning at int_to_digital.v(10): variable n0 in static task or function IntToDigital may have unintended latch behavior" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 10 0 0 } } } 0 10776 "Verilog HDL warning at %3!s!: variable %1!s! in static task or function %2!s! may have unintended latch behavior" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VERI_2104_UNCONVERTED" "low IntToDigital int_to_digital.v(9) " "Warning (10776): Verilog HDL warning at int_to_digital.v(9): variable low in static task or function IntToDigital may have unintended latch behavior" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 9 0 0 } } } 0 10776 "Verilog HDL warning at %3!s!: variable %1!s! in static task or function %2!s! may have unintended latch behavior" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "IntToDigital.low\[6..0\] 0 int_to_digital.v(9) " "Warning (10030): Net \"IntToDigital.low\[6..0\]\" at int_to_digital.v(9) has no driver or initial value, using a default initial value '0'" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "" 0 -1}
+{ "Info" "IVRFX_MULTI_DIMENSION_OBJECT_INFO" "field " "Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"field\" into its bus" { } { } 0 10008 "Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"%1!s!\" into its bus" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ClockDivider ClockDivider:inst1 " "Info: Elaborating entity \"ClockDivider\" for hierarchy \"ClockDivider:inst1\"" { } { { "TotalScheme.bdf" "inst1" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -192 160 312 -128 "inst1" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Debouncer Debouncer:inst2 " "Info: Elaborating entity \"Debouncer\" for hierarchy \"Debouncer:inst2\"" { } { { "TotalScheme.bdf" "inst2" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -96 168 304 0 "inst2" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ILPMS_INFERENCING_SUMMARY" "6 " "Info: Inferred 6 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div3 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div3\"" { } { { "Arkanoid.v" "Div3" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 299 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div2 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div2\"" { } { { "Arkanoid.v" "Div2" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 298 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Mod1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Mod1\"" { } { { "int_to_digital.v" "Mod1" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div1\"" { } { { "int_to_digital.v" "Div1" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Mod0 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Mod0\"" { } { { "int_to_digital.v" "Mod0" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div0 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div0\"" { } { { "int_to_digital.v" "Div0" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 -1}
+{ "Info" "ISGN_ELABORATION_HEADER" "Arkanoid:inst\|lpm_divide:Div3 " "Info: Elaborated megafunction instantiation \"Arkanoid:inst\|lpm_divide:Div3\"" { } { { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 299 -1 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "Arkanoid:inst\|lpm_divide:Div3 " "Info: Instantiated megafunction \"Arkanoid:inst\|lpm_divide:Div3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Info: Parameter \"LPM_WIDTHN\" = \"32\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 6 " "Info: Parameter \"LPM_WIDTHD\" = \"6\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION SIGNED " "Info: Parameter \"LPM_NREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION SIGNED " "Info: Parameter \"LPM_DREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT LPM_REMAINDERPOSITIVE=FALSE " "Info: Parameter \"LPM_HINT\" = \"LPM_REMAINDERPOSITIVE=FALSE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 299 -1 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_8so.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_8so.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_8so " "Info: Found entity 1: lpm_divide_8so" { } { { "db/lpm_divide_8so.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_divide_8so.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/abs_divider_lbg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/abs_divider_lbg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 abs_divider_lbg " "Info: Found entity 1: abs_divider_lbg" { } { { "db/abs_divider_lbg.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/abs_divider_lbg.tdf" 28 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_m2f.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_m2f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_m2f " "Info: Found entity 1: alt_u_div_m2f" { } { { "db/alt_u_div_m2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_m2f.tdf" 26 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_lkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_lkc " "Info: Found entity 1: add_sub_lkc" { } { { "db/add_sub_lkc.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/add_sub_lkc.tdf" 22 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_mkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_mkc " "Info: Found entity 1: add_sub_mkc" { } { { "db/add_sub_mkc.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/add_sub_mkc.tdf" 22 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_hq9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_hq9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_hq9 " "Info: Found entity 1: lpm_abs_hq9" { } { { "db/lpm_abs_hq9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_hq9.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_0s9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_0s9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_0s9 " "Info: Found entity 1: lpm_abs_0s9" { } { { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_ELABORATION_HEADER" "Arkanoid:inst\|lpm_divide:Mod1 " "Info: Elaborated megafunction instantiation \"Arkanoid:inst\|lpm_divide:Mod1\"" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "Arkanoid:inst\|lpm_divide:Mod1 " "Info: Instantiated megafunction \"Arkanoid:inst\|lpm_divide:Mod1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Info: Parameter \"LPM_WIDTHN\" = \"32\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 5 " "Info: Parameter \"LPM_WIDTHD\" = \"5\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION SIGNED " "Info: Parameter \"LPM_NREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION SIGNED " "Info: Parameter \"LPM_DREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT LPM_REMAINDERPOSITIVE=FALSE " "Info: Parameter \"LPM_HINT\" = \"LPM_REMAINDERPOSITIVE=FALSE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_ako.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_ako.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_ako " "Info: Found entity 1: lpm_divide_ako" { } { { "db/lpm_divide_ako.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_divide_ako.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/abs_divider_kbg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/abs_divider_kbg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 abs_divider_kbg " "Info: Found entity 1: abs_divider_kbg" { } { { "db/abs_divider_kbg.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/abs_divider_kbg.tdf" 28 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_k2f.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_k2f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_k2f " "Info: Found entity 1: alt_u_div_k2f" { } { { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 26 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_gq9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_gq9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_gq9 " "Info: Found entity 1: lpm_abs_gq9" { } { { "db/lpm_abs_gq9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_gq9.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_ELABORATION_HEADER" "Arkanoid:inst\|lpm_divide:Div1 " "Info: Elaborated megafunction instantiation \"Arkanoid:inst\|lpm_divide:Div1\"" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "Arkanoid:inst\|lpm_divide:Div1 " "Info: Instantiated megafunction \"Arkanoid:inst\|lpm_divide:Div1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Info: Parameter \"LPM_WIDTHN\" = \"32\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 5 " "Info: Parameter \"LPM_WIDTHD\" = \"5\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION SIGNED " "Info: Parameter \"LPM_NREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION SIGNED " "Info: Parameter \"LPM_DREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT LPM_REMAINDERPOSITIVE=FALSE " "Info: Parameter \"LPM_HINT\" = \"LPM_REMAINDERPOSITIVE=FALSE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_7so.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_7so.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_7so " "Info: Found entity 1: lpm_divide_7so" { } { { "db/lpm_divide_7so.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_divide_7so.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 2 " "Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Arkanoid:inst\|ball_direction~6 " "Info: Register \"Arkanoid:inst\|ball_direction~6\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Arkanoid:inst\|ball_direction~7 " "Info: Register \"Arkanoid:inst\|ball_direction~7\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} } { } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "8037 " "Info: Implemented 8037 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "50 " "Info: Implemented 50 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "7982 " "Info: Implemented 7982 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "227 " "Info: Peak virtual memory: 227 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 28 14:21:58 2012 " "Info: Processing ended: Mon May 28 14:21:58 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:03:02 " "Info: Elapsed time: 00:03:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:03:06 " "Info: Total CPU time (on all processors): 00:03:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/db/myArkanoid.map_bb.cdb b/db/myArkanoid.map_bb.cdb
new file mode 100644
index 0000000..482e3ec
Binary files /dev/null and b/db/myArkanoid.map_bb.cdb differ
diff --git a/db/myArkanoid.map_bb.hdb b/db/myArkanoid.map_bb.hdb
new file mode 100644
index 0000000..d52e499
Binary files /dev/null and b/db/myArkanoid.map_bb.hdb differ
diff --git a/db/myArkanoid.map_bb.logdb b/db/myArkanoid.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/db/myArkanoid.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/db/myArkanoid.pre_map.cdb b/db/myArkanoid.pre_map.cdb
new file mode 100644
index 0000000..f515262
Binary files /dev/null and b/db/myArkanoid.pre_map.cdb differ
diff --git a/db/myArkanoid.pre_map.hdb b/db/myArkanoid.pre_map.hdb
new file mode 100644
index 0000000..0e9ea76
Binary files /dev/null and b/db/myArkanoid.pre_map.hdb differ
diff --git a/db/myArkanoid.rpp.qmsg b/db/myArkanoid.rpp.qmsg
new file mode 100644
index 0000000..8436389
--- /dev/null
+++ b/db/myArkanoid.rpp.qmsg
@@ -0,0 +1,4 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus II " "Info: Running Quartus II Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 26 12:34:36 2012 " "Info: Processing started: Sat May 26 12:34:36 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_rpp myArkanoid -c myArkanoid --netlist_type=sgate " "Info: Command: quartus_rpp myArkanoid -c myArkanoid --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus II " "Info: Quartus II Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "143 " "Info: Peak virtual memory: 143 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 26 12:34:37 2012 " "Info: Processing ended: Sat May 26 12:34:37 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/db/myArkanoid.rtlv.hdb b/db/myArkanoid.rtlv.hdb
new file mode 100644
index 0000000..75968f3
Binary files /dev/null and b/db/myArkanoid.rtlv.hdb differ
diff --git a/db/myArkanoid.rtlv_sg.cdb b/db/myArkanoid.rtlv_sg.cdb
new file mode 100644
index 0000000..2bbd288
Binary files /dev/null and b/db/myArkanoid.rtlv_sg.cdb differ
diff --git a/db/myArkanoid.rtlv_sg_swap.cdb b/db/myArkanoid.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..2867265
Binary files /dev/null and b/db/myArkanoid.rtlv_sg_swap.cdb differ
diff --git a/db/myArkanoid.sgate.rvd b/db/myArkanoid.sgate.rvd
new file mode 100644
index 0000000..e19778b
Binary files /dev/null and b/db/myArkanoid.sgate.rvd differ
diff --git a/db/myArkanoid.sgate_sm.rvd b/db/myArkanoid.sgate_sm.rvd
new file mode 100644
index 0000000..7b82059
Binary files /dev/null and b/db/myArkanoid.sgate_sm.rvd differ
diff --git a/db/myArkanoid.sgdiff.cdb b/db/myArkanoid.sgdiff.cdb
new file mode 100644
index 0000000..2be146f
Binary files /dev/null and b/db/myArkanoid.sgdiff.cdb differ
diff --git a/db/myArkanoid.sgdiff.hdb b/db/myArkanoid.sgdiff.hdb
new file mode 100644
index 0000000..f1928b5
Binary files /dev/null and b/db/myArkanoid.sgdiff.hdb differ
diff --git a/db/myArkanoid.sim.hdb b/db/myArkanoid.sim.hdb
new file mode 100644
index 0000000..5c3c9e5
Binary files /dev/null and b/db/myArkanoid.sim.hdb differ
diff --git a/db/myArkanoid.sim.qmsg b/db/myArkanoid.sim.qmsg
new file mode 100644
index 0000000..30f3acb
--- /dev/null
+++ b/db/myArkanoid.sim.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 22 17:24:20 2012 " "Info: Processing started: Tue May 22 17:24:20 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISDB_NO_SPECIFIED_VECTOR_FILE_FOUND" "G:/Verilog/Arkanoid2PDE1/myArkanoid.vwf " "Info: Can't find specified vector source file \"G:/Verilog/Arkanoid2PDE1/myArkanoid.vwf\"" { } { } 0 0 "Can't find specified vector source file \"%1!s!\"" 0 0 "" 0 -1}
+{ "Error" "ESDB_NO_VECTOR_FILE_FOUND" "G:/Verilog/Arkanoid2PDE1/myArkanoid.cvwf " "Error: No valid vector source file specified and default file \"G:/Verilog/Arkanoid2PDE1/myArkanoid.cvwf\" does not exist" { } { } 0 0 "No valid vector source file specified and default file \"%1!s!\" does not exist" 0 0 "" 0 -1}
+{ "Error" "EQEXE_ERROR_COUNT" "Simulator 1 0 s Quartus II " "Error: Quartus II Simulator was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "144 " "Error: Peak virtual memory: 144 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Error" "EQEXE_END_BANNER_TIME" "Tue May 22 17:24:20 2012 " "Error: Processing ended: Tue May 22 17:24:20 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Error: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Error: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/db/myArkanoid.sim.rdb b/db/myArkanoid.sim.rdb
new file mode 100644
index 0000000..504147e
Binary files /dev/null and b/db/myArkanoid.sim.rdb differ
diff --git a/db/myArkanoid.sld_design_entry.sci b/db/myArkanoid.sld_design_entry.sci
new file mode 100644
index 0000000..c9c669f
Binary files /dev/null and b/db/myArkanoid.sld_design_entry.sci differ
diff --git a/db/myArkanoid.sld_design_entry_dsc.sci b/db/myArkanoid.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..e3410b7
Binary files /dev/null and b/db/myArkanoid.sld_design_entry_dsc.sci differ
diff --git a/db/myArkanoid.smart_action.txt b/db/myArkanoid.smart_action.txt
new file mode 100644
index 0000000..c8e8a13
--- /dev/null
+++ b/db/myArkanoid.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/db/myArkanoid.smp_dump.txt b/db/myArkanoid.smp_dump.txt
new file mode 100644
index 0000000..79b5c19
--- /dev/null
+++ b/db/myArkanoid.smp_dump.txt
@@ -0,0 +1,7 @@
+
+State Machine - |TotalScheme|Arkanoid:inst|ball_direction
+Name ball_direction.RIGHT_DOWN ball_direction.LEFT_DOWN ball_direction.RIGHT_UP ball_direction.LEFT_UP
+ball_direction.LEFT_UP 0 0 0 0
+ball_direction.RIGHT_UP 0 0 1 1
+ball_direction.LEFT_DOWN 0 1 0 1
+ball_direction.RIGHT_DOWN 1 0 0 1
diff --git a/db/myArkanoid.syn_hier_info b/db/myArkanoid.syn_hier_info
new file mode 100644
index 0000000..e69de29
diff --git a/db/myArkanoid.tan.qmsg b/db/myArkanoid.tan.qmsg
new file mode 100644
index 0000000..8f0b20e
--- /dev/null
+++ b/db/myArkanoid.tan.qmsg
@@ -0,0 +1,11 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 28 14:22:32 2012 " "Info: Processing started: Mon May 28 14:22:32 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_50MHz " "Info: Assuming node \"clk_50MHz\" is an undefined clock" { } { { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -168 -72 96 -152 "clk_50MHz" "" } } } } { "c:/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_50MHz" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
+{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "ClockDivider:inst1\|clk25MHz_ " "Info: Detected ripple clock \"ClockDivider:inst1\|clk25MHz_\" as buffer" { } { { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } { "c:/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "ClockDivider:inst1\|clk25MHz_" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_50MHz register Arkanoid:inst\|platform1_position\[3\] register Arkanoid:inst\|hex0_\[6\] 7.55 MHz 132.461 ns Internal " "Info: Clock \"clk_50MHz\" has Internal fmax of 7.55 MHz between source register \"Arkanoid:inst\|platform1_position\[3\]\" and destination register \"Arkanoid:inst\|hex0_\[6\]\" (period= 132.461 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "132.203 ns + Longest register register " "Info: + Longest register to register delay is 132.203 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Arkanoid:inst\|platform1_position\[3\] 1 REG LCFF_X33_Y12_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y12_N7; Fanout = 4; REG Node = 'Arkanoid:inst\|platform1_position\[3\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { Arkanoid:inst|platform1_position[3] } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.188 ns) + CELL(0.178 ns) 1.366 ns Arkanoid:inst\|platform1_position~64 2 COMB LCCOMB_X34_Y12_N6 1 " "Info: 2: + IC(1.188 ns) + CELL(0.178 ns) = 1.366 ns; Loc. = LCCOMB_X34_Y12_N6; Fanout = 1; COMB Node = 'Arkanoid:inst\|platform1_position~64'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.366 ns" { Arkanoid:inst|platform1_position[3] Arkanoid:inst|platform1_position~64 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.313 ns) + CELL(0.512 ns) 2.191 ns Arkanoid:inst\|platform1_position~68 3 COMB LCCOMB_X34_Y12_N14 1 " "Info: 3: + IC(0.313 ns) + CELL(0.512 ns) = 2.191 ns; Loc. = LCCOMB_X34_Y12_N14; Fanout = 1; COMB Node = 'Arkanoid:inst\|platform1_position~68'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.825 ns" { Arkanoid:inst|platform1_position~64 Arkanoid:inst|platform1_position~68 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.830 ns) + CELL(0.521 ns) 3.542 ns Arkanoid:inst\|platform1_position~74 4 COMB LCCOMB_X34_Y11_N0 32 " "Info: 4: + IC(0.830 ns) + CELL(0.521 ns) = 3.542 ns; Loc. = LCCOMB_X34_Y11_N0; Fanout = 32; COMB Node = 'Arkanoid:inst\|platform1_position~74'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.351 ns" { Arkanoid:inst|platform1_position~68 Arkanoid:inst|platform1_position~74 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.490 ns) + CELL(0.322 ns) 5.354 ns Arkanoid:inst\|Add2~80 5 COMB LCCOMB_X34_Y9_N28 5 " "Info: 5: + IC(1.490 ns) + CELL(0.322 ns) = 5.354 ns; Loc. = LCCOMB_X34_Y9_N28; Fanout = 5; COMB Node = 'Arkanoid:inst\|Add2~80'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.812 ns" { Arkanoid:inst|platform1_position~74 Arkanoid:inst|Add2~80 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.926 ns) + CELL(0.455 ns) 6.735 ns Arkanoid:inst\|LessThan1~6 6 COMB LCCOMB_X34_Y13_N4 1 " "Info: 6: + IC(0.926 ns) + CELL(0.455 ns) = 6.735 ns; Loc. = LCCOMB_X34_Y13_N4; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan1~6'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.381 ns" { Arkanoid:inst|Add2~80 Arkanoid:inst|LessThan1~6 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 53 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.298 ns) + CELL(0.491 ns) 7.524 ns Arkanoid:inst\|LessThan1~9 7 COMB LCCOMB_X34_Y13_N8 1 " "Info: 7: + IC(0.298 ns) + CELL(0.491 ns) = 7.524 ns; Loc. = LCCOMB_X34_Y13_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan1~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.789 ns" { Arkanoid:inst|LessThan1~6 Arkanoid:inst|LessThan1~9 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 53 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.303 ns) + CELL(0.322 ns) 8.149 ns Arkanoid:inst\|LessThan1~10 8 COMB LCCOMB_X34_Y13_N26 2 " "Info: 8: + IC(0.303 ns) + CELL(0.322 ns) = 8.149 ns; Loc. = LCCOMB_X34_Y13_N26; Fanout = 2; COMB Node = 'Arkanoid:inst\|LessThan1~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.625 ns" { Arkanoid:inst|LessThan1~9 Arkanoid:inst|LessThan1~10 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 53 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.901 ns) + CELL(0.517 ns) 9.567 ns Arkanoid:inst\|Add3~1 9 COMB LCCOMB_X35_Y12_N0 2 " "Info: 9: + IC(0.901 ns) + CELL(0.517 ns) = 9.567 ns; Loc. = LCCOMB_X35_Y12_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add3~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.418 ns" { Arkanoid:inst|LessThan1~10 Arkanoid:inst|Add3~1 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 9.647 ns Arkanoid:inst\|Add3~3 10 COMB LCCOMB_X35_Y12_N2 2 " "Info: 10: + IC(0.000 ns) + CELL(0.080 ns) = 9.647 ns; Loc. = LCCOMB_X35_Y12_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add3~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add3~1 Arkanoid:inst|Add3~3 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 9.727 ns Arkanoid:inst\|Add3~5 11 COMB LCCOMB_X35_Y12_N4 2 " "Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 9.727 ns; Loc. = LCCOMB_X35_Y12_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add3~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add3~3 Arkanoid:inst|Add3~5 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 9.807 ns Arkanoid:inst\|Add3~7 12 COMB LCCOMB_X35_Y12_N6 2 " "Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 9.807 ns; Loc. = LCCOMB_X35_Y12_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add3~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add3~5 Arkanoid:inst|Add3~7 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 9.887 ns Arkanoid:inst\|Add3~9 13 COMB LCCOMB_X35_Y12_N8 2 " "Info: 13: + IC(0.000 ns) + CELL(0.080 ns) = 9.887 ns; Loc. = LCCOMB_X35_Y12_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add3~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add3~7 Arkanoid:inst|Add3~9 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 9.967 ns Arkanoid:inst\|Add3~11 14 COMB LCCOMB_X35_Y12_N10 2 " "Info: 14: + IC(0.000 ns) + CELL(0.080 ns) = 9.967 ns; Loc. = LCCOMB_X35_Y12_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add3~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add3~9 Arkanoid:inst|Add3~11 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 10.047 ns Arkanoid:inst\|Add3~13 15 COMB LCCOMB_X35_Y12_N12 2 " "Info: 15: + IC(0.000 ns) + CELL(0.080 ns) = 10.047 ns; Loc. = LCCOMB_X35_Y12_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add3~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add3~11 Arkanoid:inst|Add3~13 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 10.221 ns Arkanoid:inst\|Add3~15 16 COMB LCCOMB_X35_Y12_N14 2 " "Info: 16: + IC(0.000 ns) + CELL(0.174 ns) = 10.221 ns; Loc. = LCCOMB_X35_Y12_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add3~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|Add3~13 Arkanoid:inst|Add3~15 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 10.301 ns Arkanoid:inst\|Add3~17 17 COMB LCCOMB_X35_Y12_N16 2 " "Info: 17: + IC(0.000 ns) + CELL(0.080 ns) = 10.301 ns; Loc. = LCCOMB_X35_Y12_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add3~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add3~15 Arkanoid:inst|Add3~17 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 10.381 ns Arkanoid:inst\|Add3~19 18 COMB LCCOMB_X35_Y12_N18 2 " "Info: 18: + IC(0.000 ns) + CELL(0.080 ns) = 10.381 ns; Loc. = LCCOMB_X35_Y12_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add3~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add3~17 Arkanoid:inst|Add3~19 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 10.461 ns Arkanoid:inst\|Add3~21 19 COMB LCCOMB_X35_Y12_N20 2 " "Info: 19: + IC(0.000 ns) + CELL(0.080 ns) = 10.461 ns; Loc. = LCCOMB_X35_Y12_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add3~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add3~19 Arkanoid:inst|Add3~21 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 10.541 ns Arkanoid:inst\|Add3~23 20 COMB LCCOMB_X35_Y12_N22 2 " "Info: 20: + IC(0.000 ns) + CELL(0.080 ns) = 10.541 ns; Loc. = LCCOMB_X35_Y12_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add3~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add3~21 Arkanoid:inst|Add3~23 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 10.621 ns Arkanoid:inst\|Add3~25 21 COMB LCCOMB_X35_Y12_N24 2 " "Info: 21: + IC(0.000 ns) + CELL(0.080 ns) = 10.621 ns; Loc. = LCCOMB_X35_Y12_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add3~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add3~23 Arkanoid:inst|Add3~25 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 10.701 ns Arkanoid:inst\|Add3~27 22 COMB LCCOMB_X35_Y12_N26 2 " "Info: 22: + IC(0.000 ns) + CELL(0.080 ns) = 10.701 ns; Loc. = LCCOMB_X35_Y12_N26; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add3~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add3~25 Arkanoid:inst|Add3~27 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 11.159 ns Arkanoid:inst\|Add3~28 23 COMB LCCOMB_X35_Y12_N28 2 " "Info: 23: + IC(0.000 ns) + CELL(0.458 ns) = 11.159 ns; Loc. = LCCOMB_X35_Y12_N28; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add3~28'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|Add3~27 Arkanoid:inst|Add3~28 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.165 ns) + CELL(0.178 ns) 12.502 ns Arkanoid:inst\|platform1_position~127 24 COMB LCCOMB_X34_Y9_N12 3 " "Info: 24: + IC(1.165 ns) + CELL(0.178 ns) = 12.502 ns; Loc. = LCCOMB_X34_Y9_N12; Fanout = 3; COMB Node = 'Arkanoid:inst\|platform1_position~127'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.343 ns" { Arkanoid:inst|Add3~28 Arkanoid:inst|platform1_position~127 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.159 ns) + CELL(0.517 ns) 14.178 ns Arkanoid:inst\|Add13~29 25 COMB LCCOMB_X35_Y8_N28 2 " "Info: 25: + IC(1.159 ns) + CELL(0.517 ns) = 14.178 ns; Loc. = LCCOMB_X35_Y8_N28; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add13~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.676 ns" { Arkanoid:inst|platform1_position~127 Arkanoid:inst|Add13~29 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 217 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 14.339 ns Arkanoid:inst\|Add13~31 26 COMB LCCOMB_X35_Y8_N30 2 " "Info: 26: + IC(0.000 ns) + CELL(0.161 ns) = 14.339 ns; Loc. = LCCOMB_X35_Y8_N30; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add13~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.161 ns" { Arkanoid:inst|Add13~29 Arkanoid:inst|Add13~31 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 217 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 14.419 ns Arkanoid:inst\|Add13~33 27 COMB LCCOMB_X35_Y7_N0 2 " "Info: 27: + IC(0.000 ns) + CELL(0.080 ns) = 14.419 ns; Loc. = LCCOMB_X35_Y7_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add13~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add13~31 Arkanoid:inst|Add13~33 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 217 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 14.499 ns Arkanoid:inst\|Add13~35 28 COMB LCCOMB_X35_Y7_N2 2 " "Info: 28: + IC(0.000 ns) + CELL(0.080 ns) = 14.499 ns; Loc. = LCCOMB_X35_Y7_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add13~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add13~33 Arkanoid:inst|Add13~35 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 217 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 14.579 ns Arkanoid:inst\|Add13~37 29 COMB LCCOMB_X35_Y7_N4 2 " "Info: 29: + IC(0.000 ns) + CELL(0.080 ns) = 14.579 ns; Loc. = LCCOMB_X35_Y7_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add13~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add13~35 Arkanoid:inst|Add13~37 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 217 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 14.659 ns Arkanoid:inst\|Add13~39 30 COMB LCCOMB_X35_Y7_N6 2 " "Info: 30: + IC(0.000 ns) + CELL(0.080 ns) = 14.659 ns; Loc. = LCCOMB_X35_Y7_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add13~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add13~37 Arkanoid:inst|Add13~39 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 217 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 14.739 ns Arkanoid:inst\|Add13~41 31 COMB LCCOMB_X35_Y7_N8 2 " "Info: 31: + IC(0.000 ns) + CELL(0.080 ns) = 14.739 ns; Loc. = LCCOMB_X35_Y7_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add13~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add13~39 Arkanoid:inst|Add13~41 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 217 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 14.819 ns Arkanoid:inst\|Add13~43 32 COMB LCCOMB_X35_Y7_N10 2 " "Info: 32: + IC(0.000 ns) + CELL(0.080 ns) = 14.819 ns; Loc. = LCCOMB_X35_Y7_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add13~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add13~41 Arkanoid:inst|Add13~43 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 217 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 14.899 ns Arkanoid:inst\|Add13~45 33 COMB LCCOMB_X35_Y7_N12 2 " "Info: 33: + IC(0.000 ns) + CELL(0.080 ns) = 14.899 ns; Loc. = LCCOMB_X35_Y7_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add13~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add13~43 Arkanoid:inst|Add13~45 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 217 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 15.073 ns Arkanoid:inst\|Add13~47 34 COMB LCCOMB_X35_Y7_N14 2 " "Info: 34: + IC(0.000 ns) + CELL(0.174 ns) = 15.073 ns; Loc. = LCCOMB_X35_Y7_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add13~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|Add13~45 Arkanoid:inst|Add13~47 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 217 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 15.153 ns Arkanoid:inst\|Add13~49 35 COMB LCCOMB_X35_Y7_N16 2 " "Info: 35: + IC(0.000 ns) + CELL(0.080 ns) = 15.153 ns; Loc. = LCCOMB_X35_Y7_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add13~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add13~47 Arkanoid:inst|Add13~49 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 217 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 15.233 ns Arkanoid:inst\|Add13~51 36 COMB LCCOMB_X35_Y7_N18 2 " "Info: 36: + IC(0.000 ns) + CELL(0.080 ns) = 15.233 ns; Loc. = LCCOMB_X35_Y7_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add13~51'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add13~49 Arkanoid:inst|Add13~51 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 217 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 15.691 ns Arkanoid:inst\|Add13~52 37 COMB LCCOMB_X35_Y7_N20 2 " "Info: 37: + IC(0.000 ns) + CELL(0.458 ns) = 15.691 ns; Loc. = LCCOMB_X35_Y7_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add13~52'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|Add13~51 Arkanoid:inst|Add13~52 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 217 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.820 ns) + CELL(0.517 ns) 17.028 ns Arkanoid:inst\|LessThan143~53 38 COMB LCCOMB_X34_Y7_N20 1 " "Info: 38: + IC(0.820 ns) + CELL(0.517 ns) = 17.028 ns; Loc. = LCCOMB_X34_Y7_N20; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan143~53'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.337 ns" { Arkanoid:inst|Add13~52 Arkanoid:inst|LessThan143~53 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 217 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.108 ns Arkanoid:inst\|LessThan143~55 39 COMB LCCOMB_X34_Y7_N22 1 " "Info: 39: + IC(0.000 ns) + CELL(0.080 ns) = 17.108 ns; Loc. = LCCOMB_X34_Y7_N22; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan143~55'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan143~53 Arkanoid:inst|LessThan143~55 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 217 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.188 ns Arkanoid:inst\|LessThan143~57 40 COMB LCCOMB_X34_Y7_N24 1 " "Info: 40: + IC(0.000 ns) + CELL(0.080 ns) = 17.188 ns; Loc. = LCCOMB_X34_Y7_N24; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan143~57'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan143~55 Arkanoid:inst|LessThan143~57 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 217 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.268 ns Arkanoid:inst\|LessThan143~59 41 COMB LCCOMB_X34_Y7_N26 1 " "Info: 41: + IC(0.000 ns) + CELL(0.080 ns) = 17.268 ns; Loc. = LCCOMB_X34_Y7_N26; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan143~59'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan143~57 Arkanoid:inst|LessThan143~59 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 217 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.348 ns Arkanoid:inst\|LessThan143~61 42 COMB LCCOMB_X34_Y7_N28 1 " "Info: 42: + IC(0.000 ns) + CELL(0.080 ns) = 17.348 ns; Loc. = LCCOMB_X34_Y7_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan143~61'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan143~59 Arkanoid:inst|LessThan143~61 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 217 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 17.806 ns Arkanoid:inst\|LessThan143~62 43 COMB LCCOMB_X34_Y7_N30 3 " "Info: 43: + IC(0.000 ns) + CELL(0.458 ns) = 17.806 ns; Loc. = LCCOMB_X34_Y7_N30; Fanout = 3; COMB Node = 'Arkanoid:inst\|LessThan143~62'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|LessThan143~61 Arkanoid:inst|LessThan143~62 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 217 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.097 ns) + CELL(0.178 ns) 19.081 ns Arkanoid:inst\|always2~6 44 COMB LCCOMB_X29_Y7_N0 3 " "Info: 44: + IC(1.097 ns) + CELL(0.178 ns) = 19.081 ns; Loc. = LCCOMB_X29_Y7_N0; Fanout = 3; COMB Node = 'Arkanoid:inst\|always2~6'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.275 ns" { Arkanoid:inst|LessThan143~62 Arkanoid:inst|always2~6 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.158 ns) + CELL(0.495 ns) 21.734 ns Arkanoid:inst\|Add14~1 45 COMB LCCOMB_X34_Y19_N0 2 " "Info: 45: + IC(2.158 ns) + CELL(0.495 ns) = 21.734 ns; Loc. = LCCOMB_X34_Y19_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.653 ns" { Arkanoid:inst|always2~6 Arkanoid:inst|Add14~1 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 21.814 ns Arkanoid:inst\|Add14~3 46 COMB LCCOMB_X34_Y19_N2 2 " "Info: 46: + IC(0.000 ns) + CELL(0.080 ns) = 21.814 ns; Loc. = LCCOMB_X34_Y19_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~1 Arkanoid:inst|Add14~3 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 21.894 ns Arkanoid:inst\|Add14~5 47 COMB LCCOMB_X34_Y19_N4 2 " "Info: 47: + IC(0.000 ns) + CELL(0.080 ns) = 21.894 ns; Loc. = LCCOMB_X34_Y19_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~3 Arkanoid:inst|Add14~5 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 21.974 ns Arkanoid:inst\|Add14~7 48 COMB LCCOMB_X34_Y19_N6 2 " "Info: 48: + IC(0.000 ns) + CELL(0.080 ns) = 21.974 ns; Loc. = LCCOMB_X34_Y19_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~5 Arkanoid:inst|Add14~7 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 22.054 ns Arkanoid:inst\|Add14~9 49 COMB LCCOMB_X34_Y19_N8 2 " "Info: 49: + IC(0.000 ns) + CELL(0.080 ns) = 22.054 ns; Loc. = LCCOMB_X34_Y19_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~7 Arkanoid:inst|Add14~9 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 22.134 ns Arkanoid:inst\|Add14~11 50 COMB LCCOMB_X34_Y19_N10 2 " "Info: 50: + IC(0.000 ns) + CELL(0.080 ns) = 22.134 ns; Loc. = LCCOMB_X34_Y19_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~9 Arkanoid:inst|Add14~11 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 22.214 ns Arkanoid:inst\|Add14~13 51 COMB LCCOMB_X34_Y19_N12 2 " "Info: 51: + IC(0.000 ns) + CELL(0.080 ns) = 22.214 ns; Loc. = LCCOMB_X34_Y19_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~11 Arkanoid:inst|Add14~13 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 22.388 ns Arkanoid:inst\|Add14~15 52 COMB LCCOMB_X34_Y19_N14 2 " "Info: 52: + IC(0.000 ns) + CELL(0.174 ns) = 22.388 ns; Loc. = LCCOMB_X34_Y19_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|Add14~13 Arkanoid:inst|Add14~15 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 22.468 ns Arkanoid:inst\|Add14~17 53 COMB LCCOMB_X34_Y19_N16 2 " "Info: 53: + IC(0.000 ns) + CELL(0.080 ns) = 22.468 ns; Loc. = LCCOMB_X34_Y19_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~15 Arkanoid:inst|Add14~17 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 22.548 ns Arkanoid:inst\|Add14~19 54 COMB LCCOMB_X34_Y19_N18 2 " "Info: 54: + IC(0.000 ns) + CELL(0.080 ns) = 22.548 ns; Loc. = LCCOMB_X34_Y19_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~17 Arkanoid:inst|Add14~19 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 22.628 ns Arkanoid:inst\|Add14~21 55 COMB LCCOMB_X34_Y19_N20 2 " "Info: 55: + IC(0.000 ns) + CELL(0.080 ns) = 22.628 ns; Loc. = LCCOMB_X34_Y19_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~19 Arkanoid:inst|Add14~21 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 22.708 ns Arkanoid:inst\|Add14~23 56 COMB LCCOMB_X34_Y19_N22 2 " "Info: 56: + IC(0.000 ns) + CELL(0.080 ns) = 22.708 ns; Loc. = LCCOMB_X34_Y19_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~21 Arkanoid:inst|Add14~23 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 22.788 ns Arkanoid:inst\|Add14~25 57 COMB LCCOMB_X34_Y19_N24 2 " "Info: 57: + IC(0.000 ns) + CELL(0.080 ns) = 22.788 ns; Loc. = LCCOMB_X34_Y19_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~23 Arkanoid:inst|Add14~25 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 22.868 ns Arkanoid:inst\|Add14~27 58 COMB LCCOMB_X34_Y19_N26 2 " "Info: 58: + IC(0.000 ns) + CELL(0.080 ns) = 22.868 ns; Loc. = LCCOMB_X34_Y19_N26; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~25 Arkanoid:inst|Add14~27 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 22.948 ns Arkanoid:inst\|Add14~29 59 COMB LCCOMB_X34_Y19_N28 2 " "Info: 59: + IC(0.000 ns) + CELL(0.080 ns) = 22.948 ns; Loc. = LCCOMB_X34_Y19_N28; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~27 Arkanoid:inst|Add14~29 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 23.109 ns Arkanoid:inst\|Add14~31 60 COMB LCCOMB_X34_Y19_N30 2 " "Info: 60: + IC(0.000 ns) + CELL(0.161 ns) = 23.109 ns; Loc. = LCCOMB_X34_Y19_N30; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.161 ns" { Arkanoid:inst|Add14~29 Arkanoid:inst|Add14~31 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.189 ns Arkanoid:inst\|Add14~33 61 COMB LCCOMB_X34_Y18_N0 2 " "Info: 61: + IC(0.000 ns) + CELL(0.080 ns) = 23.189 ns; Loc. = LCCOMB_X34_Y18_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~31 Arkanoid:inst|Add14~33 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.269 ns Arkanoid:inst\|Add14~35 62 COMB LCCOMB_X34_Y18_N2 2 " "Info: 62: + IC(0.000 ns) + CELL(0.080 ns) = 23.269 ns; Loc. = LCCOMB_X34_Y18_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~33 Arkanoid:inst|Add14~35 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.349 ns Arkanoid:inst\|Add14~37 63 COMB LCCOMB_X34_Y18_N4 2 " "Info: 63: + IC(0.000 ns) + CELL(0.080 ns) = 23.349 ns; Loc. = LCCOMB_X34_Y18_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~35 Arkanoid:inst|Add14~37 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.429 ns Arkanoid:inst\|Add14~39 64 COMB LCCOMB_X34_Y18_N6 2 " "Info: 64: + IC(0.000 ns) + CELL(0.080 ns) = 23.429 ns; Loc. = LCCOMB_X34_Y18_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~37 Arkanoid:inst|Add14~39 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.509 ns Arkanoid:inst\|Add14~41 65 COMB LCCOMB_X34_Y18_N8 2 " "Info: 65: + IC(0.000 ns) + CELL(0.080 ns) = 23.509 ns; Loc. = LCCOMB_X34_Y18_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~39 Arkanoid:inst|Add14~41 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.589 ns Arkanoid:inst\|Add14~43 66 COMB LCCOMB_X34_Y18_N10 2 " "Info: 66: + IC(0.000 ns) + CELL(0.080 ns) = 23.589 ns; Loc. = LCCOMB_X34_Y18_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~41 Arkanoid:inst|Add14~43 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.669 ns Arkanoid:inst\|Add14~45 67 COMB LCCOMB_X34_Y18_N12 2 " "Info: 67: + IC(0.000 ns) + CELL(0.080 ns) = 23.669 ns; Loc. = LCCOMB_X34_Y18_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~43 Arkanoid:inst|Add14~45 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 23.843 ns Arkanoid:inst\|Add14~47 68 COMB LCCOMB_X34_Y18_N14 2 " "Info: 68: + IC(0.000 ns) + CELL(0.174 ns) = 23.843 ns; Loc. = LCCOMB_X34_Y18_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|Add14~45 Arkanoid:inst|Add14~47 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.923 ns Arkanoid:inst\|Add14~49 69 COMB LCCOMB_X34_Y18_N16 2 " "Info: 69: + IC(0.000 ns) + CELL(0.080 ns) = 23.923 ns; Loc. = LCCOMB_X34_Y18_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~47 Arkanoid:inst|Add14~49 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.003 ns Arkanoid:inst\|Add14~51 70 COMB LCCOMB_X34_Y18_N18 2 " "Info: 70: + IC(0.000 ns) + CELL(0.080 ns) = 24.003 ns; Loc. = LCCOMB_X34_Y18_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~51'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~49 Arkanoid:inst|Add14~51 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.083 ns Arkanoid:inst\|Add14~53 71 COMB LCCOMB_X34_Y18_N20 2 " "Info: 71: + IC(0.000 ns) + CELL(0.080 ns) = 24.083 ns; Loc. = LCCOMB_X34_Y18_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~53'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~51 Arkanoid:inst|Add14~53 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.163 ns Arkanoid:inst\|Add14~55 72 COMB LCCOMB_X34_Y18_N22 2 " "Info: 72: + IC(0.000 ns) + CELL(0.080 ns) = 24.163 ns; Loc. = LCCOMB_X34_Y18_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~55'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~53 Arkanoid:inst|Add14~55 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.243 ns Arkanoid:inst\|Add14~57 73 COMB LCCOMB_X34_Y18_N24 2 " "Info: 73: + IC(0.000 ns) + CELL(0.080 ns) = 24.243 ns; Loc. = LCCOMB_X34_Y18_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~57'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~55 Arkanoid:inst|Add14~57 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.323 ns Arkanoid:inst\|Add14~59 74 COMB LCCOMB_X34_Y18_N26 2 " "Info: 74: + IC(0.000 ns) + CELL(0.080 ns) = 24.323 ns; Loc. = LCCOMB_X34_Y18_N26; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add14~59'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~57 Arkanoid:inst|Add14~59 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.403 ns Arkanoid:inst\|Add14~61 75 COMB LCCOMB_X34_Y18_N28 1 " "Info: 75: + IC(0.000 ns) + CELL(0.080 ns) = 24.403 ns; Loc. = LCCOMB_X34_Y18_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|Add14~61'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add14~59 Arkanoid:inst|Add14~61 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 24.861 ns Arkanoid:inst\|Add14~63 76 COMB LCCOMB_X34_Y18_N30 3 " "Info: 76: + IC(0.000 ns) + CELL(0.458 ns) = 24.861 ns; Loc. = LCCOMB_X34_Y18_N30; Fanout = 3; COMB Node = 'Arkanoid:inst\|Add14~63'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|Add14~61 Arkanoid:inst|Add14~63 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.950 ns) + CELL(0.178 ns) 25.989 ns Arkanoid:inst\|Add14~65 77 COMB LCCOMB_X35_Y22_N0 151 " "Info: 77: + IC(0.950 ns) + CELL(0.178 ns) = 25.989 ns; Loc. = LCCOMB_X35_Y22_N0; Fanout = 151; COMB Node = 'Arkanoid:inst\|Add14~65'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.128 ns" { Arkanoid:inst|Add14~63 Arkanoid:inst|Add14~65 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.012 ns) + CELL(0.517 ns) 27.518 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~4 78 COMB LCCOMB_X35_Y20_N4 2 " "Info: 78: + IC(1.012 ns) + CELL(0.517 ns) = 27.518 ns; Loc. = LCCOMB_X35_Y20_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~4'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.529 ns" { Arkanoid:inst|Add14~65 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~4 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 27.598 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~6 79 COMB LCCOMB_X35_Y20_N6 2 " "Info: 79: + IC(0.000 ns) + CELL(0.080 ns) = 27.598 ns; Loc. = LCCOMB_X35_Y20_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~6'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~4 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~6 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 27.678 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~8 80 COMB LCCOMB_X35_Y20_N8 2 " "Info: 80: + IC(0.000 ns) + CELL(0.080 ns) = 27.678 ns; Loc. = LCCOMB_X35_Y20_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~8'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~6 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~8 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 27.758 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~10 81 COMB LCCOMB_X35_Y20_N10 2 " "Info: 81: + IC(0.000 ns) + CELL(0.080 ns) = 27.758 ns; Loc. = LCCOMB_X35_Y20_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~8 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~10 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 27.838 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~12 82 COMB LCCOMB_X35_Y20_N12 2 " "Info: 82: + IC(0.000 ns) + CELL(0.080 ns) = 27.838 ns; Loc. = LCCOMB_X35_Y20_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~12'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~12 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 28.012 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~14 83 COMB LCCOMB_X35_Y20_N14 2 " "Info: 83: + IC(0.000 ns) + CELL(0.174 ns) = 28.012 ns; Loc. = LCCOMB_X35_Y20_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~14'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~12 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~14 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 28.092 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~16 84 COMB LCCOMB_X35_Y20_N16 2 " "Info: 84: + IC(0.000 ns) + CELL(0.080 ns) = 28.092 ns; Loc. = LCCOMB_X35_Y20_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~16'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~14 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~16 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 28.172 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~18 85 COMB LCCOMB_X35_Y20_N18 2 " "Info: 85: + IC(0.000 ns) + CELL(0.080 ns) = 28.172 ns; Loc. = LCCOMB_X35_Y20_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~18'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~16 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~18 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 28.252 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~20 86 COMB LCCOMB_X35_Y20_N20 2 " "Info: 86: + IC(0.000 ns) + CELL(0.080 ns) = 28.252 ns; Loc. = LCCOMB_X35_Y20_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~20'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~18 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~20 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 28.332 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~22 87 COMB LCCOMB_X35_Y20_N22 2 " "Info: 87: + IC(0.000 ns) + CELL(0.080 ns) = 28.332 ns; Loc. = LCCOMB_X35_Y20_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~22'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~20 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~22 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 28.412 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~24 88 COMB LCCOMB_X35_Y20_N24 2 " "Info: 88: + IC(0.000 ns) + CELL(0.080 ns) = 28.412 ns; Loc. = LCCOMB_X35_Y20_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~24'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~22 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~24 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 28.492 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~26 89 COMB LCCOMB_X35_Y20_N26 2 " "Info: 89: + IC(0.000 ns) + CELL(0.080 ns) = 28.492 ns; Loc. = LCCOMB_X35_Y20_N26; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~26'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~24 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~26 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 28.572 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~28 90 COMB LCCOMB_X35_Y20_N28 2 " "Info: 90: + IC(0.000 ns) + CELL(0.080 ns) = 28.572 ns; Loc. = LCCOMB_X35_Y20_N28; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~28'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~26 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~28 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 28.733 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~30 91 COMB LCCOMB_X35_Y20_N30 2 " "Info: 91: + IC(0.000 ns) + CELL(0.161 ns) = 28.733 ns; Loc. = LCCOMB_X35_Y20_N30; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~30'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.161 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~28 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~30 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 28.813 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~32 92 COMB LCCOMB_X35_Y19_N0 2 " "Info: 92: + IC(0.000 ns) + CELL(0.080 ns) = 28.813 ns; Loc. = LCCOMB_X35_Y19_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~32'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~30 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~32 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 28.893 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~34 93 COMB LCCOMB_X35_Y19_N2 2 " "Info: 93: + IC(0.000 ns) + CELL(0.080 ns) = 28.893 ns; Loc. = LCCOMB_X35_Y19_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~34'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~32 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~34 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 28.973 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~36 94 COMB LCCOMB_X35_Y19_N4 2 " "Info: 94: + IC(0.000 ns) + CELL(0.080 ns) = 28.973 ns; Loc. = LCCOMB_X35_Y19_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~36'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~34 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~36 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 29.053 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~38 95 COMB LCCOMB_X35_Y19_N6 2 " "Info: 95: + IC(0.000 ns) + CELL(0.080 ns) = 29.053 ns; Loc. = LCCOMB_X35_Y19_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~38'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~36 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~38 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 29.133 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~40 96 COMB LCCOMB_X35_Y19_N8 2 " "Info: 96: + IC(0.000 ns) + CELL(0.080 ns) = 29.133 ns; Loc. = LCCOMB_X35_Y19_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~40'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~38 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~40 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 29.213 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~42 97 COMB LCCOMB_X35_Y19_N10 2 " "Info: 97: + IC(0.000 ns) + CELL(0.080 ns) = 29.213 ns; Loc. = LCCOMB_X35_Y19_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~42'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~40 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~42 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 29.293 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~44 98 COMB LCCOMB_X35_Y19_N12 2 " "Info: 98: + IC(0.000 ns) + CELL(0.080 ns) = 29.293 ns; Loc. = LCCOMB_X35_Y19_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~44'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~42 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~44 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 29.467 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~46 99 COMB LCCOMB_X35_Y19_N14 2 " "Info: 99: + IC(0.000 ns) + CELL(0.174 ns) = 29.467 ns; Loc. = LCCOMB_X35_Y19_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~46'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~44 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~46 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 29.547 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~48 100 COMB LCCOMB_X35_Y19_N16 2 " "Info: 100: + IC(0.000 ns) + CELL(0.080 ns) = 29.547 ns; Loc. = LCCOMB_X35_Y19_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~48'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~46 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~48 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 29.627 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~50 101 COMB LCCOMB_X35_Y19_N18 2 " "Info: 101: + IC(0.000 ns) + CELL(0.080 ns) = 29.627 ns; Loc. = LCCOMB_X35_Y19_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~50'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~48 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~50 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 29.707 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~52 102 COMB LCCOMB_X35_Y19_N20 2 " "Info: 102: + IC(0.000 ns) + CELL(0.080 ns) = 29.707 ns; Loc. = LCCOMB_X35_Y19_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~52'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~50 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~52 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 29.787 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~54 103 COMB LCCOMB_X35_Y19_N22 2 " "Info: 103: + IC(0.000 ns) + CELL(0.080 ns) = 29.787 ns; Loc. = LCCOMB_X35_Y19_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~54'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~52 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~54 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 29.867 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~56 104 COMB LCCOMB_X35_Y19_N24 2 " "Info: 104: + IC(0.000 ns) + CELL(0.080 ns) = 29.867 ns; Loc. = LCCOMB_X35_Y19_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~56'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~54 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~56 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 30.325 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~57 105 COMB LCCOMB_X35_Y19_N26 4 " "Info: 105: + IC(0.000 ns) + CELL(0.458 ns) = 30.325 ns; Loc. = LCCOMB_X35_Y19_N26; Fanout = 4; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~57'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~56 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~57 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.186 ns) + CELL(0.517 ns) 32.028 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[1\]~1 106 COMB LCCOMB_X38_Y21_N18 2 " "Info: 106: + IC(1.186 ns) + CELL(0.517 ns) = 32.028 ns; Loc. = LCCOMB_X38_Y21_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.703 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~57 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 141 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.108 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[2\]~3 107 COMB LCCOMB_X38_Y21_N20 2 " "Info: 107: + IC(0.000 ns) + CELL(0.080 ns) = 32.108 ns; Loc. = LCCOMB_X38_Y21_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 141 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.188 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[3\]~5 108 COMB LCCOMB_X38_Y21_N22 1 " "Info: 108: + IC(0.000 ns) + CELL(0.080 ns) = 32.188 ns; Loc. = LCCOMB_X38_Y21_N22; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 141 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 32.646 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[4\]~6 109 COMB LCCOMB_X38_Y21_N24 11 " "Info: 109: + IC(0.000 ns) + CELL(0.458 ns) = 32.646 ns; Loc. = LCCOMB_X38_Y21_N24; Fanout = 11; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[4\]~6'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 141 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.373 ns) + CELL(0.319 ns) 33.338 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[18\]~358 110 COMB LCCOMB_X38_Y21_N12 2 " "Info: 110: + IC(0.373 ns) + CELL(0.319 ns) = 33.338 ns; Loc. = LCCOMB_X38_Y21_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[18\]~358'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.692 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[18]~358 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.559 ns) + CELL(0.517 ns) 34.414 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[1\]~1 111 COMB LCCOMB_X39_Y21_N0 2 " "Info: 111: + IC(0.559 ns) + CELL(0.517 ns) = 34.414 ns; Loc. = LCCOMB_X39_Y21_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.076 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[18]~358 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 34.494 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[2\]~3 112 COMB LCCOMB_X39_Y21_N2 2 " "Info: 112: + IC(0.000 ns) + CELL(0.080 ns) = 34.494 ns; Loc. = LCCOMB_X39_Y21_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 34.574 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[3\]~5 113 COMB LCCOMB_X39_Y21_N4 2 " "Info: 113: + IC(0.000 ns) + CELL(0.080 ns) = 34.574 ns; Loc. = LCCOMB_X39_Y21_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 34.654 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[4\]~7 114 COMB LCCOMB_X39_Y21_N6 1 " "Info: 114: + IC(0.000 ns) + CELL(0.080 ns) = 34.654 ns; Loc. = LCCOMB_X39_Y21_N6; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 35.112 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[5\]~8 115 COMB LCCOMB_X39_Y21_N8 13 " "Info: 115: + IC(0.000 ns) + CELL(0.458 ns) = 35.112 ns; Loc. = LCCOMB_X39_Y21_N8; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[5\]~8'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.235 ns) + CELL(0.178 ns) 36.525 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[24\]~365 116 COMB LCCOMB_X42_Y19_N8 2 " "Info: 116: + IC(1.235 ns) + CELL(0.178 ns) = 36.525 ns; Loc. = LCCOMB_X42_Y19_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[24\]~365'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.413 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[24]~365 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.187 ns) + CELL(0.517 ns) 38.229 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[1\]~1 117 COMB LCCOMB_X39_Y21_N18 2 " "Info: 117: + IC(1.187 ns) + CELL(0.517 ns) = 38.229 ns; Loc. = LCCOMB_X39_Y21_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.704 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[24]~365 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 38.309 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[2\]~3 118 COMB LCCOMB_X39_Y21_N20 2 " "Info: 118: + IC(0.000 ns) + CELL(0.080 ns) = 38.309 ns; Loc. = LCCOMB_X39_Y21_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 38.389 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[3\]~5 119 COMB LCCOMB_X39_Y21_N22 2 " "Info: 119: + IC(0.000 ns) + CELL(0.080 ns) = 38.389 ns; Loc. = LCCOMB_X39_Y21_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 38.469 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[4\]~7 120 COMB LCCOMB_X39_Y21_N24 1 " "Info: 120: + IC(0.000 ns) + CELL(0.080 ns) = 38.469 ns; Loc. = LCCOMB_X39_Y21_N24; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 38.549 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[5\]~9 121 COMB LCCOMB_X39_Y21_N26 1 " "Info: 121: + IC(0.000 ns) + CELL(0.080 ns) = 38.549 ns; Loc. = LCCOMB_X39_Y21_N26; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 39.007 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[6\]~10 122 COMB LCCOMB_X39_Y21_N28 13 " "Info: 122: + IC(0.000 ns) + CELL(0.458 ns) = 39.007 ns; Loc. = LCCOMB_X39_Y21_N28; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.249 ns) + CELL(0.322 ns) 40.578 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[32\]~369 123 COMB LCCOMB_X42_Y19_N0 2 " "Info: 123: + IC(1.249 ns) + CELL(0.322 ns) = 40.578 ns; Loc. = LCCOMB_X42_Y19_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[32\]~369'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.571 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[32]~369 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.544 ns) + CELL(0.517 ns) 41.639 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[3\]~5 124 COMB LCCOMB_X43_Y19_N24 2 " "Info: 124: + IC(0.544 ns) + CELL(0.517 ns) = 41.639 ns; Loc. = LCCOMB_X43_Y19_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.061 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[32]~369 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 41.719 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[4\]~7 125 COMB LCCOMB_X43_Y19_N26 1 " "Info: 125: + IC(0.000 ns) + CELL(0.080 ns) = 41.719 ns; Loc. = LCCOMB_X43_Y19_N26; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 41.799 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[5\]~9 126 COMB LCCOMB_X43_Y19_N28 1 " "Info: 126: + IC(0.000 ns) + CELL(0.080 ns) = 41.799 ns; Loc. = LCCOMB_X43_Y19_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 42.257 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[6\]~10 127 COMB LCCOMB_X43_Y19_N30 13 " "Info: 127: + IC(0.000 ns) + CELL(0.458 ns) = 42.257 ns; Loc. = LCCOMB_X43_Y19_N30; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.502 ns) + CELL(0.322 ns) 43.081 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[36\]~380 128 COMB LCCOMB_X44_Y19_N2 2 " "Info: 128: + IC(0.502 ns) + CELL(0.322 ns) = 43.081 ns; Loc. = LCCOMB_X44_Y19_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[36\]~380'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.824 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~380 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.535 ns) + CELL(0.517 ns) 44.133 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[1\]~1 129 COMB LCCOMB_X43_Y19_N0 2 " "Info: 129: + IC(0.535 ns) + CELL(0.517 ns) = 44.133 ns; Loc. = LCCOMB_X43_Y19_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.052 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~380 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 44.213 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[2\]~3 130 COMB LCCOMB_X43_Y19_N2 2 " "Info: 130: + IC(0.000 ns) + CELL(0.080 ns) = 44.213 ns; Loc. = LCCOMB_X43_Y19_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 44.293 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[3\]~5 131 COMB LCCOMB_X43_Y19_N4 2 " "Info: 131: + IC(0.000 ns) + CELL(0.080 ns) = 44.293 ns; Loc. = LCCOMB_X43_Y19_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 44.373 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[4\]~7 132 COMB LCCOMB_X43_Y19_N6 1 " "Info: 132: + IC(0.000 ns) + CELL(0.080 ns) = 44.373 ns; Loc. = LCCOMB_X43_Y19_N6; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 44.453 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[5\]~9 133 COMB LCCOMB_X43_Y19_N8 1 " "Info: 133: + IC(0.000 ns) + CELL(0.080 ns) = 44.453 ns; Loc. = LCCOMB_X43_Y19_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 44.911 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[6\]~10 134 COMB LCCOMB_X43_Y19_N10 13 " "Info: 134: + IC(0.000 ns) + CELL(0.458 ns) = 44.911 ns; Loc. = LCCOMB_X43_Y19_N10; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.562 ns) + CELL(0.322 ns) 45.795 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[44\]~615 135 COMB LCCOMB_X42_Y19_N22 3 " "Info: 135: + IC(0.562 ns) + CELL(0.322 ns) = 45.795 ns; Loc. = LCCOMB_X42_Y19_N22; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[44\]~615'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.884 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[44]~615 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.148 ns) + CELL(0.495 ns) 47.438 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[3\]~5 136 COMB LCCOMB_X44_Y17_N4 2 " "Info: 136: + IC(1.148 ns) + CELL(0.495 ns) = 47.438 ns; Loc. = LCCOMB_X44_Y17_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.643 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[44]~615 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 47.518 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[4\]~7 137 COMB LCCOMB_X44_Y17_N6 1 " "Info: 137: + IC(0.000 ns) + CELL(0.080 ns) = 47.518 ns; Loc. = LCCOMB_X44_Y17_N6; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 47.598 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[5\]~9 138 COMB LCCOMB_X44_Y17_N8 1 " "Info: 138: + IC(0.000 ns) + CELL(0.080 ns) = 47.598 ns; Loc. = LCCOMB_X44_Y17_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 48.056 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[6\]~10 139 COMB LCCOMB_X44_Y17_N10 13 " "Info: 139: + IC(0.000 ns) + CELL(0.458 ns) = 48.056 ns; Loc. = LCCOMB_X44_Y17_N10; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.886 ns) + CELL(0.178 ns) 49.120 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[50\]~616 140 COMB LCCOMB_X44_Y19_N28 3 " "Info: 140: + IC(0.886 ns) + CELL(0.178 ns) = 49.120 ns; Loc. = LCCOMB_X44_Y19_N28; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[50\]~616'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.064 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[50]~616 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.168 ns) + CELL(0.517 ns) 50.805 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[3\]~5 141 COMB LCCOMB_X44_Y17_N18 2 " "Info: 141: + IC(1.168 ns) + CELL(0.517 ns) = 50.805 ns; Loc. = LCCOMB_X44_Y17_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.685 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[50]~616 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 50.885 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[4\]~7 142 COMB LCCOMB_X44_Y17_N20 1 " "Info: 142: + IC(0.000 ns) + CELL(0.080 ns) = 50.885 ns; Loc. = LCCOMB_X44_Y17_N20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 50.965 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[5\]~9 143 COMB LCCOMB_X44_Y17_N22 1 " "Info: 143: + IC(0.000 ns) + CELL(0.080 ns) = 50.965 ns; Loc. = LCCOMB_X44_Y17_N22; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 51.423 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[6\]~10 144 COMB LCCOMB_X44_Y17_N24 13 " "Info: 144: + IC(0.000 ns) + CELL(0.458 ns) = 51.423 ns; Loc. = LCCOMB_X44_Y17_N24; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.889 ns) + CELL(0.322 ns) 52.634 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[56\]~617 145 COMB LCCOMB_X44_Y19_N22 3 " "Info: 145: + IC(0.889 ns) + CELL(0.322 ns) = 52.634 ns; Loc. = LCCOMB_X44_Y19_N22; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[56\]~617'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.211 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[56]~617 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.198 ns) + CELL(0.517 ns) 54.349 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[3\]~5 146 COMB LCCOMB_X42_Y17_N22 2 " "Info: 146: + IC(1.198 ns) + CELL(0.517 ns) = 54.349 ns; Loc. = LCCOMB_X42_Y17_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.715 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[56]~617 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 36 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 54.429 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[4\]~7 147 COMB LCCOMB_X42_Y17_N24 1 " "Info: 147: + IC(0.000 ns) + CELL(0.080 ns) = 54.429 ns; Loc. = LCCOMB_X42_Y17_N24; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 36 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 54.509 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[5\]~9 148 COMB LCCOMB_X42_Y17_N26 1 " "Info: 148: + IC(0.000 ns) + CELL(0.080 ns) = 54.509 ns; Loc. = LCCOMB_X42_Y17_N26; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 36 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 54.967 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[6\]~10 149 COMB LCCOMB_X42_Y17_N28 13 " "Info: 149: + IC(0.000 ns) + CELL(0.458 ns) = 54.967 ns; Loc. = LCCOMB_X42_Y17_N28; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 36 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.871 ns) + CELL(0.178 ns) 56.016 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[60\]~407 150 COMB LCCOMB_X40_Y17_N24 2 " "Info: 150: + IC(0.871 ns) + CELL(0.178 ns) = 56.016 ns; Loc. = LCCOMB_X40_Y17_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[60\]~407'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.049 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[60]~407 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.854 ns) + CELL(0.517 ns) 57.387 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[1\]~1 151 COMB LCCOMB_X42_Y17_N2 2 " "Info: 151: + IC(0.854 ns) + CELL(0.517 ns) = 57.387 ns; Loc. = LCCOMB_X42_Y17_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.371 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[60]~407 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 57.467 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[2\]~3 152 COMB LCCOMB_X42_Y17_N4 2 " "Info: 152: + IC(0.000 ns) + CELL(0.080 ns) = 57.467 ns; Loc. = LCCOMB_X42_Y17_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 57.547 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[3\]~5 153 COMB LCCOMB_X42_Y17_N6 2 " "Info: 153: + IC(0.000 ns) + CELL(0.080 ns) = 57.547 ns; Loc. = LCCOMB_X42_Y17_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 57.627 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[4\]~7 154 COMB LCCOMB_X42_Y17_N8 1 " "Info: 154: + IC(0.000 ns) + CELL(0.080 ns) = 57.627 ns; Loc. = LCCOMB_X42_Y17_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 57.707 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[5\]~9 155 COMB LCCOMB_X42_Y17_N10 1 " "Info: 155: + IC(0.000 ns) + CELL(0.080 ns) = 57.707 ns; Loc. = LCCOMB_X42_Y17_N10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 58.165 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[6\]~10 156 COMB LCCOMB_X42_Y17_N12 13 " "Info: 156: + IC(0.000 ns) + CELL(0.458 ns) = 58.165 ns; Loc. = LCCOMB_X42_Y17_N12; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(0.177 ns) 59.235 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[66\]~415 157 COMB LCCOMB_X40_Y17_N16 2 " "Info: 157: + IC(0.893 ns) + CELL(0.177 ns) = 59.235 ns; Loc. = LCCOMB_X40_Y17_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[66\]~415'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.070 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[66]~415 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.552 ns) + CELL(0.517 ns) 60.304 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[1\]~1 158 COMB LCCOMB_X39_Y17_N6 2 " "Info: 158: + IC(0.552 ns) + CELL(0.517 ns) = 60.304 ns; Loc. = LCCOMB_X39_Y17_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.069 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[66]~415 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 60.384 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[2\]~3 159 COMB LCCOMB_X39_Y17_N8 2 " "Info: 159: + IC(0.000 ns) + CELL(0.080 ns) = 60.384 ns; Loc. = LCCOMB_X39_Y17_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 60.464 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[3\]~5 160 COMB LCCOMB_X39_Y17_N10 2 " "Info: 160: + IC(0.000 ns) + CELL(0.080 ns) = 60.464 ns; Loc. = LCCOMB_X39_Y17_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 60.544 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[4\]~7 161 COMB LCCOMB_X39_Y17_N12 1 " "Info: 161: + IC(0.000 ns) + CELL(0.080 ns) = 60.544 ns; Loc. = LCCOMB_X39_Y17_N12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 60.718 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[5\]~9 162 COMB LCCOMB_X39_Y17_N14 1 " "Info: 162: + IC(0.000 ns) + CELL(0.174 ns) = 60.718 ns; Loc. = LCCOMB_X39_Y17_N14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 61.176 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[6\]~10 163 COMB LCCOMB_X39_Y17_N16 13 " "Info: 163: + IC(0.000 ns) + CELL(0.458 ns) = 61.176 ns; Loc. = LCCOMB_X39_Y17_N16; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.895 ns) + CELL(0.177 ns) 62.248 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[72\]~422 164 COMB LCCOMB_X40_Y19_N8 2 " "Info: 164: + IC(0.895 ns) + CELL(0.177 ns) = 62.248 ns; Loc. = LCCOMB_X40_Y19_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[72\]~422'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.072 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[72]~422 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.866 ns) + CELL(0.495 ns) 63.609 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[1\]~1 165 COMB LCCOMB_X39_Y17_N18 2 " "Info: 165: + IC(0.866 ns) + CELL(0.495 ns) = 63.609 ns; Loc. = LCCOMB_X39_Y17_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.361 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[72]~422 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 51 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 63.689 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[2\]~3 166 COMB LCCOMB_X39_Y17_N20 2 " "Info: 166: + IC(0.000 ns) + CELL(0.080 ns) = 63.689 ns; Loc. = LCCOMB_X39_Y17_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 51 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 63.769 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[3\]~5 167 COMB LCCOMB_X39_Y17_N22 2 " "Info: 167: + IC(0.000 ns) + CELL(0.080 ns) = 63.769 ns; Loc. = LCCOMB_X39_Y17_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 51 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 64.227 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[4\]~6 168 COMB LCCOMB_X39_Y17_N24 1 " "Info: 168: + IC(0.000 ns) + CELL(0.458 ns) = 64.227 ns; Loc. = LCCOMB_X39_Y17_N24; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[4\]~6'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[4]~6 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 51 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.537 ns) + CELL(0.521 ns) 65.285 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[82\]~423 169 COMB LCCOMB_X40_Y17_N22 1 " "Info: 169: + IC(0.537 ns) + CELL(0.521 ns) = 65.285 ns; Loc. = LCCOMB_X40_Y17_N22; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[82\]~423'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.058 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[4]~6 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[82]~423 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.812 ns) + CELL(0.517 ns) 66.614 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[5\]~9 170 COMB LCCOMB_X38_Y17_N10 1 " "Info: 170: + IC(0.812 ns) + CELL(0.517 ns) = 66.614 ns; Loc. = LCCOMB_X38_Y17_N10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.329 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[82]~423 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 56 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 67.072 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[6\]~10 171 COMB LCCOMB_X38_Y17_N12 13 " "Info: 171: + IC(0.000 ns) + CELL(0.458 ns) = 67.072 ns; Loc. = LCCOMB_X38_Y17_N12; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 56 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.941 ns) + CELL(0.178 ns) 68.191 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[84\]~435 172 COMB LCCOMB_X38_Y16_N20 2 " "Info: 172: + IC(0.941 ns) + CELL(0.178 ns) = 68.191 ns; Loc. = LCCOMB_X38_Y16_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[84\]~435'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.119 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[84]~435 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.333 ns) + CELL(0.517 ns) 69.041 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[1\]~1 173 COMB LCCOMB_X38_Y16_N6 2 " "Info: 173: + IC(0.333 ns) + CELL(0.517 ns) = 69.041 ns; Loc. = LCCOMB_X38_Y16_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.850 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[84]~435 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 61 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 69.121 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[2\]~3 174 COMB LCCOMB_X38_Y16_N8 2 " "Info: 174: + IC(0.000 ns) + CELL(0.080 ns) = 69.121 ns; Loc. = LCCOMB_X38_Y16_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 61 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 69.201 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[3\]~5 175 COMB LCCOMB_X38_Y16_N10 2 " "Info: 175: + IC(0.000 ns) + CELL(0.080 ns) = 69.201 ns; Loc. = LCCOMB_X38_Y16_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 61 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 69.281 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[4\]~7 176 COMB LCCOMB_X38_Y16_N12 1 " "Info: 176: + IC(0.000 ns) + CELL(0.080 ns) = 69.281 ns; Loc. = LCCOMB_X38_Y16_N12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 61 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 69.455 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[5\]~9 177 COMB LCCOMB_X38_Y16_N14 1 " "Info: 177: + IC(0.000 ns) + CELL(0.174 ns) = 69.455 ns; Loc. = LCCOMB_X38_Y16_N14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 61 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 69.913 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[6\]~10 178 COMB LCCOMB_X38_Y16_N16 13 " "Info: 178: + IC(0.000 ns) + CELL(0.458 ns) = 69.913 ns; Loc. = LCCOMB_X38_Y16_N16; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 61 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.628 ns) + CELL(0.322 ns) 70.863 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[92\]~623 179 COMB LCCOMB_X37_Y16_N22 3 " "Info: 179: + IC(0.628 ns) + CELL(0.322 ns) = 70.863 ns; Loc. = LCCOMB_X37_Y16_N22; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[92\]~623'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.950 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[92]~623 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.552 ns) + CELL(0.517 ns) 71.932 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[3\]~5 180 COMB LCCOMB_X37_Y16_N4 2 " "Info: 180: + IC(0.552 ns) + CELL(0.517 ns) = 71.932 ns; Loc. = LCCOMB_X37_Y16_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.069 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[92]~623 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 72.012 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[4\]~7 181 COMB LCCOMB_X37_Y16_N6 1 " "Info: 181: + IC(0.000 ns) + CELL(0.080 ns) = 72.012 ns; Loc. = LCCOMB_X37_Y16_N6; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 72.092 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[5\]~9 182 COMB LCCOMB_X37_Y16_N8 1 " "Info: 182: + IC(0.000 ns) + CELL(0.080 ns) = 72.092 ns; Loc. = LCCOMB_X37_Y16_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 72.550 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[6\]~10 183 COMB LCCOMB_X37_Y16_N10 13 " "Info: 183: + IC(0.000 ns) + CELL(0.458 ns) = 72.550 ns; Loc. = LCCOMB_X37_Y16_N10; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.613 ns) + CELL(0.319 ns) 73.482 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[97\]~447 184 COMB LCCOMB_X36_Y16_N26 2 " "Info: 184: + IC(0.613 ns) + CELL(0.319 ns) = 73.482 ns; Loc. = LCCOMB_X36_Y16_N26; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[97\]~447'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.932 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[97]~447 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.540 ns) + CELL(0.517 ns) 74.539 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[2\]~3 185 COMB LCCOMB_X36_Y16_N8 2 " "Info: 185: + IC(0.540 ns) + CELL(0.517 ns) = 74.539 ns; Loc. = LCCOMB_X36_Y16_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.057 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[97]~447 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 74.619 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[3\]~5 186 COMB LCCOMB_X36_Y16_N10 2 " "Info: 186: + IC(0.000 ns) + CELL(0.080 ns) = 74.619 ns; Loc. = LCCOMB_X36_Y16_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 74.699 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[4\]~7 187 COMB LCCOMB_X36_Y16_N12 1 " "Info: 187: + IC(0.000 ns) + CELL(0.080 ns) = 74.699 ns; Loc. = LCCOMB_X36_Y16_N12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 74.873 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[5\]~9 188 COMB LCCOMB_X36_Y16_N14 1 " "Info: 188: + IC(0.000 ns) + CELL(0.174 ns) = 74.873 ns; Loc. = LCCOMB_X36_Y16_N14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 75.331 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[6\]~10 189 COMB LCCOMB_X36_Y16_N16 13 " "Info: 189: + IC(0.000 ns) + CELL(0.458 ns) = 75.331 ns; Loc. = LCCOMB_X36_Y16_N16; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.611 ns) + CELL(0.322 ns) 76.264 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[102\]~457 190 COMB LCCOMB_X35_Y16_N6 2 " "Info: 190: + IC(0.611 ns) + CELL(0.322 ns) = 76.264 ns; Loc. = LCCOMB_X35_Y16_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[102\]~457'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.933 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~457 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.324 ns) + CELL(0.517 ns) 77.105 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[1\]~1 191 COMB LCCOMB_X35_Y16_N16 2 " "Info: 191: + IC(0.324 ns) + CELL(0.517 ns) = 77.105 ns; Loc. = LCCOMB_X35_Y16_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.841 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~457 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 77.185 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[2\]~3 192 COMB LCCOMB_X35_Y16_N18 2 " "Info: 192: + IC(0.000 ns) + CELL(0.080 ns) = 77.185 ns; Loc. = LCCOMB_X35_Y16_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 77.265 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[3\]~5 193 COMB LCCOMB_X35_Y16_N20 2 " "Info: 193: + IC(0.000 ns) + CELL(0.080 ns) = 77.265 ns; Loc. = LCCOMB_X35_Y16_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 77.345 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[4\]~7 194 COMB LCCOMB_X35_Y16_N22 1 " "Info: 194: + IC(0.000 ns) + CELL(0.080 ns) = 77.345 ns; Loc. = LCCOMB_X35_Y16_N22; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 77.425 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[5\]~9 195 COMB LCCOMB_X35_Y16_N24 1 " "Info: 195: + IC(0.000 ns) + CELL(0.080 ns) = 77.425 ns; Loc. = LCCOMB_X35_Y16_N24; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 77.883 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[6\]~10 196 COMB LCCOMB_X35_Y16_N26 13 " "Info: 196: + IC(0.000 ns) + CELL(0.458 ns) = 77.883 ns; Loc. = LCCOMB_X35_Y16_N26; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.134 ns) + CELL(0.322 ns) 79.339 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[108\]~464 197 COMB LCCOMB_X27_Y16_N18 2 " "Info: 197: + IC(1.134 ns) + CELL(0.322 ns) = 79.339 ns; Loc. = LCCOMB_X27_Y16_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[108\]~464'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.456 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[108]~464 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.809 ns) + CELL(0.517 ns) 80.665 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[1\]~1 198 COMB LCCOMB_X26_Y16_N12 2 " "Info: 198: + IC(0.809 ns) + CELL(0.517 ns) = 80.665 ns; Loc. = LCCOMB_X26_Y16_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.326 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[108]~464 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 80.839 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[2\]~3 199 COMB LCCOMB_X26_Y16_N14 2 " "Info: 199: + IC(0.000 ns) + CELL(0.174 ns) = 80.839 ns; Loc. = LCCOMB_X26_Y16_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 80.919 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[3\]~5 200 COMB LCCOMB_X26_Y16_N16 2 " "Info: 200: + IC(0.000 ns) + CELL(0.080 ns) = 80.919 ns; Loc. = LCCOMB_X26_Y16_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 80.999 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[4\]~7 201 COMB LCCOMB_X26_Y16_N18 1 " "Info: 201: + IC(0.000 ns) + CELL(0.080 ns) = 80.999 ns; Loc. = LCCOMB_X26_Y16_N18; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 81.079 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[5\]~9 202 COMB LCCOMB_X26_Y16_N20 1 " "Info: 202: + IC(0.000 ns) + CELL(0.080 ns) = 81.079 ns; Loc. = LCCOMB_X26_Y16_N20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 81.537 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[6\]~10 203 COMB LCCOMB_X26_Y16_N22 13 " "Info: 203: + IC(0.000 ns) + CELL(0.458 ns) = 81.537 ns; Loc. = LCCOMB_X26_Y16_N22; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.409 ns) + CELL(0.178 ns) 83.124 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[116\]~627 204 COMB LCCOMB_X35_Y16_N30 3 " "Info: 204: + IC(1.409 ns) + CELL(0.178 ns) = 83.124 ns; Loc. = LCCOMB_X35_Y16_N30; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[116\]~627'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.587 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[116]~627 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.417 ns) + CELL(0.517 ns) 85.058 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[3\]~5 205 COMB LCCOMB_X26_Y16_N4 2 " "Info: 205: + IC(1.417 ns) + CELL(0.517 ns) = 85.058 ns; Loc. = LCCOMB_X26_Y16_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.934 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[116]~627 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 91 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 85.138 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[4\]~7 206 COMB LCCOMB_X26_Y16_N6 1 " "Info: 206: + IC(0.000 ns) + CELL(0.080 ns) = 85.138 ns; Loc. = LCCOMB_X26_Y16_N6; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 91 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 85.218 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[5\]~9 207 COMB LCCOMB_X26_Y16_N8 1 " "Info: 207: + IC(0.000 ns) + CELL(0.080 ns) = 85.218 ns; Loc. = LCCOMB_X26_Y16_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 91 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 85.676 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[6\]~10 208 COMB LCCOMB_X26_Y16_N10 13 " "Info: 208: + IC(0.000 ns) + CELL(0.458 ns) = 85.676 ns; Loc. = LCCOMB_X26_Y16_N10; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 91 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.578 ns) + CELL(0.177 ns) 86.431 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[122\]~474 209 COMB LCCOMB_X27_Y16_N8 2 " "Info: 209: + IC(0.578 ns) + CELL(0.177 ns) = 86.431 ns; Loc. = LCCOMB_X27_Y16_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[122\]~474'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.755 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~474 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.476 ns) + CELL(0.517 ns) 88.424 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[3\]~5 210 COMB LCCOMB_X21_Y12_N24 2 " "Info: 210: + IC(1.476 ns) + CELL(0.517 ns) = 88.424 ns; Loc. = LCCOMB_X21_Y12_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.993 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~474 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 88.504 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[4\]~7 211 COMB LCCOMB_X21_Y12_N26 1 " "Info: 211: + IC(0.000 ns) + CELL(0.080 ns) = 88.504 ns; Loc. = LCCOMB_X21_Y12_N26; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 88.584 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[5\]~9 212 COMB LCCOMB_X21_Y12_N28 1 " "Info: 212: + IC(0.000 ns) + CELL(0.080 ns) = 88.584 ns; Loc. = LCCOMB_X21_Y12_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 89.042 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[6\]~10 213 COMB LCCOMB_X21_Y12_N30 13 " "Info: 213: + IC(0.000 ns) + CELL(0.458 ns) = 89.042 ns; Loc. = LCCOMB_X21_Y12_N30; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.569 ns) + CELL(0.319 ns) 89.930 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[126\]~484 214 COMB LCCOMB_X22_Y12_N12 2 " "Info: 214: + IC(0.569 ns) + CELL(0.319 ns) = 89.930 ns; Loc. = LCCOMB_X22_Y12_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[126\]~484'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.888 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[126]~484 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.820 ns) + CELL(0.517 ns) 91.267 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[1\]~1 215 COMB LCCOMB_X21_Y12_N6 2 " "Info: 215: + IC(0.820 ns) + CELL(0.517 ns) = 91.267 ns; Loc. = LCCOMB_X21_Y12_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.337 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[126]~484 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 91.347 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[2\]~3 216 COMB LCCOMB_X21_Y12_N8 2 " "Info: 216: + IC(0.000 ns) + CELL(0.080 ns) = 91.347 ns; Loc. = LCCOMB_X21_Y12_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 91.427 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[3\]~5 217 COMB LCCOMB_X21_Y12_N10 2 " "Info: 217: + IC(0.000 ns) + CELL(0.080 ns) = 91.427 ns; Loc. = LCCOMB_X21_Y12_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 91.507 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[4\]~7 218 COMB LCCOMB_X21_Y12_N12 1 " "Info: 218: + IC(0.000 ns) + CELL(0.080 ns) = 91.507 ns; Loc. = LCCOMB_X21_Y12_N12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 91.681 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[5\]~9 219 COMB LCCOMB_X21_Y12_N14 1 " "Info: 219: + IC(0.000 ns) + CELL(0.174 ns) = 91.681 ns; Loc. = LCCOMB_X21_Y12_N14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 92.139 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[6\]~10 220 COMB LCCOMB_X21_Y12_N16 13 " "Info: 220: + IC(0.000 ns) + CELL(0.458 ns) = 92.139 ns; Loc. = LCCOMB_X21_Y12_N16; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.322 ns) 93.361 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[132\]~492 221 COMB LCCOMB_X20_Y11_N2 2 " "Info: 221: + IC(0.900 ns) + CELL(0.322 ns) = 93.361 ns; Loc. = LCCOMB_X20_Y11_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[132\]~492'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.222 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[132]~492 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.548 ns) + CELL(0.517 ns) 94.426 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[1\]~1 222 COMB LCCOMB_X21_Y11_N6 2 " "Info: 222: + IC(0.548 ns) + CELL(0.517 ns) = 94.426 ns; Loc. = LCCOMB_X21_Y11_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.065 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[132]~492 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 94.506 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[2\]~3 223 COMB LCCOMB_X21_Y11_N8 2 " "Info: 223: + IC(0.000 ns) + CELL(0.080 ns) = 94.506 ns; Loc. = LCCOMB_X21_Y11_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 94.586 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[3\]~5 224 COMB LCCOMB_X21_Y11_N10 2 " "Info: 224: + IC(0.000 ns) + CELL(0.080 ns) = 94.586 ns; Loc. = LCCOMB_X21_Y11_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 94.666 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[4\]~7 225 COMB LCCOMB_X21_Y11_N12 1 " "Info: 225: + IC(0.000 ns) + CELL(0.080 ns) = 94.666 ns; Loc. = LCCOMB_X21_Y11_N12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 94.840 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[5\]~9 226 COMB LCCOMB_X21_Y11_N14 1 " "Info: 226: + IC(0.000 ns) + CELL(0.174 ns) = 94.840 ns; Loc. = LCCOMB_X21_Y11_N14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 95.298 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[6\]~10 227 COMB LCCOMB_X21_Y11_N16 13 " "Info: 227: + IC(0.000 ns) + CELL(0.458 ns) = 95.298 ns; Loc. = LCCOMB_X21_Y11_N16; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.622 ns) + CELL(0.322 ns) 96.242 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[138\]~498 228 COMB LCCOMB_X20_Y11_N28 2 " "Info: 228: + IC(0.622 ns) + CELL(0.322 ns) = 96.242 ns; Loc. = LCCOMB_X20_Y11_N28; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[138\]~498'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.944 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[138]~498 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.526 ns) + CELL(0.495 ns) 97.263 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[1\]~1 229 COMB LCCOMB_X21_Y11_N20 2 " "Info: 229: + IC(0.526 ns) + CELL(0.495 ns) = 97.263 ns; Loc. = LCCOMB_X21_Y11_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.021 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[138]~498 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 97.343 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[2\]~3 230 COMB LCCOMB_X21_Y11_N22 2 " "Info: 230: + IC(0.000 ns) + CELL(0.080 ns) = 97.343 ns; Loc. = LCCOMB_X21_Y11_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 97.423 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[3\]~5 231 COMB LCCOMB_X21_Y11_N24 2 " "Info: 231: + IC(0.000 ns) + CELL(0.080 ns) = 97.423 ns; Loc. = LCCOMB_X21_Y11_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 97.503 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[4\]~7 232 COMB LCCOMB_X21_Y11_N26 1 " "Info: 232: + IC(0.000 ns) + CELL(0.080 ns) = 97.503 ns; Loc. = LCCOMB_X21_Y11_N26; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 97.583 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[5\]~9 233 COMB LCCOMB_X21_Y11_N28 1 " "Info: 233: + IC(0.000 ns) + CELL(0.080 ns) = 97.583 ns; Loc. = LCCOMB_X21_Y11_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 98.041 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[6\]~10 234 COMB LCCOMB_X21_Y11_N30 13 " "Info: 234: + IC(0.000 ns) + CELL(0.458 ns) = 98.041 ns; Loc. = LCCOMB_X21_Y11_N30; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.833 ns) + CELL(0.177 ns) 99.051 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[146\]~502 235 COMB LCCOMB_X20_Y11_N0 2 " "Info: 235: + IC(0.833 ns) + CELL(0.177 ns) = 99.051 ns; Loc. = LCCOMB_X20_Y11_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[146\]~502'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.010 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~502 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.622 ns) + CELL(0.517 ns) 101.190 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[3\]~5 236 COMB LCCOMB_X20_Y20_N6 2 " "Info: 236: + IC(1.622 ns) + CELL(0.517 ns) = 101.190 ns; Loc. = LCCOMB_X20_Y20_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~502 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 101.270 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[4\]~7 237 COMB LCCOMB_X20_Y20_N8 1 " "Info: 237: + IC(0.000 ns) + CELL(0.080 ns) = 101.270 ns; Loc. = LCCOMB_X20_Y20_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 101.350 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[5\]~9 238 COMB LCCOMB_X20_Y20_N10 1 " "Info: 238: + IC(0.000 ns) + CELL(0.080 ns) = 101.350 ns; Loc. = LCCOMB_X20_Y20_N10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 101.808 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[6\]~10 239 COMB LCCOMB_X20_Y20_N12 13 " "Info: 239: + IC(0.000 ns) + CELL(0.458 ns) = 101.808 ns; Loc. = LCCOMB_X20_Y20_N12; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.616 ns) + CELL(0.178 ns) 102.602 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[152\]~633 240 COMB LCCOMB_X21_Y20_N12 3 " "Info: 240: + IC(0.616 ns) + CELL(0.178 ns) = 102.602 ns; Loc. = LCCOMB_X21_Y20_N12; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[152\]~633'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.794 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[152]~633 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.838 ns) + CELL(0.517 ns) 103.957 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[3\]~5 241 COMB LCCOMB_X20_Y20_N20 2 " "Info: 241: + IC(0.838 ns) + CELL(0.517 ns) = 103.957 ns; Loc. = LCCOMB_X20_Y20_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.355 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[152]~633 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 104.037 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[4\]~7 242 COMB LCCOMB_X20_Y20_N22 1 " "Info: 242: + IC(0.000 ns) + CELL(0.080 ns) = 104.037 ns; Loc. = LCCOMB_X20_Y20_N22; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 104.117 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[5\]~9 243 COMB LCCOMB_X20_Y20_N24 1 " "Info: 243: + IC(0.000 ns) + CELL(0.080 ns) = 104.117 ns; Loc. = LCCOMB_X20_Y20_N24; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 104.575 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[6\]~10 244 COMB LCCOMB_X20_Y20_N26 13 " "Info: 244: + IC(0.000 ns) + CELL(0.458 ns) = 104.575 ns; Loc. = LCCOMB_X20_Y20_N26; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.068 ns) + CELL(0.177 ns) 106.820 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[156\]~520 245 COMB LCCOMB_X36_Y21_N10 2 " "Info: 245: + IC(2.068 ns) + CELL(0.177 ns) = 106.820 ns; Loc. = LCCOMB_X36_Y21_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[156\]~520'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.245 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[156]~520 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.552 ns) + CELL(0.517 ns) 107.889 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[1\]~1 246 COMB LCCOMB_X37_Y21_N16 2 " "Info: 246: + IC(0.552 ns) + CELL(0.517 ns) = 107.889 ns; Loc. = LCCOMB_X37_Y21_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.069 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[156]~520 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 107.969 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[2\]~3 247 COMB LCCOMB_X37_Y21_N18 2 " "Info: 247: + IC(0.000 ns) + CELL(0.080 ns) = 107.969 ns; Loc. = LCCOMB_X37_Y21_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 108.049 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[3\]~5 248 COMB LCCOMB_X37_Y21_N20 2 " "Info: 248: + IC(0.000 ns) + CELL(0.080 ns) = 108.049 ns; Loc. = LCCOMB_X37_Y21_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 108.129 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[4\]~7 249 COMB LCCOMB_X37_Y21_N22 1 " "Info: 249: + IC(0.000 ns) + CELL(0.080 ns) = 108.129 ns; Loc. = LCCOMB_X37_Y21_N22; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 108.209 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[5\]~9 250 COMB LCCOMB_X37_Y21_N24 1 " "Info: 250: + IC(0.000 ns) + CELL(0.080 ns) = 108.209 ns; Loc. = LCCOMB_X37_Y21_N24; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 108.667 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[6\]~10 251 COMB LCCOMB_X37_Y21_N26 13 " "Info: 251: + IC(0.000 ns) + CELL(0.458 ns) = 108.667 ns; Loc. = LCCOMB_X37_Y21_N26; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.616 ns) + CELL(0.319 ns) 109.602 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[162\]~526 252 COMB LCCOMB_X36_Y21_N20 2 " "Info: 252: + IC(0.616 ns) + CELL(0.319 ns) = 109.602 ns; Loc. = LCCOMB_X36_Y21_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[162\]~526'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.935 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[162]~526 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.546 ns) + CELL(0.517 ns) 110.665 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[1\]~1 253 COMB LCCOMB_X37_Y21_N0 2 " "Info: 253: + IC(0.546 ns) + CELL(0.517 ns) = 110.665 ns; Loc. = LCCOMB_X37_Y21_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.063 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[162]~526 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 110.745 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[2\]~3 254 COMB LCCOMB_X37_Y21_N2 2 " "Info: 254: + IC(0.000 ns) + CELL(0.080 ns) = 110.745 ns; Loc. = LCCOMB_X37_Y21_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 110.825 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[3\]~5 255 COMB LCCOMB_X37_Y21_N4 2 " "Info: 255: + IC(0.000 ns) + CELL(0.080 ns) = 110.825 ns; Loc. = LCCOMB_X37_Y21_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 110.905 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[4\]~7 256 COMB LCCOMB_X37_Y21_N6 1 " "Info: 256: + IC(0.000 ns) + CELL(0.080 ns) = 110.905 ns; Loc. = LCCOMB_X37_Y21_N6; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 110.985 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[5\]~9 257 COMB LCCOMB_X37_Y21_N8 1 " "Info: 257: + IC(0.000 ns) + CELL(0.080 ns) = 110.985 ns; Loc. = LCCOMB_X37_Y21_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 111.443 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[6\]~10 258 COMB LCCOMB_X37_Y21_N10 13 " "Info: 258: + IC(0.000 ns) + CELL(0.458 ns) = 111.443 ns; Loc. = LCCOMB_X37_Y21_N10; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.180 ns) + CELL(0.322 ns) 112.945 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[169\]~532 259 COMB LCCOMB_X39_Y20_N6 2 " "Info: 259: + IC(1.180 ns) + CELL(0.322 ns) = 112.945 ns; Loc. = LCCOMB_X39_Y20_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[169\]~532'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.502 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[169]~532 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.557 ns) + CELL(0.517 ns) 114.019 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[2\]~3 260 COMB LCCOMB_X38_Y20_N4 2 " "Info: 260: + IC(0.557 ns) + CELL(0.517 ns) = 114.019 ns; Loc. = LCCOMB_X38_Y20_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.074 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[169]~532 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 114.099 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[3\]~5 261 COMB LCCOMB_X38_Y20_N6 2 " "Info: 261: + IC(0.000 ns) + CELL(0.080 ns) = 114.099 ns; Loc. = LCCOMB_X38_Y20_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 114.179 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[4\]~7 262 COMB LCCOMB_X38_Y20_N8 1 " "Info: 262: + IC(0.000 ns) + CELL(0.080 ns) = 114.179 ns; Loc. = LCCOMB_X38_Y20_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 114.259 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[5\]~9 263 COMB LCCOMB_X38_Y20_N10 1 " "Info: 263: + IC(0.000 ns) + CELL(0.080 ns) = 114.259 ns; Loc. = LCCOMB_X38_Y20_N10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 114.717 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[6\]~10 264 COMB LCCOMB_X38_Y20_N12 13 " "Info: 264: + IC(0.000 ns) + CELL(0.458 ns) = 114.717 ns; Loc. = LCCOMB_X38_Y20_N12; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.622 ns) + CELL(0.178 ns) 115.517 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[176\]~637 265 COMB LCCOMB_X39_Y20_N14 3 " "Info: 265: + IC(0.622 ns) + CELL(0.178 ns) = 115.517 ns; Loc. = LCCOMB_X39_Y20_N14; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[176\]~637'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~637 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.862 ns) + CELL(0.517 ns) 116.896 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[3\]~5 266 COMB LCCOMB_X38_Y20_N18 2 " "Info: 266: + IC(0.862 ns) + CELL(0.517 ns) = 116.896 ns; Loc. = LCCOMB_X38_Y20_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.379 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~637 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 116.976 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[4\]~7 267 COMB LCCOMB_X38_Y20_N20 1 " "Info: 267: + IC(0.000 ns) + CELL(0.080 ns) = 116.976 ns; Loc. = LCCOMB_X38_Y20_N20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 117.056 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[5\]~9 268 COMB LCCOMB_X38_Y20_N22 1 " "Info: 268: + IC(0.000 ns) + CELL(0.080 ns) = 117.056 ns; Loc. = LCCOMB_X38_Y20_N22; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 117.514 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[6\]~10 269 COMB LCCOMB_X38_Y20_N24 13 " "Info: 269: + IC(0.000 ns) + CELL(0.458 ns) = 117.514 ns; Loc. = LCCOMB_X38_Y20_N24; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.914 ns) + CELL(0.322 ns) 118.750 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[180\]~548 270 COMB LCCOMB_X37_Y22_N26 2 " "Info: 270: + IC(0.914 ns) + CELL(0.322 ns) = 118.750 ns; Loc. = LCCOMB_X37_Y22_N26; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[180\]~548'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.236 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[180]~548 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.895 ns) + CELL(0.517 ns) 120.162 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[1\]~1 271 COMB LCCOMB_X37_Y20_N20 2 " "Info: 271: + IC(0.895 ns) + CELL(0.517 ns) = 120.162 ns; Loc. = LCCOMB_X37_Y20_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.412 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[180]~548 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 120.242 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[2\]~3 272 COMB LCCOMB_X37_Y20_N22 2 " "Info: 272: + IC(0.000 ns) + CELL(0.080 ns) = 120.242 ns; Loc. = LCCOMB_X37_Y20_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 120.322 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[3\]~5 273 COMB LCCOMB_X37_Y20_N24 2 " "Info: 273: + IC(0.000 ns) + CELL(0.080 ns) = 120.322 ns; Loc. = LCCOMB_X37_Y20_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 120.402 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[4\]~7 274 COMB LCCOMB_X37_Y20_N26 1 " "Info: 274: + IC(0.000 ns) + CELL(0.080 ns) = 120.402 ns; Loc. = LCCOMB_X37_Y20_N26; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 120.482 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[5\]~9 275 COMB LCCOMB_X37_Y20_N28 1 " "Info: 275: + IC(0.000 ns) + CELL(0.080 ns) = 120.482 ns; Loc. = LCCOMB_X37_Y20_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 120.940 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[6\]~10 276 COMB LCCOMB_X37_Y20_N30 10 " "Info: 276: + IC(0.000 ns) + CELL(0.458 ns) = 120.940 ns; Loc. = LCCOMB_X37_Y20_N30; Fanout = 10; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.981 ns) + CELL(0.178 ns) 123.099 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[187\]~550 277 COMB LCCOMB_X13_Y19_N18 3 " "Info: 277: + IC(1.981 ns) + CELL(0.178 ns) = 123.099 ns; Loc. = LCCOMB_X13_Y19_N18; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[187\]~550'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.159 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[187]~550 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.802 ns) + CELL(0.521 ns) 125.422 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|op_2~2 278 COMB LCCOMB_X36_Y20_N16 1 " "Info: 278: + IC(1.802 ns) + CELL(0.521 ns) = 125.422 ns; Loc. = LCCOMB_X36_Y20_N16; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|op_2~2'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.323 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[187]~550 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|op_2~2 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.114 ns) + CELL(0.178 ns) 127.714 ns Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|remainder\[1\]~1 279 COMB LCCOMB_X13_Y19_N22 8 " "Info: 279: + IC(2.114 ns) + CELL(0.178 ns) = 127.714 ns; Loc. = LCCOMB_X13_Y19_N22; Fanout = 8; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod1\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|remainder\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.292 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|op_2~2 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|remainder[1]~1 } "NODE_NAME" } } { "db/abs_divider_kbg.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/abs_divider_kbg.tdf" 33 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.137 ns) + CELL(0.322 ns) 129.173 ns Arkanoid:inst\|Equal36~0 280 COMB LCCOMB_X9_Y20_N22 3 " "Info: 280: + IC(1.137 ns) + CELL(0.322 ns) = 129.173 ns; Loc. = LCCOMB_X9_Y20_N22; Fanout = 3; COMB Node = 'Arkanoid:inst\|Equal36~0'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.459 ns" { Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|remainder[1]~1 Arkanoid:inst|Equal36~0 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.299 ns) + CELL(0.178 ns) 129.650 ns Arkanoid:inst\|low~4 281 COMB LCCOMB_X9_Y20_N16 4 " "Info: 281: + IC(0.299 ns) + CELL(0.178 ns) = 129.650 ns; Loc. = LCCOMB_X9_Y20_N16; Fanout = 4; COMB Node = 'Arkanoid:inst\|low~4'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.477 ns" { Arkanoid:inst|Equal36~0 Arkanoid:inst|low~4 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.798 ns) + CELL(0.322 ns) 130.770 ns Arkanoid:inst\|low~5 282 COMB LCCOMB_X13_Y19_N26 3 " "Info: 282: + IC(0.798 ns) + CELL(0.322 ns) = 130.770 ns; Loc. = LCCOMB_X13_Y19_N26; Fanout = 3; COMB Node = 'Arkanoid:inst\|low~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.120 ns" { Arkanoid:inst|low~4 Arkanoid:inst|low~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.159 ns) + CELL(0.178 ns) 132.107 ns Arkanoid:inst\|low~29 283 COMB LCCOMB_X9_Y20_N8 1 " "Info: 283: + IC(1.159 ns) + CELL(0.178 ns) = 132.107 ns; Loc. = LCCOMB_X9_Y20_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|low~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.337 ns" { Arkanoid:inst|low~5 Arkanoid:inst|low~29 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 132.203 ns Arkanoid:inst\|hex0_\[6\] 284 REG LCFF_X9_Y20_N9 1 " "Info: 284: + IC(0.000 ns) + CELL(0.096 ns) = 132.203 ns; Loc. = LCFF_X9_Y20_N9; Fanout = 1; REG Node = 'Arkanoid:inst\|hex0_\[6\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { Arkanoid:inst|low~29 Arkanoid:inst|hex0_[6] } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "60.731 ns ( 45.94 % ) " "Info: Total cell delay = 60.731 ns ( 45.94 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "71.472 ns ( 54.06 % ) " "Info: Total interconnect delay = 71.472 ns ( 54.06 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "132.203 ns" { Arkanoid:inst|platform1_position[3] Arkanoid:inst|platform1_position~64 Arkanoid:inst|platform1_position~68 Arkanoid:inst|platform1_position~74 Arkanoid:inst|Add2~80 Arkanoid:inst|LessThan1~6 Arkanoid:inst|LessThan1~9 Arkanoid:inst|LessThan1~10 Arkanoid:inst|Add3~1 Arkanoid:inst|Add3~3 Arkanoid:inst|Add3~5 Arkanoid:inst|Add3~7 Arkanoid:inst|Add3~9 Arkanoid:inst|Add3~11 Arkanoid:inst|Add3~13 Arkanoid:inst|Add3~15 Arkanoid:inst|Add3~17 Arkanoid:inst|Add3~19 Arkanoid:inst|Add3~21 Arkanoid:inst|Add3~23 Arkanoid:inst|Add3~25 Arkanoid:inst|Add3~27 Arkanoid:inst|Add3~28 Arkanoid:inst|platform1_position~127 Arkanoid:inst|Add13~29 Arkanoid:inst|Add13~31 Arkanoid:inst|Add13~33 Arkanoid:inst|Add13~35 Arkanoid:inst|Add13~37 Arkanoid:inst|Add13~39 Arkanoid:inst|Add13~41 Arkanoid:inst|Add13~43 Arkanoid:inst|Add13~45 Arkanoid:inst|Add13~47 Arkanoid:inst|Add13~49 Arkanoid:inst|Add13~51 Arkanoid:inst|Add13~52 Arkanoid:inst|LessThan143~53 Arkanoid:inst|LessThan143~55 Arkanoid:inst|LessThan143~57 Arkanoid:inst|LessThan143~59 Arkanoid:inst|LessThan143~61 Arkanoid:inst|LessThan143~62 Arkanoid:inst|always2~6 Arkanoid:inst|Add14~1 Arkanoid:inst|Add14~3 Arkanoid:inst|Add14~5 Arkanoid:inst|Add14~7 Arkanoid:inst|Add14~9 Arkanoid:inst|Add14~11 Arkanoid:inst|Add14~13 Arkanoid:inst|Add14~15 Arkanoid:inst|Add14~17 Arkanoid:inst|Add14~19 Arkanoid:inst|Add14~21 Arkanoid:inst|Add14~23 Arkanoid:inst|Add14~25 Arkanoid:inst|Add14~27 Arkanoid:inst|Add14~29 Arkanoid:inst|Add14~31 Arkanoid:inst|Add14~33 Arkanoid:inst|Add14~35 Arkanoid:inst|Add14~37 Arkanoid:inst|Add14~39 Arkanoid:inst|Add14~41 Arkanoid:inst|Add14~43 Arkanoid:inst|Add14~45 Arkanoid:inst|Add14~47 Arkanoid:inst|Add14~49 Arkanoid:inst|Add14~51 Arkanoid:inst|Add14~53 Arkanoid:inst|Add14~55 Arkanoid:inst|Add14~57 Arkanoid:inst|Add14~59 Arkanoid:inst|Add14~61 Arkanoid:inst|Add14~63 Arkanoid:inst|Add14~65 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~4 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~6 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~8 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~12 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~14 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~16 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~18 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~20 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~22 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~24 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~26 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~28 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~30 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~32 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~34 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~36 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~38 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~40 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~42 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~44 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~46 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~48 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~50 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~52 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~54 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~56 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~57 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[18]~358 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[24]~365 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[32]~369 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~380 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[44]~615 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[50]~616 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[56]~617 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[60]~407 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[66]~415 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[72]~422 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[4]~6 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[82]~423 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[84]~435 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[92]~623 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[97]~447 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~457 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[108]~464 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[116]~627 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~474 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[126]~484 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[132]~492 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[138]~498 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~502 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[152]~633 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[156]~520 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[162]~526 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[169]~532 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~637 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[180]~548 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[187]~550 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|op_2~2 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|remainder[1]~1 Arkanoid:inst|Equal36~0 Arkanoid:inst|low~4 Arkanoid:inst|low~5 Arkanoid:inst|low~29 Arkanoid:inst|hex0_[6] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "132.203 ns" { Arkanoid:inst|platform1_position[3] {} Arkanoid:inst|platform1_position~64 {} Arkanoid:inst|platform1_position~68 {} Arkanoid:inst|platform1_position~74 {} Arkanoid:inst|Add2~80 {} Arkanoid:inst|LessThan1~6 {} Arkanoid:inst|LessThan1~9 {} Arkanoid:inst|LessThan1~10 {} Arkanoid:inst|Add3~1 {} Arkanoid:inst|Add3~3 {} Arkanoid:inst|Add3~5 {} Arkanoid:inst|Add3~7 {} Arkanoid:inst|Add3~9 {} Arkanoid:inst|Add3~11 {} Arkanoid:inst|Add3~13 {} Arkanoid:inst|Add3~15 {} Arkanoid:inst|Add3~17 {} Arkanoid:inst|Add3~19 {} Arkanoid:inst|Add3~21 {} Arkanoid:inst|Add3~23 {} Arkanoid:inst|Add3~25 {} Arkanoid:inst|Add3~27 {} Arkanoid:inst|Add3~28 {} Arkanoid:inst|platform1_position~127 {} Arkanoid:inst|Add13~29 {} Arkanoid:inst|Add13~31 {} Arkanoid:inst|Add13~33 {} Arkanoid:inst|Add13~35 {} Arkanoid:inst|Add13~37 {} Arkanoid:inst|Add13~39 {} Arkanoid:inst|Add13~41 {} Arkanoid:inst|Add13~43 {} Arkanoid:inst|Add13~45 {} Arkanoid:inst|Add13~47 {} Arkanoid:inst|Add13~49 {} Arkanoid:inst|Add13~51 {} Arkanoid:inst|Add13~52 {} Arkanoid:inst|LessThan143~53 {} Arkanoid:inst|LessThan143~55 {} Arkanoid:inst|LessThan143~57 {} Arkanoid:inst|LessThan143~59 {} Arkanoid:inst|LessThan143~61 {} Arkanoid:inst|LessThan143~62 {} Arkanoid:inst|always2~6 {} Arkanoid:inst|Add14~1 {} Arkanoid:inst|Add14~3 {} Arkanoid:inst|Add14~5 {} Arkanoid:inst|Add14~7 {} Arkanoid:inst|Add14~9 {} Arkanoid:inst|Add14~11 {} Arkanoid:inst|Add14~13 {} Arkanoid:inst|Add14~15 {} Arkanoid:inst|Add14~17 {} Arkanoid:inst|Add14~19 {} Arkanoid:inst|Add14~21 {} Arkanoid:inst|Add14~23 {} Arkanoid:inst|Add14~25 {} Arkanoid:inst|Add14~27 {} Arkanoid:inst|Add14~29 {} Arkanoid:inst|Add14~31 {} Arkanoid:inst|Add14~33 {} Arkanoid:inst|Add14~35 {} Arkanoid:inst|Add14~37 {} Arkanoid:inst|Add14~39 {} Arkanoid:inst|Add14~41 {} Arkanoid:inst|Add14~43 {} Arkanoid:inst|Add14~45 {} Arkanoid:inst|Add14~47 {} Arkanoid:inst|Add14~49 {} Arkanoid:inst|Add14~51 {} Arkanoid:inst|Add14~53 {} Arkanoid:inst|Add14~55 {} Arkanoid:inst|Add14~57 {} Arkanoid:inst|Add14~59 {} Arkanoid:inst|Add14~61 {} Arkanoid:inst|Add14~63 {} Arkanoid:inst|Add14~65 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~4 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~6 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~8 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~12 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~14 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~16 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~18 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~20 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~22 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~24 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~26 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~28 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~30 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~32 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~34 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~36 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~38 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~40 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~42 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~44 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~46 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~48 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~50 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~52 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~54 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~56 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~57 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[18]~358 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[24]~365 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[32]~369 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~380 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[44]~615 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[50]~616 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[56]~617 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[60]~407 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[66]~415 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[72]~422 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[4]~6 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[82]~423 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[84]~435 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[92]~623 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[97]~447 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~457 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[108]~464 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[116]~627 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~474 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[126]~484 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[132]~492 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[138]~498 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~502 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[152]~633 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[156]~520 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[162]~526 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[169]~532 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~637 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[180]~548 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[187]~550 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|op_2~2 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|remainder[1]~1 {} Arkanoid:inst|Equal36~0 {} Arkanoid:inst|low~4 {} Arkanoid:inst|low~5 {} Arkanoid:inst|low~29 {} Arkanoid:inst|hex0_[6] {} } { 0.000ns 1.188ns 0.313ns 0.830ns 1.490ns 0.926ns 0.298ns 0.303ns 0.901ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.165ns 1.159ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.820ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.097ns 2.158ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.950ns 1.012ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.186ns 0.000ns 0.000ns 0.000ns 0.373ns 0.559ns 0.000ns 0.000ns 0.000ns 0.000ns 1.235ns 1.187ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.249ns 0.544ns 0.000ns 0.000ns 0.000ns 0.502ns 0.535ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.562ns 1.148ns 0.000ns 0.000ns 0.000ns 0.886ns 1.168ns 0.000ns 0.000ns 0.000ns 0.889ns 1.198ns 0.000ns 0.000ns 0.000ns 0.871ns 0.854ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.893ns 0.552ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.895ns 0.866ns 0.000ns 0.000ns 0.000ns 0.537ns 0.812ns 0.000ns 0.941ns 0.333ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.628ns 0.552ns 0.000ns 0.000ns 0.000ns 0.613ns 0.540ns 0.000ns 0.000ns 0.000ns 0.000ns 0.611ns 0.324ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.134ns 0.809ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.409ns 1.417ns 0.000ns 0.000ns 0.000ns 0.578ns 1.476ns 0.000ns 0.000ns 0.000ns 0.569ns 0.820ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.900ns 0.548ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.622ns 0.526ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.833ns 1.622ns 0.000ns 0.000ns 0.000ns 0.616ns 0.838ns 0.000ns 0.000ns 0.000ns 2.068ns 0.552ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.616ns 0.546ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.180ns 0.557ns 0.000ns 0.000ns 0.000ns 0.000ns 0.622ns 0.862ns 0.000ns 0.000ns 0.000ns 0.914ns 0.895ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.981ns 1.802ns 2.114ns 1.137ns 0.299ns 0.798ns 1.159ns 0.000ns } { 0.000ns 0.178ns 0.512ns 0.521ns 0.322ns 0.455ns 0.491ns 0.322ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.161ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.458ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.161ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.161ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.517ns 0.080ns 0.080ns 0.458ns 0.319ns 0.517ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.322ns 0.495ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.177ns 0.517ns 0.080ns 0.080ns 0.080ns 0.174ns 0.458ns 0.177ns 0.495ns 0.080ns 0.080ns 0.458ns 0.521ns 0.517ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.080ns 0.174ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.458ns 0.319ns 0.517ns 0.080ns 0.080ns 0.174ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.174ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.458ns 0.177ns 0.517ns 0.080ns 0.080ns 0.458ns 0.319ns 0.517ns 0.080ns 0.080ns 0.080ns 0.174ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.080ns 0.174ns 0.458ns 0.322ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.177ns 0.517ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.458ns 0.177ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.319ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.521ns 0.178ns 0.322ns 0.178ns 0.322ns 0.178ns 0.096ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.019 ns - Smallest " "Info: - Smallest clock skew is -0.019 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz destination 4.591 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_50MHz\" to destination register is 4.591 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk_50MHz 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -168 -72 96 -152 "clk_50MHz" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.404 ns) + CELL(0.879 ns) 2.309 ns ClockDivider:inst1\|clk25MHz_ 2 REG LCFF_X1_Y13_N29 2 " "Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'ClockDivider:inst1\|clk25MHz_'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.283 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.703 ns) + CELL(0.000 ns) 3.012 ns ClockDivider:inst1\|clk25MHz_~clkctrl 3 COMB CLKCTRL_G0 1085 " "Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G0; Fanout = 1085; COMB Node = 'ClockDivider:inst1\|clk25MHz_~clkctrl'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.703 ns" { ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.977 ns) + CELL(0.602 ns) 4.591 ns Arkanoid:inst\|hex0_\[6\] 4 REG LCFF_X9_Y20_N9 1 " "Info: 4: + IC(0.977 ns) + CELL(0.602 ns) = 4.591 ns; Loc. = LCFF_X9_Y20_N9; Fanout = 1; REG Node = 'Arkanoid:inst\|hex0_\[6\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.579 ns" { ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|hex0_[6] } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 54.61 % ) " "Info: Total cell delay = 2.507 ns ( 54.61 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.084 ns ( 45.39 % ) " "Info: Total interconnect delay = 2.084 ns ( 45.39 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.591 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|hex0_[6] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.591 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|hex0_[6] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.977ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz source 4.610 ns - Longest register " "Info: - Longest clock path from clock \"clk_50MHz\" to source register is 4.610 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk_50MHz 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -168 -72 96 -152 "clk_50MHz" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.404 ns) + CELL(0.879 ns) 2.309 ns ClockDivider:inst1\|clk25MHz_ 2 REG LCFF_X1_Y13_N29 2 " "Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'ClockDivider:inst1\|clk25MHz_'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.283 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.703 ns) + CELL(0.000 ns) 3.012 ns ClockDivider:inst1\|clk25MHz_~clkctrl 3 COMB CLKCTRL_G0 1085 " "Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G0; Fanout = 1085; COMB Node = 'ClockDivider:inst1\|clk25MHz_~clkctrl'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.703 ns" { ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.996 ns) + CELL(0.602 ns) 4.610 ns Arkanoid:inst\|platform1_position\[3\] 4 REG LCFF_X33_Y12_N7 4 " "Info: 4: + IC(0.996 ns) + CELL(0.602 ns) = 4.610 ns; Loc. = LCFF_X33_Y12_N7; Fanout = 4; REG Node = 'Arkanoid:inst\|platform1_position\[3\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.598 ns" { ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|platform1_position[3] } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 54.38 % ) " "Info: Total cell delay = 2.507 ns ( 54.38 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.103 ns ( 45.62 % ) " "Info: Total interconnect delay = 2.103 ns ( 45.62 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.610 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|platform1_position[3] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.610 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|platform1_position[3] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.996ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.591 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|hex0_[6] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.591 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|hex0_[6] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.977ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.610 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|platform1_position[3] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.610 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|platform1_position[3] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.996ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" { } { { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 19 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" { } { { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 19 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "132.203 ns" { Arkanoid:inst|platform1_position[3] Arkanoid:inst|platform1_position~64 Arkanoid:inst|platform1_position~68 Arkanoid:inst|platform1_position~74 Arkanoid:inst|Add2~80 Arkanoid:inst|LessThan1~6 Arkanoid:inst|LessThan1~9 Arkanoid:inst|LessThan1~10 Arkanoid:inst|Add3~1 Arkanoid:inst|Add3~3 Arkanoid:inst|Add3~5 Arkanoid:inst|Add3~7 Arkanoid:inst|Add3~9 Arkanoid:inst|Add3~11 Arkanoid:inst|Add3~13 Arkanoid:inst|Add3~15 Arkanoid:inst|Add3~17 Arkanoid:inst|Add3~19 Arkanoid:inst|Add3~21 Arkanoid:inst|Add3~23 Arkanoid:inst|Add3~25 Arkanoid:inst|Add3~27 Arkanoid:inst|Add3~28 Arkanoid:inst|platform1_position~127 Arkanoid:inst|Add13~29 Arkanoid:inst|Add13~31 Arkanoid:inst|Add13~33 Arkanoid:inst|Add13~35 Arkanoid:inst|Add13~37 Arkanoid:inst|Add13~39 Arkanoid:inst|Add13~41 Arkanoid:inst|Add13~43 Arkanoid:inst|Add13~45 Arkanoid:inst|Add13~47 Arkanoid:inst|Add13~49 Arkanoid:inst|Add13~51 Arkanoid:inst|Add13~52 Arkanoid:inst|LessThan143~53 Arkanoid:inst|LessThan143~55 Arkanoid:inst|LessThan143~57 Arkanoid:inst|LessThan143~59 Arkanoid:inst|LessThan143~61 Arkanoid:inst|LessThan143~62 Arkanoid:inst|always2~6 Arkanoid:inst|Add14~1 Arkanoid:inst|Add14~3 Arkanoid:inst|Add14~5 Arkanoid:inst|Add14~7 Arkanoid:inst|Add14~9 Arkanoid:inst|Add14~11 Arkanoid:inst|Add14~13 Arkanoid:inst|Add14~15 Arkanoid:inst|Add14~17 Arkanoid:inst|Add14~19 Arkanoid:inst|Add14~21 Arkanoid:inst|Add14~23 Arkanoid:inst|Add14~25 Arkanoid:inst|Add14~27 Arkanoid:inst|Add14~29 Arkanoid:inst|Add14~31 Arkanoid:inst|Add14~33 Arkanoid:inst|Add14~35 Arkanoid:inst|Add14~37 Arkanoid:inst|Add14~39 Arkanoid:inst|Add14~41 Arkanoid:inst|Add14~43 Arkanoid:inst|Add14~45 Arkanoid:inst|Add14~47 Arkanoid:inst|Add14~49 Arkanoid:inst|Add14~51 Arkanoid:inst|Add14~53 Arkanoid:inst|Add14~55 Arkanoid:inst|Add14~57 Arkanoid:inst|Add14~59 Arkanoid:inst|Add14~61 Arkanoid:inst|Add14~63 Arkanoid:inst|Add14~65 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~4 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~6 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~8 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~12 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~14 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~16 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~18 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~20 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~22 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~24 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~26 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~28 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~30 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~32 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~34 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~36 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~38 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~40 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~42 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~44 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~46 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~48 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~50 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~52 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~54 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~56 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~57 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[18]~358 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[24]~365 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[32]~369 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~380 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[44]~615 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[50]~616 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[56]~617 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[60]~407 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[66]~415 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[72]~422 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[4]~6 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[82]~423 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[84]~435 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[92]~623 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[97]~447 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~457 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[108]~464 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[116]~627 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~474 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[126]~484 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[132]~492 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[138]~498 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~502 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[152]~633 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[156]~520 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[162]~526 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[169]~532 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~637 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[180]~548 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[1]~1 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[2]~3 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[187]~550 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|op_2~2 Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|remainder[1]~1 Arkanoid:inst|Equal36~0 Arkanoid:inst|low~4 Arkanoid:inst|low~5 Arkanoid:inst|low~29 Arkanoid:inst|hex0_[6] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "132.203 ns" { Arkanoid:inst|platform1_position[3] {} Arkanoid:inst|platform1_position~64 {} Arkanoid:inst|platform1_position~68 {} Arkanoid:inst|platform1_position~74 {} Arkanoid:inst|Add2~80 {} Arkanoid:inst|LessThan1~6 {} Arkanoid:inst|LessThan1~9 {} Arkanoid:inst|LessThan1~10 {} Arkanoid:inst|Add3~1 {} Arkanoid:inst|Add3~3 {} Arkanoid:inst|Add3~5 {} Arkanoid:inst|Add3~7 {} Arkanoid:inst|Add3~9 {} Arkanoid:inst|Add3~11 {} Arkanoid:inst|Add3~13 {} Arkanoid:inst|Add3~15 {} Arkanoid:inst|Add3~17 {} Arkanoid:inst|Add3~19 {} Arkanoid:inst|Add3~21 {} Arkanoid:inst|Add3~23 {} Arkanoid:inst|Add3~25 {} Arkanoid:inst|Add3~27 {} Arkanoid:inst|Add3~28 {} Arkanoid:inst|platform1_position~127 {} Arkanoid:inst|Add13~29 {} Arkanoid:inst|Add13~31 {} Arkanoid:inst|Add13~33 {} Arkanoid:inst|Add13~35 {} Arkanoid:inst|Add13~37 {} Arkanoid:inst|Add13~39 {} Arkanoid:inst|Add13~41 {} Arkanoid:inst|Add13~43 {} Arkanoid:inst|Add13~45 {} Arkanoid:inst|Add13~47 {} Arkanoid:inst|Add13~49 {} Arkanoid:inst|Add13~51 {} Arkanoid:inst|Add13~52 {} Arkanoid:inst|LessThan143~53 {} Arkanoid:inst|LessThan143~55 {} Arkanoid:inst|LessThan143~57 {} Arkanoid:inst|LessThan143~59 {} Arkanoid:inst|LessThan143~61 {} Arkanoid:inst|LessThan143~62 {} Arkanoid:inst|always2~6 {} Arkanoid:inst|Add14~1 {} Arkanoid:inst|Add14~3 {} Arkanoid:inst|Add14~5 {} Arkanoid:inst|Add14~7 {} Arkanoid:inst|Add14~9 {} Arkanoid:inst|Add14~11 {} Arkanoid:inst|Add14~13 {} Arkanoid:inst|Add14~15 {} Arkanoid:inst|Add14~17 {} Arkanoid:inst|Add14~19 {} Arkanoid:inst|Add14~21 {} Arkanoid:inst|Add14~23 {} Arkanoid:inst|Add14~25 {} Arkanoid:inst|Add14~27 {} Arkanoid:inst|Add14~29 {} Arkanoid:inst|Add14~31 {} Arkanoid:inst|Add14~33 {} Arkanoid:inst|Add14~35 {} Arkanoid:inst|Add14~37 {} Arkanoid:inst|Add14~39 {} Arkanoid:inst|Add14~41 {} Arkanoid:inst|Add14~43 {} Arkanoid:inst|Add14~45 {} Arkanoid:inst|Add14~47 {} Arkanoid:inst|Add14~49 {} Arkanoid:inst|Add14~51 {} Arkanoid:inst|Add14~53 {} Arkanoid:inst|Add14~55 {} Arkanoid:inst|Add14~57 {} Arkanoid:inst|Add14~59 {} Arkanoid:inst|Add14~61 {} Arkanoid:inst|Add14~63 {} Arkanoid:inst|Add14~65 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~4 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~6 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~8 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~12 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~14 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~16 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~18 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~20 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~22 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~24 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~26 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~28 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~30 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~32 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~34 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~36 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~38 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~40 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~42 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~44 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~46 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~48 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~50 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~52 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~54 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~56 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~57 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[18]~358 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[24]~365 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[32]~369 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~380 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[44]~615 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[50]~616 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[56]~617 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[60]~407 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[66]~415 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[72]~422 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[4]~6 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[82]~423 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[84]~435 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[92]~623 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[97]~447 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~457 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[108]~464 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[116]~627 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~474 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[126]~484 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[132]~492 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[138]~498 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~502 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[152]~633 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[156]~520 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[162]~526 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[169]~532 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~637 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[180]~548 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[187]~550 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|op_2~2 {} Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|remainder[1]~1 {} Arkanoid:inst|Equal36~0 {} Arkanoid:inst|low~4 {} Arkanoid:inst|low~5 {} Arkanoid:inst|low~29 {} Arkanoid:inst|hex0_[6] {} } { 0.000ns 1.188ns 0.313ns 0.830ns 1.490ns 0.926ns 0.298ns 0.303ns 0.901ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.165ns 1.159ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.820ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.097ns 2.158ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.950ns 1.012ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.186ns 0.000ns 0.000ns 0.000ns 0.373ns 0.559ns 0.000ns 0.000ns 0.000ns 0.000ns 1.235ns 1.187ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.249ns 0.544ns 0.000ns 0.000ns 0.000ns 0.502ns 0.535ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.562ns 1.148ns 0.000ns 0.000ns 0.000ns 0.886ns 1.168ns 0.000ns 0.000ns 0.000ns 0.889ns 1.198ns 0.000ns 0.000ns 0.000ns 0.871ns 0.854ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.893ns 0.552ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.895ns 0.866ns 0.000ns 0.000ns 0.000ns 0.537ns 0.812ns 0.000ns 0.941ns 0.333ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.628ns 0.552ns 0.000ns 0.000ns 0.000ns 0.613ns 0.540ns 0.000ns 0.000ns 0.000ns 0.000ns 0.611ns 0.324ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.134ns 0.809ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.409ns 1.417ns 0.000ns 0.000ns 0.000ns 0.578ns 1.476ns 0.000ns 0.000ns 0.000ns 0.569ns 0.820ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.900ns 0.548ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.622ns 0.526ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.833ns 1.622ns 0.000ns 0.000ns 0.000ns 0.616ns 0.838ns 0.000ns 0.000ns 0.000ns 2.068ns 0.552ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.616ns 0.546ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.180ns 0.557ns 0.000ns 0.000ns 0.000ns 0.000ns 0.622ns 0.862ns 0.000ns 0.000ns 0.000ns 0.914ns 0.895ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.981ns 1.802ns 2.114ns 1.137ns 0.299ns 0.798ns 1.159ns 0.000ns } { 0.000ns 0.178ns 0.512ns 0.521ns 0.322ns 0.455ns 0.491ns 0.322ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.161ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.458ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.161ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.161ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.517ns 0.080ns 0.080ns 0.458ns 0.319ns 0.517ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.322ns 0.495ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.177ns 0.517ns 0.080ns 0.080ns 0.080ns 0.174ns 0.458ns 0.177ns 0.495ns 0.080ns 0.080ns 0.458ns 0.521ns 0.517ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.080ns 0.174ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.458ns 0.319ns 0.517ns 0.080ns 0.080ns 0.174ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.174ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.458ns 0.177ns 0.517ns 0.080ns 0.080ns 0.458ns 0.319ns 0.517ns 0.080ns 0.080ns 0.080ns 0.174ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.080ns 0.174ns 0.458ns 0.322ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.177ns 0.517ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.458ns 0.177ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.319ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.521ns 0.178ns 0.322ns 0.178ns 0.322ns 0.178ns 0.096ns } "" } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.591 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|hex0_[6] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.591 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|hex0_[6] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.977ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.610 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|platform1_position[3] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.610 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|platform1_position[3] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.996ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
+{ "Info" "ITDB_TSU_RESULT" "Debouncer:inst5\|button_reg\[0\] button4 clk_50MHz 3.159 ns register " "Info: tsu for register \"Debouncer:inst5\|button_reg\[0\]\" (data pin = \"button4\", clock pin = \"clk_50MHz\") is 3.159 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.814 ns + Longest pin register " "Info: + Longest pin to register delay is 7.814 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns button4 1 PIN PIN_R22 1 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_R22; Fanout = 1; PIN Node = 'button4'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { button4 } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { 216 -72 96 232 "button4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.537 ns) + CELL(0.413 ns) 7.814 ns Debouncer:inst5\|button_reg\[0\] 2 REG LCFF_X12_Y12_N29 2 " "Info: 2: + IC(6.537 ns) + CELL(0.413 ns) = 7.814 ns; Loc. = LCFF_X12_Y12_N29; Fanout = 2; REG Node = 'Debouncer:inst5\|button_reg\[0\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.950 ns" { button4 Debouncer:inst5|button_reg[0] } "NODE_NAME" } } { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.277 ns ( 16.34 % ) " "Info: Total cell delay = 1.277 ns ( 16.34 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.537 ns ( 83.66 % ) " "Info: Total interconnect delay = 6.537 ns ( 83.66 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "7.814 ns" { button4 Debouncer:inst5|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "7.814 ns" { button4 {} button4~combout {} Debouncer:inst5|button_reg[0] {} } { 0.000ns 0.000ns 6.537ns } { 0.000ns 0.864ns 0.413ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" { } { { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 9 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz destination 4.617 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_50MHz\" to destination register is 4.617 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk_50MHz 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -168 -72 96 -152 "clk_50MHz" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.404 ns) + CELL(0.879 ns) 2.309 ns ClockDivider:inst1\|clk25MHz_ 2 REG LCFF_X1_Y13_N29 2 " "Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'ClockDivider:inst1\|clk25MHz_'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.283 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.703 ns) + CELL(0.000 ns) 3.012 ns ClockDivider:inst1\|clk25MHz_~clkctrl 3 COMB CLKCTRL_G0 1085 " "Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G0; Fanout = 1085; COMB Node = 'ClockDivider:inst1\|clk25MHz_~clkctrl'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.703 ns" { ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.003 ns) + CELL(0.602 ns) 4.617 ns Debouncer:inst5\|button_reg\[0\] 4 REG LCFF_X12_Y12_N29 2 " "Info: 4: + IC(1.003 ns) + CELL(0.602 ns) = 4.617 ns; Loc. = LCFF_X12_Y12_N29; Fanout = 2; REG Node = 'Debouncer:inst5\|button_reg\[0\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.605 ns" { ClockDivider:inst1|clk25MHz_~clkctrl Debouncer:inst5|button_reg[0] } "NODE_NAME" } } { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 54.30 % ) " "Info: Total cell delay = 2.507 ns ( 54.30 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.110 ns ( 45.70 % ) " "Info: Total interconnect delay = 2.110 ns ( 45.70 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.617 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Debouncer:inst5|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.617 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Debouncer:inst5|button_reg[0] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 1.003ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "7.814 ns" { button4 Debouncer:inst5|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "7.814 ns" { button4 {} button4~combout {} Debouncer:inst5|button_reg[0] {} } { 0.000ns 0.000ns 6.537ns } { 0.000ns 0.864ns 0.413ns } "" } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.617 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Debouncer:inst5|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.617 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Debouncer:inst5|button_reg[0] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 1.003ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TCO_RESULT" "clk_50MHz h_sync Arkanoid:inst\|h_counter\[0\] 14.776 ns register " "Info: tco from clock \"clk_50MHz\" to destination pin \"h_sync\" through register \"Arkanoid:inst\|h_counter\[0\]\" is 14.776 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz source 4.595 ns + Longest register " "Info: + Longest clock path from clock \"clk_50MHz\" to source register is 4.595 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk_50MHz 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -168 -72 96 -152 "clk_50MHz" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.404 ns) + CELL(0.879 ns) 2.309 ns ClockDivider:inst1\|clk25MHz_ 2 REG LCFF_X1_Y13_N29 2 " "Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'ClockDivider:inst1\|clk25MHz_'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.283 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.703 ns) + CELL(0.000 ns) 3.012 ns ClockDivider:inst1\|clk25MHz_~clkctrl 3 COMB CLKCTRL_G0 1085 " "Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G0; Fanout = 1085; COMB Node = 'ClockDivider:inst1\|clk25MHz_~clkctrl'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.703 ns" { ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.981 ns) + CELL(0.602 ns) 4.595 ns Arkanoid:inst\|h_counter\[0\] 4 REG LCFF_X26_Y5_N1 7 " "Info: 4: + IC(0.981 ns) + CELL(0.602 ns) = 4.595 ns; Loc. = LCFF_X26_Y5_N1; Fanout = 7; REG Node = 'Arkanoid:inst\|h_counter\[0\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.583 ns" { ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|h_counter[0] } "NODE_NAME" } } { "vga_sync.v" "" { Text "G:/Verilog/Arkanoid2PDE1/vga_sync.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 54.56 % ) " "Info: Total cell delay = 2.507 ns ( 54.56 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.088 ns ( 45.44 % ) " "Info: Total interconnect delay = 2.088 ns ( 45.44 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.595 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|h_counter[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.595 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|h_counter[0] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.981ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" { } { { "vga_sync.v" "" { Text "G:/Verilog/Arkanoid2PDE1/vga_sync.v" 9 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.904 ns + Longest register pin " "Info: + Longest register to pin delay is 9.904 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Arkanoid:inst\|h_counter\[0\] 1 REG LCFF_X26_Y5_N1 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y5_N1; Fanout = 7; REG Node = 'Arkanoid:inst\|h_counter\[0\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { Arkanoid:inst|h_counter[0] } "NODE_NAME" } } { "vga_sync.v" "" { Text "G:/Verilog/Arkanoid2PDE1/vga_sync.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.640 ns) + CELL(0.512 ns) 1.152 ns Arkanoid:inst\|Equal0~0 2 COMB LCCOMB_X27_Y5_N2 3 " "Info: 2: + IC(0.640 ns) + CELL(0.512 ns) = 1.152 ns; Loc. = LCCOMB_X27_Y5_N2; Fanout = 3; COMB Node = 'Arkanoid:inst\|Equal0~0'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.152 ns" { Arkanoid:inst|h_counter[0] Arkanoid:inst|Equal0~0 } "NODE_NAME" } } { "vga_sync.v" "" { Text "G:/Verilog/Arkanoid2PDE1/vga_sync.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.181 ns) + CELL(0.545 ns) 2.878 ns Arkanoid:inst\|LessThan156~0 3 COMB LCCOMB_X25_Y6_N22 1 " "Info: 3: + IC(1.181 ns) + CELL(0.545 ns) = 2.878 ns; Loc. = LCCOMB_X25_Y6_N22; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan156~0'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.726 ns" { Arkanoid:inst|Equal0~0 Arkanoid:inst|LessThan156~0 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 385 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.301 ns) + CELL(0.521 ns) 3.700 ns Arkanoid:inst\|h_sync~1 4 COMB LCCOMB_X25_Y6_N4 1 " "Info: 4: + IC(0.301 ns) + CELL(0.521 ns) = 3.700 ns; Loc. = LCCOMB_X25_Y6_N4; Fanout = 1; COMB Node = 'Arkanoid:inst\|h_sync~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.822 ns" { Arkanoid:inst|LessThan156~0 Arkanoid:inst|h_sync~1 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.198 ns) + CELL(3.006 ns) 9.904 ns h_sync 5 PIN PIN_A11 0 " "Info: 5: + IC(3.198 ns) + CELL(3.006 ns) = 9.904 ns; Loc. = PIN_A11; Fanout = 0; PIN Node = 'h_sync'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.204 ns" { Arkanoid:inst|h_sync~1 h_sync } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { 96 856 1032 112 "h_sync" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.584 ns ( 46.28 % ) " "Info: Total cell delay = 4.584 ns ( 46.28 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.320 ns ( 53.72 % ) " "Info: Total interconnect delay = 5.320 ns ( 53.72 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "9.904 ns" { Arkanoid:inst|h_counter[0] Arkanoid:inst|Equal0~0 Arkanoid:inst|LessThan156~0 Arkanoid:inst|h_sync~1 h_sync } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "9.904 ns" { Arkanoid:inst|h_counter[0] {} Arkanoid:inst|Equal0~0 {} Arkanoid:inst|LessThan156~0 {} Arkanoid:inst|h_sync~1 {} h_sync {} } { 0.000ns 0.640ns 1.181ns 0.301ns 3.198ns } { 0.000ns 0.512ns 0.545ns 0.521ns 3.006ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.595 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|h_counter[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.595 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|h_counter[0] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.981ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "9.904 ns" { Arkanoid:inst|h_counter[0] Arkanoid:inst|Equal0~0 Arkanoid:inst|LessThan156~0 Arkanoid:inst|h_sync~1 h_sync } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "9.904 ns" { Arkanoid:inst|h_counter[0] {} Arkanoid:inst|Equal0~0 {} Arkanoid:inst|LessThan156~0 {} Arkanoid:inst|h_sync~1 {} h_sync {} } { 0.000ns 0.640ns 1.181ns 0.301ns 3.198ns } { 0.000ns 0.512ns 0.545ns 0.521ns 3.006ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_TH_RESULT" "Debouncer:inst2\|button_reg\[0\] button1 clk_50MHz -1.772 ns register " "Info: th for register \"Debouncer:inst2\|button_reg\[0\]\" (data pin = \"button1\", clock pin = \"clk_50MHz\") is -1.772 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz destination 4.606 ns + Longest register " "Info: + Longest clock path from clock \"clk_50MHz\" to destination register is 4.606 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk_50MHz 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -168 -72 96 -152 "clk_50MHz" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.404 ns) + CELL(0.879 ns) 2.309 ns ClockDivider:inst1\|clk25MHz_ 2 REG LCFF_X1_Y13_N29 2 " "Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'ClockDivider:inst1\|clk25MHz_'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.283 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.703 ns) + CELL(0.000 ns) 3.012 ns ClockDivider:inst1\|clk25MHz_~clkctrl 3 COMB CLKCTRL_G0 1085 " "Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G0; Fanout = 1085; COMB Node = 'ClockDivider:inst1\|clk25MHz_~clkctrl'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.703 ns" { ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.602 ns) 4.606 ns Debouncer:inst2\|button_reg\[0\] 4 REG LCFF_X45_Y9_N9 2 " "Info: 4: + IC(0.992 ns) + CELL(0.602 ns) = 4.606 ns; Loc. = LCFF_X45_Y9_N9; Fanout = 2; REG Node = 'Debouncer:inst2\|button_reg\[0\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.594 ns" { ClockDivider:inst1|clk25MHz_~clkctrl Debouncer:inst2|button_reg[0] } "NODE_NAME" } } { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 54.43 % ) " "Info: Total cell delay = 2.507 ns ( 54.43 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.099 ns ( 45.57 % ) " "Info: Total interconnect delay = 2.099 ns ( 45.57 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.606 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Debouncer:inst2|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.606 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Debouncer:inst2|button_reg[0] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.992ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" { } { { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 9 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.664 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.664 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.874 ns) 0.874 ns button1 1 PIN PIN_T21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.874 ns) = 0.874 ns; Loc. = PIN_T21; Fanout = 1; PIN Node = 'button1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { button1 } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -72 -72 96 -56 "button1" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.377 ns) + CELL(0.413 ns) 6.664 ns Debouncer:inst2\|button_reg\[0\] 2 REG LCFF_X45_Y9_N9 2 " "Info: 2: + IC(5.377 ns) + CELL(0.413 ns) = 6.664 ns; Loc. = LCFF_X45_Y9_N9; Fanout = 2; REG Node = 'Debouncer:inst2\|button_reg\[0\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.790 ns" { button1 Debouncer:inst2|button_reg[0] } "NODE_NAME" } } { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.287 ns ( 19.31 % ) " "Info: Total cell delay = 1.287 ns ( 19.31 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.377 ns ( 80.69 % ) " "Info: Total interconnect delay = 5.377 ns ( 80.69 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.664 ns" { button1 Debouncer:inst2|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "6.664 ns" { button1 {} button1~combout {} Debouncer:inst2|button_reg[0] {} } { 0.000ns 0.000ns 5.377ns } { 0.000ns 0.874ns 0.413ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.606 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Debouncer:inst2|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.606 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Debouncer:inst2|button_reg[0] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.992ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.664 ns" { button1 Debouncer:inst2|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "6.664 ns" { button1 {} button1~combout {} Debouncer:inst2|button_reg[0] {} } { 0.000ns 0.000ns 5.377ns } { 0.000ns 0.874ns 0.413ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "201 " "Info: Peak virtual memory: 201 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 28 14:22:38 2012 " "Info: Processing ended: Mon May 28 14:22:38 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Info: Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/db/myArkanoid.tis_db_list.ddb b/db/myArkanoid.tis_db_list.ddb
new file mode 100644
index 0000000..6cdb8ef
Binary files /dev/null and b/db/myArkanoid.tis_db_list.ddb differ
diff --git a/db/myArkanoid.tmw_info b/db/myArkanoid.tmw_info
new file mode 100644
index 0000000..217be58
--- /dev/null
+++ b/db/myArkanoid.tmw_info
@@ -0,0 +1,6 @@
+start_full_compilation:s:00:03:44
+start_analysis_synthesis:s:00:03:03-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:29-start_full_compilation
+start_assembler:s:00:00:04-start_full_compilation
+start_timing_analyzer:s:00:00:08-start_full_compilation
diff --git a/db/prev_cmp_myArkanoid.asm.qmsg b/db/prev_cmp_myArkanoid.asm.qmsg
new file mode 100644
index 0000000..2e9dc7d
--- /dev/null
+++ b/db/prev_cmp_myArkanoid.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 27 20:49:24 2012 " "Info: Processing started: Sun May 27 20:49:24 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "219 " "Info: Peak virtual memory: 219 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 27 20:49:27 2012 " "Info: Processing ended: Sun May 27 20:49:27 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/db/prev_cmp_myArkanoid.fit.qmsg b/db/prev_cmp_myArkanoid.fit.qmsg
new file mode 100644
index 0000000..0af049e
--- /dev/null
+++ b/db/prev_cmp_myArkanoid.fit.qmsg
@@ -0,0 +1,38 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 27 20:48:53 2012 " "Info: Processing started: Sun May 27 20:48:53 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "IMPP_MPP_USER_DEVICE" "myArkanoid EP2C20F484C7 " "Info: Selected device EP2C20F484C7 for design \"myArkanoid\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C15AF484C7 " "Info: Device EP2C15AF484C7 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484C7 " "Info: Device EP2C35F484C7 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C7 " "Info: Device EP2C50F484C7 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ C4 " "Info: Pin ~ASDO~ is reserved at location C4" { } { { "c:/quartus/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/quartus/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/Verilog/Arkanoid2PDE1/" 0 { } { { 0 { 0 ""} 0 12662 3016 4146 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ C3 " "Info: Pin ~nCSO~ is reserved at location C3" { } { { "c:/quartus/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/quartus/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/Verilog/Arkanoid2PDE1/" 0 { } { { 0 { 0 ""} 0 12663 3016 4146 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS91p/nCEO~ W20 " "Info: Pin ~LVDS91p/nCEO~ is reserved at location W20" { } { { "c:/quartus/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/quartus/quartus/bin/pin_planner.ppl" { ~LVDS91p/nCEO~ } } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS91p/nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/Verilog/Arkanoid2PDE1/" 0 { } { { 0 { 0 ""} 0 12664 3016 4146 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
+{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Timing-driven compilation is using the Classic Timing Analyzer" { } { } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
+{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ClockDivider:inst1\|clk25MHz_ " "Info: Automatically promoted node ClockDivider:inst1\|clk25MHz_ " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ClockDivider:inst1\|clk25MHz_~0 " "Info: Destination node ClockDivider:inst1\|clk25MHz_~0" { } { { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { ClockDivider:inst1|clk25MHz_~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/Verilog/Arkanoid2PDE1/" 0 { } { { 0 { 0 ""} 0 12656 3016 4146 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1} } { { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { ClockDivider:inst1|clk25MHz_ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/Verilog/Arkanoid2PDE1/" 0 { } { { 0 { 0 ""} 0 19 3016 4146 0} } } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Info: Fitter preparation operations ending: elapsed time is 00:00:03" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:05 " "Info: Fitter placement operations ending: elapsed time is 00:00:05" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "142.293 ns register register " "Info: Estimated most critical path is register to register delay of 142.293 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Arkanoid:inst\|button2_state 1 REG LAB_X30_Y11 36 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X30_Y11; Fanout = 36; REG Node = 'Arkanoid:inst\|button2_state'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { Arkanoid:inst|button2_state } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 108 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.768 ns) + CELL(0.544 ns) 1.312 ns Arkanoid:inst\|platform2_position~4 2 COMB LAB_X30_Y12 69 " "Info: 2: + IC(0.768 ns) + CELL(0.544 ns) = 1.312 ns; Loc. = LAB_X30_Y12; Fanout = 69; COMB Node = 'Arkanoid:inst\|platform2_position~4'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.312 ns" { Arkanoid:inst|button2_state Arkanoid:inst|platform2_position~4 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.695 ns) + CELL(0.521 ns) 2.528 ns Arkanoid:inst\|platform2_position~5 3 COMB LAB_X27_Y12 63 " "Info: 3: + IC(0.695 ns) + CELL(0.521 ns) = 2.528 ns; Loc. = LAB_X27_Y12; Fanout = 63; COMB Node = 'Arkanoid:inst\|platform2_position~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.216 ns" { Arkanoid:inst|platform2_position~4 Arkanoid:inst|platform2_position~5 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.495 ns) 4.112 ns Arkanoid:inst\|Add4~1 4 COMB LAB_X27_Y16 2 " "Info: 4: + IC(1.089 ns) + CELL(0.495 ns) = 4.112 ns; Loc. = LAB_X27_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.584 ns" { Arkanoid:inst|platform2_position~5 Arkanoid:inst|Add4~1 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.192 ns Arkanoid:inst\|Add4~3 5 COMB LAB_X27_Y16 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 4.192 ns; Loc. = LAB_X27_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~1 Arkanoid:inst|Add4~3 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.272 ns Arkanoid:inst\|Add4~5 6 COMB LAB_X27_Y16 2 " "Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 4.272 ns; Loc. = LAB_X27_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~3 Arkanoid:inst|Add4~5 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.352 ns Arkanoid:inst\|Add4~7 7 COMB LAB_X27_Y16 2 " "Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 4.352 ns; Loc. = LAB_X27_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~5 Arkanoid:inst|Add4~7 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.432 ns Arkanoid:inst\|Add4~9 8 COMB LAB_X27_Y16 2 " "Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 4.432 ns; Loc. = LAB_X27_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~7 Arkanoid:inst|Add4~9 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.512 ns Arkanoid:inst\|Add4~11 9 COMB LAB_X27_Y16 2 " "Info: 9: + IC(0.000 ns) + CELL(0.080 ns) = 4.512 ns; Loc. = LAB_X27_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~9 Arkanoid:inst|Add4~11 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.592 ns Arkanoid:inst\|Add4~13 10 COMB LAB_X27_Y16 2 " "Info: 10: + IC(0.000 ns) + CELL(0.080 ns) = 4.592 ns; Loc. = LAB_X27_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~11 Arkanoid:inst|Add4~13 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.672 ns Arkanoid:inst\|Add4~15 11 COMB LAB_X27_Y16 2 " "Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 4.672 ns; Loc. = LAB_X27_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~13 Arkanoid:inst|Add4~15 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.752 ns Arkanoid:inst\|Add4~17 12 COMB LAB_X27_Y16 2 " "Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 4.752 ns; Loc. = LAB_X27_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~15 Arkanoid:inst|Add4~17 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.832 ns Arkanoid:inst\|Add4~19 13 COMB LAB_X27_Y16 2 " "Info: 13: + IC(0.000 ns) + CELL(0.080 ns) = 4.832 ns; Loc. = LAB_X27_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~17 Arkanoid:inst|Add4~19 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.912 ns Arkanoid:inst\|Add4~21 14 COMB LAB_X27_Y16 2 " "Info: 14: + IC(0.000 ns) + CELL(0.080 ns) = 4.912 ns; Loc. = LAB_X27_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~19 Arkanoid:inst|Add4~21 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.992 ns Arkanoid:inst\|Add4~23 15 COMB LAB_X27_Y16 2 " "Info: 15: + IC(0.000 ns) + CELL(0.080 ns) = 4.992 ns; Loc. = LAB_X27_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~21 Arkanoid:inst|Add4~23 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.072 ns Arkanoid:inst\|Add4~25 16 COMB LAB_X27_Y16 2 " "Info: 16: + IC(0.000 ns) + CELL(0.080 ns) = 5.072 ns; Loc. = LAB_X27_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~23 Arkanoid:inst|Add4~25 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.152 ns Arkanoid:inst\|Add4~27 17 COMB LAB_X27_Y16 2 " "Info: 17: + IC(0.000 ns) + CELL(0.080 ns) = 5.152 ns; Loc. = LAB_X27_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~25 Arkanoid:inst|Add4~27 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.232 ns Arkanoid:inst\|Add4~29 18 COMB LAB_X27_Y16 2 " "Info: 18: + IC(0.000 ns) + CELL(0.080 ns) = 5.232 ns; Loc. = LAB_X27_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~27 Arkanoid:inst|Add4~29 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.312 ns Arkanoid:inst\|Add4~31 19 COMB LAB_X27_Y16 2 " "Info: 19: + IC(0.000 ns) + CELL(0.080 ns) = 5.312 ns; Loc. = LAB_X27_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~29 Arkanoid:inst|Add4~31 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.098 ns) + CELL(0.080 ns) 5.490 ns Arkanoid:inst\|Add4~33 20 COMB LAB_X27_Y15 2 " "Info: 20: + IC(0.098 ns) + CELL(0.080 ns) = 5.490 ns; Loc. = LAB_X27_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { Arkanoid:inst|Add4~31 Arkanoid:inst|Add4~33 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.570 ns Arkanoid:inst\|Add4~35 21 COMB LAB_X27_Y15 2 " "Info: 21: + IC(0.000 ns) + CELL(0.080 ns) = 5.570 ns; Loc. = LAB_X27_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~33 Arkanoid:inst|Add4~35 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.650 ns Arkanoid:inst\|Add4~37 22 COMB LAB_X27_Y15 2 " "Info: 22: + IC(0.000 ns) + CELL(0.080 ns) = 5.650 ns; Loc. = LAB_X27_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~35 Arkanoid:inst|Add4~37 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.730 ns Arkanoid:inst\|Add4~39 23 COMB LAB_X27_Y15 2 " "Info: 23: + IC(0.000 ns) + CELL(0.080 ns) = 5.730 ns; Loc. = LAB_X27_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~37 Arkanoid:inst|Add4~39 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.810 ns Arkanoid:inst\|Add4~41 24 COMB LAB_X27_Y15 2 " "Info: 24: + IC(0.000 ns) + CELL(0.080 ns) = 5.810 ns; Loc. = LAB_X27_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~39 Arkanoid:inst|Add4~41 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.890 ns Arkanoid:inst\|Add4~43 25 COMB LAB_X27_Y15 2 " "Info: 25: + IC(0.000 ns) + CELL(0.080 ns) = 5.890 ns; Loc. = LAB_X27_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~41 Arkanoid:inst|Add4~43 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.970 ns Arkanoid:inst\|Add4~45 26 COMB LAB_X27_Y15 2 " "Info: 26: + IC(0.000 ns) + CELL(0.080 ns) = 5.970 ns; Loc. = LAB_X27_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~43 Arkanoid:inst|Add4~45 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 6.050 ns Arkanoid:inst\|Add4~47 27 COMB LAB_X27_Y15 2 " "Info: 27: + IC(0.000 ns) + CELL(0.080 ns) = 6.050 ns; Loc. = LAB_X27_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~45 Arkanoid:inst|Add4~47 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 6.130 ns Arkanoid:inst\|Add4~49 28 COMB LAB_X27_Y15 2 " "Info: 28: + IC(0.000 ns) + CELL(0.080 ns) = 6.130 ns; Loc. = LAB_X27_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~47 Arkanoid:inst|Add4~49 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 6.210 ns Arkanoid:inst\|Add4~51 29 COMB LAB_X27_Y15 2 " "Info: 29: + IC(0.000 ns) + CELL(0.080 ns) = 6.210 ns; Loc. = LAB_X27_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~51'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~49 Arkanoid:inst|Add4~51 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 6.290 ns Arkanoid:inst\|Add4~53 30 COMB LAB_X27_Y15 2 " "Info: 30: + IC(0.000 ns) + CELL(0.080 ns) = 6.290 ns; Loc. = LAB_X27_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~53'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~51 Arkanoid:inst|Add4~53 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 6.748 ns Arkanoid:inst\|Add4~54 31 COMB LAB_X27_Y15 1 " "Info: 31: + IC(0.000 ns) + CELL(0.458 ns) = 6.748 ns; Loc. = LAB_X27_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|Add4~54'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|Add4~53 Arkanoid:inst|Add4~54 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.521 ns) 8.014 ns Arkanoid:inst\|platform2_position~37 32 COMB LAB_X27_Y12 4 " "Info: 32: + IC(0.745 ns) + CELL(0.521 ns) = 8.014 ns; Loc. = LAB_X27_Y12; Fanout = 4; COMB Node = 'Arkanoid:inst\|platform2_position~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.266 ns" { Arkanoid:inst|Add4~54 Arkanoid:inst|platform2_position~37 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.177 ns) 8.689 ns Arkanoid:inst\|LessThan3~3 33 COMB LAB_X27_Y12 1 " "Info: 33: + IC(0.498 ns) + CELL(0.177 ns) = 8.689 ns; Loc. = LAB_X27_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan3~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.675 ns" { Arkanoid:inst|platform2_position~37 Arkanoid:inst|LessThan3~3 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 92 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.178 ns) 9.365 ns Arkanoid:inst\|LessThan3~4 34 COMB LAB_X27_Y12 1 " "Info: 34: + IC(0.498 ns) + CELL(0.178 ns) = 9.365 ns; Loc. = LAB_X27_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan3~4'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { Arkanoid:inst|LessThan3~3 Arkanoid:inst|LessThan3~4 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 92 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.588 ns) + CELL(0.322 ns) 10.275 ns Arkanoid:inst\|LessThan3~10 35 COMB LAB_X26_Y12 2 " "Info: 35: + IC(0.588 ns) + CELL(0.322 ns) = 10.275 ns; Loc. = LAB_X26_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|LessThan3~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.910 ns" { Arkanoid:inst|LessThan3~4 Arkanoid:inst|LessThan3~10 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 92 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.107 ns) + CELL(0.495 ns) 11.877 ns Arkanoid:inst\|Add5~1 36 COMB LAB_X27_Y14 2 " "Info: 36: + IC(1.107 ns) + CELL(0.495 ns) = 11.877 ns; Loc. = LAB_X27_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.602 ns" { Arkanoid:inst|LessThan3~10 Arkanoid:inst|Add5~1 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 11.957 ns Arkanoid:inst\|Add5~3 37 COMB LAB_X27_Y14 2 " "Info: 37: + IC(0.000 ns) + CELL(0.080 ns) = 11.957 ns; Loc. = LAB_X27_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~1 Arkanoid:inst|Add5~3 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.037 ns Arkanoid:inst\|Add5~5 38 COMB LAB_X27_Y14 2 " "Info: 38: + IC(0.000 ns) + CELL(0.080 ns) = 12.037 ns; Loc. = LAB_X27_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~3 Arkanoid:inst|Add5~5 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.117 ns Arkanoid:inst\|Add5~7 39 COMB LAB_X27_Y14 2 " "Info: 39: + IC(0.000 ns) + CELL(0.080 ns) = 12.117 ns; Loc. = LAB_X27_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~5 Arkanoid:inst|Add5~7 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.197 ns Arkanoid:inst\|Add5~9 40 COMB LAB_X27_Y14 2 " "Info: 40: + IC(0.000 ns) + CELL(0.080 ns) = 12.197 ns; Loc. = LAB_X27_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~7 Arkanoid:inst|Add5~9 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.277 ns Arkanoid:inst\|Add5~11 41 COMB LAB_X27_Y14 2 " "Info: 41: + IC(0.000 ns) + CELL(0.080 ns) = 12.277 ns; Loc. = LAB_X27_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~9 Arkanoid:inst|Add5~11 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.357 ns Arkanoid:inst\|Add5~13 42 COMB LAB_X27_Y14 2 " "Info: 42: + IC(0.000 ns) + CELL(0.080 ns) = 12.357 ns; Loc. = LAB_X27_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~11 Arkanoid:inst|Add5~13 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.437 ns Arkanoid:inst\|Add5~15 43 COMB LAB_X27_Y14 2 " "Info: 43: + IC(0.000 ns) + CELL(0.080 ns) = 12.437 ns; Loc. = LAB_X27_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~13 Arkanoid:inst|Add5~15 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.517 ns Arkanoid:inst\|Add5~17 44 COMB LAB_X27_Y14 2 " "Info: 44: + IC(0.000 ns) + CELL(0.080 ns) = 12.517 ns; Loc. = LAB_X27_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~15 Arkanoid:inst|Add5~17 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.597 ns Arkanoid:inst\|Add5~19 45 COMB LAB_X27_Y14 2 " "Info: 45: + IC(0.000 ns) + CELL(0.080 ns) = 12.597 ns; Loc. = LAB_X27_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~17 Arkanoid:inst|Add5~19 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.677 ns Arkanoid:inst\|Add5~21 46 COMB LAB_X27_Y14 2 " "Info: 46: + IC(0.000 ns) + CELL(0.080 ns) = 12.677 ns; Loc. = LAB_X27_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~19 Arkanoid:inst|Add5~21 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 13.135 ns Arkanoid:inst\|Add5~22 47 COMB LAB_X27_Y14 1 " "Info: 47: + IC(0.000 ns) + CELL(0.458 ns) = 13.135 ns; Loc. = LAB_X27_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|Add5~22'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|Add5~21 Arkanoid:inst|Add5~22 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.739 ns) + CELL(0.521 ns) 14.395 ns Arkanoid:inst\|platform2_position~64 48 COMB LAB_X26_Y12 5 " "Info: 48: + IC(0.739 ns) + CELL(0.521 ns) = 14.395 ns; Loc. = LAB_X26_Y12; Fanout = 5; COMB Node = 'Arkanoid:inst\|platform2_position~64'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.260 ns" { Arkanoid:inst|Add5~22 Arkanoid:inst|platform2_position~64 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.439 ns) + CELL(0.517 ns) 16.351 ns Arkanoid:inst\|Add7~23 49 COMB LAB_X27_Y18 2 " "Info: 49: + IC(1.439 ns) + CELL(0.517 ns) = 16.351 ns; Loc. = LAB_X27_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add7~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.956 ns" { Arkanoid:inst|platform2_position~64 Arkanoid:inst|Add7~23 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 16.809 ns Arkanoid:inst\|Add7~24 50 COMB LAB_X27_Y18 2 " "Info: 50: + IC(0.000 ns) + CELL(0.458 ns) = 16.809 ns; Loc. = LAB_X27_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add7~24'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|Add7~23 Arkanoid:inst|Add7~24 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.709 ns) + CELL(0.517 ns) 18.035 ns Arkanoid:inst\|LessThan139~25 51 COMB LAB_X26_Y18 1 " "Info: 51: + IC(0.709 ns) + CELL(0.517 ns) = 18.035 ns; Loc. = LAB_X26_Y18; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.226 ns" { Arkanoid:inst|Add7~24 Arkanoid:inst|LessThan139~25 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.115 ns Arkanoid:inst\|LessThan139~27 52 COMB LAB_X26_Y18 1 " "Info: 52: + IC(0.000 ns) + CELL(0.080 ns) = 18.115 ns; Loc. = LAB_X26_Y18; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~25 Arkanoid:inst|LessThan139~27 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.195 ns Arkanoid:inst\|LessThan139~29 53 COMB LAB_X26_Y18 1 " "Info: 53: + IC(0.000 ns) + CELL(0.080 ns) = 18.195 ns; Loc. = LAB_X26_Y18; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~27 Arkanoid:inst|LessThan139~29 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.275 ns Arkanoid:inst\|LessThan139~31 54 COMB LAB_X26_Y18 1 " "Info: 54: + IC(0.000 ns) + CELL(0.080 ns) = 18.275 ns; Loc. = LAB_X26_Y18; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~29 Arkanoid:inst|LessThan139~31 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.098 ns) + CELL(0.080 ns) 18.453 ns Arkanoid:inst\|LessThan139~33 55 COMB LAB_X26_Y17 1 " "Info: 55: + IC(0.098 ns) + CELL(0.080 ns) = 18.453 ns; Loc. = LAB_X26_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { Arkanoid:inst|LessThan139~31 Arkanoid:inst|LessThan139~33 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.533 ns Arkanoid:inst\|LessThan139~35 56 COMB LAB_X26_Y17 1 " "Info: 56: + IC(0.000 ns) + CELL(0.080 ns) = 18.533 ns; Loc. = LAB_X26_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~33 Arkanoid:inst|LessThan139~35 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.613 ns Arkanoid:inst\|LessThan139~37 57 COMB LAB_X26_Y17 1 " "Info: 57: + IC(0.000 ns) + CELL(0.080 ns) = 18.613 ns; Loc. = LAB_X26_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~35 Arkanoid:inst|LessThan139~37 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.693 ns Arkanoid:inst\|LessThan139~39 58 COMB LAB_X26_Y17 1 " "Info: 58: + IC(0.000 ns) + CELL(0.080 ns) = 18.693 ns; Loc. = LAB_X26_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~37 Arkanoid:inst|LessThan139~39 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.773 ns Arkanoid:inst\|LessThan139~41 59 COMB LAB_X26_Y17 1 " "Info: 59: + IC(0.000 ns) + CELL(0.080 ns) = 18.773 ns; Loc. = LAB_X26_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~39 Arkanoid:inst|LessThan139~41 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.853 ns Arkanoid:inst\|LessThan139~43 60 COMB LAB_X26_Y17 1 " "Info: 60: + IC(0.000 ns) + CELL(0.080 ns) = 18.853 ns; Loc. = LAB_X26_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~41 Arkanoid:inst|LessThan139~43 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.933 ns Arkanoid:inst\|LessThan139~45 61 COMB LAB_X26_Y17 1 " "Info: 61: + IC(0.000 ns) + CELL(0.080 ns) = 18.933 ns; Loc. = LAB_X26_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~43 Arkanoid:inst|LessThan139~45 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.013 ns Arkanoid:inst\|LessThan139~47 62 COMB LAB_X26_Y17 1 " "Info: 62: + IC(0.000 ns) + CELL(0.080 ns) = 19.013 ns; Loc. = LAB_X26_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~45 Arkanoid:inst|LessThan139~47 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.093 ns Arkanoid:inst\|LessThan139~49 63 COMB LAB_X26_Y17 1 " "Info: 63: + IC(0.000 ns) + CELL(0.080 ns) = 19.093 ns; Loc. = LAB_X26_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~47 Arkanoid:inst|LessThan139~49 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.173 ns Arkanoid:inst\|LessThan139~51 64 COMB LAB_X26_Y17 1 " "Info: 64: + IC(0.000 ns) + CELL(0.080 ns) = 19.173 ns; Loc. = LAB_X26_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~51'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~49 Arkanoid:inst|LessThan139~51 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.253 ns Arkanoid:inst\|LessThan139~53 65 COMB LAB_X26_Y17 1 " "Info: 65: + IC(0.000 ns) + CELL(0.080 ns) = 19.253 ns; Loc. = LAB_X26_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~53'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~51 Arkanoid:inst|LessThan139~53 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.333 ns Arkanoid:inst\|LessThan139~55 66 COMB LAB_X26_Y17 1 " "Info: 66: + IC(0.000 ns) + CELL(0.080 ns) = 19.333 ns; Loc. = LAB_X26_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~55'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~53 Arkanoid:inst|LessThan139~55 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.413 ns Arkanoid:inst\|LessThan139~57 67 COMB LAB_X26_Y17 1 " "Info: 67: + IC(0.000 ns) + CELL(0.080 ns) = 19.413 ns; Loc. = LAB_X26_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~57'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~55 Arkanoid:inst|LessThan139~57 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.493 ns Arkanoid:inst\|LessThan139~59 68 COMB LAB_X26_Y17 1 " "Info: 68: + IC(0.000 ns) + CELL(0.080 ns) = 19.493 ns; Loc. = LAB_X26_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~59'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~57 Arkanoid:inst|LessThan139~59 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.573 ns Arkanoid:inst\|LessThan139~61 69 COMB LAB_X26_Y17 1 " "Info: 69: + IC(0.000 ns) + CELL(0.080 ns) = 19.573 ns; Loc. = LAB_X26_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~61'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~59 Arkanoid:inst|LessThan139~61 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 20.031 ns Arkanoid:inst\|LessThan139~62 70 COMB LAB_X26_Y17 3 " "Info: 70: + IC(0.000 ns) + CELL(0.458 ns) = 20.031 ns; Loc. = LAB_X26_Y17; Fanout = 3; COMB Node = 'Arkanoid:inst\|LessThan139~62'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|LessThan139~61 Arkanoid:inst|LessThan139~62 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.411 ns) + CELL(0.521 ns) 20.963 ns Arkanoid:inst\|always2~4 71 COMB LAB_X25_Y17 2 " "Info: 71: + IC(0.411 ns) + CELL(0.521 ns) = 20.963 ns; Loc. = LAB_X25_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|always2~4'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.932 ns" { Arkanoid:inst|LessThan139~62 Arkanoid:inst|always2~4 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.977 ns) + CELL(0.495 ns) 23.435 ns Arkanoid:inst\|Add9~1 72 COMB LAB_X12_Y20 2 " "Info: 72: + IC(1.977 ns) + CELL(0.495 ns) = 23.435 ns; Loc. = LAB_X12_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.472 ns" { Arkanoid:inst|always2~4 Arkanoid:inst|Add9~1 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.515 ns Arkanoid:inst\|Add9~3 73 COMB LAB_X12_Y20 2 " "Info: 73: + IC(0.000 ns) + CELL(0.080 ns) = 23.515 ns; Loc. = LAB_X12_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~1 Arkanoid:inst|Add9~3 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.595 ns Arkanoid:inst\|Add9~5 74 COMB LAB_X12_Y20 2 " "Info: 74: + IC(0.000 ns) + CELL(0.080 ns) = 23.595 ns; Loc. = LAB_X12_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~3 Arkanoid:inst|Add9~5 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.675 ns Arkanoid:inst\|Add9~7 75 COMB LAB_X12_Y20 2 " "Info: 75: + IC(0.000 ns) + CELL(0.080 ns) = 23.675 ns; Loc. = LAB_X12_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~5 Arkanoid:inst|Add9~7 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.755 ns Arkanoid:inst\|Add9~9 76 COMB LAB_X12_Y20 2 " "Info: 76: + IC(0.000 ns) + CELL(0.080 ns) = 23.755 ns; Loc. = LAB_X12_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~7 Arkanoid:inst|Add9~9 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.835 ns Arkanoid:inst\|Add9~11 77 COMB LAB_X12_Y20 2 " "Info: 77: + IC(0.000 ns) + CELL(0.080 ns) = 23.835 ns; Loc. = LAB_X12_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~9 Arkanoid:inst|Add9~11 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.915 ns Arkanoid:inst\|Add9~13 78 COMB LAB_X12_Y20 2 " "Info: 78: + IC(0.000 ns) + CELL(0.080 ns) = 23.915 ns; Loc. = LAB_X12_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~11 Arkanoid:inst|Add9~13 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.995 ns Arkanoid:inst\|Add9~15 79 COMB LAB_X12_Y20 2 " "Info: 79: + IC(0.000 ns) + CELL(0.080 ns) = 23.995 ns; Loc. = LAB_X12_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~13 Arkanoid:inst|Add9~15 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.075 ns Arkanoid:inst\|Add9~17 80 COMB LAB_X12_Y20 2 " "Info: 80: + IC(0.000 ns) + CELL(0.080 ns) = 24.075 ns; Loc. = LAB_X12_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~15 Arkanoid:inst|Add9~17 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.155 ns Arkanoid:inst\|Add9~19 81 COMB LAB_X12_Y20 2 " "Info: 81: + IC(0.000 ns) + CELL(0.080 ns) = 24.155 ns; Loc. = LAB_X12_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~17 Arkanoid:inst|Add9~19 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.235 ns Arkanoid:inst\|Add9~21 82 COMB LAB_X12_Y20 2 " "Info: 82: + IC(0.000 ns) + CELL(0.080 ns) = 24.235 ns; Loc. = LAB_X12_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~19 Arkanoid:inst|Add9~21 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.315 ns Arkanoid:inst\|Add9~23 83 COMB LAB_X12_Y20 2 " "Info: 83: + IC(0.000 ns) + CELL(0.080 ns) = 24.315 ns; Loc. = LAB_X12_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~21 Arkanoid:inst|Add9~23 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.395 ns Arkanoid:inst\|Add9~25 84 COMB LAB_X12_Y20 2 " "Info: 84: + IC(0.000 ns) + CELL(0.080 ns) = 24.395 ns; Loc. = LAB_X12_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~23 Arkanoid:inst|Add9~25 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.475 ns Arkanoid:inst\|Add9~27 85 COMB LAB_X12_Y20 2 " "Info: 85: + IC(0.000 ns) + CELL(0.080 ns) = 24.475 ns; Loc. = LAB_X12_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~25 Arkanoid:inst|Add9~27 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.555 ns Arkanoid:inst\|Add9~29 86 COMB LAB_X12_Y20 2 " "Info: 86: + IC(0.000 ns) + CELL(0.080 ns) = 24.555 ns; Loc. = LAB_X12_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~27 Arkanoid:inst|Add9~29 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.635 ns Arkanoid:inst\|Add9~31 87 COMB LAB_X12_Y20 2 " "Info: 87: + IC(0.000 ns) + CELL(0.080 ns) = 24.635 ns; Loc. = LAB_X12_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~29 Arkanoid:inst|Add9~31 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.098 ns) + CELL(0.080 ns) 24.813 ns Arkanoid:inst\|Add9~33 88 COMB LAB_X12_Y19 2 " "Info: 88: + IC(0.098 ns) + CELL(0.080 ns) = 24.813 ns; Loc. = LAB_X12_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { Arkanoid:inst|Add9~31 Arkanoid:inst|Add9~33 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.893 ns Arkanoid:inst\|Add9~35 89 COMB LAB_X12_Y19 2 " "Info: 89: + IC(0.000 ns) + CELL(0.080 ns) = 24.893 ns; Loc. = LAB_X12_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~33 Arkanoid:inst|Add9~35 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.973 ns Arkanoid:inst\|Add9~37 90 COMB LAB_X12_Y19 2 " "Info: 90: + IC(0.000 ns) + CELL(0.080 ns) = 24.973 ns; Loc. = LAB_X12_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~35 Arkanoid:inst|Add9~37 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.053 ns Arkanoid:inst\|Add9~39 91 COMB LAB_X12_Y19 2 " "Info: 91: + IC(0.000 ns) + CELL(0.080 ns) = 25.053 ns; Loc. = LAB_X12_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~37 Arkanoid:inst|Add9~39 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.133 ns Arkanoid:inst\|Add9~41 92 COMB LAB_X12_Y19 2 " "Info: 92: + IC(0.000 ns) + CELL(0.080 ns) = 25.133 ns; Loc. = LAB_X12_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~39 Arkanoid:inst|Add9~41 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.213 ns Arkanoid:inst\|Add9~43 93 COMB LAB_X12_Y19 2 " "Info: 93: + IC(0.000 ns) + CELL(0.080 ns) = 25.213 ns; Loc. = LAB_X12_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~41 Arkanoid:inst|Add9~43 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.293 ns Arkanoid:inst\|Add9~45 94 COMB LAB_X12_Y19 2 " "Info: 94: + IC(0.000 ns) + CELL(0.080 ns) = 25.293 ns; Loc. = LAB_X12_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~43 Arkanoid:inst|Add9~45 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.373 ns Arkanoid:inst\|Add9~47 95 COMB LAB_X12_Y19 2 " "Info: 95: + IC(0.000 ns) + CELL(0.080 ns) = 25.373 ns; Loc. = LAB_X12_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~45 Arkanoid:inst|Add9~47 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.453 ns Arkanoid:inst\|Add9~49 96 COMB LAB_X12_Y19 2 " "Info: 96: + IC(0.000 ns) + CELL(0.080 ns) = 25.453 ns; Loc. = LAB_X12_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~47 Arkanoid:inst|Add9~49 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.533 ns Arkanoid:inst\|Add9~51 97 COMB LAB_X12_Y19 2 " "Info: 97: + IC(0.000 ns) + CELL(0.080 ns) = 25.533 ns; Loc. = LAB_X12_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~51'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~49 Arkanoid:inst|Add9~51 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.613 ns Arkanoid:inst\|Add9~53 98 COMB LAB_X12_Y19 2 " "Info: 98: + IC(0.000 ns) + CELL(0.080 ns) = 25.613 ns; Loc. = LAB_X12_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~53'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~51 Arkanoid:inst|Add9~53 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.693 ns Arkanoid:inst\|Add9~55 99 COMB LAB_X12_Y19 2 " "Info: 99: + IC(0.000 ns) + CELL(0.080 ns) = 25.693 ns; Loc. = LAB_X12_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~55'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~53 Arkanoid:inst|Add9~55 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.773 ns Arkanoid:inst\|Add9~57 100 COMB LAB_X12_Y19 2 " "Info: 100: + IC(0.000 ns) + CELL(0.080 ns) = 25.773 ns; Loc. = LAB_X12_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~57'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~55 Arkanoid:inst|Add9~57 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.853 ns Arkanoid:inst\|Add9~59 101 COMB LAB_X12_Y19 2 " "Info: 101: + IC(0.000 ns) + CELL(0.080 ns) = 25.853 ns; Loc. = LAB_X12_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~59'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~57 Arkanoid:inst|Add9~59 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.933 ns Arkanoid:inst\|Add9~61 102 COMB LAB_X12_Y19 1 " "Info: 102: + IC(0.000 ns) + CELL(0.080 ns) = 25.933 ns; Loc. = LAB_X12_Y19; Fanout = 1; COMB Node = 'Arkanoid:inst\|Add9~61'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~59 Arkanoid:inst|Add9~61 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 26.391 ns Arkanoid:inst\|Add9~63 103 COMB LAB_X12_Y19 3 " "Info: 103: + IC(0.000 ns) + CELL(0.458 ns) = 26.391 ns; Loc. = LAB_X12_Y19; Fanout = 3; COMB Node = 'Arkanoid:inst\|Add9~63'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|Add9~61 Arkanoid:inst|Add9~63 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.937 ns) + CELL(0.521 ns) 28.849 ns Arkanoid:inst\|lpm_divide:Mod0\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[0\]~0 104 COMB LAB_X42_Y17 4 " "Info: 104: + IC(1.937 ns) + CELL(0.521 ns) = 28.849 ns; Loc. = LAB_X42_Y17; Fanout = 4; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod0\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[0\]~0'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.458 ns" { Arkanoid:inst|Add9~63 Arkanoid:inst|lpm_divide:Mod0|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[0]~0 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.987 ns) + CELL(0.495 ns) 31.331 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~1 105 COMB LAB_X14_Y20 2 " "Info: 105: + IC(1.987 ns) + CELL(0.495 ns) = 31.331 ns; Loc. = LAB_X14_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.482 ns" { Arkanoid:inst|lpm_divide:Mod0|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[0]~0 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~1 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.411 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~3 106 COMB LAB_X14_Y20 2 " "Info: 106: + IC(0.000 ns) + CELL(0.080 ns) = 31.411 ns; Loc. = LAB_X14_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.491 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~5 107 COMB LAB_X14_Y20 2 " "Info: 107: + IC(0.000 ns) + CELL(0.080 ns) = 31.491 ns; Loc. = LAB_X14_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.571 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~7 108 COMB LAB_X14_Y20 2 " "Info: 108: + IC(0.000 ns) + CELL(0.080 ns) = 31.571 ns; Loc. = LAB_X14_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.651 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~9 109 COMB LAB_X14_Y20 2 " "Info: 109: + IC(0.000 ns) + CELL(0.080 ns) = 31.651 ns; Loc. = LAB_X14_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.731 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~11 110 COMB LAB_X14_Y20 2 " "Info: 110: + IC(0.000 ns) + CELL(0.080 ns) = 31.731 ns; Loc. = LAB_X14_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.811 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~13 111 COMB LAB_X14_Y20 2 " "Info: 111: + IC(0.000 ns) + CELL(0.080 ns) = 31.811 ns; Loc. = LAB_X14_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.891 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~15 112 COMB LAB_X14_Y20 2 " "Info: 112: + IC(0.000 ns) + CELL(0.080 ns) = 31.891 ns; Loc. = LAB_X14_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.971 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~17 113 COMB LAB_X14_Y20 2 " "Info: 113: + IC(0.000 ns) + CELL(0.080 ns) = 31.971 ns; Loc. = LAB_X14_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.051 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~19 114 COMB LAB_X14_Y20 2 " "Info: 114: + IC(0.000 ns) + CELL(0.080 ns) = 32.051 ns; Loc. = LAB_X14_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.131 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~21 115 COMB LAB_X14_Y20 2 " "Info: 115: + IC(0.000 ns) + CELL(0.080 ns) = 32.131 ns; Loc. = LAB_X14_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.211 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~23 116 COMB LAB_X14_Y20 2 " "Info: 116: + IC(0.000 ns) + CELL(0.080 ns) = 32.211 ns; Loc. = LAB_X14_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.291 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~25 117 COMB LAB_X14_Y20 2 " "Info: 117: + IC(0.000 ns) + CELL(0.080 ns) = 32.291 ns; Loc. = LAB_X14_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.371 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~27 118 COMB LAB_X14_Y20 2 " "Info: 118: + IC(0.000 ns) + CELL(0.080 ns) = 32.371 ns; Loc. = LAB_X14_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.451 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~29 119 COMB LAB_X14_Y20 2 " "Info: 119: + IC(0.000 ns) + CELL(0.080 ns) = 32.451 ns; Loc. = LAB_X14_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.098 ns) + CELL(0.080 ns) 32.629 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~31 120 COMB LAB_X14_Y19 2 " "Info: 120: + IC(0.098 ns) + CELL(0.080 ns) = 32.629 ns; Loc. = LAB_X14_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.709 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~33 121 COMB LAB_X14_Y19 2 " "Info: 121: + IC(0.000 ns) + CELL(0.080 ns) = 32.709 ns; Loc. = LAB_X14_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.789 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~35 122 COMB LAB_X14_Y19 2 " "Info: 122: + IC(0.000 ns) + CELL(0.080 ns) = 32.789 ns; Loc. = LAB_X14_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.869 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~37 123 COMB LAB_X14_Y19 2 " "Info: 123: + IC(0.000 ns) + CELL(0.080 ns) = 32.869 ns; Loc. = LAB_X14_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.949 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~39 124 COMB LAB_X14_Y19 2 " "Info: 124: + IC(0.000 ns) + CELL(0.080 ns) = 32.949 ns; Loc. = LAB_X14_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 33.029 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~41 125 COMB LAB_X14_Y19 2 " "Info: 125: + IC(0.000 ns) + CELL(0.080 ns) = 33.029 ns; Loc. = LAB_X14_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 33.109 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~43 126 COMB LAB_X14_Y19 2 " "Info: 126: + IC(0.000 ns) + CELL(0.080 ns) = 33.109 ns; Loc. = LAB_X14_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 33.189 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~45 127 COMB LAB_X14_Y19 2 " "Info: 127: + IC(0.000 ns) + CELL(0.080 ns) = 33.189 ns; Loc. = LAB_X14_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 33.269 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~47 128 COMB LAB_X14_Y19 2 " "Info: 128: + IC(0.000 ns) + CELL(0.080 ns) = 33.269 ns; Loc. = LAB_X14_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 33.349 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~49 129 COMB LAB_X14_Y19 2 " "Info: 129: + IC(0.000 ns) + CELL(0.080 ns) = 33.349 ns; Loc. = LAB_X14_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 33.429 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~51 130 COMB LAB_X14_Y19 2 " "Info: 130: + IC(0.000 ns) + CELL(0.080 ns) = 33.429 ns; Loc. = LAB_X14_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~51'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 33.509 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~53 131 COMB LAB_X14_Y19 2 " "Info: 131: + IC(0.000 ns) + CELL(0.080 ns) = 33.509 ns; Loc. = LAB_X14_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~53'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 33.589 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~55 132 COMB LAB_X14_Y19 2 " "Info: 132: + IC(0.000 ns) + CELL(0.080 ns) = 33.589 ns; Loc. = LAB_X14_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~55'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 34.047 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~56 133 COMB LAB_X14_Y19 4 " "Info: 133: + IC(0.000 ns) + CELL(0.458 ns) = 34.047 ns; Loc. = LAB_X14_Y19; Fanout = 4; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~56'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~56 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.388 ns) + CELL(0.517 ns) 35.952 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[1\]~1 134 COMB LAB_X18_Y15 2 " "Info: 134: + IC(1.388 ns) + CELL(0.517 ns) = 35.952 ns; Loc. = LAB_X18_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.905 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~56 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 141 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 36.032 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[2\]~3 135 COMB LAB_X18_Y15 2 " "Info: 135: + IC(0.000 ns) + CELL(0.080 ns) = 36.032 ns; Loc. = LAB_X18_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 141 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 36.112 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[3\]~5 136 COMB LAB_X18_Y15 1 " "Info: 136: + IC(0.000 ns) + CELL(0.080 ns) = 36.112 ns; Loc. = LAB_X18_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 141 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 36.570 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[4\]~6 137 COMB LAB_X18_Y15 14 " "Info: 137: + IC(0.000 ns) + CELL(0.458 ns) = 36.570 ns; Loc. = LAB_X18_Y15; Fanout = 14; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[4\]~6'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 141 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.177 ns) 37.479 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[18\]~111 138 COMB LAB_X19_Y15 2 " "Info: 138: + IC(0.732 ns) + CELL(0.177 ns) = 37.479 ns; Loc. = LAB_X19_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[18\]~111'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[18]~111 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.495 ns) 38.472 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[1\]~1 139 COMB LAB_X19_Y15 2 " "Info: 139: + IC(0.498 ns) + CELL(0.495 ns) = 38.472 ns; Loc. = LAB_X19_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.993 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[18]~111 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 38.552 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[2\]~3 140 COMB LAB_X19_Y15 2 " "Info: 140: + IC(0.000 ns) + CELL(0.080 ns) = 38.552 ns; Loc. = LAB_X19_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 38.632 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[3\]~5 141 COMB LAB_X19_Y15 2 " "Info: 141: + IC(0.000 ns) + CELL(0.080 ns) = 38.632 ns; Loc. = LAB_X19_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 38.712 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[4\]~7 142 COMB LAB_X19_Y15 1 " "Info: 142: + IC(0.000 ns) + CELL(0.080 ns) = 38.712 ns; Loc. = LAB_X19_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 39.170 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[5\]~8 143 COMB LAB_X19_Y15 17 " "Info: 143: + IC(0.000 ns) + CELL(0.458 ns) = 39.170 ns; Loc. = LAB_X19_Y15; Fanout = 17; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[5\]~8'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.177 ns) 40.420 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[24\]~121 144 COMB LAB_X19_Y16 2 " "Info: 144: + IC(1.073 ns) + CELL(0.177 ns) = 40.420 ns; Loc. = LAB_X19_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[24\]~121'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.250 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[24]~121 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.495 ns) 41.988 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[1\]~1 145 COMB LAB_X19_Y15 2 " "Info: 145: + IC(1.073 ns) + CELL(0.495 ns) = 41.988 ns; Loc. = LAB_X19_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.568 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[24]~121 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 42.068 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[2\]~3 146 COMB LAB_X19_Y15 2 " "Info: 146: + IC(0.000 ns) + CELL(0.080 ns) = 42.068 ns; Loc. = LAB_X19_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 42.148 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[3\]~5 147 COMB LAB_X19_Y15 2 " "Info: 147: + IC(0.000 ns) + CELL(0.080 ns) = 42.148 ns; Loc. = LAB_X19_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 42.228 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[4\]~7 148 COMB LAB_X19_Y15 1 " "Info: 148: + IC(0.000 ns) + CELL(0.080 ns) = 42.228 ns; Loc. = LAB_X19_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 42.308 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[5\]~9 149 COMB LAB_X19_Y15 1 " "Info: 149: + IC(0.000 ns) + CELL(0.080 ns) = 42.308 ns; Loc. = LAB_X19_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 42.766 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[6\]~10 150 COMB LAB_X19_Y15 16 " "Info: 150: + IC(0.000 ns) + CELL(0.458 ns) = 42.766 ns; Loc. = LAB_X19_Y15; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.177 ns) 44.016 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[30\]~129 151 COMB LAB_X18_Y16 2 " "Info: 151: + IC(1.073 ns) + CELL(0.177 ns) = 44.016 ns; Loc. = LAB_X18_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[30\]~129'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.250 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[30]~129 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.495 ns) 45.243 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[1\]~1 152 COMB LAB_X19_Y16 2 " "Info: 152: + IC(0.732 ns) + CELL(0.495 ns) = 45.243 ns; Loc. = LAB_X19_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.227 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[30]~129 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 45.323 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[2\]~3 153 COMB LAB_X19_Y16 2 " "Info: 153: + IC(0.000 ns) + CELL(0.080 ns) = 45.323 ns; Loc. = LAB_X19_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 45.403 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[3\]~5 154 COMB LAB_X19_Y16 2 " "Info: 154: + IC(0.000 ns) + CELL(0.080 ns) = 45.403 ns; Loc. = LAB_X19_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 45.483 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[4\]~7 155 COMB LAB_X19_Y16 1 " "Info: 155: + IC(0.000 ns) + CELL(0.080 ns) = 45.483 ns; Loc. = LAB_X19_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 45.563 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[5\]~9 156 COMB LAB_X19_Y16 1 " "Info: 156: + IC(0.000 ns) + CELL(0.080 ns) = 45.563 ns; Loc. = LAB_X19_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 46.021 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[6\]~10 157 COMB LAB_X19_Y16 16 " "Info: 157: + IC(0.000 ns) + CELL(0.458 ns) = 46.021 ns; Loc. = LAB_X19_Y16; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.966 ns) + CELL(0.177 ns) 48.164 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[36\]~137 158 COMB LAB_X36_Y13 2 " "Info: 158: + IC(1.966 ns) + CELL(0.177 ns) = 48.164 ns; Loc. = LAB_X36_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[36\]~137'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.143 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~137 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.967 ns) + CELL(0.495 ns) 50.626 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[1\]~1 159 COMB LAB_X18_Y16 2 " "Info: 159: + IC(1.967 ns) + CELL(0.495 ns) = 50.626 ns; Loc. = LAB_X18_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.462 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~137 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 50.706 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[2\]~3 160 COMB LAB_X18_Y16 2 " "Info: 160: + IC(0.000 ns) + CELL(0.080 ns) = 50.706 ns; Loc. = LAB_X18_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 50.786 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[3\]~5 161 COMB LAB_X18_Y16 2 " "Info: 161: + IC(0.000 ns) + CELL(0.080 ns) = 50.786 ns; Loc. = LAB_X18_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 50.866 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[4\]~7 162 COMB LAB_X18_Y16 1 " "Info: 162: + IC(0.000 ns) + CELL(0.080 ns) = 50.866 ns; Loc. = LAB_X18_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 50.946 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[5\]~9 163 COMB LAB_X18_Y16 1 " "Info: 163: + IC(0.000 ns) + CELL(0.080 ns) = 50.946 ns; Loc. = LAB_X18_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 51.404 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[6\]~10 164 COMB LAB_X18_Y16 16 " "Info: 164: + IC(0.000 ns) + CELL(0.458 ns) = 51.404 ns; Loc. = LAB_X18_Y16; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.965 ns) + CELL(0.177 ns) 53.546 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[42\]~145 165 COMB LAB_X35_Y13 2 " "Info: 165: + IC(1.965 ns) + CELL(0.177 ns) = 53.546 ns; Loc. = LAB_X35_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[42\]~145'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.142 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[42]~145 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.495 ns) 54.773 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[1\]~1 166 COMB LAB_X36_Y13 2 " "Info: 166: + IC(0.732 ns) + CELL(0.495 ns) = 54.773 ns; Loc. = LAB_X36_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.227 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[42]~145 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 54.853 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[2\]~3 167 COMB LAB_X36_Y13 2 " "Info: 167: + IC(0.000 ns) + CELL(0.080 ns) = 54.853 ns; Loc. = LAB_X36_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 54.933 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[3\]~5 168 COMB LAB_X36_Y13 2 " "Info: 168: + IC(0.000 ns) + CELL(0.080 ns) = 54.933 ns; Loc. = LAB_X36_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 55.013 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[4\]~7 169 COMB LAB_X36_Y13 1 " "Info: 169: + IC(0.000 ns) + CELL(0.080 ns) = 55.013 ns; Loc. = LAB_X36_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 55.093 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[5\]~9 170 COMB LAB_X36_Y13 1 " "Info: 170: + IC(0.000 ns) + CELL(0.080 ns) = 55.093 ns; Loc. = LAB_X36_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 55.551 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[6\]~10 171 COMB LAB_X36_Y13 16 " "Info: 171: + IC(0.000 ns) + CELL(0.458 ns) = 55.551 ns; Loc. = LAB_X36_Y13; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.823 ns) + CELL(0.319 ns) 57.693 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[51\]~337 172 COMB LAB_X18_Y16 3 " "Info: 172: + IC(1.823 ns) + CELL(0.319 ns) = 57.693 ns; Loc. = LAB_X18_Y16; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[51\]~337'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.142 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[51]~337 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.942 ns) + CELL(0.517 ns) 60.152 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[4\]~7 173 COMB LAB_X35_Y13 1 " "Info: 173: + IC(1.942 ns) + CELL(0.517 ns) = 60.152 ns; Loc. = LAB_X35_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.459 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[51]~337 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 60.232 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[5\]~9 174 COMB LAB_X35_Y13 1 " "Info: 174: + IC(0.000 ns) + CELL(0.080 ns) = 60.232 ns; Loc. = LAB_X35_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 60.690 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[6\]~10 175 COMB LAB_X35_Y13 16 " "Info: 175: + IC(0.000 ns) + CELL(0.458 ns) = 60.690 ns; Loc. = LAB_X35_Y13; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.521 ns) 61.940 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[55\]~158 176 COMB LAB_X34_Y14 2 " "Info: 176: + IC(0.729 ns) + CELL(0.521 ns) = 61.940 ns; Loc. = LAB_X34_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[55\]~158'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.250 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[55]~158 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.015 ns) + CELL(0.517 ns) 63.472 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[2\]~3 177 COMB LAB_X36_Y14 2 " "Info: 177: + IC(1.015 ns) + CELL(0.517 ns) = 63.472 ns; Loc. = LAB_X36_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.532 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[55]~158 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 36 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 63.552 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[3\]~5 178 COMB LAB_X36_Y14 2 " "Info: 178: + IC(0.000 ns) + CELL(0.080 ns) = 63.552 ns; Loc. = LAB_X36_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 36 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 63.632 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[4\]~7 179 COMB LAB_X36_Y14 1 " "Info: 179: + IC(0.000 ns) + CELL(0.080 ns) = 63.632 ns; Loc. = LAB_X36_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 36 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 63.712 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[5\]~9 180 COMB LAB_X36_Y14 1 " "Info: 180: + IC(0.000 ns) + CELL(0.080 ns) = 63.712 ns; Loc. = LAB_X36_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 36 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 64.170 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[6\]~10 181 COMB LAB_X36_Y14 16 " "Info: 181: + IC(0.000 ns) + CELL(0.458 ns) = 64.170 ns; Loc. = LAB_X36_Y14; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 36 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.319 ns) 65.418 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[63\]~341 182 COMB LAB_X35_Y13 3 " "Info: 182: + IC(0.929 ns) + CELL(0.319 ns) = 65.418 ns; Loc. = LAB_X35_Y13; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[63\]~341'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.248 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[63]~341 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.050 ns) + CELL(0.517 ns) 66.985 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[4\]~7 183 COMB LAB_X34_Y14 1 " "Info: 183: + IC(1.050 ns) + CELL(0.517 ns) = 66.985 ns; Loc. = LAB_X34_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.567 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[63]~341 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 67.065 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[5\]~9 184 COMB LAB_X34_Y14 1 " "Info: 184: + IC(0.000 ns) + CELL(0.080 ns) = 67.065 ns; Loc. = LAB_X34_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 67.523 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[6\]~10 185 COMB LAB_X34_Y14 16 " "Info: 185: + IC(0.000 ns) + CELL(0.458 ns) = 67.523 ns; Loc. = LAB_X34_Y14; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.397 ns) + CELL(0.177 ns) 69.097 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[66\]~177 186 COMB LAB_X36_Y18 2 " "Info: 186: + IC(1.397 ns) + CELL(0.177 ns) = 69.097 ns; Loc. = LAB_X36_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[66\]~177'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.574 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[66]~177 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.495 ns) 70.681 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[1\]~1 187 COMB LAB_X36_Y14 2 " "Info: 187: + IC(1.089 ns) + CELL(0.495 ns) = 70.681 ns; Loc. = LAB_X36_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.584 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[66]~177 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 70.761 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[2\]~3 188 COMB LAB_X36_Y14 2 " "Info: 188: + IC(0.000 ns) + CELL(0.080 ns) = 70.761 ns; Loc. = LAB_X36_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 70.841 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[3\]~5 189 COMB LAB_X36_Y14 2 " "Info: 189: + IC(0.000 ns) + CELL(0.080 ns) = 70.841 ns; Loc. = LAB_X36_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 70.921 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[4\]~7 190 COMB LAB_X36_Y14 1 " "Info: 190: + IC(0.000 ns) + CELL(0.080 ns) = 70.921 ns; Loc. = LAB_X36_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 71.001 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[5\]~9 191 COMB LAB_X36_Y14 1 " "Info: 191: + IC(0.000 ns) + CELL(0.080 ns) = 71.001 ns; Loc. = LAB_X36_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 71.459 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[6\]~10 192 COMB LAB_X36_Y14 16 " "Info: 192: + IC(0.000 ns) + CELL(0.458 ns) = 71.459 ns; Loc. = LAB_X36_Y14; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.894 ns) + CELL(0.319 ns) 72.672 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[76\]~344 193 COMB LAB_X34_Y14 1 " "Info: 193: + IC(0.894 ns) + CELL(0.319 ns) = 72.672 ns; Loc. = LAB_X34_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[76\]~344'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.213 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[76]~344 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.016 ns) + CELL(0.517 ns) 74.205 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[5\]~9 194 COMB LAB_X37_Y14 1 " "Info: 194: + IC(1.016 ns) + CELL(0.517 ns) = 74.205 ns; Loc. = LAB_X37_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.533 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[76]~344 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 51 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 74.663 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[6\]~10 195 COMB LAB_X37_Y14 16 " "Info: 195: + IC(0.000 ns) + CELL(0.458 ns) = 74.663 ns; Loc. = LAB_X37_Y14; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 51 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.177 ns) 75.878 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[82\]~186 196 COMB LAB_X35_Y14 1 " "Info: 196: + IC(1.038 ns) + CELL(0.177 ns) = 75.878 ns; Loc. = LAB_X35_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[82\]~186'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.215 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[82]~186 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.495 ns) 77.462 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[5\]~9 197 COMB LAB_X36_Y18 1 " "Info: 197: + IC(1.089 ns) + CELL(0.495 ns) = 77.462 ns; Loc. = LAB_X36_Y18; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.584 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[82]~186 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 56 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 77.920 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[6\]~10 198 COMB LAB_X36_Y18 16 " "Info: 198: + IC(0.000 ns) + CELL(0.458 ns) = 77.920 ns; Loc. = LAB_X36_Y18; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 56 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.177 ns) 79.186 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[88\]~194 199 COMB LAB_X35_Y14 1 " "Info: 199: + IC(1.089 ns) + CELL(0.177 ns) = 79.186 ns; Loc. = LAB_X35_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[88\]~194'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.266 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[88]~194 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.444 ns) + CELL(0.495 ns) 81.125 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[5\]~9 200 COMB LAB_X36_Y22 1 " "Info: 200: + IC(1.444 ns) + CELL(0.495 ns) = 81.125 ns; Loc. = LAB_X36_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.939 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[88]~194 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 61 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 81.583 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[6\]~10 201 COMB LAB_X36_Y22 16 " "Info: 201: + IC(0.000 ns) + CELL(0.458 ns) = 81.583 ns; Loc. = LAB_X36_Y22; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 61 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.177 ns) 82.492 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[90\]~209 202 COMB LAB_X35_Y22 2 " "Info: 202: + IC(0.732 ns) + CELL(0.177 ns) = 82.492 ns; Loc. = LAB_X35_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[90\]~209'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[90]~209 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.495 ns) 83.485 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[1\]~1 203 COMB LAB_X35_Y22 2 " "Info: 203: + IC(0.498 ns) + CELL(0.495 ns) = 83.485 ns; Loc. = LAB_X35_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.993 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[90]~209 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 83.565 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[2\]~3 204 COMB LAB_X35_Y22 2 " "Info: 204: + IC(0.000 ns) + CELL(0.080 ns) = 83.565 ns; Loc. = LAB_X35_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 83.645 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[3\]~5 205 COMB LAB_X35_Y22 2 " "Info: 205: + IC(0.000 ns) + CELL(0.080 ns) = 83.645 ns; Loc. = LAB_X35_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 83.725 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[4\]~7 206 COMB LAB_X35_Y22 1 " "Info: 206: + IC(0.000 ns) + CELL(0.080 ns) = 83.725 ns; Loc. = LAB_X35_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 83.805 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[5\]~9 207 COMB LAB_X35_Y22 1 " "Info: 207: + IC(0.000 ns) + CELL(0.080 ns) = 83.805 ns; Loc. = LAB_X35_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 84.263 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[6\]~10 208 COMB LAB_X35_Y22 16 " "Info: 208: + IC(0.000 ns) + CELL(0.458 ns) = 84.263 ns; Loc. = LAB_X35_Y22; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.177 ns) 85.513 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[96\]~217 209 COMB LAB_X35_Y23 2 " "Info: 209: + IC(1.073 ns) + CELL(0.177 ns) = 85.513 ns; Loc. = LAB_X35_Y23; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[96\]~217'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.250 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[96]~217 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.495 ns) 86.506 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[1\]~1 210 COMB LAB_X35_Y23 2 " "Info: 210: + IC(0.498 ns) + CELL(0.495 ns) = 86.506 ns; Loc. = LAB_X35_Y23; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.993 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[96]~217 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 86.586 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[2\]~3 211 COMB LAB_X35_Y23 2 " "Info: 211: + IC(0.000 ns) + CELL(0.080 ns) = 86.586 ns; Loc. = LAB_X35_Y23; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 86.666 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[3\]~5 212 COMB LAB_X35_Y23 2 " "Info: 212: + IC(0.000 ns) + CELL(0.080 ns) = 86.666 ns; Loc. = LAB_X35_Y23; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 86.746 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[4\]~7 213 COMB LAB_X35_Y23 1 " "Info: 213: + IC(0.000 ns) + CELL(0.080 ns) = 86.746 ns; Loc. = LAB_X35_Y23; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 86.826 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[5\]~9 214 COMB LAB_X35_Y23 1 " "Info: 214: + IC(0.000 ns) + CELL(0.080 ns) = 86.826 ns; Loc. = LAB_X35_Y23; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 87.284 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[6\]~10 215 COMB LAB_X35_Y23 16 " "Info: 215: + IC(0.000 ns) + CELL(0.458 ns) = 87.284 ns; Loc. = LAB_X35_Y23; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.177 ns) 88.193 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[102\]~225 216 COMB LAB_X34_Y23 2 " "Info: 216: + IC(0.732 ns) + CELL(0.177 ns) = 88.193 ns; Loc. = LAB_X34_Y23; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[102\]~225'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~225 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.495 ns) 89.186 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[1\]~1 217 COMB LAB_X34_Y23 2 " "Info: 217: + IC(0.498 ns) + CELL(0.495 ns) = 89.186 ns; Loc. = LAB_X34_Y23; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.993 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~225 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 89.266 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[2\]~3 218 COMB LAB_X34_Y23 2 " "Info: 218: + IC(0.000 ns) + CELL(0.080 ns) = 89.266 ns; Loc. = LAB_X34_Y23; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 89.346 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[3\]~5 219 COMB LAB_X34_Y23 2 " "Info: 219: + IC(0.000 ns) + CELL(0.080 ns) = 89.346 ns; Loc. = LAB_X34_Y23; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 89.426 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[4\]~7 220 COMB LAB_X34_Y23 1 " "Info: 220: + IC(0.000 ns) + CELL(0.080 ns) = 89.426 ns; Loc. = LAB_X34_Y23; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 89.506 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[5\]~9 221 COMB LAB_X34_Y23 1 " "Info: 221: + IC(0.000 ns) + CELL(0.080 ns) = 89.506 ns; Loc. = LAB_X34_Y23; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 89.964 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[6\]~10 222 COMB LAB_X34_Y23 16 " "Info: 222: + IC(0.000 ns) + CELL(0.458 ns) = 89.964 ns; Loc. = LAB_X34_Y23; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.177 ns) 91.179 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[108\]~233 223 COMB LAB_X32_Y23 2 " "Info: 223: + IC(1.038 ns) + CELL(0.177 ns) = 91.179 ns; Loc. = LAB_X32_Y23; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[108\]~233'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.215 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[108]~233 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.495 ns) 92.172 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[1\]~1 224 COMB LAB_X32_Y23 2 " "Info: 224: + IC(0.498 ns) + CELL(0.495 ns) = 92.172 ns; Loc. = LAB_X32_Y23; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.993 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[108]~233 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 92.252 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[2\]~3 225 COMB LAB_X32_Y23 2 " "Info: 225: + IC(0.000 ns) + CELL(0.080 ns) = 92.252 ns; Loc. = LAB_X32_Y23; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 92.332 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[3\]~5 226 COMB LAB_X32_Y23 2 " "Info: 226: + IC(0.000 ns) + CELL(0.080 ns) = 92.332 ns; Loc. = LAB_X32_Y23; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 92.412 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[4\]~7 227 COMB LAB_X32_Y23 1 " "Info: 227: + IC(0.000 ns) + CELL(0.080 ns) = 92.412 ns; Loc. = LAB_X32_Y23; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 92.492 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[5\]~9 228 COMB LAB_X32_Y23 1 " "Info: 228: + IC(0.000 ns) + CELL(0.080 ns) = 92.492 ns; Loc. = LAB_X32_Y23; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 92.950 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[6\]~10 229 COMB LAB_X32_Y23 16 " "Info: 229: + IC(0.000 ns) + CELL(0.458 ns) = 92.950 ns; Loc. = LAB_X32_Y23; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.177 ns) 93.859 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[118\]~234 230 COMB LAB_X33_Y23 1 " "Info: 230: + IC(0.732 ns) + CELL(0.177 ns) = 93.859 ns; Loc. = LAB_X33_Y23; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[118\]~234'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[118]~234 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.495 ns) 95.392 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[5\]~9 231 COMB LAB_X31_Y23 1 " "Info: 231: + IC(1.038 ns) + CELL(0.495 ns) = 95.392 ns; Loc. = LAB_X31_Y23; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.533 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[118]~234 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 91 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 95.850 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[6\]~10 232 COMB LAB_X31_Y23 16 " "Info: 232: + IC(0.000 ns) + CELL(0.458 ns) = 95.850 ns; Loc. = LAB_X31_Y23; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 91 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.544 ns) 96.759 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[122\]~244 233 COMB LAB_X32_Y23 3 " "Info: 233: + IC(0.365 ns) + CELL(0.544 ns) = 96.759 ns; Loc. = LAB_X32_Y23; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[122\]~244'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~244 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.050 ns) + CELL(0.517 ns) 98.326 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[3\]~5 234 COMB LAB_X31_Y22 2 " "Info: 234: + IC(1.050 ns) + CELL(0.517 ns) = 98.326 ns; Loc. = LAB_X31_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.567 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~244 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 98.406 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[4\]~7 235 COMB LAB_X31_Y22 1 " "Info: 235: + IC(0.000 ns) + CELL(0.080 ns) = 98.406 ns; Loc. = LAB_X31_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 98.486 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[5\]~9 236 COMB LAB_X31_Y22 1 " "Info: 236: + IC(0.000 ns) + CELL(0.080 ns) = 98.486 ns; Loc. = LAB_X31_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 98.944 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[6\]~10 237 COMB LAB_X31_Y22 16 " "Info: 237: + IC(0.000 ns) + CELL(0.458 ns) = 98.944 ns; Loc. = LAB_X31_Y22; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.706 ns) + CELL(0.544 ns) 100.194 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[128\]~252 238 COMB LAB_X31_Y23 3 " "Info: 238: + IC(0.706 ns) + CELL(0.544 ns) = 100.194 ns; Loc. = LAB_X31_Y23; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[128\]~252'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.250 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[128]~252 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.050 ns) + CELL(0.517 ns) 101.761 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[3\]~5 239 COMB LAB_X30_Y22 2 " "Info: 239: + IC(1.050 ns) + CELL(0.517 ns) = 101.761 ns; Loc. = LAB_X30_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.567 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[128]~252 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 101.841 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[4\]~7 240 COMB LAB_X30_Y22 1 " "Info: 240: + IC(0.000 ns) + CELL(0.080 ns) = 101.841 ns; Loc. = LAB_X30_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 101.921 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[5\]~9 241 COMB LAB_X30_Y22 1 " "Info: 241: + IC(0.000 ns) + CELL(0.080 ns) = 101.921 ns; Loc. = LAB_X30_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 102.379 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[6\]~10 242 COMB LAB_X30_Y22 16 " "Info: 242: + IC(0.000 ns) + CELL(0.458 ns) = 102.379 ns; Loc. = LAB_X30_Y22; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.544 ns) 103.288 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[134\]~260 243 COMB LAB_X31_Y22 3 " "Info: 243: + IC(0.365 ns) + CELL(0.544 ns) = 103.288 ns; Loc. = LAB_X31_Y22; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[134\]~260'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[134]~260 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.015 ns) + CELL(0.517 ns) 104.820 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[3\]~5 244 COMB LAB_X29_Y22 2 " "Info: 244: + IC(1.015 ns) + CELL(0.517 ns) = 104.820 ns; Loc. = LAB_X29_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.532 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[134]~260 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 104.900 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[4\]~7 245 COMB LAB_X29_Y22 1 " "Info: 245: + IC(0.000 ns) + CELL(0.080 ns) = 104.900 ns; Loc. = LAB_X29_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 104.980 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[5\]~9 246 COMB LAB_X29_Y22 1 " "Info: 246: + IC(0.000 ns) + CELL(0.080 ns) = 104.980 ns; Loc. = LAB_X29_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 105.438 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[6\]~10 247 COMB LAB_X29_Y22 16 " "Info: 247: + IC(0.000 ns) + CELL(0.458 ns) = 105.438 ns; Loc. = LAB_X29_Y22; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.544 ns) 106.347 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[140\]~268 248 COMB LAB_X30_Y22 3 " "Info: 248: + IC(0.365 ns) + CELL(0.544 ns) = 106.347 ns; Loc. = LAB_X30_Y22; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[140\]~268'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[140]~268 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.061 ns) + CELL(0.517 ns) 107.925 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[3\]~5 249 COMB LAB_X30_Y20 2 " "Info: 249: + IC(1.061 ns) + CELL(0.517 ns) = 107.925 ns; Loc. = LAB_X30_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.578 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[140]~268 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 108.005 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[4\]~7 250 COMB LAB_X30_Y20 1 " "Info: 250: + IC(0.000 ns) + CELL(0.080 ns) = 108.005 ns; Loc. = LAB_X30_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 108.085 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[5\]~9 251 COMB LAB_X30_Y20 1 " "Info: 251: + IC(0.000 ns) + CELL(0.080 ns) = 108.085 ns; Loc. = LAB_X30_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 108.543 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[6\]~10 252 COMB LAB_X30_Y20 16 " "Info: 252: + IC(0.000 ns) + CELL(0.458 ns) = 108.543 ns; Loc. = LAB_X30_Y20; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.717 ns) + CELL(0.544 ns) 109.804 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[146\]~276 253 COMB LAB_X29_Y22 3 " "Info: 253: + IC(0.717 ns) + CELL(0.544 ns) = 109.804 ns; Loc. = LAB_X29_Y22; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[146\]~276'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.261 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~276 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.369 ns) + CELL(0.517 ns) 111.690 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[3\]~5 254 COMB LAB_X31_Y20 2 " "Info: 254: + IC(1.369 ns) + CELL(0.517 ns) = 111.690 ns; Loc. = LAB_X31_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.886 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~276 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 111.770 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[4\]~7 255 COMB LAB_X31_Y20 1 " "Info: 255: + IC(0.000 ns) + CELL(0.080 ns) = 111.770 ns; Loc. = LAB_X31_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 111.850 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[5\]~9 256 COMB LAB_X31_Y20 1 " "Info: 256: + IC(0.000 ns) + CELL(0.080 ns) = 111.850 ns; Loc. = LAB_X31_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 112.308 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[6\]~10 257 COMB LAB_X31_Y20 16 " "Info: 257: + IC(0.000 ns) + CELL(0.458 ns) = 112.308 ns; Loc. = LAB_X31_Y20; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.544 ns) 113.217 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[152\]~284 258 COMB LAB_X30_Y20 3 " "Info: 258: + IC(0.365 ns) + CELL(0.544 ns) = 113.217 ns; Loc. = LAB_X30_Y20; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[152\]~284'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[152]~284 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.015 ns) + CELL(0.517 ns) 114.749 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[3\]~5 259 COMB LAB_X32_Y20 2 " "Info: 259: + IC(1.015 ns) + CELL(0.517 ns) = 114.749 ns; Loc. = LAB_X32_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.532 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[152]~284 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 114.829 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[4\]~7 260 COMB LAB_X32_Y20 1 " "Info: 260: + IC(0.000 ns) + CELL(0.080 ns) = 114.829 ns; Loc. = LAB_X32_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 114.909 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[5\]~9 261 COMB LAB_X32_Y20 1 " "Info: 261: + IC(0.000 ns) + CELL(0.080 ns) = 114.909 ns; Loc. = LAB_X32_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 115.367 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[6\]~10 262 COMB LAB_X32_Y20 16 " "Info: 262: + IC(0.000 ns) + CELL(0.458 ns) = 115.367 ns; Loc. = LAB_X32_Y20; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.544 ns) 116.276 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[158\]~292 263 COMB LAB_X31_Y20 3 " "Info: 263: + IC(0.365 ns) + CELL(0.544 ns) = 116.276 ns; Loc. = LAB_X31_Y20; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[158\]~292'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[158]~292 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.035 ns) + CELL(0.517 ns) 117.828 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[3\]~5 264 COMB LAB_X36_Y20 2 " "Info: 264: + IC(1.035 ns) + CELL(0.517 ns) = 117.828 ns; Loc. = LAB_X36_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.552 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[158]~292 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 117.908 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[4\]~7 265 COMB LAB_X36_Y20 1 " "Info: 265: + IC(0.000 ns) + CELL(0.080 ns) = 117.908 ns; Loc. = LAB_X36_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 117.988 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[5\]~9 266 COMB LAB_X36_Y20 1 " "Info: 266: + IC(0.000 ns) + CELL(0.080 ns) = 117.988 ns; Loc. = LAB_X36_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 118.446 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[6\]~10 267 COMB LAB_X36_Y20 16 " "Info: 267: + IC(0.000 ns) + CELL(0.458 ns) = 118.446 ns; Loc. = LAB_X36_Y20; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.673 ns) + CELL(0.544 ns) 119.663 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[164\]~300 268 COMB LAB_X32_Y20 3 " "Info: 268: + IC(0.673 ns) + CELL(0.544 ns) = 119.663 ns; Loc. = LAB_X32_Y20; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[164\]~300'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.217 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[164]~300 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.035 ns) + CELL(0.517 ns) 121.215 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[3\]~5 269 COMB LAB_X37_Y20 2 " "Info: 269: + IC(1.035 ns) + CELL(0.517 ns) = 121.215 ns; Loc. = LAB_X37_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.552 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[164]~300 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 121.295 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[4\]~7 270 COMB LAB_X37_Y20 1 " "Info: 270: + IC(0.000 ns) + CELL(0.080 ns) = 121.295 ns; Loc. = LAB_X37_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 121.375 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[5\]~9 271 COMB LAB_X37_Y20 1 " "Info: 271: + IC(0.000 ns) + CELL(0.080 ns) = 121.375 ns; Loc. = LAB_X37_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 121.833 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[6\]~10 272 COMB LAB_X37_Y20 16 " "Info: 272: + IC(0.000 ns) + CELL(0.458 ns) = 121.833 ns; Loc. = LAB_X37_Y20; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.544 ns) 122.742 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[170\]~308 273 COMB LAB_X36_Y20 3 " "Info: 273: + IC(0.365 ns) + CELL(0.544 ns) = 122.742 ns; Loc. = LAB_X36_Y20; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[170\]~308'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[170]~308 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.015 ns) + CELL(0.517 ns) 124.274 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[3\]~5 274 COMB LAB_X38_Y20 2 " "Info: 274: + IC(1.015 ns) + CELL(0.517 ns) = 124.274 ns; Loc. = LAB_X38_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.532 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[170]~308 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 124.354 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[4\]~7 275 COMB LAB_X38_Y20 1 " "Info: 275: + IC(0.000 ns) + CELL(0.080 ns) = 124.354 ns; Loc. = LAB_X38_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 124.434 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[5\]~9 276 COMB LAB_X38_Y20 1 " "Info: 276: + IC(0.000 ns) + CELL(0.080 ns) = 124.434 ns; Loc. = LAB_X38_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 124.892 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[6\]~10 277 COMB LAB_X38_Y20 17 " "Info: 277: + IC(0.000 ns) + CELL(0.458 ns) = 124.892 ns; Loc. = LAB_X38_Y20; Fanout = 17; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.375 ns) + CELL(0.544 ns) 125.811 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[176\]~316 278 COMB LAB_X37_Y20 3 " "Info: 278: + IC(0.375 ns) + CELL(0.544 ns) = 125.811 ns; Loc. = LAB_X37_Y20; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[176\]~316'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.919 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~316 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.015 ns) + CELL(0.517 ns) 127.343 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[3\]~5 279 COMB LAB_X39_Y20 2 " "Info: 279: + IC(1.015 ns) + CELL(0.517 ns) = 127.343 ns; Loc. = LAB_X39_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.532 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~316 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 127.423 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[4\]~7 280 COMB LAB_X39_Y20 1 " "Info: 280: + IC(0.000 ns) + CELL(0.080 ns) = 127.423 ns; Loc. = LAB_X39_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 127.503 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[5\]~9 281 COMB LAB_X39_Y20 1 " "Info: 281: + IC(0.000 ns) + CELL(0.080 ns) = 127.503 ns; Loc. = LAB_X39_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 127.961 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[6\]~10 282 COMB LAB_X39_Y20 13 " "Info: 282: + IC(0.000 ns) + CELL(0.458 ns) = 127.961 ns; Loc. = LAB_X39_Y20; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.375 ns) + CELL(0.544 ns) 128.880 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[182\]~324 283 COMB LAB_X38_Y20 1 " "Info: 283: + IC(0.375 ns) + CELL(0.544 ns) = 128.880 ns; Loc. = LAB_X38_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[182\]~324'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.919 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[182]~324 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.024 ns) + CELL(0.517 ns) 130.421 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[3\]~5 284 COMB LAB_X40_Y20 1 " "Info: 284: + IC(1.024 ns) + CELL(0.517 ns) = 130.421 ns; Loc. = LAB_X40_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.541 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[182]~324 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 130.501 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[4\]~7 285 COMB LAB_X40_Y20 1 " "Info: 285: + IC(0.000 ns) + CELL(0.080 ns) = 130.501 ns; Loc. = LAB_X40_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 130.581 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[5\]~9 286 COMB LAB_X40_Y20 1 " "Info: 286: + IC(0.000 ns) + CELL(0.080 ns) = 130.581 ns; Loc. = LAB_X40_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 131.039 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[6\]~10 287 COMB LAB_X40_Y20 3 " "Info: 287: + IC(0.000 ns) + CELL(0.458 ns) = 131.039 ns; Loc. = LAB_X40_Y20; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(0.517 ns) 133.256 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~1 288 COMB LAB_X32_Y22 2 " "Info: 288: + IC(1.700 ns) + CELL(0.517 ns) = 133.256 ns; Loc. = LAB_X32_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.217 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~1 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 133.336 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~3 289 COMB LAB_X32_Y22 2 " "Info: 289: + IC(0.000 ns) + CELL(0.080 ns) = 133.336 ns; Loc. = LAB_X32_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~3 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 133.416 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~5 290 COMB LAB_X32_Y22 2 " "Info: 290: + IC(0.000 ns) + CELL(0.080 ns) = 133.416 ns; Loc. = LAB_X32_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 133.496 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~7 291 COMB LAB_X32_Y22 2 " "Info: 291: + IC(0.000 ns) + CELL(0.080 ns) = 133.496 ns; Loc. = LAB_X32_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~7 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 133.576 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~9 292 COMB LAB_X32_Y22 2 " "Info: 292: + IC(0.000 ns) + CELL(0.080 ns) = 133.576 ns; Loc. = LAB_X32_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~9 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 133.656 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~11 293 COMB LAB_X32_Y22 2 " "Info: 293: + IC(0.000 ns) + CELL(0.080 ns) = 133.656 ns; Loc. = LAB_X32_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~11 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 133.736 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~13 294 COMB LAB_X32_Y22 2 " "Info: 294: + IC(0.000 ns) + CELL(0.080 ns) = 133.736 ns; Loc. = LAB_X32_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~13 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 133.816 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~15 295 COMB LAB_X32_Y22 2 " "Info: 295: + IC(0.000 ns) + CELL(0.080 ns) = 133.816 ns; Loc. = LAB_X32_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~15 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 133.896 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~17 296 COMB LAB_X32_Y22 2 " "Info: 296: + IC(0.000 ns) + CELL(0.080 ns) = 133.896 ns; Loc. = LAB_X32_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~17 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 133.976 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~19 297 COMB LAB_X32_Y22 2 " "Info: 297: + IC(0.000 ns) + CELL(0.080 ns) = 133.976 ns; Loc. = LAB_X32_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~19 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 134.056 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~21 298 COMB LAB_X32_Y22 2 " "Info: 298: + IC(0.000 ns) + CELL(0.080 ns) = 134.056 ns; Loc. = LAB_X32_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~21 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 134.136 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~23 299 COMB LAB_X32_Y22 2 " "Info: 299: + IC(0.000 ns) + CELL(0.080 ns) = 134.136 ns; Loc. = LAB_X32_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~23 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 134.216 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~25 300 COMB LAB_X32_Y22 2 " "Info: 300: + IC(0.000 ns) + CELL(0.080 ns) = 134.216 ns; Loc. = LAB_X32_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~25 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 134.296 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~27 301 COMB LAB_X32_Y22 2 " "Info: 301: + IC(0.000 ns) + CELL(0.080 ns) = 134.296 ns; Loc. = LAB_X32_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~27 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 134.376 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~29 302 COMB LAB_X32_Y22 2 " "Info: 302: + IC(0.000 ns) + CELL(0.080 ns) = 134.376 ns; Loc. = LAB_X32_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~29 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.098 ns) + CELL(0.080 ns) 134.554 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~31 303 COMB LAB_X32_Y21 2 " "Info: 303: + IC(0.098 ns) + CELL(0.080 ns) = 134.554 ns; Loc. = LAB_X32_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~31 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 134.634 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~33 304 COMB LAB_X32_Y21 2 " "Info: 304: + IC(0.000 ns) + CELL(0.080 ns) = 134.634 ns; Loc. = LAB_X32_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~33 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 134.714 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~35 305 COMB LAB_X32_Y21 2 " "Info: 305: + IC(0.000 ns) + CELL(0.080 ns) = 134.714 ns; Loc. = LAB_X32_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~33 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~35 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 134.794 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~37 306 COMB LAB_X32_Y21 2 " "Info: 306: + IC(0.000 ns) + CELL(0.080 ns) = 134.794 ns; Loc. = LAB_X32_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~35 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~37 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 134.874 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~39 307 COMB LAB_X32_Y21 2 " "Info: 307: + IC(0.000 ns) + CELL(0.080 ns) = 134.874 ns; Loc. = LAB_X32_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~37 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~39 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 134.954 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~41 308 COMB LAB_X32_Y21 2 " "Info: 308: + IC(0.000 ns) + CELL(0.080 ns) = 134.954 ns; Loc. = LAB_X32_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~39 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~41 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 135.034 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~43 309 COMB LAB_X32_Y21 2 " "Info: 309: + IC(0.000 ns) + CELL(0.080 ns) = 135.034 ns; Loc. = LAB_X32_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~41 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~43 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 135.114 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~45 310 COMB LAB_X32_Y21 2 " "Info: 310: + IC(0.000 ns) + CELL(0.080 ns) = 135.114 ns; Loc. = LAB_X32_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~43 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~45 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 135.194 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~47 311 COMB LAB_X32_Y21 2 " "Info: 311: + IC(0.000 ns) + CELL(0.080 ns) = 135.194 ns; Loc. = LAB_X32_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~45 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~47 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 135.274 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~49 312 COMB LAB_X32_Y21 2 " "Info: 312: + IC(0.000 ns) + CELL(0.080 ns) = 135.274 ns; Loc. = LAB_X32_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~47 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~49 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 135.354 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~51 313 COMB LAB_X32_Y21 2 " "Info: 313: + IC(0.000 ns) + CELL(0.080 ns) = 135.354 ns; Loc. = LAB_X32_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~51'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~49 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~51 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 135.812 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~52 314 COMB LAB_X32_Y21 1 " "Info: 314: + IC(0.000 ns) + CELL(0.458 ns) = 135.812 ns; Loc. = LAB_X32_Y21; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~52'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~51 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~52 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.178 ns) 136.722 ns Arkanoid:inst\|Equal6~2 315 COMB LAB_X31_Y21 2 " "Info: 315: + IC(0.732 ns) + CELL(0.178 ns) = 136.722 ns; Loc. = LAB_X31_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|Equal6~2'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.910 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~52 Arkanoid:inst|Equal6~2 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.131 ns) + CELL(0.545 ns) 137.398 ns Arkanoid:inst\|Equal6~3 316 COMB LAB_X31_Y21 1 " "Info: 316: + IC(0.131 ns) + CELL(0.545 ns) = 137.398 ns; Loc. = LAB_X31_Y21; Fanout = 1; COMB Node = 'Arkanoid:inst\|Equal6~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { Arkanoid:inst|Equal6~2 Arkanoid:inst|Equal6~3 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.354 ns) + CELL(0.322 ns) 138.074 ns Arkanoid:inst\|Equal6~7 317 COMB LAB_X31_Y21 1 " "Info: 317: + IC(0.354 ns) + CELL(0.322 ns) = 138.074 ns; Loc. = LAB_X31_Y21; Fanout = 1; COMB Node = 'Arkanoid:inst\|Equal6~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { Arkanoid:inst|Equal6~3 Arkanoid:inst|Equal6~7 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.002 ns) + CELL(0.544 ns) 139.620 ns Arkanoid:inst\|Equal6~24 318 COMB LAB_X39_Y21 5 " "Info: 318: + IC(1.002 ns) + CELL(0.544 ns) = 139.620 ns; Loc. = LAB_X39_Y21; Fanout = 5; COMB Node = 'Arkanoid:inst\|Equal6~24'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.546 ns" { Arkanoid:inst|Equal6~7 Arkanoid:inst|Equal6~24 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.131 ns) + CELL(0.545 ns) 140.296 ns Arkanoid:inst\|WideNor0~4 319 COMB LAB_X39_Y21 4 " "Info: 319: + IC(0.131 ns) + CELL(0.545 ns) = 140.296 ns; Loc. = LAB_X39_Y21; Fanout = 4; COMB Node = 'Arkanoid:inst\|WideNor0~4'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { Arkanoid:inst|Equal6~24 Arkanoid:inst|WideNor0~4 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.131 ns) + CELL(0.545 ns) 140.972 ns Arkanoid:inst\|WideOr0~0 320 COMB LAB_X39_Y21 3 " "Info: 320: + IC(0.131 ns) + CELL(0.545 ns) = 140.972 ns; Loc. = LAB_X39_Y21; Fanout = 3; COMB Node = 'Arkanoid:inst\|WideOr0~0'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { Arkanoid:inst|WideNor0~4 Arkanoid:inst|WideOr0~0 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.704 ns) + CELL(0.521 ns) 142.197 ns Arkanoid:inst\|high~8 321 COMB LAB_X42_Y21 1 " "Info: 321: + IC(0.704 ns) + CELL(0.521 ns) = 142.197 ns; Loc. = LAB_X42_Y21; Fanout = 1; COMB Node = 'Arkanoid:inst\|high~8'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.225 ns" { Arkanoid:inst|WideOr0~0 Arkanoid:inst|high~8 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 142.293 ns Arkanoid:inst\|hex3_\[5\] 322 REG LAB_X42_Y21 1 " "Info: 322: + IC(0.000 ns) + CELL(0.096 ns) = 142.293 ns; Loc. = LAB_X42_Y21; Fanout = 1; REG Node = 'Arkanoid:inst\|hex3_\[5\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { Arkanoid:inst|high~8 Arkanoid:inst|hex3_[5] } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "67.931 ns ( 47.74 % ) " "Info: Total cell delay = 67.931 ns ( 47.74 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "74.362 ns ( 52.26 % ) " "Info: Total interconnect delay = 74.362 ns ( 52.26 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "142.293 ns" { Arkanoid:inst|button2_state Arkanoid:inst|platform2_position~4 Arkanoid:inst|platform2_position~5 Arkanoid:inst|Add4~1 Arkanoid:inst|Add4~3 Arkanoid:inst|Add4~5 Arkanoid:inst|Add4~7 Arkanoid:inst|Add4~9 Arkanoid:inst|Add4~11 Arkanoid:inst|Add4~13 Arkanoid:inst|Add4~15 Arkanoid:inst|Add4~17 Arkanoid:inst|Add4~19 Arkanoid:inst|Add4~21 Arkanoid:inst|Add4~23 Arkanoid:inst|Add4~25 Arkanoid:inst|Add4~27 Arkanoid:inst|Add4~29 Arkanoid:inst|Add4~31 Arkanoid:inst|Add4~33 Arkanoid:inst|Add4~35 Arkanoid:inst|Add4~37 Arkanoid:inst|Add4~39 Arkanoid:inst|Add4~41 Arkanoid:inst|Add4~43 Arkanoid:inst|Add4~45 Arkanoid:inst|Add4~47 Arkanoid:inst|Add4~49 Arkanoid:inst|Add4~51 Arkanoid:inst|Add4~53 Arkanoid:inst|Add4~54 Arkanoid:inst|platform2_position~37 Arkanoid:inst|LessThan3~3 Arkanoid:inst|LessThan3~4 Arkanoid:inst|LessThan3~10 Arkanoid:inst|Add5~1 Arkanoid:inst|Add5~3 Arkanoid:inst|Add5~5 Arkanoid:inst|Add5~7 Arkanoid:inst|Add5~9 Arkanoid:inst|Add5~11 Arkanoid:inst|Add5~13 Arkanoid:inst|Add5~15 Arkanoid:inst|Add5~17 Arkanoid:inst|Add5~19 Arkanoid:inst|Add5~21 Arkanoid:inst|Add5~22 Arkanoid:inst|platform2_position~64 Arkanoid:inst|Add7~23 Arkanoid:inst|Add7~24 Arkanoid:inst|LessThan139~25 Arkanoid:inst|LessThan139~27 Arkanoid:inst|LessThan139~29 Arkanoid:inst|LessThan139~31 Arkanoid:inst|LessThan139~33 Arkanoid:inst|LessThan139~35 Arkanoid:inst|LessThan139~37 Arkanoid:inst|LessThan139~39 Arkanoid:inst|LessThan139~41 Arkanoid:inst|LessThan139~43 Arkanoid:inst|LessThan139~45 Arkanoid:inst|LessThan139~47 Arkanoid:inst|LessThan139~49 Arkanoid:inst|LessThan139~51 Arkanoid:inst|LessThan139~53 Arkanoid:inst|LessThan139~55 Arkanoid:inst|LessThan139~57 Arkanoid:inst|LessThan139~59 Arkanoid:inst|LessThan139~61 Arkanoid:inst|LessThan139~62 Arkanoid:inst|always2~4 Arkanoid:inst|Add9~1 Arkanoid:inst|Add9~3 Arkanoid:inst|Add9~5 Arkanoid:inst|Add9~7 Arkanoid:inst|Add9~9 Arkanoid:inst|Add9~11 Arkanoid:inst|Add9~13 Arkanoid:inst|Add9~15 Arkanoid:inst|Add9~17 Arkanoid:inst|Add9~19 Arkanoid:inst|Add9~21 Arkanoid:inst|Add9~23 Arkanoid:inst|Add9~25 Arkanoid:inst|Add9~27 Arkanoid:inst|Add9~29 Arkanoid:inst|Add9~31 Arkanoid:inst|Add9~33 Arkanoid:inst|Add9~35 Arkanoid:inst|Add9~37 Arkanoid:inst|Add9~39 Arkanoid:inst|Add9~41 Arkanoid:inst|Add9~43 Arkanoid:inst|Add9~45 Arkanoid:inst|Add9~47 Arkanoid:inst|Add9~49 Arkanoid:inst|Add9~51 Arkanoid:inst|Add9~53 Arkanoid:inst|Add9~55 Arkanoid:inst|Add9~57 Arkanoid:inst|Add9~59 Arkanoid:inst|Add9~61 Arkanoid:inst|Add9~63 Arkanoid:inst|lpm_divide:Mod0|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[0]~0 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~56 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[18]~111 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[24]~121 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[30]~129 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~137 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[42]~145 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[51]~337 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[55]~158 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[63]~341 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[66]~177 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[76]~344 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[82]~186 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[88]~194 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[90]~209 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[96]~217 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~225 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[108]~233 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[118]~234 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~244 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[128]~252 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[134]~260 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[140]~268 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~276 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[152]~284 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[158]~292 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[164]~300 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[170]~308 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~316 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[182]~324 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~33 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~35 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~37 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~39 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~41 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~43 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~45 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~47 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~49 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~51 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~52 Arkanoid:inst|Equal6~2 Arkanoid:inst|Equal6~3 Arkanoid:inst|Equal6~7 Arkanoid:inst|Equal6~24 Arkanoid:inst|WideNor0~4 Arkanoid:inst|WideOr0~0 Arkanoid:inst|high~8 Arkanoid:inst|hex3_[5] } "NODE_NAME" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "13 " "Info: Average interconnect usage is 13% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "25 X12_Y14 X24_Y27 " "Info: Peak interconnect usage is 25% of the available device resources in the region that extends from location X12_Y14 to location X24_Y27" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:08 " "Info: Fitter routing operations ending: elapsed time is 00:00:08" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
+{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "50 " "Warning: Found 50 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "h_sync 0 " "Info: Pin \"h_sync\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "v_sync 0 " "Info: Pin \"v_sync\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "blue\[3\] 0 " "Info: Pin \"blue\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "blue\[2\] 0 " "Info: Pin \"blue\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "blue\[1\] 0 " "Info: Pin \"blue\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "blue\[0\] 0 " "Info: Pin \"blue\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "green\[3\] 0 " "Info: Pin \"green\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "green\[2\] 0 " "Info: Pin \"green\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "green\[1\] 0 " "Info: Pin \"green\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "green\[0\] 0 " "Info: Pin \"green\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[6\] 0 " "Info: Pin \"hex0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[5\] 0 " "Info: Pin \"hex0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[4\] 0 " "Info: Pin \"hex0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[3\] 0 " "Info: Pin \"hex0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[2\] 0 " "Info: Pin \"hex0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[1\] 0 " "Info: Pin \"hex0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[0\] 0 " "Info: Pin \"hex0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[6\] 0 " "Info: Pin \"hex1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[5\] 0 " "Info: Pin \"hex1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[4\] 0 " "Info: Pin \"hex1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[3\] 0 " "Info: Pin \"hex1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[2\] 0 " "Info: Pin \"hex1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[1\] 0 " "Info: Pin \"hex1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[0\] 0 " "Info: Pin \"hex1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex2\[6\] 0 " "Info: Pin \"hex2\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex2\[5\] 0 " "Info: Pin \"hex2\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex2\[4\] 0 " "Info: Pin \"hex2\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex2\[3\] 0 " "Info: Pin \"hex2\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex2\[2\] 0 " "Info: Pin \"hex2\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex2\[1\] 0 " "Info: Pin \"hex2\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex2\[0\] 0 " "Info: Pin \"hex2\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex3\[6\] 0 " "Info: Pin \"hex3\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex3\[5\] 0 " "Info: Pin \"hex3\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex3\[4\] 0 " "Info: Pin \"hex3\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex3\[3\] 0 " "Info: Pin \"hex3\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex3\[2\] 0 " "Info: Pin \"hex3\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex3\[1\] 0 " "Info: Pin \"hex3\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex3\[0\] 0 " "Info: Pin \"hex3\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[7\] 0 " "Info: Pin \"led\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[6\] 0 " "Info: Pin \"led\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[5\] 0 " "Info: Pin \"led\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[4\] 0 " "Info: Pin \"led\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[3\] 0 " "Info: Pin \"led\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[2\] 0 " "Info: Pin \"led\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[1\] 0 " "Info: Pin \"led\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[0\] 0 " "Info: Pin \"led\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "red\[3\] 0 " "Info: Pin \"red\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "red\[2\] 0 " "Info: Pin \"red\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "red\[1\] 0 " "Info: Pin \"red\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "red\[0\] 0 " "Info: Pin \"red\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "G:/Verilog/Arkanoid2PDE1/myArkanoid.fit.smsg " "Info: Generated suppressed messages file G:/Verilog/Arkanoid2PDE1/myArkanoid.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "267 " "Info: Peak virtual memory: 267 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 27 20:49:23 2012 " "Info: Processing ended: Sun May 27 20:49:23 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Info: Elapsed time: 00:00:30" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:35 " "Info: Total CPU time (on all processors): 00:00:35" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/db/prev_cmp_myArkanoid.map.qmsg b/db/prev_cmp_myArkanoid.map.qmsg
new file mode 100644
index 0000000..5b4e9b6
--- /dev/null
+++ b/db/prev_cmp_myArkanoid.map.qmsg
@@ -0,0 +1,43 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 27 20:45:57 2012 " "Info: Processing started: Sun May 27 20:45:57 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "debouncer.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file debouncer.v" { { "Info" "ISGN_ENTITY_NAME" "1 Debouncer " "Info: Found entity 1: Debouncer" { } { { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "totalscheme.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file totalscheme.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 TotalScheme " "Info: Found entity 1: TotalScheme" { } { { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "arkanoid.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file arkanoid.v" { { "Info" "ISGN_ENTITY_NAME" "1 Arkanoid " "Info: Found entity 1: Arkanoid" { } { { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "arkanoid_header.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file arkanoid_header.v" { } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "int_to_digital.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file int_to_digital.v" { } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga_sync.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file vga_sync.v" { } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clockdivider.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clockdivider.v" { { "Info" "ISGN_ENTITY_NAME" "1 ClockDivider " "Info: Found entity 1: ClockDivider" { } { { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_TOP" "TotalScheme " "Info: Elaborating entity \"TotalScheme\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Arkanoid Arkanoid:inst " "Info: Elaborating entity \"Arkanoid\" for hierarchy \"Arkanoid:inst\"" { } { { "TotalScheme.bdf" "inst" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { 128 464 616 352 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VERI_CANT_ANALYZE_CASE_STATEMENT" "int_to_digital.v(21) " "Warning (10762): Verilog HDL Case Statement warning at int_to_digital.v(21): can't check case statement for completeness because the case expression has too many possible states" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 21 0 0 } } } 0 10762 "Verilog HDL Case Statement warning at %1!s!: can't check case statement for completeness because the case expression has too many possible states" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VERI_2104_UNCONVERTED" "n1 IntToDigital int_to_digital.v(10) " "Warning (10776): Verilog HDL warning at int_to_digital.v(10): variable n1 in static task or function IntToDigital may have unintended latch behavior" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 10 0 0 } } } 0 10776 "Verilog HDL warning at %3!s!: variable %1!s! in static task or function %2!s! may have unintended latch behavior" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VERI_2104_UNCONVERTED" "n0 IntToDigital int_to_digital.v(10) " "Warning (10776): Verilog HDL warning at int_to_digital.v(10): variable n0 in static task or function IntToDigital may have unintended latch behavior" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 10 0 0 } } } 0 10776 "Verilog HDL warning at %3!s!: variable %1!s! in static task or function %2!s! may have unintended latch behavior" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VERI_2104_UNCONVERTED" "low IntToDigital int_to_digital.v(9) " "Warning (10776): Verilog HDL warning at int_to_digital.v(9): variable low in static task or function IntToDigital may have unintended latch behavior" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 9 0 0 } } } 0 10776 "Verilog HDL warning at %3!s!: variable %1!s! in static task or function %2!s! may have unintended latch behavior" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "IntToDigital.low\[6..0\] 0 int_to_digital.v(9) " "Warning (10030): Net \"IntToDigital.low\[6..0\]\" at int_to_digital.v(9) has no driver or initial value, using a default initial value '0'" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "" 0 -1}
+{ "Info" "IVRFX_MULTI_DIMENSION_OBJECT_INFO" "field " "Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"field\" into its bus" { } { } 0 10008 "Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"%1!s!\" into its bus" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ClockDivider ClockDivider:inst1 " "Info: Elaborating entity \"ClockDivider\" for hierarchy \"ClockDivider:inst1\"" { } { { "TotalScheme.bdf" "inst1" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -192 160 312 -128 "inst1" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Debouncer Debouncer:inst2 " "Info: Elaborating entity \"Debouncer\" for hierarchy \"Debouncer:inst2\"" { } { { "TotalScheme.bdf" "inst2" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -96 168 304 0 "inst2" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ILPMS_INFERENCING_SUMMARY" "6 " "Info: Inferred 6 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div3 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div3\"" { } { { "Arkanoid.v" "Div3" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 298 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div2 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div2\"" { } { { "Arkanoid.v" "Div2" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 297 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Mod1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Mod1\"" { } { { "int_to_digital.v" "Mod1" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div1\"" { } { { "int_to_digital.v" "Div1" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Mod0 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Mod0\"" { } { { "int_to_digital.v" "Mod0" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div0 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div0\"" { } { { "int_to_digital.v" "Div0" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 -1}
+{ "Info" "ISGN_ELABORATION_HEADER" "Arkanoid:inst\|lpm_divide:Div3 " "Info: Elaborated megafunction instantiation \"Arkanoid:inst\|lpm_divide:Div3\"" { } { { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 298 -1 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "Arkanoid:inst\|lpm_divide:Div3 " "Info: Instantiated megafunction \"Arkanoid:inst\|lpm_divide:Div3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Info: Parameter \"LPM_WIDTHN\" = \"32\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 6 " "Info: Parameter \"LPM_WIDTHD\" = \"6\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION SIGNED " "Info: Parameter \"LPM_NREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION SIGNED " "Info: Parameter \"LPM_DREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT LPM_REMAINDERPOSITIVE=FALSE " "Info: Parameter \"LPM_HINT\" = \"LPM_REMAINDERPOSITIVE=FALSE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 298 -1 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_8so.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_8so.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_8so " "Info: Found entity 1: lpm_divide_8so" { } { { "db/lpm_divide_8so.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_divide_8so.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/abs_divider_lbg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/abs_divider_lbg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 abs_divider_lbg " "Info: Found entity 1: abs_divider_lbg" { } { { "db/abs_divider_lbg.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/abs_divider_lbg.tdf" 28 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_m2f.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_m2f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_m2f " "Info: Found entity 1: alt_u_div_m2f" { } { { "db/alt_u_div_m2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_m2f.tdf" 26 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_lkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_lkc " "Info: Found entity 1: add_sub_lkc" { } { { "db/add_sub_lkc.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/add_sub_lkc.tdf" 22 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_mkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_mkc " "Info: Found entity 1: add_sub_mkc" { } { { "db/add_sub_mkc.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/add_sub_mkc.tdf" 22 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_hq9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_hq9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_hq9 " "Info: Found entity 1: lpm_abs_hq9" { } { { "db/lpm_abs_hq9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_hq9.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_0s9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_0s9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_0s9 " "Info: Found entity 1: lpm_abs_0s9" { } { { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_ELABORATION_HEADER" "Arkanoid:inst\|lpm_divide:Mod1 " "Info: Elaborated megafunction instantiation \"Arkanoid:inst\|lpm_divide:Mod1\"" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "Arkanoid:inst\|lpm_divide:Mod1 " "Info: Instantiated megafunction \"Arkanoid:inst\|lpm_divide:Mod1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Info: Parameter \"LPM_WIDTHN\" = \"32\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 5 " "Info: Parameter \"LPM_WIDTHD\" = \"5\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION SIGNED " "Info: Parameter \"LPM_NREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION SIGNED " "Info: Parameter \"LPM_DREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT LPM_REMAINDERPOSITIVE=FALSE " "Info: Parameter \"LPM_HINT\" = \"LPM_REMAINDERPOSITIVE=FALSE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_ako.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_ako.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_ako " "Info: Found entity 1: lpm_divide_ako" { } { { "db/lpm_divide_ako.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_divide_ako.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/abs_divider_kbg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/abs_divider_kbg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 abs_divider_kbg " "Info: Found entity 1: abs_divider_kbg" { } { { "db/abs_divider_kbg.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/abs_divider_kbg.tdf" 28 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_k2f.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_k2f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_k2f " "Info: Found entity 1: alt_u_div_k2f" { } { { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 26 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_gq9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_gq9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_gq9 " "Info: Found entity 1: lpm_abs_gq9" { } { { "db/lpm_abs_gq9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_gq9.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_ELABORATION_HEADER" "Arkanoid:inst\|lpm_divide:Div1 " "Info: Elaborated megafunction instantiation \"Arkanoid:inst\|lpm_divide:Div1\"" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "Arkanoid:inst\|lpm_divide:Div1 " "Info: Instantiated megafunction \"Arkanoid:inst\|lpm_divide:Div1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Info: Parameter \"LPM_WIDTHN\" = \"32\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 5 " "Info: Parameter \"LPM_WIDTHD\" = \"5\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION SIGNED " "Info: Parameter \"LPM_NREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION SIGNED " "Info: Parameter \"LPM_DREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT LPM_REMAINDERPOSITIVE=FALSE " "Info: Parameter \"LPM_HINT\" = \"LPM_REMAINDERPOSITIVE=FALSE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_7so.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_7so.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_7so " "Info: Found entity 1: lpm_divide_7so" { } { { "db/lpm_divide_7so.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_divide_7so.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 2 " "Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Arkanoid:inst\|ball_direction~6 " "Info: Register \"Arkanoid:inst\|ball_direction~6\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Arkanoid:inst\|ball_direction~7 " "Info: Register \"Arkanoid:inst\|ball_direction~7\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} } { } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "8031 " "Info: Implemented 8031 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "50 " "Info: Implemented 50 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "7976 " "Info: Implemented 7976 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "227 " "Info: Peak virtual memory: 227 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 27 20:48:52 2012 " "Info: Processing ended: Sun May 27 20:48:52 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:02:55 " "Info: Elapsed time: 00:02:55" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:02:54 " "Info: Total CPU time (on all processors): 00:02:54" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/db/prev_cmp_myArkanoid.qmsg b/db/prev_cmp_myArkanoid.qmsg
new file mode 100644
index 0000000..5a1e259
--- /dev/null
+++ b/db/prev_cmp_myArkanoid.qmsg
@@ -0,0 +1,99 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 27 20:40:53 2012 " "Info: Processing started: Sun May 27 20:40:53 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "debouncer.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file debouncer.v" { { "Info" "ISGN_ENTITY_NAME" "1 Debouncer " "Info: Found entity 1: Debouncer" { } { { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "totalscheme.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file totalscheme.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 TotalScheme " "Info: Found entity 1: TotalScheme" { } { { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "arkanoid.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file arkanoid.v" { { "Info" "ISGN_ENTITY_NAME" "1 Arkanoid " "Info: Found entity 1: Arkanoid" { } { { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "arkanoid_header.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file arkanoid_header.v" { } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "int_to_digital.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file int_to_digital.v" { } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga_sync.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file vga_sync.v" { } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clockdivider.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clockdivider.v" { { "Info" "ISGN_ENTITY_NAME" "1 ClockDivider " "Info: Found entity 1: ClockDivider" { } { { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_TOP" "TotalScheme " "Info: Elaborating entity \"TotalScheme\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Arkanoid Arkanoid:inst " "Info: Elaborating entity \"Arkanoid\" for hierarchy \"Arkanoid:inst\"" { } { { "TotalScheme.bdf" "inst" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { 128 464 616 352 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VERI_CANT_ANALYZE_CASE_STATEMENT" "int_to_digital.v(21) " "Warning (10762): Verilog HDL Case Statement warning at int_to_digital.v(21): can't check case statement for completeness because the case expression has too many possible states" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 21 0 0 } } } 0 10762 "Verilog HDL Case Statement warning at %1!s!: can't check case statement for completeness because the case expression has too many possible states" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VERI_2104_UNCONVERTED" "n1 IntToDigital int_to_digital.v(10) " "Warning (10776): Verilog HDL warning at int_to_digital.v(10): variable n1 in static task or function IntToDigital may have unintended latch behavior" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 10 0 0 } } } 0 10776 "Verilog HDL warning at %3!s!: variable %1!s! in static task or function %2!s! may have unintended latch behavior" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VERI_2104_UNCONVERTED" "n0 IntToDigital int_to_digital.v(10) " "Warning (10776): Verilog HDL warning at int_to_digital.v(10): variable n0 in static task or function IntToDigital may have unintended latch behavior" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 10 0 0 } } } 0 10776 "Verilog HDL warning at %3!s!: variable %1!s! in static task or function %2!s! may have unintended latch behavior" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VERI_2104_UNCONVERTED" "low IntToDigital int_to_digital.v(9) " "Warning (10776): Verilog HDL warning at int_to_digital.v(9): variable low in static task or function IntToDigital may have unintended latch behavior" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 9 0 0 } } } 0 10776 "Verilog HDL warning at %3!s!: variable %1!s! in static task or function %2!s! may have unintended latch behavior" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "IntToDigital.low\[6..0\] 0 int_to_digital.v(9) " "Warning (10030): Net \"IntToDigital.low\[6..0\]\" at int_to_digital.v(9) has no driver or initial value, using a default initial value '0'" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "" 0 -1}
+{ "Info" "IVRFX_MULTI_DIMENSION_OBJECT_INFO" "field " "Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"field\" into its bus" { } { } 0 10008 "Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"%1!s!\" into its bus" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ClockDivider ClockDivider:inst1 " "Info: Elaborating entity \"ClockDivider\" for hierarchy \"ClockDivider:inst1\"" { } { { "TotalScheme.bdf" "inst1" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -192 160 312 -128 "inst1" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Debouncer Debouncer:inst2 " "Info: Elaborating entity \"Debouncer\" for hierarchy \"Debouncer:inst2\"" { } { { "TotalScheme.bdf" "inst2" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -96 168 304 0 "inst2" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ILPMS_INFERENCING_SUMMARY" "6 " "Info: Inferred 6 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div3 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div3\"" { } { { "Arkanoid.v" "Div3" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 297 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div2 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div2\"" { } { { "Arkanoid.v" "Div2" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 296 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Mod1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Mod1\"" { } { { "int_to_digital.v" "Mod1" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div1\"" { } { { "int_to_digital.v" "Div1" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Mod0 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Mod0\"" { } { { "int_to_digital.v" "Mod0" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div0 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div0\"" { } { { "int_to_digital.v" "Div0" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 -1}
+{ "Info" "ISGN_ELABORATION_HEADER" "Arkanoid:inst\|lpm_divide:Div3 " "Info: Elaborated megafunction instantiation \"Arkanoid:inst\|lpm_divide:Div3\"" { } { { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 297 -1 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "Arkanoid:inst\|lpm_divide:Div3 " "Info: Instantiated megafunction \"Arkanoid:inst\|lpm_divide:Div3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Info: Parameter \"LPM_WIDTHN\" = \"32\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 6 " "Info: Parameter \"LPM_WIDTHD\" = \"6\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION SIGNED " "Info: Parameter \"LPM_NREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION SIGNED " "Info: Parameter \"LPM_DREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT LPM_REMAINDERPOSITIVE=FALSE " "Info: Parameter \"LPM_HINT\" = \"LPM_REMAINDERPOSITIVE=FALSE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 297 -1 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_8so.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_8so.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_8so " "Info: Found entity 1: lpm_divide_8so" { } { { "db/lpm_divide_8so.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_divide_8so.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/abs_divider_lbg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/abs_divider_lbg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 abs_divider_lbg " "Info: Found entity 1: abs_divider_lbg" { } { { "db/abs_divider_lbg.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/abs_divider_lbg.tdf" 28 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_m2f.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_m2f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_m2f " "Info: Found entity 1: alt_u_div_m2f" { } { { "db/alt_u_div_m2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_m2f.tdf" 26 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_lkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_lkc " "Info: Found entity 1: add_sub_lkc" { } { { "db/add_sub_lkc.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/add_sub_lkc.tdf" 22 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_mkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_mkc " "Info: Found entity 1: add_sub_mkc" { } { { "db/add_sub_mkc.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/add_sub_mkc.tdf" 22 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_hq9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_hq9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_hq9 " "Info: Found entity 1: lpm_abs_hq9" { } { { "db/lpm_abs_hq9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_hq9.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_0s9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_0s9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_0s9 " "Info: Found entity 1: lpm_abs_0s9" { } { { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_ELABORATION_HEADER" "Arkanoid:inst\|lpm_divide:Mod1 " "Info: Elaborated megafunction instantiation \"Arkanoid:inst\|lpm_divide:Mod1\"" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "Arkanoid:inst\|lpm_divide:Mod1 " "Info: Instantiated megafunction \"Arkanoid:inst\|lpm_divide:Mod1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Info: Parameter \"LPM_WIDTHN\" = \"32\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 5 " "Info: Parameter \"LPM_WIDTHD\" = \"5\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION SIGNED " "Info: Parameter \"LPM_NREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION SIGNED " "Info: Parameter \"LPM_DREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT LPM_REMAINDERPOSITIVE=FALSE " "Info: Parameter \"LPM_HINT\" = \"LPM_REMAINDERPOSITIVE=FALSE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_ako.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_ako.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_ako " "Info: Found entity 1: lpm_divide_ako" { } { { "db/lpm_divide_ako.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_divide_ako.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/abs_divider_kbg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/abs_divider_kbg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 abs_divider_kbg " "Info: Found entity 1: abs_divider_kbg" { } { { "db/abs_divider_kbg.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/abs_divider_kbg.tdf" 28 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_k2f.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_k2f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_k2f " "Info: Found entity 1: alt_u_div_k2f" { } { { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 26 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_gq9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_gq9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_gq9 " "Info: Found entity 1: lpm_abs_gq9" { } { { "db/lpm_abs_gq9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_gq9.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_ELABORATION_HEADER" "Arkanoid:inst\|lpm_divide:Div1 " "Info: Elaborated megafunction instantiation \"Arkanoid:inst\|lpm_divide:Div1\"" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "Arkanoid:inst\|lpm_divide:Div1 " "Info: Instantiated megafunction \"Arkanoid:inst\|lpm_divide:Div1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Info: Parameter \"LPM_WIDTHN\" = \"32\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 5 " "Info: Parameter \"LPM_WIDTHD\" = \"5\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION SIGNED " "Info: Parameter \"LPM_NREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION SIGNED " "Info: Parameter \"LPM_DREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT LPM_REMAINDERPOSITIVE=FALSE " "Info: Parameter \"LPM_HINT\" = \"LPM_REMAINDERPOSITIVE=FALSE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_7so.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_7so.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_7so " "Info: Found entity 1: lpm_divide_7so" { } { { "db/lpm_divide_7so.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_divide_7so.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 2 " "Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Arkanoid:inst\|ball_direction~6 " "Info: Register \"Arkanoid:inst\|ball_direction~6\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Arkanoid:inst\|ball_direction~7 " "Info: Register \"Arkanoid:inst\|ball_direction~7\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} } { } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "8017 " "Info: Implemented 8017 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "50 " "Info: Implemented 50 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "7962 " "Info: Implemented 7962 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "238 " "Info: Peak virtual memory: 238 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 27 20:42:47 2012 " "Info: Processing ended: Sun May 27 20:42:47 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:01:54 " "Info: Elapsed time: 00:01:54" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:54 " "Info: Total CPU time (on all processors): 00:01:54" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 27 20:42:48 2012 " "Info: Processing started: Sun May 27 20:42:48 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "IMPP_MPP_USER_DEVICE" "myArkanoid EP2C20F484C7 " "Info: Selected device EP2C20F484C7 for design \"myArkanoid\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C15AF484C7 " "Info: Device EP2C15AF484C7 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484C7 " "Info: Device EP2C35F484C7 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C7 " "Info: Device EP2C50F484C7 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ C4 " "Info: Pin ~ASDO~ is reserved at location C4" { } { { "c:/quartus/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/quartus/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/Verilog/Arkanoid2PDE1/" 0 { } { { 0 { 0 ""} 0 12645 3016 4146 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ C3 " "Info: Pin ~nCSO~ is reserved at location C3" { } { { "c:/quartus/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/quartus/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/Verilog/Arkanoid2PDE1/" 0 { } { { 0 { 0 ""} 0 12646 3016 4146 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS91p/nCEO~ W20 " "Info: Pin ~LVDS91p/nCEO~ is reserved at location W20" { } { { "c:/quartus/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/quartus/quartus/bin/pin_planner.ppl" { ~LVDS91p/nCEO~ } } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS91p/nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/Verilog/Arkanoid2PDE1/" 0 { } { { 0 { 0 ""} 0 12647 3016 4146 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
+{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Timing-driven compilation is using the Classic Timing Analyzer" { } { } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
+{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ClockDivider:inst1\|clk25MHz_ " "Info: Automatically promoted node ClockDivider:inst1\|clk25MHz_ " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ClockDivider:inst1\|clk25MHz_~0 " "Info: Destination node ClockDivider:inst1\|clk25MHz_~0" { } { { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { ClockDivider:inst1|clk25MHz_~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/Verilog/Arkanoid2PDE1/" 0 { } { { 0 { 0 ""} 0 12639 3016 4146 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1} } { { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { ClockDivider:inst1|clk25MHz_ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/Verilog/Arkanoid2PDE1/" 0 { } { { 0 { 0 ""} 0 19 3016 4146 0} } } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Info: Fitter preparation operations ending: elapsed time is 00:00:03" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Info: Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "139.831 ns register register " "Info: Estimated most critical path is register to register delay of 139.831 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Arkanoid:inst\|button2_state 1 REG LAB_X25_Y14 36 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X25_Y14; Fanout = 36; REG Node = 'Arkanoid:inst\|button2_state'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { Arkanoid:inst|button2_state } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 108 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.450 ns) + CELL(0.544 ns) 0.994 ns Arkanoid:inst\|platform2_position~4 2 COMB LAB_X24_Y14 71 " "Info: 2: + IC(0.450 ns) + CELL(0.544 ns) = 0.994 ns; Loc. = LAB_X24_Y14; Fanout = 71; COMB Node = 'Arkanoid:inst\|platform2_position~4'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.994 ns" { Arkanoid:inst|button2_state Arkanoid:inst|platform2_position~4 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.521 ns) 2.260 ns Arkanoid:inst\|platform2_position~6 3 COMB LAB_X23_Y10 63 " "Info: 3: + IC(0.745 ns) + CELL(0.521 ns) = 2.260 ns; Loc. = LAB_X23_Y10; Fanout = 63; COMB Node = 'Arkanoid:inst\|platform2_position~6'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.266 ns" { Arkanoid:inst|platform2_position~4 Arkanoid:inst|platform2_position~6 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.495 ns) 3.828 ns Arkanoid:inst\|Add4~1 4 COMB LAB_X24_Y11 2 " "Info: 4: + IC(1.073 ns) + CELL(0.495 ns) = 3.828 ns; Loc. = LAB_X24_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.568 ns" { Arkanoid:inst|platform2_position~6 Arkanoid:inst|Add4~1 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 3.908 ns Arkanoid:inst\|Add4~3 5 COMB LAB_X24_Y11 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 3.908 ns; Loc. = LAB_X24_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~1 Arkanoid:inst|Add4~3 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 3.988 ns Arkanoid:inst\|Add4~5 6 COMB LAB_X24_Y11 2 " "Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 3.988 ns; Loc. = LAB_X24_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~3 Arkanoid:inst|Add4~5 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.068 ns Arkanoid:inst\|Add4~7 7 COMB LAB_X24_Y11 2 " "Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 4.068 ns; Loc. = LAB_X24_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~5 Arkanoid:inst|Add4~7 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.148 ns Arkanoid:inst\|Add4~9 8 COMB LAB_X24_Y11 2 " "Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 4.148 ns; Loc. = LAB_X24_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~7 Arkanoid:inst|Add4~9 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.228 ns Arkanoid:inst\|Add4~11 9 COMB LAB_X24_Y11 2 " "Info: 9: + IC(0.000 ns) + CELL(0.080 ns) = 4.228 ns; Loc. = LAB_X24_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~9 Arkanoid:inst|Add4~11 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.308 ns Arkanoid:inst\|Add4~13 10 COMB LAB_X24_Y11 2 " "Info: 10: + IC(0.000 ns) + CELL(0.080 ns) = 4.308 ns; Loc. = LAB_X24_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~11 Arkanoid:inst|Add4~13 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.388 ns Arkanoid:inst\|Add4~15 11 COMB LAB_X24_Y11 2 " "Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 4.388 ns; Loc. = LAB_X24_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~13 Arkanoid:inst|Add4~15 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.468 ns Arkanoid:inst\|Add4~17 12 COMB LAB_X24_Y11 2 " "Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 4.468 ns; Loc. = LAB_X24_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~15 Arkanoid:inst|Add4~17 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.548 ns Arkanoid:inst\|Add4~19 13 COMB LAB_X24_Y11 2 " "Info: 13: + IC(0.000 ns) + CELL(0.080 ns) = 4.548 ns; Loc. = LAB_X24_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~17 Arkanoid:inst|Add4~19 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.628 ns Arkanoid:inst\|Add4~21 14 COMB LAB_X24_Y11 2 " "Info: 14: + IC(0.000 ns) + CELL(0.080 ns) = 4.628 ns; Loc. = LAB_X24_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~19 Arkanoid:inst|Add4~21 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.708 ns Arkanoid:inst\|Add4~23 15 COMB LAB_X24_Y11 2 " "Info: 15: + IC(0.000 ns) + CELL(0.080 ns) = 4.708 ns; Loc. = LAB_X24_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~21 Arkanoid:inst|Add4~23 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.788 ns Arkanoid:inst\|Add4~25 16 COMB LAB_X24_Y11 2 " "Info: 16: + IC(0.000 ns) + CELL(0.080 ns) = 4.788 ns; Loc. = LAB_X24_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~23 Arkanoid:inst|Add4~25 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.868 ns Arkanoid:inst\|Add4~27 17 COMB LAB_X24_Y11 2 " "Info: 17: + IC(0.000 ns) + CELL(0.080 ns) = 4.868 ns; Loc. = LAB_X24_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~25 Arkanoid:inst|Add4~27 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.948 ns Arkanoid:inst\|Add4~29 18 COMB LAB_X24_Y11 2 " "Info: 18: + IC(0.000 ns) + CELL(0.080 ns) = 4.948 ns; Loc. = LAB_X24_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~27 Arkanoid:inst|Add4~29 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.028 ns Arkanoid:inst\|Add4~31 19 COMB LAB_X24_Y11 2 " "Info: 19: + IC(0.000 ns) + CELL(0.080 ns) = 5.028 ns; Loc. = LAB_X24_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~29 Arkanoid:inst|Add4~31 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.098 ns) + CELL(0.080 ns) 5.206 ns Arkanoid:inst\|Add4~33 20 COMB LAB_X24_Y10 2 " "Info: 20: + IC(0.098 ns) + CELL(0.080 ns) = 5.206 ns; Loc. = LAB_X24_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { Arkanoid:inst|Add4~31 Arkanoid:inst|Add4~33 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.286 ns Arkanoid:inst\|Add4~35 21 COMB LAB_X24_Y10 2 " "Info: 21: + IC(0.000 ns) + CELL(0.080 ns) = 5.286 ns; Loc. = LAB_X24_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~33 Arkanoid:inst|Add4~35 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.366 ns Arkanoid:inst\|Add4~37 22 COMB LAB_X24_Y10 2 " "Info: 22: + IC(0.000 ns) + CELL(0.080 ns) = 5.366 ns; Loc. = LAB_X24_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~35 Arkanoid:inst|Add4~37 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.446 ns Arkanoid:inst\|Add4~39 23 COMB LAB_X24_Y10 2 " "Info: 23: + IC(0.000 ns) + CELL(0.080 ns) = 5.446 ns; Loc. = LAB_X24_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~37 Arkanoid:inst|Add4~39 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.526 ns Arkanoid:inst\|Add4~41 24 COMB LAB_X24_Y10 2 " "Info: 24: + IC(0.000 ns) + CELL(0.080 ns) = 5.526 ns; Loc. = LAB_X24_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~39 Arkanoid:inst|Add4~41 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.606 ns Arkanoid:inst\|Add4~43 25 COMB LAB_X24_Y10 2 " "Info: 25: + IC(0.000 ns) + CELL(0.080 ns) = 5.606 ns; Loc. = LAB_X24_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~41 Arkanoid:inst|Add4~43 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.686 ns Arkanoid:inst\|Add4~45 26 COMB LAB_X24_Y10 2 " "Info: 26: + IC(0.000 ns) + CELL(0.080 ns) = 5.686 ns; Loc. = LAB_X24_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~43 Arkanoid:inst|Add4~45 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.766 ns Arkanoid:inst\|Add4~47 27 COMB LAB_X24_Y10 2 " "Info: 27: + IC(0.000 ns) + CELL(0.080 ns) = 5.766 ns; Loc. = LAB_X24_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~45 Arkanoid:inst|Add4~47 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.846 ns Arkanoid:inst\|Add4~49 28 COMB LAB_X24_Y10 2 " "Info: 28: + IC(0.000 ns) + CELL(0.080 ns) = 5.846 ns; Loc. = LAB_X24_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~47 Arkanoid:inst|Add4~49 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.926 ns Arkanoid:inst\|Add4~51 29 COMB LAB_X24_Y10 2 " "Info: 29: + IC(0.000 ns) + CELL(0.080 ns) = 5.926 ns; Loc. = LAB_X24_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~51'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~49 Arkanoid:inst|Add4~51 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 6.384 ns Arkanoid:inst\|Add4~52 30 COMB LAB_X24_Y10 1 " "Info: 30: + IC(0.000 ns) + CELL(0.458 ns) = 6.384 ns; Loc. = LAB_X24_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|Add4~52'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|Add4~51 Arkanoid:inst|Add4~52 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.388 ns) + CELL(0.521 ns) 7.293 ns Arkanoid:inst\|platform2_position~33 31 COMB LAB_X25_Y10 4 " "Info: 31: + IC(0.388 ns) + CELL(0.521 ns) = 7.293 ns; Loc. = LAB_X25_Y10; Fanout = 4; COMB Node = 'Arkanoid:inst\|platform2_position~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|Add4~52 Arkanoid:inst|platform2_position~33 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.131 ns) + CELL(0.455 ns) 7.879 ns Arkanoid:inst\|LessThan3~2 32 COMB LAB_X25_Y10 1 " "Info: 32: + IC(0.131 ns) + CELL(0.455 ns) = 7.879 ns; Loc. = LAB_X25_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan3~2'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.586 ns" { Arkanoid:inst|platform2_position~33 Arkanoid:inst|LessThan3~2 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 92 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.717 ns) + CELL(0.521 ns) 9.117 ns Arkanoid:inst\|LessThan3~3 33 COMB LAB_X23_Y10 1 " "Info: 33: + IC(0.717 ns) + CELL(0.521 ns) = 9.117 ns; Loc. = LAB_X23_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan3~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.238 ns" { Arkanoid:inst|LessThan3~2 Arkanoid:inst|LessThan3~3 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 92 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.322 ns) 10.368 ns Arkanoid:inst\|LessThan3~9 34 COMB LAB_X23_Y11 2 " "Info: 34: + IC(0.929 ns) + CELL(0.322 ns) = 10.368 ns; Loc. = LAB_X23_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|LessThan3~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.251 ns" { Arkanoid:inst|LessThan3~3 Arkanoid:inst|LessThan3~9 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 92 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.039 ns) + CELL(0.495 ns) 11.902 ns Arkanoid:inst\|Add5~1 35 COMB LAB_X26_Y11 2 " "Info: 35: + IC(1.039 ns) + CELL(0.495 ns) = 11.902 ns; Loc. = LAB_X26_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.534 ns" { Arkanoid:inst|LessThan3~9 Arkanoid:inst|Add5~1 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 11.982 ns Arkanoid:inst\|Add5~3 36 COMB LAB_X26_Y11 2 " "Info: 36: + IC(0.000 ns) + CELL(0.080 ns) = 11.982 ns; Loc. = LAB_X26_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~1 Arkanoid:inst|Add5~3 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.062 ns Arkanoid:inst\|Add5~5 37 COMB LAB_X26_Y11 2 " "Info: 37: + IC(0.000 ns) + CELL(0.080 ns) = 12.062 ns; Loc. = LAB_X26_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~3 Arkanoid:inst|Add5~5 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.142 ns Arkanoid:inst\|Add5~7 38 COMB LAB_X26_Y11 2 " "Info: 38: + IC(0.000 ns) + CELL(0.080 ns) = 12.142 ns; Loc. = LAB_X26_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~5 Arkanoid:inst|Add5~7 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.222 ns Arkanoid:inst\|Add5~9 39 COMB LAB_X26_Y11 2 " "Info: 39: + IC(0.000 ns) + CELL(0.080 ns) = 12.222 ns; Loc. = LAB_X26_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~7 Arkanoid:inst|Add5~9 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.302 ns Arkanoid:inst\|Add5~11 40 COMB LAB_X26_Y11 2 " "Info: 40: + IC(0.000 ns) + CELL(0.080 ns) = 12.302 ns; Loc. = LAB_X26_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~9 Arkanoid:inst|Add5~11 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.382 ns Arkanoid:inst\|Add5~13 41 COMB LAB_X26_Y11 2 " "Info: 41: + IC(0.000 ns) + CELL(0.080 ns) = 12.382 ns; Loc. = LAB_X26_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~11 Arkanoid:inst|Add5~13 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.462 ns Arkanoid:inst\|Add5~15 42 COMB LAB_X26_Y11 2 " "Info: 42: + IC(0.000 ns) + CELL(0.080 ns) = 12.462 ns; Loc. = LAB_X26_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~13 Arkanoid:inst|Add5~15 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.542 ns Arkanoid:inst\|Add5~17 43 COMB LAB_X26_Y11 2 " "Info: 43: + IC(0.000 ns) + CELL(0.080 ns) = 12.542 ns; Loc. = LAB_X26_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~15 Arkanoid:inst|Add5~17 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.622 ns Arkanoid:inst\|Add5~19 44 COMB LAB_X26_Y11 2 " "Info: 44: + IC(0.000 ns) + CELL(0.080 ns) = 12.622 ns; Loc. = LAB_X26_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~17 Arkanoid:inst|Add5~19 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.702 ns Arkanoid:inst\|Add5~21 45 COMB LAB_X26_Y11 2 " "Info: 45: + IC(0.000 ns) + CELL(0.080 ns) = 12.702 ns; Loc. = LAB_X26_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~19 Arkanoid:inst|Add5~21 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.782 ns Arkanoid:inst\|Add5~23 46 COMB LAB_X26_Y11 2 " "Info: 46: + IC(0.000 ns) + CELL(0.080 ns) = 12.782 ns; Loc. = LAB_X26_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~21 Arkanoid:inst|Add5~23 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.862 ns Arkanoid:inst\|Add5~25 47 COMB LAB_X26_Y11 2 " "Info: 47: + IC(0.000 ns) + CELL(0.080 ns) = 12.862 ns; Loc. = LAB_X26_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~23 Arkanoid:inst|Add5~25 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.942 ns Arkanoid:inst\|Add5~27 48 COMB LAB_X26_Y11 2 " "Info: 48: + IC(0.000 ns) + CELL(0.080 ns) = 12.942 ns; Loc. = LAB_X26_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~25 Arkanoid:inst|Add5~27 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 13.022 ns Arkanoid:inst\|Add5~29 49 COMB LAB_X26_Y11 2 " "Info: 49: + IC(0.000 ns) + CELL(0.080 ns) = 13.022 ns; Loc. = LAB_X26_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~27 Arkanoid:inst|Add5~29 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 13.102 ns Arkanoid:inst\|Add5~31 50 COMB LAB_X26_Y11 2 " "Info: 50: + IC(0.000 ns) + CELL(0.080 ns) = 13.102 ns; Loc. = LAB_X26_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~29 Arkanoid:inst|Add5~31 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.098 ns) + CELL(0.458 ns) 13.658 ns Arkanoid:inst\|Add5~32 51 COMB LAB_X26_Y10 1 " "Info: 51: + IC(0.098 ns) + CELL(0.458 ns) = 13.658 ns; Loc. = LAB_X26_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|Add5~32'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.556 ns" { Arkanoid:inst|Add5~31 Arkanoid:inst|Add5~32 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.752 ns) + CELL(0.521 ns) 14.931 ns Arkanoid:inst\|platform2_position~70 52 COMB LAB_X27_Y11 6 " "Info: 52: + IC(0.752 ns) + CELL(0.521 ns) = 14.931 ns; Loc. = LAB_X27_Y11; Fanout = 6; COMB Node = 'Arkanoid:inst\|platform2_position~70'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.273 ns" { Arkanoid:inst|Add5~32 Arkanoid:inst|platform2_position~70 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.369 ns) + CELL(0.517 ns) 16.817 ns Arkanoid:inst\|Add7~33 53 COMB LAB_X29_Y13 2 " "Info: 53: + IC(1.369 ns) + CELL(0.517 ns) = 16.817 ns; Loc. = LAB_X29_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add7~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.886 ns" { Arkanoid:inst|platform2_position~70 Arkanoid:inst|Add7~33 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 17.275 ns Arkanoid:inst\|Add7~34 54 COMB LAB_X29_Y13 2 " "Info: 54: + IC(0.000 ns) + CELL(0.458 ns) = 17.275 ns; Loc. = LAB_X29_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add7~34'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|Add7~33 Arkanoid:inst|Add7~34 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.709 ns) + CELL(0.517 ns) 18.501 ns Arkanoid:inst\|LessThan139~35 55 COMB LAB_X30_Y13 1 " "Info: 55: + IC(0.709 ns) + CELL(0.517 ns) = 18.501 ns; Loc. = LAB_X30_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.226 ns" { Arkanoid:inst|Add7~34 Arkanoid:inst|LessThan139~35 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.581 ns Arkanoid:inst\|LessThan139~37 56 COMB LAB_X30_Y13 1 " "Info: 56: + IC(0.000 ns) + CELL(0.080 ns) = 18.581 ns; Loc. = LAB_X30_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~35 Arkanoid:inst|LessThan139~37 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.661 ns Arkanoid:inst\|LessThan139~39 57 COMB LAB_X30_Y13 1 " "Info: 57: + IC(0.000 ns) + CELL(0.080 ns) = 18.661 ns; Loc. = LAB_X30_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~37 Arkanoid:inst|LessThan139~39 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.741 ns Arkanoid:inst\|LessThan139~41 58 COMB LAB_X30_Y13 1 " "Info: 58: + IC(0.000 ns) + CELL(0.080 ns) = 18.741 ns; Loc. = LAB_X30_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~39 Arkanoid:inst|LessThan139~41 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.821 ns Arkanoid:inst\|LessThan139~43 59 COMB LAB_X30_Y13 1 " "Info: 59: + IC(0.000 ns) + CELL(0.080 ns) = 18.821 ns; Loc. = LAB_X30_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~41 Arkanoid:inst|LessThan139~43 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.901 ns Arkanoid:inst\|LessThan139~45 60 COMB LAB_X30_Y13 1 " "Info: 60: + IC(0.000 ns) + CELL(0.080 ns) = 18.901 ns; Loc. = LAB_X30_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~43 Arkanoid:inst|LessThan139~45 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 18.981 ns Arkanoid:inst\|LessThan139~47 61 COMB LAB_X30_Y13 1 " "Info: 61: + IC(0.000 ns) + CELL(0.080 ns) = 18.981 ns; Loc. = LAB_X30_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~45 Arkanoid:inst|LessThan139~47 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.061 ns Arkanoid:inst\|LessThan139~49 62 COMB LAB_X30_Y13 1 " "Info: 62: + IC(0.000 ns) + CELL(0.080 ns) = 19.061 ns; Loc. = LAB_X30_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~47 Arkanoid:inst|LessThan139~49 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.141 ns Arkanoid:inst\|LessThan139~51 63 COMB LAB_X30_Y13 1 " "Info: 63: + IC(0.000 ns) + CELL(0.080 ns) = 19.141 ns; Loc. = LAB_X30_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~51'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~49 Arkanoid:inst|LessThan139~51 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.221 ns Arkanoid:inst\|LessThan139~53 64 COMB LAB_X30_Y13 1 " "Info: 64: + IC(0.000 ns) + CELL(0.080 ns) = 19.221 ns; Loc. = LAB_X30_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~53'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~51 Arkanoid:inst|LessThan139~53 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.301 ns Arkanoid:inst\|LessThan139~55 65 COMB LAB_X30_Y13 1 " "Info: 65: + IC(0.000 ns) + CELL(0.080 ns) = 19.301 ns; Loc. = LAB_X30_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~55'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~53 Arkanoid:inst|LessThan139~55 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.381 ns Arkanoid:inst\|LessThan139~57 66 COMB LAB_X30_Y13 1 " "Info: 66: + IC(0.000 ns) + CELL(0.080 ns) = 19.381 ns; Loc. = LAB_X30_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~57'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~55 Arkanoid:inst|LessThan139~57 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.461 ns Arkanoid:inst\|LessThan139~59 67 COMB LAB_X30_Y13 1 " "Info: 67: + IC(0.000 ns) + CELL(0.080 ns) = 19.461 ns; Loc. = LAB_X30_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~59'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~57 Arkanoid:inst|LessThan139~59 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.541 ns Arkanoid:inst\|LessThan139~61 68 COMB LAB_X30_Y13 1 " "Info: 68: + IC(0.000 ns) + CELL(0.080 ns) = 19.541 ns; Loc. = LAB_X30_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~61'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~59 Arkanoid:inst|LessThan139~61 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 19.999 ns Arkanoid:inst\|LessThan139~62 69 COMB LAB_X30_Y13 4 " "Info: 69: + IC(0.000 ns) + CELL(0.458 ns) = 19.999 ns; Loc. = LAB_X30_Y13; Fanout = 4; COMB Node = 'Arkanoid:inst\|LessThan139~62'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|LessThan139~61 Arkanoid:inst|LessThan139~62 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.704 ns) + CELL(0.521 ns) 22.224 ns Arkanoid:inst\|always2~4 70 COMB LAB_X25_Y18 2 " "Info: 70: + IC(1.704 ns) + CELL(0.521 ns) = 22.224 ns; Loc. = LAB_X25_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|always2~4'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.225 ns" { Arkanoid:inst|LessThan139~62 Arkanoid:inst|always2~4 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.410 ns) + CELL(0.495 ns) 24.129 ns Arkanoid:inst\|Add9~1 71 COMB LAB_X16_Y18 2 " "Info: 71: + IC(1.410 ns) + CELL(0.495 ns) = 24.129 ns; Loc. = LAB_X16_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.905 ns" { Arkanoid:inst|always2~4 Arkanoid:inst|Add9~1 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.209 ns Arkanoid:inst\|Add9~3 72 COMB LAB_X16_Y18 2 " "Info: 72: + IC(0.000 ns) + CELL(0.080 ns) = 24.209 ns; Loc. = LAB_X16_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~1 Arkanoid:inst|Add9~3 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.289 ns Arkanoid:inst\|Add9~5 73 COMB LAB_X16_Y18 2 " "Info: 73: + IC(0.000 ns) + CELL(0.080 ns) = 24.289 ns; Loc. = LAB_X16_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~3 Arkanoid:inst|Add9~5 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.369 ns Arkanoid:inst\|Add9~7 74 COMB LAB_X16_Y18 2 " "Info: 74: + IC(0.000 ns) + CELL(0.080 ns) = 24.369 ns; Loc. = LAB_X16_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~5 Arkanoid:inst|Add9~7 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.449 ns Arkanoid:inst\|Add9~9 75 COMB LAB_X16_Y18 2 " "Info: 75: + IC(0.000 ns) + CELL(0.080 ns) = 24.449 ns; Loc. = LAB_X16_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~7 Arkanoid:inst|Add9~9 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.529 ns Arkanoid:inst\|Add9~11 76 COMB LAB_X16_Y18 2 " "Info: 76: + IC(0.000 ns) + CELL(0.080 ns) = 24.529 ns; Loc. = LAB_X16_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~9 Arkanoid:inst|Add9~11 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.609 ns Arkanoid:inst\|Add9~13 77 COMB LAB_X16_Y18 2 " "Info: 77: + IC(0.000 ns) + CELL(0.080 ns) = 24.609 ns; Loc. = LAB_X16_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~11 Arkanoid:inst|Add9~13 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.689 ns Arkanoid:inst\|Add9~15 78 COMB LAB_X16_Y18 2 " "Info: 78: + IC(0.000 ns) + CELL(0.080 ns) = 24.689 ns; Loc. = LAB_X16_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~13 Arkanoid:inst|Add9~15 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.769 ns Arkanoid:inst\|Add9~17 79 COMB LAB_X16_Y18 2 " "Info: 79: + IC(0.000 ns) + CELL(0.080 ns) = 24.769 ns; Loc. = LAB_X16_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~15 Arkanoid:inst|Add9~17 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.849 ns Arkanoid:inst\|Add9~19 80 COMB LAB_X16_Y18 2 " "Info: 80: + IC(0.000 ns) + CELL(0.080 ns) = 24.849 ns; Loc. = LAB_X16_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~17 Arkanoid:inst|Add9~19 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.929 ns Arkanoid:inst\|Add9~21 81 COMB LAB_X16_Y18 2 " "Info: 81: + IC(0.000 ns) + CELL(0.080 ns) = 24.929 ns; Loc. = LAB_X16_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~19 Arkanoid:inst|Add9~21 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.009 ns Arkanoid:inst\|Add9~23 82 COMB LAB_X16_Y18 2 " "Info: 82: + IC(0.000 ns) + CELL(0.080 ns) = 25.009 ns; Loc. = LAB_X16_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~21 Arkanoid:inst|Add9~23 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.089 ns Arkanoid:inst\|Add9~25 83 COMB LAB_X16_Y18 2 " "Info: 83: + IC(0.000 ns) + CELL(0.080 ns) = 25.089 ns; Loc. = LAB_X16_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~23 Arkanoid:inst|Add9~25 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.169 ns Arkanoid:inst\|Add9~27 84 COMB LAB_X16_Y18 2 " "Info: 84: + IC(0.000 ns) + CELL(0.080 ns) = 25.169 ns; Loc. = LAB_X16_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~25 Arkanoid:inst|Add9~27 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.249 ns Arkanoid:inst\|Add9~29 85 COMB LAB_X16_Y18 2 " "Info: 85: + IC(0.000 ns) + CELL(0.080 ns) = 25.249 ns; Loc. = LAB_X16_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~27 Arkanoid:inst|Add9~29 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.329 ns Arkanoid:inst\|Add9~31 86 COMB LAB_X16_Y18 2 " "Info: 86: + IC(0.000 ns) + CELL(0.080 ns) = 25.329 ns; Loc. = LAB_X16_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~29 Arkanoid:inst|Add9~31 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.098 ns) + CELL(0.080 ns) 25.507 ns Arkanoid:inst\|Add9~33 87 COMB LAB_X16_Y17 2 " "Info: 87: + IC(0.098 ns) + CELL(0.080 ns) = 25.507 ns; Loc. = LAB_X16_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { Arkanoid:inst|Add9~31 Arkanoid:inst|Add9~33 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.587 ns Arkanoid:inst\|Add9~35 88 COMB LAB_X16_Y17 2 " "Info: 88: + IC(0.000 ns) + CELL(0.080 ns) = 25.587 ns; Loc. = LAB_X16_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~33 Arkanoid:inst|Add9~35 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.667 ns Arkanoid:inst\|Add9~37 89 COMB LAB_X16_Y17 2 " "Info: 89: + IC(0.000 ns) + CELL(0.080 ns) = 25.667 ns; Loc. = LAB_X16_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~35 Arkanoid:inst|Add9~37 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.747 ns Arkanoid:inst\|Add9~39 90 COMB LAB_X16_Y17 2 " "Info: 90: + IC(0.000 ns) + CELL(0.080 ns) = 25.747 ns; Loc. = LAB_X16_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~37 Arkanoid:inst|Add9~39 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.827 ns Arkanoid:inst\|Add9~41 91 COMB LAB_X16_Y17 2 " "Info: 91: + IC(0.000 ns) + CELL(0.080 ns) = 25.827 ns; Loc. = LAB_X16_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~39 Arkanoid:inst|Add9~41 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.907 ns Arkanoid:inst\|Add9~43 92 COMB LAB_X16_Y17 2 " "Info: 92: + IC(0.000 ns) + CELL(0.080 ns) = 25.907 ns; Loc. = LAB_X16_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~41 Arkanoid:inst|Add9~43 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.987 ns Arkanoid:inst\|Add9~45 93 COMB LAB_X16_Y17 2 " "Info: 93: + IC(0.000 ns) + CELL(0.080 ns) = 25.987 ns; Loc. = LAB_X16_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~43 Arkanoid:inst|Add9~45 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 26.067 ns Arkanoid:inst\|Add9~47 94 COMB LAB_X16_Y17 2 " "Info: 94: + IC(0.000 ns) + CELL(0.080 ns) = 26.067 ns; Loc. = LAB_X16_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~45 Arkanoid:inst|Add9~47 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 26.147 ns Arkanoid:inst\|Add9~49 95 COMB LAB_X16_Y17 2 " "Info: 95: + IC(0.000 ns) + CELL(0.080 ns) = 26.147 ns; Loc. = LAB_X16_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~47 Arkanoid:inst|Add9~49 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 26.227 ns Arkanoid:inst\|Add9~51 96 COMB LAB_X16_Y17 2 " "Info: 96: + IC(0.000 ns) + CELL(0.080 ns) = 26.227 ns; Loc. = LAB_X16_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~51'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~49 Arkanoid:inst|Add9~51 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 26.307 ns Arkanoid:inst\|Add9~53 97 COMB LAB_X16_Y17 2 " "Info: 97: + IC(0.000 ns) + CELL(0.080 ns) = 26.307 ns; Loc. = LAB_X16_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~53'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~51 Arkanoid:inst|Add9~53 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 26.387 ns Arkanoid:inst\|Add9~55 98 COMB LAB_X16_Y17 2 " "Info: 98: + IC(0.000 ns) + CELL(0.080 ns) = 26.387 ns; Loc. = LAB_X16_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~55'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~53 Arkanoid:inst|Add9~55 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 26.467 ns Arkanoid:inst\|Add9~57 99 COMB LAB_X16_Y17 2 " "Info: 99: + IC(0.000 ns) + CELL(0.080 ns) = 26.467 ns; Loc. = LAB_X16_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~57'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~55 Arkanoid:inst|Add9~57 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 26.547 ns Arkanoid:inst\|Add9~59 100 COMB LAB_X16_Y17 2 " "Info: 100: + IC(0.000 ns) + CELL(0.080 ns) = 26.547 ns; Loc. = LAB_X16_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~59'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~57 Arkanoid:inst|Add9~59 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 26.627 ns Arkanoid:inst\|Add9~61 101 COMB LAB_X16_Y17 1 " "Info: 101: + IC(0.000 ns) + CELL(0.080 ns) = 26.627 ns; Loc. = LAB_X16_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst\|Add9~61'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~59 Arkanoid:inst|Add9~61 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 27.085 ns Arkanoid:inst\|Add9~63 102 COMB LAB_X16_Y17 3 " "Info: 102: + IC(0.000 ns) + CELL(0.458 ns) = 27.085 ns; Loc. = LAB_X16_Y17; Fanout = 3; COMB Node = 'Arkanoid:inst\|Add9~63'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|Add9~61 Arkanoid:inst|Add9~63 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.521 ns) 28.335 ns Arkanoid:inst\|lpm_divide:Mod0\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[0\]~0 103 COMB LAB_X16_Y16 4 " "Info: 103: + IC(0.729 ns) + CELL(0.521 ns) = 28.335 ns; Loc. = LAB_X16_Y16; Fanout = 4; COMB Node = 'Arkanoid:inst\|lpm_divide:Mod0\|lpm_divide_ako:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[0\]~0'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.250 ns" { Arkanoid:inst|Add9~63 Arkanoid:inst|lpm_divide:Mod0|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[0]~0 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.393 ns) + CELL(0.495 ns) 30.223 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~1 104 COMB LAB_X19_Y18 2 " "Info: 104: + IC(1.393 ns) + CELL(0.495 ns) = 30.223 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.888 ns" { Arkanoid:inst|lpm_divide:Mod0|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[0]~0 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~1 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.303 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~3 105 COMB LAB_X19_Y18 2 " "Info: 105: + IC(0.000 ns) + CELL(0.080 ns) = 30.303 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.383 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~5 106 COMB LAB_X19_Y18 2 " "Info: 106: + IC(0.000 ns) + CELL(0.080 ns) = 30.383 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.463 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~7 107 COMB LAB_X19_Y18 2 " "Info: 107: + IC(0.000 ns) + CELL(0.080 ns) = 30.463 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.543 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~9 108 COMB LAB_X19_Y18 2 " "Info: 108: + IC(0.000 ns) + CELL(0.080 ns) = 30.543 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.623 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~11 109 COMB LAB_X19_Y18 2 " "Info: 109: + IC(0.000 ns) + CELL(0.080 ns) = 30.623 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.703 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~13 110 COMB LAB_X19_Y18 2 " "Info: 110: + IC(0.000 ns) + CELL(0.080 ns) = 30.703 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.783 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~15 111 COMB LAB_X19_Y18 2 " "Info: 111: + IC(0.000 ns) + CELL(0.080 ns) = 30.783 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.863 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~17 112 COMB LAB_X19_Y18 2 " "Info: 112: + IC(0.000 ns) + CELL(0.080 ns) = 30.863 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.943 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~19 113 COMB LAB_X19_Y18 2 " "Info: 113: + IC(0.000 ns) + CELL(0.080 ns) = 30.943 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.023 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~21 114 COMB LAB_X19_Y18 2 " "Info: 114: + IC(0.000 ns) + CELL(0.080 ns) = 31.023 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.103 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~23 115 COMB LAB_X19_Y18 2 " "Info: 115: + IC(0.000 ns) + CELL(0.080 ns) = 31.103 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.183 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~25 116 COMB LAB_X19_Y18 2 " "Info: 116: + IC(0.000 ns) + CELL(0.080 ns) = 31.183 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.263 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~27 117 COMB LAB_X19_Y18 2 " "Info: 117: + IC(0.000 ns) + CELL(0.080 ns) = 31.263 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.343 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~29 118 COMB LAB_X19_Y18 2 " "Info: 118: + IC(0.000 ns) + CELL(0.080 ns) = 31.343 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.098 ns) + CELL(0.080 ns) 31.521 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~31 119 COMB LAB_X19_Y17 2 " "Info: 119: + IC(0.098 ns) + CELL(0.080 ns) = 31.521 ns; Loc. = LAB_X19_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.601 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~33 120 COMB LAB_X19_Y17 2 " "Info: 120: + IC(0.000 ns) + CELL(0.080 ns) = 31.601 ns; Loc. = LAB_X19_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.681 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~35 121 COMB LAB_X19_Y17 2 " "Info: 121: + IC(0.000 ns) + CELL(0.080 ns) = 31.681 ns; Loc. = LAB_X19_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.761 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~37 122 COMB LAB_X19_Y17 2 " "Info: 122: + IC(0.000 ns) + CELL(0.080 ns) = 31.761 ns; Loc. = LAB_X19_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.841 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~39 123 COMB LAB_X19_Y17 2 " "Info: 123: + IC(0.000 ns) + CELL(0.080 ns) = 31.841 ns; Loc. = LAB_X19_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.921 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~41 124 COMB LAB_X19_Y17 2 " "Info: 124: + IC(0.000 ns) + CELL(0.080 ns) = 31.921 ns; Loc. = LAB_X19_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.001 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~43 125 COMB LAB_X19_Y17 2 " "Info: 125: + IC(0.000 ns) + CELL(0.080 ns) = 32.001 ns; Loc. = LAB_X19_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.081 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~45 126 COMB LAB_X19_Y17 2 " "Info: 126: + IC(0.000 ns) + CELL(0.080 ns) = 32.081 ns; Loc. = LAB_X19_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.161 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~47 127 COMB LAB_X19_Y17 2 " "Info: 127: + IC(0.000 ns) + CELL(0.080 ns) = 32.161 ns; Loc. = LAB_X19_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.241 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~49 128 COMB LAB_X19_Y17 2 " "Info: 128: + IC(0.000 ns) + CELL(0.080 ns) = 32.241 ns; Loc. = LAB_X19_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.321 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~51 129 COMB LAB_X19_Y17 2 " "Info: 129: + IC(0.000 ns) + CELL(0.080 ns) = 32.321 ns; Loc. = LAB_X19_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~51'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.401 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~53 130 COMB LAB_X19_Y17 2 " "Info: 130: + IC(0.000 ns) + CELL(0.080 ns) = 32.401 ns; Loc. = LAB_X19_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~53'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.481 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~55 131 COMB LAB_X19_Y17 2 " "Info: 131: + IC(0.000 ns) + CELL(0.080 ns) = 32.481 ns; Loc. = LAB_X19_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~55'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 32.939 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~56 132 COMB LAB_X19_Y17 4 " "Info: 132: + IC(0.000 ns) + CELL(0.458 ns) = 32.939 ns; Loc. = LAB_X19_Y17; Fanout = 4; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~56'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~56 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.681 ns) + CELL(0.517 ns) 35.137 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[1\]~1 133 COMB LAB_X25_Y15 2 " "Info: 133: + IC(1.681 ns) + CELL(0.517 ns) = 35.137 ns; Loc. = LAB_X25_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.198 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~56 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 141 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 35.217 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[2\]~3 134 COMB LAB_X25_Y15 2 " "Info: 134: + IC(0.000 ns) + CELL(0.080 ns) = 35.217 ns; Loc. = LAB_X25_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 141 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 35.297 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[3\]~5 135 COMB LAB_X25_Y15 1 " "Info: 135: + IC(0.000 ns) + CELL(0.080 ns) = 35.297 ns; Loc. = LAB_X25_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 141 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 35.755 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[4\]~6 136 COMB LAB_X25_Y15 14 " "Info: 136: + IC(0.000 ns) + CELL(0.458 ns) = 35.755 ns; Loc. = LAB_X25_Y15; Fanout = 14; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[4\]~6'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 141 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.755 ns) + CELL(0.177 ns) 36.687 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[18\]~111 137 COMB LAB_X24_Y15 2 " "Info: 137: + IC(0.755 ns) + CELL(0.177 ns) = 36.687 ns; Loc. = LAB_X24_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[18\]~111'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.932 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[18]~111 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.495 ns) 37.914 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[1\]~1 138 COMB LAB_X25_Y15 2 " "Info: 138: + IC(0.732 ns) + CELL(0.495 ns) = 37.914 ns; Loc. = LAB_X25_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.227 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[18]~111 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 37.994 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[2\]~3 139 COMB LAB_X25_Y15 2 " "Info: 139: + IC(0.000 ns) + CELL(0.080 ns) = 37.994 ns; Loc. = LAB_X25_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 38.074 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[3\]~5 140 COMB LAB_X25_Y15 2 " "Info: 140: + IC(0.000 ns) + CELL(0.080 ns) = 38.074 ns; Loc. = LAB_X25_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 38.154 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[4\]~7 141 COMB LAB_X25_Y15 1 " "Info: 141: + IC(0.000 ns) + CELL(0.080 ns) = 38.154 ns; Loc. = LAB_X25_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 38.612 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[5\]~8 142 COMB LAB_X25_Y15 17 " "Info: 142: + IC(0.000 ns) + CELL(0.458 ns) = 38.612 ns; Loc. = LAB_X25_Y15; Fanout = 17; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[5\]~8'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.112 ns) + CELL(0.177 ns) 39.901 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[26\]~117 143 COMB LAB_X25_Y19 2 " "Info: 143: + IC(1.112 ns) + CELL(0.177 ns) = 39.901 ns; Loc. = LAB_X25_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[26\]~117'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.289 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[26]~117 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.112 ns) + CELL(0.495 ns) 41.508 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[3\]~5 144 COMB LAB_X24_Y15 2 " "Info: 144: + IC(1.112 ns) + CELL(0.495 ns) = 41.508 ns; Loc. = LAB_X24_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.607 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[26]~117 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 41.588 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[4\]~7 145 COMB LAB_X24_Y15 1 " "Info: 145: + IC(0.000 ns) + CELL(0.080 ns) = 41.588 ns; Loc. = LAB_X24_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 41.668 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[5\]~9 146 COMB LAB_X24_Y15 1 " "Info: 146: + IC(0.000 ns) + CELL(0.080 ns) = 41.668 ns; Loc. = LAB_X24_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 42.126 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[6\]~10 147 COMB LAB_X24_Y15 16 " "Info: 147: + IC(0.000 ns) + CELL(0.458 ns) = 42.126 ns; Loc. = LAB_X24_Y15; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.177 ns) 43.392 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[30\]~129 148 COMB LAB_X23_Y12 2 " "Info: 148: + IC(1.089 ns) + CELL(0.177 ns) = 43.392 ns; Loc. = LAB_X23_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[30\]~129'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.266 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[30]~129 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.495 ns) 44.976 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[1\]~1 149 COMB LAB_X23_Y15 2 " "Info: 149: + IC(1.089 ns) + CELL(0.495 ns) = 44.976 ns; Loc. = LAB_X23_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.584 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[30]~129 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 45.056 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[2\]~3 150 COMB LAB_X23_Y15 2 " "Info: 150: + IC(0.000 ns) + CELL(0.080 ns) = 45.056 ns; Loc. = LAB_X23_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 45.136 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[3\]~5 151 COMB LAB_X23_Y15 2 " "Info: 151: + IC(0.000 ns) + CELL(0.080 ns) = 45.136 ns; Loc. = LAB_X23_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 45.216 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[4\]~7 152 COMB LAB_X23_Y15 1 " "Info: 152: + IC(0.000 ns) + CELL(0.080 ns) = 45.216 ns; Loc. = LAB_X23_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 45.296 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[5\]~9 153 COMB LAB_X23_Y15 1 " "Info: 153: + IC(0.000 ns) + CELL(0.080 ns) = 45.296 ns; Loc. = LAB_X23_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 45.754 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[6\]~10 154 COMB LAB_X23_Y15 16 " "Info: 154: + IC(0.000 ns) + CELL(0.458 ns) = 45.754 ns; Loc. = LAB_X23_Y15; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.177 ns) 47.020 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[36\]~137 155 COMB LAB_X22_Y12 2 " "Info: 155: + IC(1.089 ns) + CELL(0.177 ns) = 47.020 ns; Loc. = LAB_X22_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[36\]~137'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.266 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~137 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.495 ns) 48.247 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[1\]~1 156 COMB LAB_X23_Y12 2 " "Info: 156: + IC(0.732 ns) + CELL(0.495 ns) = 48.247 ns; Loc. = LAB_X23_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.227 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~137 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 48.327 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[2\]~3 157 COMB LAB_X23_Y12 2 " "Info: 157: + IC(0.000 ns) + CELL(0.080 ns) = 48.327 ns; Loc. = LAB_X23_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 48.407 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[3\]~5 158 COMB LAB_X23_Y12 2 " "Info: 158: + IC(0.000 ns) + CELL(0.080 ns) = 48.407 ns; Loc. = LAB_X23_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 48.487 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[4\]~7 159 COMB LAB_X23_Y12 1 " "Info: 159: + IC(0.000 ns) + CELL(0.080 ns) = 48.487 ns; Loc. = LAB_X23_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 48.567 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[5\]~9 160 COMB LAB_X23_Y12 1 " "Info: 160: + IC(0.000 ns) + CELL(0.080 ns) = 48.567 ns; Loc. = LAB_X23_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 49.025 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[6\]~10 161 COMB LAB_X23_Y12 16 " "Info: 161: + IC(0.000 ns) + CELL(0.458 ns) = 49.025 ns; Loc. = LAB_X23_Y12; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.040 ns) + CELL(0.177 ns) 50.242 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[42\]~145 162 COMB LAB_X19_Y12 2 " "Info: 162: + IC(1.040 ns) + CELL(0.177 ns) = 50.242 ns; Loc. = LAB_X19_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[42\]~145'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.217 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[42]~145 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.039 ns) + CELL(0.495 ns) 51.776 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[1\]~1 163 COMB LAB_X22_Y12 2 " "Info: 163: + IC(1.039 ns) + CELL(0.495 ns) = 51.776 ns; Loc. = LAB_X22_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.534 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[42]~145 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 51.856 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[2\]~3 164 COMB LAB_X22_Y12 2 " "Info: 164: + IC(0.000 ns) + CELL(0.080 ns) = 51.856 ns; Loc. = LAB_X22_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 51.936 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[3\]~5 165 COMB LAB_X22_Y12 2 " "Info: 165: + IC(0.000 ns) + CELL(0.080 ns) = 51.936 ns; Loc. = LAB_X22_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 52.016 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[4\]~7 166 COMB LAB_X22_Y12 1 " "Info: 166: + IC(0.000 ns) + CELL(0.080 ns) = 52.016 ns; Loc. = LAB_X22_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 52.096 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[5\]~9 167 COMB LAB_X22_Y12 1 " "Info: 167: + IC(0.000 ns) + CELL(0.080 ns) = 52.096 ns; Loc. = LAB_X22_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 52.554 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[6\]~10 168 COMB LAB_X22_Y12 16 " "Info: 168: + IC(0.000 ns) + CELL(0.458 ns) = 52.554 ns; Loc. = LAB_X22_Y12; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.402 ns) + CELL(0.177 ns) 54.133 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[48\]~153 169 COMB LAB_X18_Y8 2 " "Info: 169: + IC(1.402 ns) + CELL(0.177 ns) = 54.133 ns; Loc. = LAB_X18_Y8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[48\]~153'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.579 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[48]~153 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.495 ns) 55.717 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[1\]~1 170 COMB LAB_X19_Y12 2 " "Info: 170: + IC(1.089 ns) + CELL(0.495 ns) = 55.717 ns; Loc. = LAB_X19_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.584 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[48]~153 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 55.797 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[2\]~3 171 COMB LAB_X19_Y12 2 " "Info: 171: + IC(0.000 ns) + CELL(0.080 ns) = 55.797 ns; Loc. = LAB_X19_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 55.877 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[3\]~5 172 COMB LAB_X19_Y12 2 " "Info: 172: + IC(0.000 ns) + CELL(0.080 ns) = 55.877 ns; Loc. = LAB_X19_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 55.957 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[4\]~7 173 COMB LAB_X19_Y12 1 " "Info: 173: + IC(0.000 ns) + CELL(0.080 ns) = 55.957 ns; Loc. = LAB_X19_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 56.037 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[5\]~9 174 COMB LAB_X19_Y12 1 " "Info: 174: + IC(0.000 ns) + CELL(0.080 ns) = 56.037 ns; Loc. = LAB_X19_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 56.495 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[6\]~10 175 COMB LAB_X19_Y12 16 " "Info: 175: + IC(0.000 ns) + CELL(0.458 ns) = 56.495 ns; Loc. = LAB_X19_Y12; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.895 ns) + CELL(0.319 ns) 57.709 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[57\]~339 176 COMB LAB_X22_Y12 3 " "Info: 176: + IC(0.895 ns) + CELL(0.319 ns) = 57.709 ns; Loc. = LAB_X22_Y12; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[57\]~339'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.214 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[57]~339 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.376 ns) + CELL(0.517 ns) 59.602 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[4\]~7 177 COMB LAB_X19_Y8 1 " "Info: 177: + IC(1.376 ns) + CELL(0.517 ns) = 59.602 ns; Loc. = LAB_X19_Y8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.893 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[57]~339 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 36 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 59.682 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[5\]~9 178 COMB LAB_X19_Y8 1 " "Info: 178: + IC(0.000 ns) + CELL(0.080 ns) = 59.682 ns; Loc. = LAB_X19_Y8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 36 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 60.140 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[6\]~10 179 COMB LAB_X19_Y8 16 " "Info: 179: + IC(0.000 ns) + CELL(0.458 ns) = 60.140 ns; Loc. = LAB_X19_Y8; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 36 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.177 ns) 61.390 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[60\]~169 180 COMB LAB_X19_Y7 2 " "Info: 180: + IC(1.073 ns) + CELL(0.177 ns) = 61.390 ns; Loc. = LAB_X19_Y7; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[60\]~169'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.250 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[60]~169 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.495 ns) 62.958 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[1\]~1 181 COMB LAB_X18_Y8 2 " "Info: 181: + IC(1.073 ns) + CELL(0.495 ns) = 62.958 ns; Loc. = LAB_X18_Y8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.568 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[60]~169 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 63.038 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[2\]~3 182 COMB LAB_X18_Y8 2 " "Info: 182: + IC(0.000 ns) + CELL(0.080 ns) = 63.038 ns; Loc. = LAB_X18_Y8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 63.118 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[3\]~5 183 COMB LAB_X18_Y8 2 " "Info: 183: + IC(0.000 ns) + CELL(0.080 ns) = 63.118 ns; Loc. = LAB_X18_Y8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 63.198 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[4\]~7 184 COMB LAB_X18_Y8 1 " "Info: 184: + IC(0.000 ns) + CELL(0.080 ns) = 63.198 ns; Loc. = LAB_X18_Y8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 63.278 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[5\]~9 185 COMB LAB_X18_Y8 1 " "Info: 185: + IC(0.000 ns) + CELL(0.080 ns) = 63.278 ns; Loc. = LAB_X18_Y8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 63.736 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[6\]~10 186 COMB LAB_X18_Y8 16 " "Info: 186: + IC(0.000 ns) + CELL(0.458 ns) = 63.736 ns; Loc. = LAB_X18_Y8; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.381 ns) + CELL(0.177 ns) 65.294 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[66\]~177 187 COMB LAB_X20_Y7 2 " "Info: 187: + IC(1.381 ns) + CELL(0.177 ns) = 65.294 ns; Loc. = LAB_X20_Y7; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[66\]~177'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.558 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[66]~177 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.495 ns) 66.862 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[1\]~1 188 COMB LAB_X19_Y8 2 " "Info: 188: + IC(1.073 ns) + CELL(0.495 ns) = 66.862 ns; Loc. = LAB_X19_Y8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.568 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[66]~177 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 66.942 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[2\]~3 189 COMB LAB_X19_Y8 2 " "Info: 189: + IC(0.000 ns) + CELL(0.080 ns) = 66.942 ns; Loc. = LAB_X19_Y8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 67.022 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[3\]~5 190 COMB LAB_X19_Y8 2 " "Info: 190: + IC(0.000 ns) + CELL(0.080 ns) = 67.022 ns; Loc. = LAB_X19_Y8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 67.102 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[4\]~7 191 COMB LAB_X19_Y8 1 " "Info: 191: + IC(0.000 ns) + CELL(0.080 ns) = 67.102 ns; Loc. = LAB_X19_Y8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 67.182 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[5\]~9 192 COMB LAB_X19_Y8 1 " "Info: 192: + IC(0.000 ns) + CELL(0.080 ns) = 67.182 ns; Loc. = LAB_X19_Y8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 67.640 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[6\]~10 193 COMB LAB_X19_Y8 16 " "Info: 193: + IC(0.000 ns) + CELL(0.458 ns) = 67.640 ns; Loc. = LAB_X19_Y8; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.177 ns) 68.890 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[72\]~185 194 COMB LAB_X19_Y7 2 " "Info: 194: + IC(1.073 ns) + CELL(0.177 ns) = 68.890 ns; Loc. = LAB_X19_Y7; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[72\]~185'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.250 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[72]~185 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.495 ns) 69.883 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[1\]~1 195 COMB LAB_X19_Y7 2 " "Info: 195: + IC(0.498 ns) + CELL(0.495 ns) = 69.883 ns; Loc. = LAB_X19_Y7; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.993 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[72]~185 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 51 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 69.963 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[2\]~3 196 COMB LAB_X19_Y7 2 " "Info: 196: + IC(0.000 ns) + CELL(0.080 ns) = 69.963 ns; Loc. = LAB_X19_Y7; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 51 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 70.043 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[3\]~5 197 COMB LAB_X19_Y7 2 " "Info: 197: + IC(0.000 ns) + CELL(0.080 ns) = 70.043 ns; Loc. = LAB_X19_Y7; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 51 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 70.123 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[4\]~7 198 COMB LAB_X19_Y7 1 " "Info: 198: + IC(0.000 ns) + CELL(0.080 ns) = 70.123 ns; Loc. = LAB_X19_Y7; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 51 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 70.203 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[5\]~9 199 COMB LAB_X19_Y7 1 " "Info: 199: + IC(0.000 ns) + CELL(0.080 ns) = 70.203 ns; Loc. = LAB_X19_Y7; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 51 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 70.661 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[6\]~10 200 COMB LAB_X19_Y7 16 " "Info: 200: + IC(0.000 ns) + CELL(0.458 ns) = 70.661 ns; Loc. = LAB_X19_Y7; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 51 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.177 ns) 71.911 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[82\]~186 201 COMB LAB_X20_Y8 1 " "Info: 201: + IC(1.073 ns) + CELL(0.177 ns) = 71.911 ns; Loc. = LAB_X20_Y8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[82\]~186'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.250 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[82]~186 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.495 ns) 73.479 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[5\]~9 202 COMB LAB_X20_Y7 1 " "Info: 202: + IC(1.073 ns) + CELL(0.495 ns) = 73.479 ns; Loc. = LAB_X20_Y7; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.568 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[82]~186 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 56 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 73.937 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[6\]~10 203 COMB LAB_X20_Y7 16 " "Info: 203: + IC(0.000 ns) + CELL(0.458 ns) = 73.937 ns; Loc. = LAB_X20_Y7; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 56 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.177 ns) 75.187 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[88\]~194 204 COMB LAB_X20_Y8 1 " "Info: 204: + IC(1.073 ns) + CELL(0.177 ns) = 75.187 ns; Loc. = LAB_X20_Y8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[88\]~194'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.250 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[88]~194 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.084 ns) + CELL(0.495 ns) 76.766 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[5\]~9 205 COMB LAB_X19_Y6 1 " "Info: 205: + IC(1.084 ns) + CELL(0.495 ns) = 76.766 ns; Loc. = LAB_X19_Y6; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.579 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[88]~194 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 61 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 77.224 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[6\]~10 206 COMB LAB_X19_Y6 16 " "Info: 206: + IC(0.000 ns) + CELL(0.458 ns) = 77.224 ns; Loc. = LAB_X19_Y6; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 61 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.177 ns) 78.133 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[90\]~209 207 COMB LAB_X20_Y6 2 " "Info: 207: + IC(0.732 ns) + CELL(0.177 ns) = 78.133 ns; Loc. = LAB_X20_Y6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[90\]~209'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[90]~209 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.495 ns) 79.126 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[1\]~1 208 COMB LAB_X20_Y6 2 " "Info: 208: + IC(0.498 ns) + CELL(0.495 ns) = 79.126 ns; Loc. = LAB_X20_Y6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.993 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[90]~209 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 79.206 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[2\]~3 209 COMB LAB_X20_Y6 2 " "Info: 209: + IC(0.000 ns) + CELL(0.080 ns) = 79.206 ns; Loc. = LAB_X20_Y6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 79.286 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[3\]~5 210 COMB LAB_X20_Y6 2 " "Info: 210: + IC(0.000 ns) + CELL(0.080 ns) = 79.286 ns; Loc. = LAB_X20_Y6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 79.366 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[4\]~7 211 COMB LAB_X20_Y6 1 " "Info: 211: + IC(0.000 ns) + CELL(0.080 ns) = 79.366 ns; Loc. = LAB_X20_Y6; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 79.446 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[5\]~9 212 COMB LAB_X20_Y6 1 " "Info: 212: + IC(0.000 ns) + CELL(0.080 ns) = 79.446 ns; Loc. = LAB_X20_Y6; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 79.904 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[6\]~10 213 COMB LAB_X20_Y6 16 " "Info: 213: + IC(0.000 ns) + CELL(0.458 ns) = 79.904 ns; Loc. = LAB_X20_Y6; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.177 ns) 80.813 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[96\]~217 214 COMB LAB_X21_Y6 2 " "Info: 214: + IC(0.732 ns) + CELL(0.177 ns) = 80.813 ns; Loc. = LAB_X21_Y6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[96\]~217'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[96]~217 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.495 ns) 81.806 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[1\]~1 215 COMB LAB_X21_Y6 2 " "Info: 215: + IC(0.498 ns) + CELL(0.495 ns) = 81.806 ns; Loc. = LAB_X21_Y6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.993 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[96]~217 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 81.886 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[2\]~3 216 COMB LAB_X21_Y6 2 " "Info: 216: + IC(0.000 ns) + CELL(0.080 ns) = 81.886 ns; Loc. = LAB_X21_Y6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 81.966 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[3\]~5 217 COMB LAB_X21_Y6 2 " "Info: 217: + IC(0.000 ns) + CELL(0.080 ns) = 81.966 ns; Loc. = LAB_X21_Y6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 82.046 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[4\]~7 218 COMB LAB_X21_Y6 1 " "Info: 218: + IC(0.000 ns) + CELL(0.080 ns) = 82.046 ns; Loc. = LAB_X21_Y6; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 82.126 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[5\]~9 219 COMB LAB_X21_Y6 1 " "Info: 219: + IC(0.000 ns) + CELL(0.080 ns) = 82.126 ns; Loc. = LAB_X21_Y6; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 82.584 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[6\]~10 220 COMB LAB_X21_Y6 16 " "Info: 220: + IC(0.000 ns) + CELL(0.458 ns) = 82.584 ns; Loc. = LAB_X21_Y6; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.177 ns) 83.493 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[102\]~225 221 COMB LAB_X22_Y6 2 " "Info: 221: + IC(0.732 ns) + CELL(0.177 ns) = 83.493 ns; Loc. = LAB_X22_Y6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[102\]~225'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~225 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.495 ns) 84.486 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[1\]~1 222 COMB LAB_X22_Y6 2 " "Info: 222: + IC(0.498 ns) + CELL(0.495 ns) = 84.486 ns; Loc. = LAB_X22_Y6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.993 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~225 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 84.566 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[2\]~3 223 COMB LAB_X22_Y6 2 " "Info: 223: + IC(0.000 ns) + CELL(0.080 ns) = 84.566 ns; Loc. = LAB_X22_Y6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 84.646 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[3\]~5 224 COMB LAB_X22_Y6 2 " "Info: 224: + IC(0.000 ns) + CELL(0.080 ns) = 84.646 ns; Loc. = LAB_X22_Y6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 84.726 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[4\]~7 225 COMB LAB_X22_Y6 1 " "Info: 225: + IC(0.000 ns) + CELL(0.080 ns) = 84.726 ns; Loc. = LAB_X22_Y6; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 84.806 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[5\]~9 226 COMB LAB_X22_Y6 1 " "Info: 226: + IC(0.000 ns) + CELL(0.080 ns) = 84.806 ns; Loc. = LAB_X22_Y6; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 85.264 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[6\]~10 227 COMB LAB_X22_Y6 16 " "Info: 227: + IC(0.000 ns) + CELL(0.458 ns) = 85.264 ns; Loc. = LAB_X22_Y6; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.084 ns) + CELL(0.177 ns) 86.525 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[109\]~231 228 COMB LAB_X21_Y8 2 " "Info: 228: + IC(1.084 ns) + CELL(0.177 ns) = 86.525 ns; Loc. = LAB_X21_Y8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[109\]~231'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.261 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[109]~231 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.495 ns) 87.752 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[2\]~3 229 COMB LAB_X22_Y8 2 " "Info: 229: + IC(0.732 ns) + CELL(0.495 ns) = 87.752 ns; Loc. = LAB_X22_Y8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.227 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[109]~231 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 87.832 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[3\]~5 230 COMB LAB_X22_Y8 2 " "Info: 230: + IC(0.000 ns) + CELL(0.080 ns) = 87.832 ns; Loc. = LAB_X22_Y8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 87.912 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[4\]~7 231 COMB LAB_X22_Y8 1 " "Info: 231: + IC(0.000 ns) + CELL(0.080 ns) = 87.912 ns; Loc. = LAB_X22_Y8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 87.992 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[5\]~9 232 COMB LAB_X22_Y8 1 " "Info: 232: + IC(0.000 ns) + CELL(0.080 ns) = 87.992 ns; Loc. = LAB_X22_Y8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 88.450 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[6\]~10 233 COMB LAB_X22_Y8 16 " "Info: 233: + IC(0.000 ns) + CELL(0.458 ns) = 88.450 ns; Loc. = LAB_X22_Y8; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.177 ns) 89.359 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[118\]~234 234 COMB LAB_X21_Y8 1 " "Info: 234: + IC(0.732 ns) + CELL(0.177 ns) = 89.359 ns; Loc. = LAB_X21_Y8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[118\]~234'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[118]~234 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.495 ns) 90.892 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[5\]~9 235 COMB LAB_X23_Y8 1 " "Info: 235: + IC(1.038 ns) + CELL(0.495 ns) = 90.892 ns; Loc. = LAB_X23_Y8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.533 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[118]~234 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 91 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 91.350 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[6\]~10 236 COMB LAB_X23_Y8 16 " "Info: 236: + IC(0.000 ns) + CELL(0.458 ns) = 91.350 ns; Loc. = LAB_X23_Y8; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 91 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.544 ns) 92.259 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[122\]~244 237 COMB LAB_X22_Y8 3 " "Info: 237: + IC(0.365 ns) + CELL(0.544 ns) = 92.259 ns; Loc. = LAB_X22_Y8; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[122\]~244'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~244 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.015 ns) + CELL(0.517 ns) 93.791 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[3\]~5 238 COMB LAB_X24_Y8 2 " "Info: 238: + IC(1.015 ns) + CELL(0.517 ns) = 93.791 ns; Loc. = LAB_X24_Y8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.532 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~244 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 93.871 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[4\]~7 239 COMB LAB_X24_Y8 1 " "Info: 239: + IC(0.000 ns) + CELL(0.080 ns) = 93.871 ns; Loc. = LAB_X24_Y8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 93.951 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[5\]~9 240 COMB LAB_X24_Y8 1 " "Info: 240: + IC(0.000 ns) + CELL(0.080 ns) = 93.951 ns; Loc. = LAB_X24_Y8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 94.409 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[6\]~10 241 COMB LAB_X24_Y8 16 " "Info: 241: + IC(0.000 ns) + CELL(0.458 ns) = 94.409 ns; Loc. = LAB_X24_Y8; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.544 ns) 95.318 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[128\]~252 242 COMB LAB_X23_Y8 3 " "Info: 242: + IC(0.365 ns) + CELL(0.544 ns) = 95.318 ns; Loc. = LAB_X23_Y8; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[128\]~252'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[128]~252 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.517 ns) 96.901 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[3\]~5 243 COMB LAB_X24_Y12 2 " "Info: 243: + IC(1.066 ns) + CELL(0.517 ns) = 96.901 ns; Loc. = LAB_X24_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.583 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[128]~252 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 96.981 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[4\]~7 244 COMB LAB_X24_Y12 1 " "Info: 244: + IC(0.000 ns) + CELL(0.080 ns) = 96.981 ns; Loc. = LAB_X24_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 97.061 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[5\]~9 245 COMB LAB_X24_Y12 1 " "Info: 245: + IC(0.000 ns) + CELL(0.080 ns) = 97.061 ns; Loc. = LAB_X24_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 97.519 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[6\]~10 246 COMB LAB_X24_Y12 16 " "Info: 246: + IC(0.000 ns) + CELL(0.458 ns) = 97.519 ns; Loc. = LAB_X24_Y12; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.544 ns) 98.785 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[134\]~260 247 COMB LAB_X24_Y8 3 " "Info: 247: + IC(0.722 ns) + CELL(0.544 ns) = 98.785 ns; Loc. = LAB_X24_Y8; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[134\]~260'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.266 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[134]~260 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.517 ns) 100.368 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[3\]~5 248 COMB LAB_X25_Y12 2 " "Info: 248: + IC(1.066 ns) + CELL(0.517 ns) = 100.368 ns; Loc. = LAB_X25_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.583 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[134]~260 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 100.448 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[4\]~7 249 COMB LAB_X25_Y12 1 " "Info: 249: + IC(0.000 ns) + CELL(0.080 ns) = 100.448 ns; Loc. = LAB_X25_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 100.528 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[5\]~9 250 COMB LAB_X25_Y12 1 " "Info: 250: + IC(0.000 ns) + CELL(0.080 ns) = 100.528 ns; Loc. = LAB_X25_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 100.986 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[6\]~10 251 COMB LAB_X25_Y12 16 " "Info: 251: + IC(0.000 ns) + CELL(0.458 ns) = 100.986 ns; Loc. = LAB_X25_Y12; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.388 ns) + CELL(0.544 ns) 101.918 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[140\]~268 252 COMB LAB_X24_Y12 3 " "Info: 252: + IC(0.388 ns) + CELL(0.544 ns) = 101.918 ns; Loc. = LAB_X24_Y12; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[140\]~268'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.932 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[140]~268 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.015 ns) + CELL(0.517 ns) 103.450 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[3\]~5 253 COMB LAB_X26_Y12 2 " "Info: 253: + IC(1.015 ns) + CELL(0.517 ns) = 103.450 ns; Loc. = LAB_X26_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.532 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[140]~268 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 103.530 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[4\]~7 254 COMB LAB_X26_Y12 1 " "Info: 254: + IC(0.000 ns) + CELL(0.080 ns) = 103.530 ns; Loc. = LAB_X26_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 103.610 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[5\]~9 255 COMB LAB_X26_Y12 1 " "Info: 255: + IC(0.000 ns) + CELL(0.080 ns) = 103.610 ns; Loc. = LAB_X26_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 104.068 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[6\]~10 256 COMB LAB_X26_Y12 16 " "Info: 256: + IC(0.000 ns) + CELL(0.458 ns) = 104.068 ns; Loc. = LAB_X26_Y12; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.388 ns) + CELL(0.544 ns) 105.000 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[146\]~276 257 COMB LAB_X25_Y12 3 " "Info: 257: + IC(0.388 ns) + CELL(0.544 ns) = 105.000 ns; Loc. = LAB_X25_Y12; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[146\]~276'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.932 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~276 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.517 ns) 106.555 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[3\]~5 258 COMB LAB_X27_Y12 2 " "Info: 258: + IC(1.038 ns) + CELL(0.517 ns) = 106.555 ns; Loc. = LAB_X27_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.555 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~276 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 106.635 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[4\]~7 259 COMB LAB_X27_Y12 1 " "Info: 259: + IC(0.000 ns) + CELL(0.080 ns) = 106.635 ns; Loc. = LAB_X27_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 106.715 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[5\]~9 260 COMB LAB_X27_Y12 1 " "Info: 260: + IC(0.000 ns) + CELL(0.080 ns) = 106.715 ns; Loc. = LAB_X27_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 107.173 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[6\]~10 261 COMB LAB_X27_Y12 16 " "Info: 261: + IC(0.000 ns) + CELL(0.458 ns) = 107.173 ns; Loc. = LAB_X27_Y12; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.544 ns) 108.082 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[152\]~284 262 COMB LAB_X26_Y12 3 " "Info: 262: + IC(0.365 ns) + CELL(0.544 ns) = 108.082 ns; Loc. = LAB_X26_Y12; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[152\]~284'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[152]~284 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.084 ns) + CELL(0.517 ns) 109.683 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[3\]~5 263 COMB LAB_X27_Y10 2 " "Info: 263: + IC(1.084 ns) + CELL(0.517 ns) = 109.683 ns; Loc. = LAB_X27_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.601 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[152]~284 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 109.763 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[4\]~7 264 COMB LAB_X27_Y10 1 " "Info: 264: + IC(0.000 ns) + CELL(0.080 ns) = 109.763 ns; Loc. = LAB_X27_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 109.843 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[5\]~9 265 COMB LAB_X27_Y10 1 " "Info: 265: + IC(0.000 ns) + CELL(0.080 ns) = 109.843 ns; Loc. = LAB_X27_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 110.301 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[6\]~10 266 COMB LAB_X27_Y10 16 " "Info: 266: + IC(0.000 ns) + CELL(0.458 ns) = 110.301 ns; Loc. = LAB_X27_Y10; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.717 ns) + CELL(0.544 ns) 111.562 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[158\]~292 267 COMB LAB_X27_Y12 3 " "Info: 267: + IC(0.717 ns) + CELL(0.544 ns) = 111.562 ns; Loc. = LAB_X27_Y12; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[158\]~292'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.261 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[158]~292 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.373 ns) + CELL(0.517 ns) 113.452 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[3\]~5 268 COMB LAB_X31_Y10 2 " "Info: 268: + IC(1.373 ns) + CELL(0.517 ns) = 113.452 ns; Loc. = LAB_X31_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.890 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[158]~292 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 113.532 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[4\]~7 269 COMB LAB_X31_Y10 1 " "Info: 269: + IC(0.000 ns) + CELL(0.080 ns) = 113.532 ns; Loc. = LAB_X31_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 113.612 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[5\]~9 270 COMB LAB_X31_Y10 1 " "Info: 270: + IC(0.000 ns) + CELL(0.080 ns) = 113.612 ns; Loc. = LAB_X31_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 114.070 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[6\]~10 271 COMB LAB_X31_Y10 16 " "Info: 271: + IC(0.000 ns) + CELL(0.458 ns) = 114.070 ns; Loc. = LAB_X31_Y10; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.673 ns) + CELL(0.544 ns) 115.287 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[164\]~300 272 COMB LAB_X27_Y10 3 " "Info: 272: + IC(0.673 ns) + CELL(0.544 ns) = 115.287 ns; Loc. = LAB_X27_Y10; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[164\]~300'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.217 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[164]~300 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.364 ns) + CELL(0.517 ns) 117.168 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[3\]~5 273 COMB LAB_X36_Y10 2 " "Info: 273: + IC(1.364 ns) + CELL(0.517 ns) = 117.168 ns; Loc. = LAB_X36_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.881 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[164]~300 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 117.248 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[4\]~7 274 COMB LAB_X36_Y10 1 " "Info: 274: + IC(0.000 ns) + CELL(0.080 ns) = 117.248 ns; Loc. = LAB_X36_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 117.328 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[5\]~9 275 COMB LAB_X36_Y10 1 " "Info: 275: + IC(0.000 ns) + CELL(0.080 ns) = 117.328 ns; Loc. = LAB_X36_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 117.786 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[6\]~10 276 COMB LAB_X36_Y10 16 " "Info: 276: + IC(0.000 ns) + CELL(0.458 ns) = 117.786 ns; Loc. = LAB_X36_Y10; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.691 ns) + CELL(0.544 ns) 119.021 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[170\]~308 277 COMB LAB_X31_Y10 3 " "Info: 277: + IC(0.691 ns) + CELL(0.544 ns) = 119.021 ns; Loc. = LAB_X31_Y10; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[170\]~308'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.235 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[170]~308 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.327 ns) + CELL(0.517 ns) 120.865 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[3\]~5 278 COMB LAB_X37_Y10 2 " "Info: 278: + IC(1.327 ns) + CELL(0.517 ns) = 120.865 ns; Loc. = LAB_X37_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.844 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[170]~308 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 120.945 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[4\]~7 279 COMB LAB_X37_Y10 1 " "Info: 279: + IC(0.000 ns) + CELL(0.080 ns) = 120.945 ns; Loc. = LAB_X37_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 121.025 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[5\]~9 280 COMB LAB_X37_Y10 1 " "Info: 280: + IC(0.000 ns) + CELL(0.080 ns) = 121.025 ns; Loc. = LAB_X37_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 121.483 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[6\]~10 281 COMB LAB_X37_Y10 17 " "Info: 281: + IC(0.000 ns) + CELL(0.458 ns) = 121.483 ns; Loc. = LAB_X37_Y10; Fanout = 17; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.544 ns) 122.392 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[176\]~316 282 COMB LAB_X36_Y10 3 " "Info: 282: + IC(0.365 ns) + CELL(0.544 ns) = 122.392 ns; Loc. = LAB_X36_Y10; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[176\]~316'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~316 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.517 ns) 123.975 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[3\]~5 283 COMB LAB_X37_Y14 2 " "Info: 283: + IC(1.066 ns) + CELL(0.517 ns) = 123.975 ns; Loc. = LAB_X37_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.583 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~316 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 124.055 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[4\]~7 284 COMB LAB_X37_Y14 1 " "Info: 284: + IC(0.000 ns) + CELL(0.080 ns) = 124.055 ns; Loc. = LAB_X37_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 124.135 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[5\]~9 285 COMB LAB_X37_Y14 1 " "Info: 285: + IC(0.000 ns) + CELL(0.080 ns) = 124.135 ns; Loc. = LAB_X37_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 124.593 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[6\]~10 286 COMB LAB_X37_Y14 13 " "Info: 286: + IC(0.000 ns) + CELL(0.458 ns) = 124.593 ns; Loc. = LAB_X37_Y14; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.544 ns) 125.859 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[182\]~324 287 COMB LAB_X37_Y10 1 " "Info: 287: + IC(0.722 ns) + CELL(0.544 ns) = 125.859 ns; Loc. = LAB_X37_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[182\]~324'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.266 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[182]~324 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.421 ns) + CELL(0.517 ns) 127.797 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[3\]~5 288 COMB LAB_X37_Y18 1 " "Info: 288: + IC(1.421 ns) + CELL(0.517 ns) = 127.797 ns; Loc. = LAB_X37_Y18; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.938 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[182]~324 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 127.877 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[4\]~7 289 COMB LAB_X37_Y18 1 " "Info: 289: + IC(0.000 ns) + CELL(0.080 ns) = 127.877 ns; Loc. = LAB_X37_Y18; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 127.957 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[5\]~9 290 COMB LAB_X37_Y18 1 " "Info: 290: + IC(0.000 ns) + CELL(0.080 ns) = 127.957 ns; Loc. = LAB_X37_Y18; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 128.415 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[6\]~10 291 COMB LAB_X37_Y18 3 " "Info: 291: + IC(0.000 ns) + CELL(0.458 ns) = 128.415 ns; Loc. = LAB_X37_Y18; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.933 ns) + CELL(0.517 ns) 130.865 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~1 292 COMB LAB_X23_Y22 2 " "Info: 292: + IC(1.933 ns) + CELL(0.517 ns) = 130.865 ns; Loc. = LAB_X23_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.450 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~1 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 130.945 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~3 293 COMB LAB_X23_Y22 2 " "Info: 293: + IC(0.000 ns) + CELL(0.080 ns) = 130.945 ns; Loc. = LAB_X23_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~3 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.025 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~5 294 COMB LAB_X23_Y22 2 " "Info: 294: + IC(0.000 ns) + CELL(0.080 ns) = 131.025 ns; Loc. = LAB_X23_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.105 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~7 295 COMB LAB_X23_Y22 2 " "Info: 295: + IC(0.000 ns) + CELL(0.080 ns) = 131.105 ns; Loc. = LAB_X23_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~7 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.185 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~9 296 COMB LAB_X23_Y22 2 " "Info: 296: + IC(0.000 ns) + CELL(0.080 ns) = 131.185 ns; Loc. = LAB_X23_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~9 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.265 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~11 297 COMB LAB_X23_Y22 2 " "Info: 297: + IC(0.000 ns) + CELL(0.080 ns) = 131.265 ns; Loc. = LAB_X23_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~11 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.345 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~13 298 COMB LAB_X23_Y22 2 " "Info: 298: + IC(0.000 ns) + CELL(0.080 ns) = 131.345 ns; Loc. = LAB_X23_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~13 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.425 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~15 299 COMB LAB_X23_Y22 2 " "Info: 299: + IC(0.000 ns) + CELL(0.080 ns) = 131.425 ns; Loc. = LAB_X23_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~15 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.505 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~17 300 COMB LAB_X23_Y22 2 " "Info: 300: + IC(0.000 ns) + CELL(0.080 ns) = 131.505 ns; Loc. = LAB_X23_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~17 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.585 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~19 301 COMB LAB_X23_Y22 2 " "Info: 301: + IC(0.000 ns) + CELL(0.080 ns) = 131.585 ns; Loc. = LAB_X23_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~19 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.665 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~21 302 COMB LAB_X23_Y22 2 " "Info: 302: + IC(0.000 ns) + CELL(0.080 ns) = 131.665 ns; Loc. = LAB_X23_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~21 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.745 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~23 303 COMB LAB_X23_Y22 2 " "Info: 303: + IC(0.000 ns) + CELL(0.080 ns) = 131.745 ns; Loc. = LAB_X23_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~23 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.825 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~25 304 COMB LAB_X23_Y22 2 " "Info: 304: + IC(0.000 ns) + CELL(0.080 ns) = 131.825 ns; Loc. = LAB_X23_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~25 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.905 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~27 305 COMB LAB_X23_Y22 2 " "Info: 305: + IC(0.000 ns) + CELL(0.080 ns) = 131.905 ns; Loc. = LAB_X23_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~27 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 131.985 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~29 306 COMB LAB_X23_Y22 2 " "Info: 306: + IC(0.000 ns) + CELL(0.080 ns) = 131.985 ns; Loc. = LAB_X23_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~29 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.098 ns) + CELL(0.080 ns) 132.163 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~31 307 COMB LAB_X23_Y21 2 " "Info: 307: + IC(0.098 ns) + CELL(0.080 ns) = 132.163 ns; Loc. = LAB_X23_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~31 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 132.243 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~33 308 COMB LAB_X23_Y21 2 " "Info: 308: + IC(0.000 ns) + CELL(0.080 ns) = 132.243 ns; Loc. = LAB_X23_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~33 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 132.323 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~35 309 COMB LAB_X23_Y21 2 " "Info: 309: + IC(0.000 ns) + CELL(0.080 ns) = 132.323 ns; Loc. = LAB_X23_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~33 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~35 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 132.403 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~37 310 COMB LAB_X23_Y21 2 " "Info: 310: + IC(0.000 ns) + CELL(0.080 ns) = 132.403 ns; Loc. = LAB_X23_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~35 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~37 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 132.483 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~39 311 COMB LAB_X23_Y21 2 " "Info: 311: + IC(0.000 ns) + CELL(0.080 ns) = 132.483 ns; Loc. = LAB_X23_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~37 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~39 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 132.563 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~41 312 COMB LAB_X23_Y21 2 " "Info: 312: + IC(0.000 ns) + CELL(0.080 ns) = 132.563 ns; Loc. = LAB_X23_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~39 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~41 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 132.643 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~43 313 COMB LAB_X23_Y21 2 " "Info: 313: + IC(0.000 ns) + CELL(0.080 ns) = 132.643 ns; Loc. = LAB_X23_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~41 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~43 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 132.723 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~45 314 COMB LAB_X23_Y21 2 " "Info: 314: + IC(0.000 ns) + CELL(0.080 ns) = 132.723 ns; Loc. = LAB_X23_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~43 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~45 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 132.803 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~47 315 COMB LAB_X23_Y21 2 " "Info: 315: + IC(0.000 ns) + CELL(0.080 ns) = 132.803 ns; Loc. = LAB_X23_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~45 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~47 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 132.883 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~49 316 COMB LAB_X23_Y21 2 " "Info: 316: + IC(0.000 ns) + CELL(0.080 ns) = 132.883 ns; Loc. = LAB_X23_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~47 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~49 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 132.963 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~51 317 COMB LAB_X23_Y21 2 " "Info: 317: + IC(0.000 ns) + CELL(0.080 ns) = 132.963 ns; Loc. = LAB_X23_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~51'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~49 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~51 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 133.421 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~52 318 COMB LAB_X23_Y21 1 " "Info: 318: + IC(0.000 ns) + CELL(0.458 ns) = 133.421 ns; Loc. = LAB_X23_Y21; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~52'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~51 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~52 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.178 ns) 134.331 ns Arkanoid:inst\|Equal6~2 319 COMB LAB_X22_Y21 2 " "Info: 319: + IC(0.732 ns) + CELL(0.178 ns) = 134.331 ns; Loc. = LAB_X22_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst\|Equal6~2'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.910 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~52 Arkanoid:inst|Equal6~2 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.131 ns) + CELL(0.545 ns) 135.007 ns Arkanoid:inst\|Equal6~3 320 COMB LAB_X22_Y21 1 " "Info: 320: + IC(0.131 ns) + CELL(0.545 ns) = 135.007 ns; Loc. = LAB_X22_Y21; Fanout = 1; COMB Node = 'Arkanoid:inst\|Equal6~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { Arkanoid:inst|Equal6~2 Arkanoid:inst|Equal6~3 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.354 ns) + CELL(0.322 ns) 135.683 ns Arkanoid:inst\|Equal6~7 321 COMB LAB_X22_Y21 1 " "Info: 321: + IC(0.354 ns) + CELL(0.322 ns) = 135.683 ns; Loc. = LAB_X22_Y21; Fanout = 1; COMB Node = 'Arkanoid:inst\|Equal6~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { Arkanoid:inst|Equal6~3 Arkanoid:inst|Equal6~7 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.706 ns) + CELL(0.544 ns) 136.933 ns Arkanoid:inst\|Equal6~24 322 COMB LAB_X21_Y20 5 " "Info: 322: + IC(0.706 ns) + CELL(0.544 ns) = 136.933 ns; Loc. = LAB_X21_Y20; Fanout = 5; COMB Node = 'Arkanoid:inst\|Equal6~24'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.250 ns" { Arkanoid:inst|Equal6~7 Arkanoid:inst|Equal6~24 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.178 ns) 137.609 ns Arkanoid:inst\|WideNor0~5 323 COMB LAB_X21_Y20 1 " "Info: 323: + IC(0.498 ns) + CELL(0.178 ns) = 137.609 ns; Loc. = LAB_X21_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst\|WideNor0~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { Arkanoid:inst|Equal6~24 Arkanoid:inst|WideNor0~5 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.804 ns) + CELL(0.322 ns) 139.735 ns Arkanoid:inst\|high~9 324 COMB LAB_X37_Y18 1 " "Info: 324: + IC(1.804 ns) + CELL(0.322 ns) = 139.735 ns; Loc. = LAB_X37_Y18; Fanout = 1; COMB Node = 'Arkanoid:inst\|high~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.126 ns" { Arkanoid:inst|WideNor0~5 Arkanoid:inst|high~9 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 139.831 ns Arkanoid:inst\|hex3_\[4\] 325 REG LAB_X37_Y18 1 " "Info: 325: + IC(0.000 ns) + CELL(0.096 ns) = 139.831 ns; Loc. = LAB_X37_Y18; Fanout = 1; REG Node = 'Arkanoid:inst\|hex3_\[4\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { Arkanoid:inst|high~9 Arkanoid:inst|hex3_[4] } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "67.067 ns ( 47.96 % ) " "Info: Total cell delay = 67.067 ns ( 47.96 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "72.764 ns ( 52.04 % ) " "Info: Total interconnect delay = 72.764 ns ( 52.04 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "139.831 ns" { Arkanoid:inst|button2_state Arkanoid:inst|platform2_position~4 Arkanoid:inst|platform2_position~6 Arkanoid:inst|Add4~1 Arkanoid:inst|Add4~3 Arkanoid:inst|Add4~5 Arkanoid:inst|Add4~7 Arkanoid:inst|Add4~9 Arkanoid:inst|Add4~11 Arkanoid:inst|Add4~13 Arkanoid:inst|Add4~15 Arkanoid:inst|Add4~17 Arkanoid:inst|Add4~19 Arkanoid:inst|Add4~21 Arkanoid:inst|Add4~23 Arkanoid:inst|Add4~25 Arkanoid:inst|Add4~27 Arkanoid:inst|Add4~29 Arkanoid:inst|Add4~31 Arkanoid:inst|Add4~33 Arkanoid:inst|Add4~35 Arkanoid:inst|Add4~37 Arkanoid:inst|Add4~39 Arkanoid:inst|Add4~41 Arkanoid:inst|Add4~43 Arkanoid:inst|Add4~45 Arkanoid:inst|Add4~47 Arkanoid:inst|Add4~49 Arkanoid:inst|Add4~51 Arkanoid:inst|Add4~52 Arkanoid:inst|platform2_position~33 Arkanoid:inst|LessThan3~2 Arkanoid:inst|LessThan3~3 Arkanoid:inst|LessThan3~9 Arkanoid:inst|Add5~1 Arkanoid:inst|Add5~3 Arkanoid:inst|Add5~5 Arkanoid:inst|Add5~7 Arkanoid:inst|Add5~9 Arkanoid:inst|Add5~11 Arkanoid:inst|Add5~13 Arkanoid:inst|Add5~15 Arkanoid:inst|Add5~17 Arkanoid:inst|Add5~19 Arkanoid:inst|Add5~21 Arkanoid:inst|Add5~23 Arkanoid:inst|Add5~25 Arkanoid:inst|Add5~27 Arkanoid:inst|Add5~29 Arkanoid:inst|Add5~31 Arkanoid:inst|Add5~32 Arkanoid:inst|platform2_position~70 Arkanoid:inst|Add7~33 Arkanoid:inst|Add7~34 Arkanoid:inst|LessThan139~35 Arkanoid:inst|LessThan139~37 Arkanoid:inst|LessThan139~39 Arkanoid:inst|LessThan139~41 Arkanoid:inst|LessThan139~43 Arkanoid:inst|LessThan139~45 Arkanoid:inst|LessThan139~47 Arkanoid:inst|LessThan139~49 Arkanoid:inst|LessThan139~51 Arkanoid:inst|LessThan139~53 Arkanoid:inst|LessThan139~55 Arkanoid:inst|LessThan139~57 Arkanoid:inst|LessThan139~59 Arkanoid:inst|LessThan139~61 Arkanoid:inst|LessThan139~62 Arkanoid:inst|always2~4 Arkanoid:inst|Add9~1 Arkanoid:inst|Add9~3 Arkanoid:inst|Add9~5 Arkanoid:inst|Add9~7 Arkanoid:inst|Add9~9 Arkanoid:inst|Add9~11 Arkanoid:inst|Add9~13 Arkanoid:inst|Add9~15 Arkanoid:inst|Add9~17 Arkanoid:inst|Add9~19 Arkanoid:inst|Add9~21 Arkanoid:inst|Add9~23 Arkanoid:inst|Add9~25 Arkanoid:inst|Add9~27 Arkanoid:inst|Add9~29 Arkanoid:inst|Add9~31 Arkanoid:inst|Add9~33 Arkanoid:inst|Add9~35 Arkanoid:inst|Add9~37 Arkanoid:inst|Add9~39 Arkanoid:inst|Add9~41 Arkanoid:inst|Add9~43 Arkanoid:inst|Add9~45 Arkanoid:inst|Add9~47 Arkanoid:inst|Add9~49 Arkanoid:inst|Add9~51 Arkanoid:inst|Add9~53 Arkanoid:inst|Add9~55 Arkanoid:inst|Add9~57 Arkanoid:inst|Add9~59 Arkanoid:inst|Add9~61 Arkanoid:inst|Add9~63 Arkanoid:inst|lpm_divide:Mod0|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[0]~0 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~56 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[18]~111 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[26]~117 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[30]~129 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~137 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[42]~145 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[48]~153 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[57]~339 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[60]~169 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[66]~177 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[72]~185 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[82]~186 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[88]~194 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[90]~209 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[96]~217 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~225 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[109]~231 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[118]~234 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~244 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[128]~252 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[134]~260 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[140]~268 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~276 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[152]~284 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[158]~292 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[164]~300 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[170]~308 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~316 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[182]~324 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~33 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~35 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~37 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~39 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~41 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~43 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~45 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~47 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~49 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~51 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~52 Arkanoid:inst|Equal6~2 Arkanoid:inst|Equal6~3 Arkanoid:inst|Equal6~7 Arkanoid:inst|Equal6~24 Arkanoid:inst|WideNor0~5 Arkanoid:inst|high~9 Arkanoid:inst|hex3_[4] } "NODE_NAME" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "15 " "Info: Average interconnect usage is 15% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "30 X12_Y0 X24_Y13 " "Info: Peak interconnect usage is 30% of the available device resources in the region that extends from location X12_Y0 to location X24_Y13" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:09 " "Info: Fitter routing operations ending: elapsed time is 00:00:09" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
+{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "50 " "Warning: Found 50 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "h_sync 0 " "Info: Pin \"h_sync\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "v_sync 0 " "Info: Pin \"v_sync\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "blue\[3\] 0 " "Info: Pin \"blue\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "blue\[2\] 0 " "Info: Pin \"blue\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "blue\[1\] 0 " "Info: Pin \"blue\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "blue\[0\] 0 " "Info: Pin \"blue\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "green\[3\] 0 " "Info: Pin \"green\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "green\[2\] 0 " "Info: Pin \"green\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "green\[1\] 0 " "Info: Pin \"green\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "green\[0\] 0 " "Info: Pin \"green\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[6\] 0 " "Info: Pin \"hex0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[5\] 0 " "Info: Pin \"hex0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[4\] 0 " "Info: Pin \"hex0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[3\] 0 " "Info: Pin \"hex0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[2\] 0 " "Info: Pin \"hex0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[1\] 0 " "Info: Pin \"hex0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[0\] 0 " "Info: Pin \"hex0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[6\] 0 " "Info: Pin \"hex1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[5\] 0 " "Info: Pin \"hex1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[4\] 0 " "Info: Pin \"hex1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[3\] 0 " "Info: Pin \"hex1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[2\] 0 " "Info: Pin \"hex1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[1\] 0 " "Info: Pin \"hex1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[0\] 0 " "Info: Pin \"hex1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex2\[6\] 0 " "Info: Pin \"hex2\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex2\[5\] 0 " "Info: Pin \"hex2\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex2\[4\] 0 " "Info: Pin \"hex2\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex2\[3\] 0 " "Info: Pin \"hex2\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex2\[2\] 0 " "Info: Pin \"hex2\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex2\[1\] 0 " "Info: Pin \"hex2\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex2\[0\] 0 " "Info: Pin \"hex2\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex3\[6\] 0 " "Info: Pin \"hex3\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex3\[5\] 0 " "Info: Pin \"hex3\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex3\[4\] 0 " "Info: Pin \"hex3\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex3\[3\] 0 " "Info: Pin \"hex3\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex3\[2\] 0 " "Info: Pin \"hex3\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex3\[1\] 0 " "Info: Pin \"hex3\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex3\[0\] 0 " "Info: Pin \"hex3\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[7\] 0 " "Info: Pin \"led\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[6\] 0 " "Info: Pin \"led\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[5\] 0 " "Info: Pin \"led\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[4\] 0 " "Info: Pin \"led\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[3\] 0 " "Info: Pin \"led\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[2\] 0 " "Info: Pin \"led\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[1\] 0 " "Info: Pin \"led\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[0\] 0 " "Info: Pin \"led\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "red\[3\] 0 " "Info: Pin \"red\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "red\[2\] 0 " "Info: Pin \"red\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "red\[1\] 0 " "Info: Pin \"red\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "red\[0\] 0 " "Info: Pin \"red\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "G:/Verilog/Arkanoid2PDE1/myArkanoid.fit.smsg " "Info: Generated suppressed messages file G:/Verilog/Arkanoid2PDE1/myArkanoid.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "265 " "Info: Peak virtual memory: 265 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 27 20:43:18 2012 " "Info: Processing ended: Sun May 27 20:43:18 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Info: Elapsed time: 00:00:30" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:34 " "Info: Total CPU time (on all processors): 00:00:34" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 27 20:43:19 2012 " "Info: Processing started: Sun May 27 20:43:19 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "219 " "Info: Peak virtual memory: 219 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 27 20:43:22 2012 " "Info: Processing ended: Sun May 27 20:43:22 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 27 20:43:23 2012 " "Info: Processing started: Sun May 27 20:43:23 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_50MHz " "Info: Assuming node \"clk_50MHz\" is an undefined clock" { } { { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -168 -72 96 -152 "clk_50MHz" "" } } } } { "c:/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_50MHz" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
+{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "ClockDivider:inst1\|clk25MHz_ " "Info: Detected ripple clock \"ClockDivider:inst1\|clk25MHz_\" as buffer" { } { { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } { "c:/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "ClockDivider:inst1\|clk25MHz_" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_50MHz register Arkanoid:inst\|button1_state register Arkanoid:inst\|hex3_\[5\] 7.48 MHz 133.626 ns Internal " "Info: Clock \"clk_50MHz\" has Internal fmax of 7.48 MHz between source register \"Arkanoid:inst\|button1_state\" and destination register \"Arkanoid:inst\|hex3_\[5\]\" (period= 133.626 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "133.354 ns + Longest register register " "Info: + Longest register to register delay is 133.354 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Arkanoid:inst\|button1_state 1 REG LCFF_X24_Y14_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y14_N7; Fanout = 4; REG Node = 'Arkanoid:inst\|button1_state'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { Arkanoid:inst|button1_state } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 107 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.545 ns) 0.945 ns Arkanoid:inst\|platform2_position~4 2 COMB LCCOMB_X24_Y14_N4 71 " "Info: 2: + IC(0.400 ns) + CELL(0.545 ns) = 0.945 ns; Loc. = LCCOMB_X24_Y14_N4; Fanout = 71; COMB Node = 'Arkanoid:inst\|platform2_position~4'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.945 ns" { Arkanoid:inst|button1_state Arkanoid:inst|platform2_position~4 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.941 ns) + CELL(0.178 ns) 2.064 ns Arkanoid:inst\|platform2_position~6 3 COMB LCCOMB_X23_Y10_N2 63 " "Info: 3: + IC(0.941 ns) + CELL(0.178 ns) = 2.064 ns; Loc. = LCCOMB_X23_Y10_N2; Fanout = 63; COMB Node = 'Arkanoid:inst\|platform2_position~6'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.119 ns" { Arkanoid:inst|platform2_position~4 Arkanoid:inst|platform2_position~6 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.961 ns) + CELL(0.495 ns) 3.520 ns Arkanoid:inst\|Add4~1 4 COMB LCCOMB_X24_Y11_N0 2 " "Info: 4: + IC(0.961 ns) + CELL(0.495 ns) = 3.520 ns; Loc. = LCCOMB_X24_Y11_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.456 ns" { Arkanoid:inst|platform2_position~6 Arkanoid:inst|Add4~1 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 3.600 ns Arkanoid:inst\|Add4~3 5 COMB LCCOMB_X24_Y11_N2 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 3.600 ns; Loc. = LCCOMB_X24_Y11_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~1 Arkanoid:inst|Add4~3 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 3.680 ns Arkanoid:inst\|Add4~5 6 COMB LCCOMB_X24_Y11_N4 2 " "Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 3.680 ns; Loc. = LCCOMB_X24_Y11_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~3 Arkanoid:inst|Add4~5 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 3.760 ns Arkanoid:inst\|Add4~7 7 COMB LCCOMB_X24_Y11_N6 2 " "Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 3.760 ns; Loc. = LCCOMB_X24_Y11_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~5 Arkanoid:inst|Add4~7 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 3.840 ns Arkanoid:inst\|Add4~9 8 COMB LCCOMB_X24_Y11_N8 2 " "Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 3.840 ns; Loc. = LCCOMB_X24_Y11_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~7 Arkanoid:inst|Add4~9 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 3.920 ns Arkanoid:inst\|Add4~11 9 COMB LCCOMB_X24_Y11_N10 2 " "Info: 9: + IC(0.000 ns) + CELL(0.080 ns) = 3.920 ns; Loc. = LCCOMB_X24_Y11_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~9 Arkanoid:inst|Add4~11 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.000 ns Arkanoid:inst\|Add4~13 10 COMB LCCOMB_X24_Y11_N12 2 " "Info: 10: + IC(0.000 ns) + CELL(0.080 ns) = 4.000 ns; Loc. = LCCOMB_X24_Y11_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~11 Arkanoid:inst|Add4~13 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 4.174 ns Arkanoid:inst\|Add4~15 11 COMB LCCOMB_X24_Y11_N14 2 " "Info: 11: + IC(0.000 ns) + CELL(0.174 ns) = 4.174 ns; Loc. = LCCOMB_X24_Y11_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|Add4~13 Arkanoid:inst|Add4~15 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.254 ns Arkanoid:inst\|Add4~17 12 COMB LCCOMB_X24_Y11_N16 2 " "Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 4.254 ns; Loc. = LCCOMB_X24_Y11_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~15 Arkanoid:inst|Add4~17 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.334 ns Arkanoid:inst\|Add4~19 13 COMB LCCOMB_X24_Y11_N18 2 " "Info: 13: + IC(0.000 ns) + CELL(0.080 ns) = 4.334 ns; Loc. = LCCOMB_X24_Y11_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~17 Arkanoid:inst|Add4~19 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.414 ns Arkanoid:inst\|Add4~21 14 COMB LCCOMB_X24_Y11_N20 2 " "Info: 14: + IC(0.000 ns) + CELL(0.080 ns) = 4.414 ns; Loc. = LCCOMB_X24_Y11_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~19 Arkanoid:inst|Add4~21 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.494 ns Arkanoid:inst\|Add4~23 15 COMB LCCOMB_X24_Y11_N22 2 " "Info: 15: + IC(0.000 ns) + CELL(0.080 ns) = 4.494 ns; Loc. = LCCOMB_X24_Y11_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~21 Arkanoid:inst|Add4~23 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.574 ns Arkanoid:inst\|Add4~25 16 COMB LCCOMB_X24_Y11_N24 2 " "Info: 16: + IC(0.000 ns) + CELL(0.080 ns) = 4.574 ns; Loc. = LCCOMB_X24_Y11_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~23 Arkanoid:inst|Add4~25 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.654 ns Arkanoid:inst\|Add4~27 17 COMB LCCOMB_X24_Y11_N26 2 " "Info: 17: + IC(0.000 ns) + CELL(0.080 ns) = 4.654 ns; Loc. = LCCOMB_X24_Y11_N26; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~25 Arkanoid:inst|Add4~27 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.734 ns Arkanoid:inst\|Add4~29 18 COMB LCCOMB_X24_Y11_N28 2 " "Info: 18: + IC(0.000 ns) + CELL(0.080 ns) = 4.734 ns; Loc. = LCCOMB_X24_Y11_N28; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~27 Arkanoid:inst|Add4~29 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 4.895 ns Arkanoid:inst\|Add4~31 19 COMB LCCOMB_X24_Y11_N30 2 " "Info: 19: + IC(0.000 ns) + CELL(0.161 ns) = 4.895 ns; Loc. = LCCOMB_X24_Y11_N30; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.161 ns" { Arkanoid:inst|Add4~29 Arkanoid:inst|Add4~31 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.975 ns Arkanoid:inst\|Add4~33 20 COMB LCCOMB_X24_Y10_N0 2 " "Info: 20: + IC(0.000 ns) + CELL(0.080 ns) = 4.975 ns; Loc. = LCCOMB_X24_Y10_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~31 Arkanoid:inst|Add4~33 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.055 ns Arkanoid:inst\|Add4~35 21 COMB LCCOMB_X24_Y10_N2 2 " "Info: 21: + IC(0.000 ns) + CELL(0.080 ns) = 5.055 ns; Loc. = LCCOMB_X24_Y10_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~33 Arkanoid:inst|Add4~35 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.135 ns Arkanoid:inst\|Add4~37 22 COMB LCCOMB_X24_Y10_N4 2 " "Info: 22: + IC(0.000 ns) + CELL(0.080 ns) = 5.135 ns; Loc. = LCCOMB_X24_Y10_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~35 Arkanoid:inst|Add4~37 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.215 ns Arkanoid:inst\|Add4~39 23 COMB LCCOMB_X24_Y10_N6 2 " "Info: 23: + IC(0.000 ns) + CELL(0.080 ns) = 5.215 ns; Loc. = LCCOMB_X24_Y10_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~37 Arkanoid:inst|Add4~39 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.295 ns Arkanoid:inst\|Add4~41 24 COMB LCCOMB_X24_Y10_N8 2 " "Info: 24: + IC(0.000 ns) + CELL(0.080 ns) = 5.295 ns; Loc. = LCCOMB_X24_Y10_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~39 Arkanoid:inst|Add4~41 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.375 ns Arkanoid:inst\|Add4~43 25 COMB LCCOMB_X24_Y10_N10 2 " "Info: 25: + IC(0.000 ns) + CELL(0.080 ns) = 5.375 ns; Loc. = LCCOMB_X24_Y10_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~41 Arkanoid:inst|Add4~43 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.455 ns Arkanoid:inst\|Add4~45 26 COMB LCCOMB_X24_Y10_N12 2 " "Info: 26: + IC(0.000 ns) + CELL(0.080 ns) = 5.455 ns; Loc. = LCCOMB_X24_Y10_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~43 Arkanoid:inst|Add4~45 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 5.629 ns Arkanoid:inst\|Add4~47 27 COMB LCCOMB_X24_Y10_N14 2 " "Info: 27: + IC(0.000 ns) + CELL(0.174 ns) = 5.629 ns; Loc. = LCCOMB_X24_Y10_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|Add4~45 Arkanoid:inst|Add4~47 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.709 ns Arkanoid:inst\|Add4~49 28 COMB LCCOMB_X24_Y10_N16 2 " "Info: 28: + IC(0.000 ns) + CELL(0.080 ns) = 5.709 ns; Loc. = LCCOMB_X24_Y10_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add4~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add4~47 Arkanoid:inst|Add4~49 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 6.167 ns Arkanoid:inst\|Add4~50 29 COMB LCCOMB_X24_Y10_N18 1 " "Info: 29: + IC(0.000 ns) + CELL(0.458 ns) = 6.167 ns; Loc. = LCCOMB_X24_Y10_N18; Fanout = 1; COMB Node = 'Arkanoid:inst\|Add4~50'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|Add4~49 Arkanoid:inst|Add4~50 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.527 ns) + CELL(0.178 ns) 6.872 ns Arkanoid:inst\|platform2_position~34 30 COMB LCCOMB_X25_Y10_N18 4 " "Info: 30: + IC(0.527 ns) + CELL(0.178 ns) = 6.872 ns; Loc. = LCCOMB_X25_Y10_N18; Fanout = 4; COMB Node = 'Arkanoid:inst\|platform2_position~34'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.705 ns" { Arkanoid:inst|Add4~50 Arkanoid:inst|platform2_position~34 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.595 ns) + CELL(0.455 ns) 7.922 ns Arkanoid:inst\|LessThan3~2 31 COMB LCCOMB_X25_Y10_N8 1 " "Info: 31: + IC(0.595 ns) + CELL(0.455 ns) = 7.922 ns; Loc. = LCCOMB_X25_Y10_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan3~2'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.050 ns" { Arkanoid:inst|platform2_position~34 Arkanoid:inst|LessThan3~2 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 92 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.821 ns) + CELL(0.322 ns) 9.065 ns Arkanoid:inst\|LessThan3~3 32 COMB LCCOMB_X23_Y10_N0 1 " "Info: 32: + IC(0.821 ns) + CELL(0.322 ns) = 9.065 ns; Loc. = LCCOMB_X23_Y10_N0; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan3~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.143 ns" { Arkanoid:inst|LessThan3~2 Arkanoid:inst|LessThan3~3 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 92 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.534 ns) + CELL(0.521 ns) 10.120 ns Arkanoid:inst\|LessThan3~9 33 COMB LCCOMB_X23_Y11_N18 2 " "Info: 33: + IC(0.534 ns) + CELL(0.521 ns) = 10.120 ns; Loc. = LCCOMB_X23_Y11_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|LessThan3~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.055 ns" { Arkanoid:inst|LessThan3~3 Arkanoid:inst|LessThan3~9 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 92 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.825 ns) + CELL(0.495 ns) 11.440 ns Arkanoid:inst\|Add5~1 34 COMB LCCOMB_X26_Y11_N0 2 " "Info: 34: + IC(0.825 ns) + CELL(0.495 ns) = 11.440 ns; Loc. = LCCOMB_X26_Y11_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.320 ns" { Arkanoid:inst|LessThan3~9 Arkanoid:inst|Add5~1 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 11.520 ns Arkanoid:inst\|Add5~3 35 COMB LCCOMB_X26_Y11_N2 2 " "Info: 35: + IC(0.000 ns) + CELL(0.080 ns) = 11.520 ns; Loc. = LCCOMB_X26_Y11_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~1 Arkanoid:inst|Add5~3 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 11.600 ns Arkanoid:inst\|Add5~5 36 COMB LCCOMB_X26_Y11_N4 2 " "Info: 36: + IC(0.000 ns) + CELL(0.080 ns) = 11.600 ns; Loc. = LCCOMB_X26_Y11_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~3 Arkanoid:inst|Add5~5 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 11.680 ns Arkanoid:inst\|Add5~7 37 COMB LCCOMB_X26_Y11_N6 2 " "Info: 37: + IC(0.000 ns) + CELL(0.080 ns) = 11.680 ns; Loc. = LCCOMB_X26_Y11_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~5 Arkanoid:inst|Add5~7 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 11.760 ns Arkanoid:inst\|Add5~9 38 COMB LCCOMB_X26_Y11_N8 2 " "Info: 38: + IC(0.000 ns) + CELL(0.080 ns) = 11.760 ns; Loc. = LCCOMB_X26_Y11_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~7 Arkanoid:inst|Add5~9 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 11.840 ns Arkanoid:inst\|Add5~11 39 COMB LCCOMB_X26_Y11_N10 2 " "Info: 39: + IC(0.000 ns) + CELL(0.080 ns) = 11.840 ns; Loc. = LCCOMB_X26_Y11_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~9 Arkanoid:inst|Add5~11 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 11.920 ns Arkanoid:inst\|Add5~13 40 COMB LCCOMB_X26_Y11_N12 2 " "Info: 40: + IC(0.000 ns) + CELL(0.080 ns) = 11.920 ns; Loc. = LCCOMB_X26_Y11_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~11 Arkanoid:inst|Add5~13 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 12.094 ns Arkanoid:inst\|Add5~15 41 COMB LCCOMB_X26_Y11_N14 2 " "Info: 41: + IC(0.000 ns) + CELL(0.174 ns) = 12.094 ns; Loc. = LCCOMB_X26_Y11_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|Add5~13 Arkanoid:inst|Add5~15 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.174 ns Arkanoid:inst\|Add5~17 42 COMB LCCOMB_X26_Y11_N16 2 " "Info: 42: + IC(0.000 ns) + CELL(0.080 ns) = 12.174 ns; Loc. = LCCOMB_X26_Y11_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~15 Arkanoid:inst|Add5~17 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.254 ns Arkanoid:inst\|Add5~19 43 COMB LCCOMB_X26_Y11_N18 2 " "Info: 43: + IC(0.000 ns) + CELL(0.080 ns) = 12.254 ns; Loc. = LCCOMB_X26_Y11_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~17 Arkanoid:inst|Add5~19 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.334 ns Arkanoid:inst\|Add5~21 44 COMB LCCOMB_X26_Y11_N20 2 " "Info: 44: + IC(0.000 ns) + CELL(0.080 ns) = 12.334 ns; Loc. = LCCOMB_X26_Y11_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~19 Arkanoid:inst|Add5~21 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.414 ns Arkanoid:inst\|Add5~23 45 COMB LCCOMB_X26_Y11_N22 2 " "Info: 45: + IC(0.000 ns) + CELL(0.080 ns) = 12.414 ns; Loc. = LCCOMB_X26_Y11_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~21 Arkanoid:inst|Add5~23 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.494 ns Arkanoid:inst\|Add5~25 46 COMB LCCOMB_X26_Y11_N24 2 " "Info: 46: + IC(0.000 ns) + CELL(0.080 ns) = 12.494 ns; Loc. = LCCOMB_X26_Y11_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~23 Arkanoid:inst|Add5~25 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.574 ns Arkanoid:inst\|Add5~27 47 COMB LCCOMB_X26_Y11_N26 2 " "Info: 47: + IC(0.000 ns) + CELL(0.080 ns) = 12.574 ns; Loc. = LCCOMB_X26_Y11_N26; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~25 Arkanoid:inst|Add5~27 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.654 ns Arkanoid:inst\|Add5~29 48 COMB LCCOMB_X26_Y11_N28 2 " "Info: 48: + IC(0.000 ns) + CELL(0.080 ns) = 12.654 ns; Loc. = LCCOMB_X26_Y11_N28; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~27 Arkanoid:inst|Add5~29 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 12.815 ns Arkanoid:inst\|Add5~31 49 COMB LCCOMB_X26_Y11_N30 2 " "Info: 49: + IC(0.000 ns) + CELL(0.161 ns) = 12.815 ns; Loc. = LCCOMB_X26_Y11_N30; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.161 ns" { Arkanoid:inst|Add5~29 Arkanoid:inst|Add5~31 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.895 ns Arkanoid:inst\|Add5~33 50 COMB LCCOMB_X26_Y10_N0 2 " "Info: 50: + IC(0.000 ns) + CELL(0.080 ns) = 12.895 ns; Loc. = LCCOMB_X26_Y10_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~31 Arkanoid:inst|Add5~33 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.975 ns Arkanoid:inst\|Add5~35 51 COMB LCCOMB_X26_Y10_N2 2 " "Info: 51: + IC(0.000 ns) + CELL(0.080 ns) = 12.975 ns; Loc. = LCCOMB_X26_Y10_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~33 Arkanoid:inst|Add5~35 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 13.055 ns Arkanoid:inst\|Add5~37 52 COMB LCCOMB_X26_Y10_N4 2 " "Info: 52: + IC(0.000 ns) + CELL(0.080 ns) = 13.055 ns; Loc. = LCCOMB_X26_Y10_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~35 Arkanoid:inst|Add5~37 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 13.135 ns Arkanoid:inst\|Add5~39 53 COMB LCCOMB_X26_Y10_N6 2 " "Info: 53: + IC(0.000 ns) + CELL(0.080 ns) = 13.135 ns; Loc. = LCCOMB_X26_Y10_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~37 Arkanoid:inst|Add5~39 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 13.215 ns Arkanoid:inst\|Add5~41 54 COMB LCCOMB_X26_Y10_N8 2 " "Info: 54: + IC(0.000 ns) + CELL(0.080 ns) = 13.215 ns; Loc. = LCCOMB_X26_Y10_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~39 Arkanoid:inst|Add5~41 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 13.295 ns Arkanoid:inst\|Add5~43 55 COMB LCCOMB_X26_Y10_N10 2 " "Info: 55: + IC(0.000 ns) + CELL(0.080 ns) = 13.295 ns; Loc. = LCCOMB_X26_Y10_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~41 Arkanoid:inst|Add5~43 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 13.375 ns Arkanoid:inst\|Add5~45 56 COMB LCCOMB_X26_Y10_N12 2 " "Info: 56: + IC(0.000 ns) + CELL(0.080 ns) = 13.375 ns; Loc. = LCCOMB_X26_Y10_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~43 Arkanoid:inst|Add5~45 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 13.549 ns Arkanoid:inst\|Add5~47 57 COMB LCCOMB_X26_Y10_N14 2 " "Info: 57: + IC(0.000 ns) + CELL(0.174 ns) = 13.549 ns; Loc. = LCCOMB_X26_Y10_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|Add5~45 Arkanoid:inst|Add5~47 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 13.629 ns Arkanoid:inst\|Add5~49 58 COMB LCCOMB_X26_Y10_N16 2 " "Info: 58: + IC(0.000 ns) + CELL(0.080 ns) = 13.629 ns; Loc. = LCCOMB_X26_Y10_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~47 Arkanoid:inst|Add5~49 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 13.709 ns Arkanoid:inst\|Add5~51 59 COMB LCCOMB_X26_Y10_N18 2 " "Info: 59: + IC(0.000 ns) + CELL(0.080 ns) = 13.709 ns; Loc. = LCCOMB_X26_Y10_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~51'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~49 Arkanoid:inst|Add5~51 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 14.167 ns Arkanoid:inst\|Add5~52 60 COMB LCCOMB_X26_Y10_N20 1 " "Info: 60: + IC(0.000 ns) + CELL(0.458 ns) = 14.167 ns; Loc. = LCCOMB_X26_Y10_N20; Fanout = 1; COMB Node = 'Arkanoid:inst\|Add5~52'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|Add5~51 Arkanoid:inst|Add5~52 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.890 ns) + CELL(0.544 ns) 15.601 ns Arkanoid:inst\|platform2_position~84 61 COMB LCCOMB_X25_Y10_N2 5 " "Info: 61: + IC(0.890 ns) + CELL(0.544 ns) = 15.601 ns; Loc. = LCCOMB_X25_Y10_N2; Fanout = 5; COMB Node = 'Arkanoid:inst\|platform2_position~84'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.434 ns" { Arkanoid:inst|Add5~52 Arkanoid:inst|platform2_position~84 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.381 ns) + CELL(0.495 ns) 17.477 ns Arkanoid:inst\|Add7~53 62 COMB LCCOMB_X29_Y13_N20 2 " "Info: 62: + IC(1.381 ns) + CELL(0.495 ns) = 17.477 ns; Loc. = LCCOMB_X29_Y13_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add7~53'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.876 ns" { Arkanoid:inst|platform2_position~84 Arkanoid:inst|Add7~53 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.557 ns Arkanoid:inst\|Add7~55 63 COMB LCCOMB_X29_Y13_N22 2 " "Info: 63: + IC(0.000 ns) + CELL(0.080 ns) = 17.557 ns; Loc. = LCCOMB_X29_Y13_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add7~55'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add7~53 Arkanoid:inst|Add7~55 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 18.015 ns Arkanoid:inst\|Add7~56 64 COMB LCCOMB_X29_Y13_N24 2 " "Info: 64: + IC(0.000 ns) + CELL(0.458 ns) = 18.015 ns; Loc. = LCCOMB_X29_Y13_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add7~56'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|Add7~55 Arkanoid:inst|Add7~56 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.548 ns) + CELL(0.495 ns) 19.058 ns Arkanoid:inst\|LessThan139~57 65 COMB LCCOMB_X30_Y13_N24 1 " "Info: 65: + IC(0.548 ns) + CELL(0.495 ns) = 19.058 ns; Loc. = LCCOMB_X30_Y13_N24; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~57'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.043 ns" { Arkanoid:inst|Add7~56 Arkanoid:inst|LessThan139~57 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.138 ns Arkanoid:inst\|LessThan139~59 66 COMB LCCOMB_X30_Y13_N26 1 " "Info: 66: + IC(0.000 ns) + CELL(0.080 ns) = 19.138 ns; Loc. = LCCOMB_X30_Y13_N26; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~59'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~57 Arkanoid:inst|LessThan139~59 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.218 ns Arkanoid:inst\|LessThan139~61 67 COMB LCCOMB_X30_Y13_N28 1 " "Info: 67: + IC(0.000 ns) + CELL(0.080 ns) = 19.218 ns; Loc. = LCCOMB_X30_Y13_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~61'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~59 Arkanoid:inst|LessThan139~61 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 19.676 ns Arkanoid:inst\|LessThan139~62 68 COMB LCCOMB_X30_Y13_N30 4 " "Info: 68: + IC(0.000 ns) + CELL(0.458 ns) = 19.676 ns; Loc. = LCCOMB_X30_Y13_N30; Fanout = 4; COMB Node = 'Arkanoid:inst\|LessThan139~62'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|LessThan139~61 Arkanoid:inst|LessThan139~62 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.730 ns) + CELL(0.178 ns) 21.584 ns Arkanoid:inst\|always2~4 69 COMB LCCOMB_X25_Y18_N12 2 " "Info: 69: + IC(1.730 ns) + CELL(0.178 ns) = 21.584 ns; Loc. = LCCOMB_X25_Y18_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|always2~4'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.908 ns" { Arkanoid:inst|LessThan139~62 Arkanoid:inst|always2~4 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.404 ns) + CELL(0.495 ns) 23.483 ns Arkanoid:inst\|Add9~1 70 COMB LCCOMB_X16_Y18_N0 2 " "Info: 70: + IC(1.404 ns) + CELL(0.495 ns) = 23.483 ns; Loc. = LCCOMB_X16_Y18_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.899 ns" { Arkanoid:inst|always2~4 Arkanoid:inst|Add9~1 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.563 ns Arkanoid:inst\|Add9~3 71 COMB LCCOMB_X16_Y18_N2 2 " "Info: 71: + IC(0.000 ns) + CELL(0.080 ns) = 23.563 ns; Loc. = LCCOMB_X16_Y18_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~1 Arkanoid:inst|Add9~3 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.643 ns Arkanoid:inst\|Add9~5 72 COMB LCCOMB_X16_Y18_N4 2 " "Info: 72: + IC(0.000 ns) + CELL(0.080 ns) = 23.643 ns; Loc. = LCCOMB_X16_Y18_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~3 Arkanoid:inst|Add9~5 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.723 ns Arkanoid:inst\|Add9~7 73 COMB LCCOMB_X16_Y18_N6 2 " "Info: 73: + IC(0.000 ns) + CELL(0.080 ns) = 23.723 ns; Loc. = LCCOMB_X16_Y18_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~5 Arkanoid:inst|Add9~7 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.803 ns Arkanoid:inst\|Add9~9 74 COMB LCCOMB_X16_Y18_N8 2 " "Info: 74: + IC(0.000 ns) + CELL(0.080 ns) = 23.803 ns; Loc. = LCCOMB_X16_Y18_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~7 Arkanoid:inst|Add9~9 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.883 ns Arkanoid:inst\|Add9~11 75 COMB LCCOMB_X16_Y18_N10 2 " "Info: 75: + IC(0.000 ns) + CELL(0.080 ns) = 23.883 ns; Loc. = LCCOMB_X16_Y18_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~9 Arkanoid:inst|Add9~11 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.963 ns Arkanoid:inst\|Add9~13 76 COMB LCCOMB_X16_Y18_N12 2 " "Info: 76: + IC(0.000 ns) + CELL(0.080 ns) = 23.963 ns; Loc. = LCCOMB_X16_Y18_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~11 Arkanoid:inst|Add9~13 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 24.137 ns Arkanoid:inst\|Add9~15 77 COMB LCCOMB_X16_Y18_N14 2 " "Info: 77: + IC(0.000 ns) + CELL(0.174 ns) = 24.137 ns; Loc. = LCCOMB_X16_Y18_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|Add9~13 Arkanoid:inst|Add9~15 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.217 ns Arkanoid:inst\|Add9~17 78 COMB LCCOMB_X16_Y18_N16 2 " "Info: 78: + IC(0.000 ns) + CELL(0.080 ns) = 24.217 ns; Loc. = LCCOMB_X16_Y18_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~15 Arkanoid:inst|Add9~17 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.297 ns Arkanoid:inst\|Add9~19 79 COMB LCCOMB_X16_Y18_N18 2 " "Info: 79: + IC(0.000 ns) + CELL(0.080 ns) = 24.297 ns; Loc. = LCCOMB_X16_Y18_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~17 Arkanoid:inst|Add9~19 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.377 ns Arkanoid:inst\|Add9~21 80 COMB LCCOMB_X16_Y18_N20 2 " "Info: 80: + IC(0.000 ns) + CELL(0.080 ns) = 24.377 ns; Loc. = LCCOMB_X16_Y18_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~19 Arkanoid:inst|Add9~21 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.457 ns Arkanoid:inst\|Add9~23 81 COMB LCCOMB_X16_Y18_N22 2 " "Info: 81: + IC(0.000 ns) + CELL(0.080 ns) = 24.457 ns; Loc. = LCCOMB_X16_Y18_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~21 Arkanoid:inst|Add9~23 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.537 ns Arkanoid:inst\|Add9~25 82 COMB LCCOMB_X16_Y18_N24 2 " "Info: 82: + IC(0.000 ns) + CELL(0.080 ns) = 24.537 ns; Loc. = LCCOMB_X16_Y18_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~23 Arkanoid:inst|Add9~25 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.617 ns Arkanoid:inst\|Add9~27 83 COMB LCCOMB_X16_Y18_N26 2 " "Info: 83: + IC(0.000 ns) + CELL(0.080 ns) = 24.617 ns; Loc. = LCCOMB_X16_Y18_N26; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~25 Arkanoid:inst|Add9~27 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.697 ns Arkanoid:inst\|Add9~29 84 COMB LCCOMB_X16_Y18_N28 2 " "Info: 84: + IC(0.000 ns) + CELL(0.080 ns) = 24.697 ns; Loc. = LCCOMB_X16_Y18_N28; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~27 Arkanoid:inst|Add9~29 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 24.858 ns Arkanoid:inst\|Add9~31 85 COMB LCCOMB_X16_Y18_N30 2 " "Info: 85: + IC(0.000 ns) + CELL(0.161 ns) = 24.858 ns; Loc. = LCCOMB_X16_Y18_N30; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.161 ns" { Arkanoid:inst|Add9~29 Arkanoid:inst|Add9~31 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.938 ns Arkanoid:inst\|Add9~33 86 COMB LCCOMB_X16_Y17_N0 2 " "Info: 86: + IC(0.000 ns) + CELL(0.080 ns) = 24.938 ns; Loc. = LCCOMB_X16_Y17_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~31 Arkanoid:inst|Add9~33 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.018 ns Arkanoid:inst\|Add9~35 87 COMB LCCOMB_X16_Y17_N2 2 " "Info: 87: + IC(0.000 ns) + CELL(0.080 ns) = 25.018 ns; Loc. = LCCOMB_X16_Y17_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~33 Arkanoid:inst|Add9~35 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.098 ns Arkanoid:inst\|Add9~37 88 COMB LCCOMB_X16_Y17_N4 2 " "Info: 88: + IC(0.000 ns) + CELL(0.080 ns) = 25.098 ns; Loc. = LCCOMB_X16_Y17_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~35 Arkanoid:inst|Add9~37 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.178 ns Arkanoid:inst\|Add9~39 89 COMB LCCOMB_X16_Y17_N6 2 " "Info: 89: + IC(0.000 ns) + CELL(0.080 ns) = 25.178 ns; Loc. = LCCOMB_X16_Y17_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~37 Arkanoid:inst|Add9~39 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.258 ns Arkanoid:inst\|Add9~41 90 COMB LCCOMB_X16_Y17_N8 2 " "Info: 90: + IC(0.000 ns) + CELL(0.080 ns) = 25.258 ns; Loc. = LCCOMB_X16_Y17_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~39 Arkanoid:inst|Add9~41 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.338 ns Arkanoid:inst\|Add9~43 91 COMB LCCOMB_X16_Y17_N10 2 " "Info: 91: + IC(0.000 ns) + CELL(0.080 ns) = 25.338 ns; Loc. = LCCOMB_X16_Y17_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~41 Arkanoid:inst|Add9~43 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.418 ns Arkanoid:inst\|Add9~45 92 COMB LCCOMB_X16_Y17_N12 2 " "Info: 92: + IC(0.000 ns) + CELL(0.080 ns) = 25.418 ns; Loc. = LCCOMB_X16_Y17_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~43 Arkanoid:inst|Add9~45 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 25.592 ns Arkanoid:inst\|Add9~47 93 COMB LCCOMB_X16_Y17_N14 2 " "Info: 93: + IC(0.000 ns) + CELL(0.174 ns) = 25.592 ns; Loc. = LCCOMB_X16_Y17_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|Add9~45 Arkanoid:inst|Add9~47 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.672 ns Arkanoid:inst\|Add9~49 94 COMB LCCOMB_X16_Y17_N16 2 " "Info: 94: + IC(0.000 ns) + CELL(0.080 ns) = 25.672 ns; Loc. = LCCOMB_X16_Y17_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~47 Arkanoid:inst|Add9~49 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.752 ns Arkanoid:inst\|Add9~51 95 COMB LCCOMB_X16_Y17_N18 2 " "Info: 95: + IC(0.000 ns) + CELL(0.080 ns) = 25.752 ns; Loc. = LCCOMB_X16_Y17_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~51'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~49 Arkanoid:inst|Add9~51 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.832 ns Arkanoid:inst\|Add9~53 96 COMB LCCOMB_X16_Y17_N20 2 " "Info: 96: + IC(0.000 ns) + CELL(0.080 ns) = 25.832 ns; Loc. = LCCOMB_X16_Y17_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~53'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~51 Arkanoid:inst|Add9~53 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.912 ns Arkanoid:inst\|Add9~55 97 COMB LCCOMB_X16_Y17_N22 2 " "Info: 97: + IC(0.000 ns) + CELL(0.080 ns) = 25.912 ns; Loc. = LCCOMB_X16_Y17_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~55'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~53 Arkanoid:inst|Add9~55 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.992 ns Arkanoid:inst\|Add9~57 98 COMB LCCOMB_X16_Y17_N24 2 " "Info: 98: + IC(0.000 ns) + CELL(0.080 ns) = 25.992 ns; Loc. = LCCOMB_X16_Y17_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~57'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~55 Arkanoid:inst|Add9~57 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 26.072 ns Arkanoid:inst\|Add9~59 99 COMB LCCOMB_X16_Y17_N26 2 " "Info: 99: + IC(0.000 ns) + CELL(0.080 ns) = 26.072 ns; Loc. = LCCOMB_X16_Y17_N26; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~59'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~57 Arkanoid:inst|Add9~59 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 26.152 ns Arkanoid:inst\|Add9~61 100 COMB LCCOMB_X16_Y17_N28 1 " "Info: 100: + IC(0.000 ns) + CELL(0.080 ns) = 26.152 ns; Loc. = LCCOMB_X16_Y17_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|Add9~61'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~59 Arkanoid:inst|Add9~61 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 26.610 ns Arkanoid:inst\|Add9~63 101 COMB LCCOMB_X16_Y17_N30 3 " "Info: 101: + IC(0.000 ns) + CELL(0.458 ns) = 26.610 ns; Loc. = LCCOMB_X16_Y17_N30; Fanout = 3; COMB Node = 'Arkanoid:inst\|Add9~63'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|Add9~61 Arkanoid:inst|Add9~63 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.193 ns) + CELL(0.178 ns) 27.981 ns Arkanoid:inst\|Add9~65 102 COMB LCCOMB_X16_Y16_N28 147 " "Info: 102: + IC(1.193 ns) + CELL(0.178 ns) = 27.981 ns; Loc. = LCCOMB_X16_Y16_N28; Fanout = 147; COMB Node = 'Arkanoid:inst\|Add9~65'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.371 ns" { Arkanoid:inst|Add9~63 Arkanoid:inst|Add9~65 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.291 ns) + CELL(0.517 ns) 29.789 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~3 103 COMB LCCOMB_X19_Y18_N4 2 " "Info: 103: + IC(1.291 ns) + CELL(0.517 ns) = 29.789 ns; Loc. = LCCOMB_X19_Y18_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.808 ns" { Arkanoid:inst|Add9~65 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 29.869 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~5 104 COMB LCCOMB_X19_Y18_N6 2 " "Info: 104: + IC(0.000 ns) + CELL(0.080 ns) = 29.869 ns; Loc. = LCCOMB_X19_Y18_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 29.949 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~7 105 COMB LCCOMB_X19_Y18_N8 2 " "Info: 105: + IC(0.000 ns) + CELL(0.080 ns) = 29.949 ns; Loc. = LCCOMB_X19_Y18_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.029 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~9 106 COMB LCCOMB_X19_Y18_N10 2 " "Info: 106: + IC(0.000 ns) + CELL(0.080 ns) = 30.029 ns; Loc. = LCCOMB_X19_Y18_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.109 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~11 107 COMB LCCOMB_X19_Y18_N12 2 " "Info: 107: + IC(0.000 ns) + CELL(0.080 ns) = 30.109 ns; Loc. = LCCOMB_X19_Y18_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 30.283 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~13 108 COMB LCCOMB_X19_Y18_N14 2 " "Info: 108: + IC(0.000 ns) + CELL(0.174 ns) = 30.283 ns; Loc. = LCCOMB_X19_Y18_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.363 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~15 109 COMB LCCOMB_X19_Y18_N16 2 " "Info: 109: + IC(0.000 ns) + CELL(0.080 ns) = 30.363 ns; Loc. = LCCOMB_X19_Y18_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.443 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~17 110 COMB LCCOMB_X19_Y18_N18 2 " "Info: 110: + IC(0.000 ns) + CELL(0.080 ns) = 30.443 ns; Loc. = LCCOMB_X19_Y18_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.523 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~19 111 COMB LCCOMB_X19_Y18_N20 2 " "Info: 111: + IC(0.000 ns) + CELL(0.080 ns) = 30.523 ns; Loc. = LCCOMB_X19_Y18_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.603 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~21 112 COMB LCCOMB_X19_Y18_N22 2 " "Info: 112: + IC(0.000 ns) + CELL(0.080 ns) = 30.603 ns; Loc. = LCCOMB_X19_Y18_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.683 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~23 113 COMB LCCOMB_X19_Y18_N24 2 " "Info: 113: + IC(0.000 ns) + CELL(0.080 ns) = 30.683 ns; Loc. = LCCOMB_X19_Y18_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.763 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~25 114 COMB LCCOMB_X19_Y18_N26 2 " "Info: 114: + IC(0.000 ns) + CELL(0.080 ns) = 30.763 ns; Loc. = LCCOMB_X19_Y18_N26; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 30.843 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~27 115 COMB LCCOMB_X19_Y18_N28 2 " "Info: 115: + IC(0.000 ns) + CELL(0.080 ns) = 30.843 ns; Loc. = LCCOMB_X19_Y18_N28; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 31.004 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~29 116 COMB LCCOMB_X19_Y18_N30 2 " "Info: 116: + IC(0.000 ns) + CELL(0.161 ns) = 31.004 ns; Loc. = LCCOMB_X19_Y18_N30; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.161 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.084 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~31 117 COMB LCCOMB_X19_Y17_N0 2 " "Info: 117: + IC(0.000 ns) + CELL(0.080 ns) = 31.084 ns; Loc. = LCCOMB_X19_Y17_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.164 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~33 118 COMB LCCOMB_X19_Y17_N2 2 " "Info: 118: + IC(0.000 ns) + CELL(0.080 ns) = 31.164 ns; Loc. = LCCOMB_X19_Y17_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.244 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~35 119 COMB LCCOMB_X19_Y17_N4 2 " "Info: 119: + IC(0.000 ns) + CELL(0.080 ns) = 31.244 ns; Loc. = LCCOMB_X19_Y17_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.324 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~37 120 COMB LCCOMB_X19_Y17_N6 2 " "Info: 120: + IC(0.000 ns) + CELL(0.080 ns) = 31.324 ns; Loc. = LCCOMB_X19_Y17_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.404 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~39 121 COMB LCCOMB_X19_Y17_N8 2 " "Info: 121: + IC(0.000 ns) + CELL(0.080 ns) = 31.404 ns; Loc. = LCCOMB_X19_Y17_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.484 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~41 122 COMB LCCOMB_X19_Y17_N10 2 " "Info: 122: + IC(0.000 ns) + CELL(0.080 ns) = 31.484 ns; Loc. = LCCOMB_X19_Y17_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.564 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~43 123 COMB LCCOMB_X19_Y17_N12 2 " "Info: 123: + IC(0.000 ns) + CELL(0.080 ns) = 31.564 ns; Loc. = LCCOMB_X19_Y17_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 31.738 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~45 124 COMB LCCOMB_X19_Y17_N14 2 " "Info: 124: + IC(0.000 ns) + CELL(0.174 ns) = 31.738 ns; Loc. = LCCOMB_X19_Y17_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.818 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~47 125 COMB LCCOMB_X19_Y17_N16 2 " "Info: 125: + IC(0.000 ns) + CELL(0.080 ns) = 31.818 ns; Loc. = LCCOMB_X19_Y17_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.898 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~49 126 COMB LCCOMB_X19_Y17_N18 2 " "Info: 126: + IC(0.000 ns) + CELL(0.080 ns) = 31.898 ns; Loc. = LCCOMB_X19_Y17_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 31.978 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~51 127 COMB LCCOMB_X19_Y17_N20 2 " "Info: 127: + IC(0.000 ns) + CELL(0.080 ns) = 31.978 ns; Loc. = LCCOMB_X19_Y17_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~51'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.058 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~53 128 COMB LCCOMB_X19_Y17_N22 2 " "Info: 128: + IC(0.000 ns) + CELL(0.080 ns) = 32.058 ns; Loc. = LCCOMB_X19_Y17_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~53'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.138 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~55 129 COMB LCCOMB_X19_Y17_N24 2 " "Info: 129: + IC(0.000 ns) + CELL(0.080 ns) = 32.138 ns; Loc. = LCCOMB_X19_Y17_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~55'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 32.596 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~56 130 COMB LCCOMB_X19_Y17_N26 4 " "Info: 130: + IC(0.000 ns) + CELL(0.458 ns) = 32.596 ns; Loc. = LCCOMB_X19_Y17_N26; Fanout = 4; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~56'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~56 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.497 ns) + CELL(0.620 ns) 34.713 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[1\]~1 131 COMB LCCOMB_X25_Y15_N14 2 " "Info: 131: + IC(1.497 ns) + CELL(0.620 ns) = 34.713 ns; Loc. = LCCOMB_X25_Y15_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.117 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~56 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 141 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 34.793 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[2\]~3 132 COMB LCCOMB_X25_Y15_N16 2 " "Info: 132: + IC(0.000 ns) + CELL(0.080 ns) = 34.793 ns; Loc. = LCCOMB_X25_Y15_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 141 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 34.873 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[3\]~5 133 COMB LCCOMB_X25_Y15_N18 1 " "Info: 133: + IC(0.000 ns) + CELL(0.080 ns) = 34.873 ns; Loc. = LCCOMB_X25_Y15_N18; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 141 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 35.331 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[4\]~6 134 COMB LCCOMB_X25_Y15_N20 14 " "Info: 134: + IC(0.000 ns) + CELL(0.458 ns) = 35.331 ns; Loc. = LCCOMB_X25_Y15_N20; Fanout = 14; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[4\]~6'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 141 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.583 ns) + CELL(0.319 ns) 36.233 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[20\]~106 135 COMB LCCOMB_X26_Y15_N2 2 " "Info: 135: + IC(0.583 ns) + CELL(0.319 ns) = 36.233 ns; Loc. = LCCOMB_X26_Y15_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[20\]~106'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.902 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[20]~106 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.517 ns) 37.308 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[3\]~5 136 COMB LCCOMB_X25_Y15_N8 2 " "Info: 136: + IC(0.558 ns) + CELL(0.517 ns) = 37.308 ns; Loc. = LCCOMB_X25_Y15_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.075 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[20]~106 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 37.388 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[4\]~7 137 COMB LCCOMB_X25_Y15_N10 1 " "Info: 137: + IC(0.000 ns) + CELL(0.080 ns) = 37.388 ns; Loc. = LCCOMB_X25_Y15_N10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 37.846 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[5\]~8 138 COMB LCCOMB_X25_Y15_N12 17 " "Info: 138: + IC(0.000 ns) + CELL(0.458 ns) = 37.846 ns; Loc. = LCCOMB_X25_Y15_N12; Fanout = 17; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[5\]~8'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.322 ns) 39.234 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[27\]~115 139 COMB LCCOMB_X25_Y19_N26 2 " "Info: 139: + IC(1.066 ns) + CELL(0.322 ns) = 39.234 ns; Loc. = LCCOMB_X25_Y19_N26; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[27\]~115'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.388 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[27]~115 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.939 ns) + CELL(0.517 ns) 40.690 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[4\]~7 140 COMB LCCOMB_X24_Y15_N26 1 " "Info: 140: + IC(0.939 ns) + CELL(0.517 ns) = 40.690 ns; Loc. = LCCOMB_X24_Y15_N26; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.456 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[27]~115 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 40.770 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[5\]~9 141 COMB LCCOMB_X24_Y15_N28 1 " "Info: 141: + IC(0.000 ns) + CELL(0.080 ns) = 40.770 ns; Loc. = LCCOMB_X24_Y15_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 41.228 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[6\]~10 142 COMB LCCOMB_X24_Y15_N30 16 " "Info: 142: + IC(0.000 ns) + CELL(0.458 ns) = 41.228 ns; Loc. = LCCOMB_X24_Y15_N30; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.936 ns) + CELL(0.177 ns) 42.341 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[30\]~129 143 COMB LCCOMB_X23_Y12_N10 2 " "Info: 143: + IC(0.936 ns) + CELL(0.177 ns) = 42.341 ns; Loc. = LCCOMB_X23_Y12_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[30\]~129'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.113 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[30]~129 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.939 ns) + CELL(0.517 ns) 43.797 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[1\]~1 144 COMB LCCOMB_X23_Y15_N2 2 " "Info: 144: + IC(0.939 ns) + CELL(0.517 ns) = 43.797 ns; Loc. = LCCOMB_X23_Y15_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.456 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[30]~129 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 43.877 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[2\]~3 145 COMB LCCOMB_X23_Y15_N4 2 " "Info: 145: + IC(0.000 ns) + CELL(0.080 ns) = 43.877 ns; Loc. = LCCOMB_X23_Y15_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 43.957 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[3\]~5 146 COMB LCCOMB_X23_Y15_N6 2 " "Info: 146: + IC(0.000 ns) + CELL(0.080 ns) = 43.957 ns; Loc. = LCCOMB_X23_Y15_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 44.037 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[4\]~7 147 COMB LCCOMB_X23_Y15_N8 1 " "Info: 147: + IC(0.000 ns) + CELL(0.080 ns) = 44.037 ns; Loc. = LCCOMB_X23_Y15_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 44.117 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[5\]~9 148 COMB LCCOMB_X23_Y15_N10 1 " "Info: 148: + IC(0.000 ns) + CELL(0.080 ns) = 44.117 ns; Loc. = LCCOMB_X23_Y15_N10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 44.575 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[6\]~10 149 COMB LCCOMB_X23_Y15_N12 16 " "Info: 149: + IC(0.000 ns) + CELL(0.458 ns) = 44.575 ns; Loc. = LCCOMB_X23_Y15_N12; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.948 ns) + CELL(0.322 ns) 45.845 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[36\]~136 150 COMB LCCOMB_X22_Y12_N0 2 " "Info: 150: + IC(0.948 ns) + CELL(0.322 ns) = 45.845 ns; Loc. = LCCOMB_X22_Y12_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[36\]~136'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.270 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~136 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.540 ns) + CELL(0.517 ns) 46.902 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[1\]~1 151 COMB LCCOMB_X23_Y12_N18 2 " "Info: 151: + IC(0.540 ns) + CELL(0.517 ns) = 46.902 ns; Loc. = LCCOMB_X23_Y12_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.057 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~136 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 46.982 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[2\]~3 152 COMB LCCOMB_X23_Y12_N20 2 " "Info: 152: + IC(0.000 ns) + CELL(0.080 ns) = 46.982 ns; Loc. = LCCOMB_X23_Y12_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 47.062 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[3\]~5 153 COMB LCCOMB_X23_Y12_N22 2 " "Info: 153: + IC(0.000 ns) + CELL(0.080 ns) = 47.062 ns; Loc. = LCCOMB_X23_Y12_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 47.142 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[4\]~7 154 COMB LCCOMB_X23_Y12_N24 1 " "Info: 154: + IC(0.000 ns) + CELL(0.080 ns) = 47.142 ns; Loc. = LCCOMB_X23_Y12_N24; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 47.222 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[5\]~9 155 COMB LCCOMB_X23_Y12_N26 1 " "Info: 155: + IC(0.000 ns) + CELL(0.080 ns) = 47.222 ns; Loc. = LCCOMB_X23_Y12_N26; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 47.680 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[6\]~10 156 COMB LCCOMB_X23_Y12_N28 16 " "Info: 156: + IC(0.000 ns) + CELL(0.458 ns) = 47.680 ns; Loc. = LCCOMB_X23_Y12_N28; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.836 ns) + CELL(0.178 ns) 48.694 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[42\]~144 157 COMB LCCOMB_X19_Y12_N0 2 " "Info: 157: + IC(0.836 ns) + CELL(0.178 ns) = 48.694 ns; Loc. = LCCOMB_X19_Y12_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[42\]~144'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.014 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[42]~144 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.818 ns) + CELL(0.517 ns) 50.029 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[1\]~1 158 COMB LCCOMB_X22_Y12_N20 2 " "Info: 158: + IC(0.818 ns) + CELL(0.517 ns) = 50.029 ns; Loc. = LCCOMB_X22_Y12_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.335 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[42]~144 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 50.109 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[2\]~3 159 COMB LCCOMB_X22_Y12_N22 2 " "Info: 159: + IC(0.000 ns) + CELL(0.080 ns) = 50.109 ns; Loc. = LCCOMB_X22_Y12_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 50.189 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[3\]~5 160 COMB LCCOMB_X22_Y12_N24 2 " "Info: 160: + IC(0.000 ns) + CELL(0.080 ns) = 50.189 ns; Loc. = LCCOMB_X22_Y12_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 50.269 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[4\]~7 161 COMB LCCOMB_X22_Y12_N26 1 " "Info: 161: + IC(0.000 ns) + CELL(0.080 ns) = 50.269 ns; Loc. = LCCOMB_X22_Y12_N26; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 50.349 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[5\]~9 162 COMB LCCOMB_X22_Y12_N28 1 " "Info: 162: + IC(0.000 ns) + CELL(0.080 ns) = 50.349 ns; Loc. = LCCOMB_X22_Y12_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 50.807 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[6\]~10 163 COMB LCCOMB_X22_Y12_N30 16 " "Info: 163: + IC(0.000 ns) + CELL(0.458 ns) = 50.807 ns; Loc. = LCCOMB_X22_Y12_N30; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.220 ns) + CELL(0.177 ns) 52.204 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[48\]~153 164 COMB LCCOMB_X18_Y8_N2 2 " "Info: 164: + IC(1.220 ns) + CELL(0.177 ns) = 52.204 ns; Loc. = LCCOMB_X18_Y8_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[48\]~153'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.397 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[48]~153 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.927 ns) + CELL(0.517 ns) 53.648 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[1\]~1 165 COMB LCCOMB_X19_Y12_N8 2 " "Info: 165: + IC(0.927 ns) + CELL(0.517 ns) = 53.648 ns; Loc. = LCCOMB_X19_Y12_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.444 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[48]~153 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 53.728 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[2\]~3 166 COMB LCCOMB_X19_Y12_N10 2 " "Info: 166: + IC(0.000 ns) + CELL(0.080 ns) = 53.728 ns; Loc. = LCCOMB_X19_Y12_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 53.808 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[3\]~5 167 COMB LCCOMB_X19_Y12_N12 2 " "Info: 167: + IC(0.000 ns) + CELL(0.080 ns) = 53.808 ns; Loc. = LCCOMB_X19_Y12_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 53.982 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[4\]~7 168 COMB LCCOMB_X19_Y12_N14 1 " "Info: 168: + IC(0.000 ns) + CELL(0.174 ns) = 53.982 ns; Loc. = LCCOMB_X19_Y12_N14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 54.062 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[5\]~9 169 COMB LCCOMB_X19_Y12_N16 1 " "Info: 169: + IC(0.000 ns) + CELL(0.080 ns) = 54.062 ns; Loc. = LCCOMB_X19_Y12_N16; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 54.520 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[6\]~10 170 COMB LCCOMB_X19_Y12_N18 16 " "Info: 170: + IC(0.000 ns) + CELL(0.458 ns) = 54.520 ns; Loc. = LCCOMB_X19_Y12_N18; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.178 ns) 55.535 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[57\]~339 171 COMB LCCOMB_X22_Y12_N2 3 " "Info: 171: + IC(0.837 ns) + CELL(0.178 ns) = 55.535 ns; Loc. = LCCOMB_X22_Y12_N2; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[57\]~339'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.015 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[57]~339 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.183 ns) + CELL(0.517 ns) 57.235 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[4\]~7 172 COMB LCCOMB_X19_Y8_N8 1 " "Info: 172: + IC(1.183 ns) + CELL(0.517 ns) = 57.235 ns; Loc. = LCCOMB_X19_Y8_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[57]~339 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 36 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 57.315 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[5\]~9 173 COMB LCCOMB_X19_Y8_N10 1 " "Info: 173: + IC(0.000 ns) + CELL(0.080 ns) = 57.315 ns; Loc. = LCCOMB_X19_Y8_N10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 36 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 57.773 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[6\]~10 174 COMB LCCOMB_X19_Y8_N12 16 " "Info: 174: + IC(0.000 ns) + CELL(0.458 ns) = 57.773 ns; Loc. = LCCOMB_X19_Y8_N12; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 36 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.896 ns) + CELL(0.177 ns) 58.846 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[60\]~169 175 COMB LCCOMB_X19_Y7_N2 2 " "Info: 175: + IC(0.896 ns) + CELL(0.177 ns) = 58.846 ns; Loc. = LCCOMB_X19_Y7_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[60\]~169'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.073 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[60]~169 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.180 ns) + CELL(0.517 ns) 60.543 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[1\]~1 176 COMB LCCOMB_X18_Y8_N20 2 " "Info: 176: + IC(1.180 ns) + CELL(0.517 ns) = 60.543 ns; Loc. = LCCOMB_X18_Y8_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.697 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[60]~169 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 60.623 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[2\]~3 177 COMB LCCOMB_X18_Y8_N22 2 " "Info: 177: + IC(0.000 ns) + CELL(0.080 ns) = 60.623 ns; Loc. = LCCOMB_X18_Y8_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 60.703 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[3\]~5 178 COMB LCCOMB_X18_Y8_N24 2 " "Info: 178: + IC(0.000 ns) + CELL(0.080 ns) = 60.703 ns; Loc. = LCCOMB_X18_Y8_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 60.783 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[4\]~7 179 COMB LCCOMB_X18_Y8_N26 1 " "Info: 179: + IC(0.000 ns) + CELL(0.080 ns) = 60.783 ns; Loc. = LCCOMB_X18_Y8_N26; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 60.863 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[5\]~9 180 COMB LCCOMB_X18_Y8_N28 1 " "Info: 180: + IC(0.000 ns) + CELL(0.080 ns) = 60.863 ns; Loc. = LCCOMB_X18_Y8_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 61.321 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[6\]~10 181 COMB LCCOMB_X18_Y8_N30 16 " "Info: 181: + IC(0.000 ns) + CELL(0.458 ns) = 61.321 ns; Loc. = LCCOMB_X18_Y8_N30; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.184 ns) + CELL(0.322 ns) 62.827 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[67\]~174 182 COMB LCCOMB_X19_Y7_N4 2 " "Info: 182: + IC(1.184 ns) + CELL(0.322 ns) = 62.827 ns; Loc. = LCCOMB_X19_Y7_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[67\]~174'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.506 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[67]~174 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.856 ns) + CELL(0.495 ns) 64.178 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[2\]~3 183 COMB LCCOMB_X19_Y8_N22 2 " "Info: 183: + IC(0.856 ns) + CELL(0.495 ns) = 64.178 ns; Loc. = LCCOMB_X19_Y8_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.351 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[67]~174 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 64.258 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[3\]~5 184 COMB LCCOMB_X19_Y8_N24 2 " "Info: 184: + IC(0.000 ns) + CELL(0.080 ns) = 64.258 ns; Loc. = LCCOMB_X19_Y8_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 64.338 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[4\]~7 185 COMB LCCOMB_X19_Y8_N26 1 " "Info: 185: + IC(0.000 ns) + CELL(0.080 ns) = 64.338 ns; Loc. = LCCOMB_X19_Y8_N26; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 64.418 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[5\]~9 186 COMB LCCOMB_X19_Y8_N28 1 " "Info: 186: + IC(0.000 ns) + CELL(0.080 ns) = 64.418 ns; Loc. = LCCOMB_X19_Y8_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 64.876 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[6\]~10 187 COMB LCCOMB_X19_Y8_N30 16 " "Info: 187: + IC(0.000 ns) + CELL(0.458 ns) = 64.876 ns; Loc. = LCCOMB_X19_Y8_N30; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.901 ns) + CELL(0.322 ns) 66.099 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[75\]~179 188 COMB LCCOMB_X19_Y7_N30 2 " "Info: 188: + IC(0.901 ns) + CELL(0.322 ns) = 66.099 ns; Loc. = LCCOMB_X19_Y7_N30; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[75\]~179'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.223 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[75]~179 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.484 ns) + CELL(0.620 ns) 67.203 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[4\]~7 189 COMB LCCOMB_X19_Y7_N14 1 " "Info: 189: + IC(0.484 ns) + CELL(0.620 ns) = 67.203 ns; Loc. = LCCOMB_X19_Y7_N14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.104 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[75]~179 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 51 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 67.283 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[5\]~9 190 COMB LCCOMB_X19_Y7_N16 1 " "Info: 190: + IC(0.000 ns) + CELL(0.080 ns) = 67.283 ns; Loc. = LCCOMB_X19_Y7_N16; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 51 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 67.741 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[6\]~10 191 COMB LCCOMB_X19_Y7_N18 16 " "Info: 191: + IC(0.000 ns) + CELL(0.458 ns) = 67.741 ns; Loc. = LCCOMB_X19_Y7_N18; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 51 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.174 ns) + CELL(0.322 ns) 69.237 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[82\]~186 192 COMB LCCOMB_X20_Y8_N14 1 " "Info: 192: + IC(1.174 ns) + CELL(0.322 ns) = 69.237 ns; Loc. = LCCOMB_X20_Y8_N14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[82\]~186'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.496 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[82]~186 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.835 ns) + CELL(0.495 ns) 70.567 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[5\]~9 193 COMB LCCOMB_X20_Y7_N18 1 " "Info: 193: + IC(0.835 ns) + CELL(0.495 ns) = 70.567 ns; Loc. = LCCOMB_X20_Y7_N18; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.330 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[82]~186 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 56 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 71.025 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[6\]~10 194 COMB LCCOMB_X20_Y7_N20 16 " "Info: 194: + IC(0.000 ns) + CELL(0.458 ns) = 71.025 ns; Loc. = LCCOMB_X20_Y7_N20; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 56 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.924 ns) + CELL(0.178 ns) 72.127 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[85\]~198 195 COMB LCCOMB_X19_Y6_N22 2 " "Info: 195: + IC(0.924 ns) + CELL(0.178 ns) = 72.127 ns; Loc. = LCCOMB_X19_Y6_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[85\]~198'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.102 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[85]~198 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.546 ns) + CELL(0.517 ns) 73.190 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[2\]~3 196 COMB LCCOMB_X19_Y6_N10 2 " "Info: 196: + IC(0.546 ns) + CELL(0.517 ns) = 73.190 ns; Loc. = LCCOMB_X19_Y6_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.063 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[85]~198 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 61 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 73.270 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[3\]~5 197 COMB LCCOMB_X19_Y6_N12 2 " "Info: 197: + IC(0.000 ns) + CELL(0.080 ns) = 73.270 ns; Loc. = LCCOMB_X19_Y6_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 61 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 73.444 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[4\]~7 198 COMB LCCOMB_X19_Y6_N14 1 " "Info: 198: + IC(0.000 ns) + CELL(0.174 ns) = 73.444 ns; Loc. = LCCOMB_X19_Y6_N14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 61 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 73.524 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[5\]~9 199 COMB LCCOMB_X19_Y6_N16 1 " "Info: 199: + IC(0.000 ns) + CELL(0.080 ns) = 73.524 ns; Loc. = LCCOMB_X19_Y6_N16; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 61 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 73.982 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[6\]~10 200 COMB LCCOMB_X19_Y6_N18 16 " "Info: 200: + IC(0.000 ns) + CELL(0.458 ns) = 73.982 ns; Loc. = LCCOMB_X19_Y6_N18; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 61 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.632 ns) + CELL(0.178 ns) 74.792 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[90\]~208 201 COMB LCCOMB_X20_Y6_N24 2 " "Info: 201: + IC(0.632 ns) + CELL(0.178 ns) = 74.792 ns; Loc. = LCCOMB_X20_Y6_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[90\]~208'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.810 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[90]~208 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.319 ns) + CELL(0.517 ns) 75.628 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[1\]~1 202 COMB LCCOMB_X20_Y6_N10 2 " "Info: 202: + IC(0.319 ns) + CELL(0.517 ns) = 75.628 ns; Loc. = LCCOMB_X20_Y6_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.836 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[90]~208 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 75.708 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[2\]~3 203 COMB LCCOMB_X20_Y6_N12 2 " "Info: 203: + IC(0.000 ns) + CELL(0.080 ns) = 75.708 ns; Loc. = LCCOMB_X20_Y6_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 75.882 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[3\]~5 204 COMB LCCOMB_X20_Y6_N14 2 " "Info: 204: + IC(0.000 ns) + CELL(0.174 ns) = 75.882 ns; Loc. = LCCOMB_X20_Y6_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 75.962 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[4\]~7 205 COMB LCCOMB_X20_Y6_N16 1 " "Info: 205: + IC(0.000 ns) + CELL(0.080 ns) = 75.962 ns; Loc. = LCCOMB_X20_Y6_N16; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 76.042 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[5\]~9 206 COMB LCCOMB_X20_Y6_N18 1 " "Info: 206: + IC(0.000 ns) + CELL(0.080 ns) = 76.042 ns; Loc. = LCCOMB_X20_Y6_N18; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 76.500 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[6\]~10 207 COMB LCCOMB_X20_Y6_N20 16 " "Info: 207: + IC(0.000 ns) + CELL(0.458 ns) = 76.500 ns; Loc. = LCCOMB_X20_Y6_N20; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.646 ns) + CELL(0.322 ns) 77.468 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[96\]~216 208 COMB LCCOMB_X21_Y6_N28 2 " "Info: 208: + IC(0.646 ns) + CELL(0.322 ns) = 77.468 ns; Loc. = LCCOMB_X21_Y6_N28; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[96\]~216'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.968 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[96]~216 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.537 ns) + CELL(0.517 ns) 78.522 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[1\]~1 209 COMB LCCOMB_X21_Y6_N6 2 " "Info: 209: + IC(0.537 ns) + CELL(0.517 ns) = 78.522 ns; Loc. = LCCOMB_X21_Y6_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.054 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[96]~216 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 78.602 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[2\]~3 210 COMB LCCOMB_X21_Y6_N8 2 " "Info: 210: + IC(0.000 ns) + CELL(0.080 ns) = 78.602 ns; Loc. = LCCOMB_X21_Y6_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 78.682 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[3\]~5 211 COMB LCCOMB_X21_Y6_N10 2 " "Info: 211: + IC(0.000 ns) + CELL(0.080 ns) = 78.682 ns; Loc. = LCCOMB_X21_Y6_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 78.762 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[4\]~7 212 COMB LCCOMB_X21_Y6_N12 1 " "Info: 212: + IC(0.000 ns) + CELL(0.080 ns) = 78.762 ns; Loc. = LCCOMB_X21_Y6_N12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 78.936 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[5\]~9 213 COMB LCCOMB_X21_Y6_N14 1 " "Info: 213: + IC(0.000 ns) + CELL(0.174 ns) = 78.936 ns; Loc. = LCCOMB_X21_Y6_N14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 79.394 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[6\]~10 214 COMB LCCOMB_X21_Y6_N16 16 " "Info: 214: + IC(0.000 ns) + CELL(0.458 ns) = 79.394 ns; Loc. = LCCOMB_X21_Y6_N16; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.632 ns) + CELL(0.177 ns) 80.203 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[102\]~225 215 COMB LCCOMB_X22_Y6_N24 2 " "Info: 215: + IC(0.632 ns) + CELL(0.177 ns) = 80.203 ns; Loc. = LCCOMB_X22_Y6_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[102\]~225'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.809 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~225 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.319 ns) + CELL(0.517 ns) 81.039 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[1\]~1 216 COMB LCCOMB_X22_Y6_N2 2 " "Info: 216: + IC(0.319 ns) + CELL(0.517 ns) = 81.039 ns; Loc. = LCCOMB_X22_Y6_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.836 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~225 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 81.119 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[2\]~3 217 COMB LCCOMB_X22_Y6_N4 2 " "Info: 217: + IC(0.000 ns) + CELL(0.080 ns) = 81.119 ns; Loc. = LCCOMB_X22_Y6_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 81.199 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[3\]~5 218 COMB LCCOMB_X22_Y6_N6 2 " "Info: 218: + IC(0.000 ns) + CELL(0.080 ns) = 81.199 ns; Loc. = LCCOMB_X22_Y6_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 81.279 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[4\]~7 219 COMB LCCOMB_X22_Y6_N8 1 " "Info: 219: + IC(0.000 ns) + CELL(0.080 ns) = 81.279 ns; Loc. = LCCOMB_X22_Y6_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 81.359 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[5\]~9 220 COMB LCCOMB_X22_Y6_N10 1 " "Info: 220: + IC(0.000 ns) + CELL(0.080 ns) = 81.359 ns; Loc. = LCCOMB_X22_Y6_N10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 81.817 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[6\]~10 221 COMB LCCOMB_X22_Y6_N12 16 " "Info: 221: + IC(0.000 ns) + CELL(0.458 ns) = 81.817 ns; Loc. = LCCOMB_X22_Y6_N12; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.919 ns) + CELL(0.322 ns) 83.058 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[109\]~231 222 COMB LCCOMB_X21_Y8_N30 2 " "Info: 222: + IC(0.919 ns) + CELL(0.322 ns) = 83.058 ns; Loc. = LCCOMB_X21_Y8_N30; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[109\]~231'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.241 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[109]~231 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.485 ns) + CELL(0.517 ns) 84.060 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[2\]~3 223 COMB LCCOMB_X22_Y8_N22 2 " "Info: 223: + IC(0.485 ns) + CELL(0.517 ns) = 84.060 ns; Loc. = LCCOMB_X22_Y8_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.002 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[109]~231 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 84.140 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[3\]~5 224 COMB LCCOMB_X22_Y8_N24 2 " "Info: 224: + IC(0.000 ns) + CELL(0.080 ns) = 84.140 ns; Loc. = LCCOMB_X22_Y8_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 84.220 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[4\]~7 225 COMB LCCOMB_X22_Y8_N26 1 " "Info: 225: + IC(0.000 ns) + CELL(0.080 ns) = 84.220 ns; Loc. = LCCOMB_X22_Y8_N26; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 84.300 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[5\]~9 226 COMB LCCOMB_X22_Y8_N28 1 " "Info: 226: + IC(0.000 ns) + CELL(0.080 ns) = 84.300 ns; Loc. = LCCOMB_X22_Y8_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 84.758 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[6\]~10 227 COMB LCCOMB_X22_Y8_N30 16 " "Info: 227: + IC(0.000 ns) + CELL(0.458 ns) = 84.758 ns; Loc. = LCCOMB_X22_Y8_N30; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.564 ns) + CELL(0.322 ns) 85.644 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[116\]~237 228 COMB LCCOMB_X23_Y8_N26 2 " "Info: 228: + IC(0.564 ns) + CELL(0.322 ns) = 85.644 ns; Loc. = LCCOMB_X23_Y8_N26; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[116\]~237'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.886 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[116]~237 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.581 ns) + CELL(0.517 ns) 86.742 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[3\]~5 229 COMB LCCOMB_X23_Y8_N18 2 " "Info: 229: + IC(0.581 ns) + CELL(0.517 ns) = 86.742 ns; Loc. = LCCOMB_X23_Y8_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.098 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[116]~237 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 91 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 86.822 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[4\]~7 230 COMB LCCOMB_X23_Y8_N20 1 " "Info: 230: + IC(0.000 ns) + CELL(0.080 ns) = 86.822 ns; Loc. = LCCOMB_X23_Y8_N20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 91 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 86.902 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[5\]~9 231 COMB LCCOMB_X23_Y8_N22 1 " "Info: 231: + IC(0.000 ns) + CELL(0.080 ns) = 86.902 ns; Loc. = LCCOMB_X23_Y8_N22; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 91 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 87.360 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[6\]~10 232 COMB LCCOMB_X23_Y8_N24 16 " "Info: 232: + IC(0.000 ns) + CELL(0.458 ns) = 87.360 ns; Loc. = LCCOMB_X23_Y8_N24; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 91 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.564 ns) + CELL(0.178 ns) 88.102 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[122\]~244 233 COMB LCCOMB_X22_Y8_N14 3 " "Info: 233: + IC(0.564 ns) + CELL(0.178 ns) = 88.102 ns; Loc. = LCCOMB_X22_Y8_N14; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[122\]~244'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.742 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~244 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.807 ns) + CELL(0.495 ns) 89.404 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[3\]~5 234 COMB LCCOMB_X24_Y8_N8 2 " "Info: 234: + IC(0.807 ns) + CELL(0.495 ns) = 89.404 ns; Loc. = LCCOMB_X24_Y8_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.302 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~244 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 89.484 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[4\]~7 235 COMB LCCOMB_X24_Y8_N10 1 " "Info: 235: + IC(0.000 ns) + CELL(0.080 ns) = 89.484 ns; Loc. = LCCOMB_X24_Y8_N10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 89.564 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[5\]~9 236 COMB LCCOMB_X24_Y8_N12 1 " "Info: 236: + IC(0.000 ns) + CELL(0.080 ns) = 89.564 ns; Loc. = LCCOMB_X24_Y8_N12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 90.022 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[6\]~10 237 COMB LCCOMB_X24_Y8_N14 16 " "Info: 237: + IC(0.000 ns) + CELL(0.458 ns) = 90.022 ns; Loc. = LCCOMB_X24_Y8_N14; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.519 ns) + CELL(0.322 ns) 90.863 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[128\]~252 238 COMB LCCOMB_X23_Y8_N2 3 " "Info: 238: + IC(0.519 ns) + CELL(0.322 ns) = 90.863 ns; Loc. = LCCOMB_X23_Y8_N2; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[128\]~252'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.841 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[128]~252 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.930 ns) + CELL(0.517 ns) 92.310 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[3\]~5 239 COMB LCCOMB_X24_Y12_N22 2 " "Info: 239: + IC(0.930 ns) + CELL(0.517 ns) = 92.310 ns; Loc. = LCCOMB_X24_Y12_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.447 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[128]~252 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 92.390 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[4\]~7 240 COMB LCCOMB_X24_Y12_N24 1 " "Info: 240: + IC(0.000 ns) + CELL(0.080 ns) = 92.390 ns; Loc. = LCCOMB_X24_Y12_N24; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 92.470 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[5\]~9 241 COMB LCCOMB_X24_Y12_N26 1 " "Info: 241: + IC(0.000 ns) + CELL(0.080 ns) = 92.470 ns; Loc. = LCCOMB_X24_Y12_N26; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 92.928 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[6\]~10 242 COMB LCCOMB_X24_Y12_N28 16 " "Info: 242: + IC(0.000 ns) + CELL(0.458 ns) = 92.928 ns; Loc. = LCCOMB_X24_Y12_N28; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.919 ns) + CELL(0.322 ns) 94.169 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[134\]~260 243 COMB LCCOMB_X24_Y8_N26 3 " "Info: 243: + IC(0.919 ns) + CELL(0.322 ns) = 94.169 ns; Loc. = LCCOMB_X24_Y8_N26; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[134\]~260'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.241 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[134]~260 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.899 ns) + CELL(0.495 ns) 95.563 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[3\]~5 244 COMB LCCOMB_X25_Y12_N18 2 " "Info: 244: + IC(0.899 ns) + CELL(0.495 ns) = 95.563 ns; Loc. = LCCOMB_X25_Y12_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.394 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[134]~260 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 95.643 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[4\]~7 245 COMB LCCOMB_X25_Y12_N20 1 " "Info: 245: + IC(0.000 ns) + CELL(0.080 ns) = 95.643 ns; Loc. = LCCOMB_X25_Y12_N20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 95.723 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[5\]~9 246 COMB LCCOMB_X25_Y12_N22 1 " "Info: 246: + IC(0.000 ns) + CELL(0.080 ns) = 95.723 ns; Loc. = LCCOMB_X25_Y12_N22; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 96.181 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[6\]~10 247 COMB LCCOMB_X25_Y12_N24 16 " "Info: 247: + IC(0.000 ns) + CELL(0.458 ns) = 96.181 ns; Loc. = LCCOMB_X25_Y12_N24; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.581 ns) + CELL(0.178 ns) 96.940 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[140\]~268 248 COMB LCCOMB_X24_Y12_N14 3 " "Info: 248: + IC(0.581 ns) + CELL(0.178 ns) = 96.940 ns; Loc. = LCCOMB_X24_Y12_N14; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[140\]~268'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.759 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[140]~268 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.849 ns) + CELL(0.517 ns) 98.306 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[3\]~5 249 COMB LCCOMB_X26_Y12_N6 2 " "Info: 249: + IC(0.849 ns) + CELL(0.517 ns) = 98.306 ns; Loc. = LCCOMB_X26_Y12_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.366 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[140]~268 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 98.386 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[4\]~7 250 COMB LCCOMB_X26_Y12_N8 1 " "Info: 250: + IC(0.000 ns) + CELL(0.080 ns) = 98.386 ns; Loc. = LCCOMB_X26_Y12_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 98.466 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[5\]~9 251 COMB LCCOMB_X26_Y12_N10 1 " "Info: 251: + IC(0.000 ns) + CELL(0.080 ns) = 98.466 ns; Loc. = LCCOMB_X26_Y12_N10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 98.924 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[6\]~10 252 COMB LCCOMB_X26_Y12_N12 16 " "Info: 252: + IC(0.000 ns) + CELL(0.458 ns) = 98.924 ns; Loc. = LCCOMB_X26_Y12_N12; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.584 ns) + CELL(0.322 ns) 99.830 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[146\]~276 253 COMB LCCOMB_X25_Y12_N2 3 " "Info: 253: + IC(0.584 ns) + CELL(0.322 ns) = 99.830 ns; Loc. = LCCOMB_X25_Y12_N2; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[146\]~276'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.906 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~276 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.851 ns) + CELL(0.495 ns) 101.176 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[3\]~5 254 COMB LCCOMB_X27_Y12_N16 2 " "Info: 254: + IC(0.851 ns) + CELL(0.495 ns) = 101.176 ns; Loc. = LCCOMB_X27_Y12_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.346 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~276 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 101.256 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[4\]~7 255 COMB LCCOMB_X27_Y12_N18 1 " "Info: 255: + IC(0.000 ns) + CELL(0.080 ns) = 101.256 ns; Loc. = LCCOMB_X27_Y12_N18; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 101.336 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[5\]~9 256 COMB LCCOMB_X27_Y12_N20 1 " "Info: 256: + IC(0.000 ns) + CELL(0.080 ns) = 101.336 ns; Loc. = LCCOMB_X27_Y12_N20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 101.794 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[6\]~10 257 COMB LCCOMB_X27_Y12_N22 16 " "Info: 257: + IC(0.000 ns) + CELL(0.458 ns) = 101.794 ns; Loc. = LCCOMB_X27_Y12_N22; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.917 ns) + CELL(0.322 ns) 103.033 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[150\]~289 258 COMB LCCOMB_X27_Y10_N4 2 " "Info: 258: + IC(0.917 ns) + CELL(0.322 ns) = 103.033 ns; Loc. = LCCOMB_X27_Y10_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[150\]~289'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.239 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[150]~289 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.537 ns) + CELL(0.517 ns) 104.087 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[1\]~1 259 COMB LCCOMB_X27_Y10_N10 2 " "Info: 259: + IC(0.537 ns) + CELL(0.517 ns) = 104.087 ns; Loc. = LCCOMB_X27_Y10_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.054 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[150]~289 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 104.167 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[2\]~3 260 COMB LCCOMB_X27_Y10_N12 2 " "Info: 260: + IC(0.000 ns) + CELL(0.080 ns) = 104.167 ns; Loc. = LCCOMB_X27_Y10_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 104.341 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[3\]~5 261 COMB LCCOMB_X27_Y10_N14 2 " "Info: 261: + IC(0.000 ns) + CELL(0.174 ns) = 104.341 ns; Loc. = LCCOMB_X27_Y10_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 104.421 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[4\]~7 262 COMB LCCOMB_X27_Y10_N16 1 " "Info: 262: + IC(0.000 ns) + CELL(0.080 ns) = 104.421 ns; Loc. = LCCOMB_X27_Y10_N16; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 104.501 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[5\]~9 263 COMB LCCOMB_X27_Y10_N18 1 " "Info: 263: + IC(0.000 ns) + CELL(0.080 ns) = 104.501 ns; Loc. = LCCOMB_X27_Y10_N18; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 104.959 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[6\]~10 264 COMB LCCOMB_X27_Y10_N20 16 " "Info: 264: + IC(0.000 ns) + CELL(0.458 ns) = 104.959 ns; Loc. = LCCOMB_X27_Y10_N20; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.914 ns) + CELL(0.178 ns) 106.051 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[158\]~292 265 COMB LCCOMB_X27_Y12_N26 3 " "Info: 265: + IC(0.914 ns) + CELL(0.178 ns) = 106.051 ns; Loc. = LCCOMB_X27_Y12_N26; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[158\]~292'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.092 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[158]~292 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.207 ns) + CELL(0.517 ns) 107.775 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[3\]~5 266 COMB LCCOMB_X31_Y10_N20 2 " "Info: 266: + IC(1.207 ns) + CELL(0.517 ns) = 107.775 ns; Loc. = LCCOMB_X31_Y10_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.724 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[158]~292 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 107.855 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[4\]~7 267 COMB LCCOMB_X31_Y10_N22 1 " "Info: 267: + IC(0.000 ns) + CELL(0.080 ns) = 107.855 ns; Loc. = LCCOMB_X31_Y10_N22; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 107.935 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[5\]~9 268 COMB LCCOMB_X31_Y10_N24 1 " "Info: 268: + IC(0.000 ns) + CELL(0.080 ns) = 107.935 ns; Loc. = LCCOMB_X31_Y10_N24; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 108.393 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[6\]~10 269 COMB LCCOMB_X31_Y10_N26 16 " "Info: 269: + IC(0.000 ns) + CELL(0.458 ns) = 108.393 ns; Loc. = LCCOMB_X31_Y10_N26; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.842 ns) + CELL(0.178 ns) 109.413 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[164\]~300 270 COMB LCCOMB_X27_Y10_N26 3 " "Info: 270: + IC(0.842 ns) + CELL(0.178 ns) = 109.413 ns; Loc. = LCCOMB_X27_Y10_N26; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[164\]~300'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.020 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[164]~300 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.384 ns) + CELL(0.495 ns) 111.292 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[3\]~5 271 COMB LCCOMB_X36_Y10_N16 2 " "Info: 271: + IC(1.384 ns) + CELL(0.495 ns) = 111.292 ns; Loc. = LCCOMB_X36_Y10_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.879 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[164]~300 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 111.372 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[4\]~7 272 COMB LCCOMB_X36_Y10_N18 1 " "Info: 272: + IC(0.000 ns) + CELL(0.080 ns) = 111.372 ns; Loc. = LCCOMB_X36_Y10_N18; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 111.452 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[5\]~9 273 COMB LCCOMB_X36_Y10_N20 1 " "Info: 273: + IC(0.000 ns) + CELL(0.080 ns) = 111.452 ns; Loc. = LCCOMB_X36_Y10_N20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 111.910 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[6\]~10 274 COMB LCCOMB_X36_Y10_N22 16 " "Info: 274: + IC(0.000 ns) + CELL(0.458 ns) = 111.910 ns; Loc. = LCCOMB_X36_Y10_N22; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.106 ns) + CELL(0.178 ns) 113.194 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[170\]~308 275 COMB LCCOMB_X31_Y10_N30 3 " "Info: 275: + IC(1.106 ns) + CELL(0.178 ns) = 113.194 ns; Loc. = LCCOMB_X31_Y10_N30; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[170\]~308'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.284 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[170]~308 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.058 ns) + CELL(0.495 ns) 114.747 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[3\]~5 276 COMB LCCOMB_X37_Y10_N4 2 " "Info: 276: + IC(1.058 ns) + CELL(0.495 ns) = 114.747 ns; Loc. = LCCOMB_X37_Y10_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.553 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[170]~308 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 114.827 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[4\]~7 277 COMB LCCOMB_X37_Y10_N6 1 " "Info: 277: + IC(0.000 ns) + CELL(0.080 ns) = 114.827 ns; Loc. = LCCOMB_X37_Y10_N6; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 114.907 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[5\]~9 278 COMB LCCOMB_X37_Y10_N8 1 " "Info: 278: + IC(0.000 ns) + CELL(0.080 ns) = 114.907 ns; Loc. = LCCOMB_X37_Y10_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 115.365 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[6\]~10 279 COMB LCCOMB_X37_Y10_N10 17 " "Info: 279: + IC(0.000 ns) + CELL(0.458 ns) = 115.365 ns; Loc. = LCCOMB_X37_Y10_N10; Fanout = 17; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.572 ns) + CELL(0.322 ns) 116.259 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[176\]~316 280 COMB LCCOMB_X36_Y10_N2 3 " "Info: 280: + IC(0.572 ns) + CELL(0.322 ns) = 116.259 ns; Loc. = LCCOMB_X36_Y10_N2; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[176\]~316'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.894 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~316 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.943 ns) + CELL(0.517 ns) 117.719 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[3\]~5 281 COMB LCCOMB_X37_Y14_N4 2 " "Info: 281: + IC(0.943 ns) + CELL(0.517 ns) = 117.719 ns; Loc. = LCCOMB_X37_Y14_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.460 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~316 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 117.799 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[4\]~7 282 COMB LCCOMB_X37_Y14_N6 1 " "Info: 282: + IC(0.000 ns) + CELL(0.080 ns) = 117.799 ns; Loc. = LCCOMB_X37_Y14_N6; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 117.879 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[5\]~9 283 COMB LCCOMB_X37_Y14_N8 1 " "Info: 283: + IC(0.000 ns) + CELL(0.080 ns) = 117.879 ns; Loc. = LCCOMB_X37_Y14_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 118.337 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[6\]~10 284 COMB LCCOMB_X37_Y14_N10 13 " "Info: 284: + IC(0.000 ns) + CELL(0.458 ns) = 118.337 ns; Loc. = LCCOMB_X37_Y14_N10; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.981 ns) + CELL(0.178 ns) 119.496 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[182\]~324 285 COMB LCCOMB_X37_Y10_N26 1 " "Info: 285: + IC(0.981 ns) + CELL(0.178 ns) = 119.496 ns; Loc. = LCCOMB_X37_Y10_N26; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[182\]~324'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.159 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[182]~324 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.243 ns) + CELL(0.495 ns) 121.234 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[3\]~5 286 COMB LCCOMB_X37_Y18_N6 1 " "Info: 286: + IC(1.243 ns) + CELL(0.495 ns) = 121.234 ns; Loc. = LCCOMB_X37_Y18_N6; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.738 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[182]~324 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 121.314 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[4\]~7 287 COMB LCCOMB_X37_Y18_N8 1 " "Info: 287: + IC(0.000 ns) + CELL(0.080 ns) = 121.314 ns; Loc. = LCCOMB_X37_Y18_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 121.394 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[5\]~9 288 COMB LCCOMB_X37_Y18_N10 1 " "Info: 288: + IC(0.000 ns) + CELL(0.080 ns) = 121.394 ns; Loc. = LCCOMB_X37_Y18_N10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 121.852 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[6\]~10 289 COMB LCCOMB_X37_Y18_N12 3 " "Info: 289: + IC(0.000 ns) + CELL(0.458 ns) = 121.852 ns; Loc. = LCCOMB_X37_Y18_N12; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.995 ns) + CELL(0.495 ns) 124.342 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~1 290 COMB LCCOMB_X23_Y22_N2 2 " "Info: 290: + IC(1.995 ns) + CELL(0.495 ns) = 124.342 ns; Loc. = LCCOMB_X23_Y22_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~1 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 124.422 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~3 291 COMB LCCOMB_X23_Y22_N4 2 " "Info: 291: + IC(0.000 ns) + CELL(0.080 ns) = 124.422 ns; Loc. = LCCOMB_X23_Y22_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~3 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 124.502 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~5 292 COMB LCCOMB_X23_Y22_N6 2 " "Info: 292: + IC(0.000 ns) + CELL(0.080 ns) = 124.502 ns; Loc. = LCCOMB_X23_Y22_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 124.582 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~7 293 COMB LCCOMB_X23_Y22_N8 2 " "Info: 293: + IC(0.000 ns) + CELL(0.080 ns) = 124.582 ns; Loc. = LCCOMB_X23_Y22_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~7 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 124.662 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~9 294 COMB LCCOMB_X23_Y22_N10 2 " "Info: 294: + IC(0.000 ns) + CELL(0.080 ns) = 124.662 ns; Loc. = LCCOMB_X23_Y22_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~9 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 124.742 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~11 295 COMB LCCOMB_X23_Y22_N12 2 " "Info: 295: + IC(0.000 ns) + CELL(0.080 ns) = 124.742 ns; Loc. = LCCOMB_X23_Y22_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~11 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 124.916 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~13 296 COMB LCCOMB_X23_Y22_N14 2 " "Info: 296: + IC(0.000 ns) + CELL(0.174 ns) = 124.916 ns; Loc. = LCCOMB_X23_Y22_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~13 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 124.996 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~15 297 COMB LCCOMB_X23_Y22_N16 2 " "Info: 297: + IC(0.000 ns) + CELL(0.080 ns) = 124.996 ns; Loc. = LCCOMB_X23_Y22_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~15 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 125.076 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~17 298 COMB LCCOMB_X23_Y22_N18 2 " "Info: 298: + IC(0.000 ns) + CELL(0.080 ns) = 125.076 ns; Loc. = LCCOMB_X23_Y22_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~17 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 125.156 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~19 299 COMB LCCOMB_X23_Y22_N20 2 " "Info: 299: + IC(0.000 ns) + CELL(0.080 ns) = 125.156 ns; Loc. = LCCOMB_X23_Y22_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~19 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 125.236 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~21 300 COMB LCCOMB_X23_Y22_N22 2 " "Info: 300: + IC(0.000 ns) + CELL(0.080 ns) = 125.236 ns; Loc. = LCCOMB_X23_Y22_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~21 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 125.316 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~23 301 COMB LCCOMB_X23_Y22_N24 2 " "Info: 301: + IC(0.000 ns) + CELL(0.080 ns) = 125.316 ns; Loc. = LCCOMB_X23_Y22_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~23 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 125.396 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~25 302 COMB LCCOMB_X23_Y22_N26 2 " "Info: 302: + IC(0.000 ns) + CELL(0.080 ns) = 125.396 ns; Loc. = LCCOMB_X23_Y22_N26; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~25 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 125.476 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~27 303 COMB LCCOMB_X23_Y22_N28 2 " "Info: 303: + IC(0.000 ns) + CELL(0.080 ns) = 125.476 ns; Loc. = LCCOMB_X23_Y22_N28; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~27 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 125.637 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~29 304 COMB LCCOMB_X23_Y22_N30 2 " "Info: 304: + IC(0.000 ns) + CELL(0.161 ns) = 125.637 ns; Loc. = LCCOMB_X23_Y22_N30; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.161 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~29 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 125.717 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~31 305 COMB LCCOMB_X23_Y21_N0 2 " "Info: 305: + IC(0.000 ns) + CELL(0.080 ns) = 125.717 ns; Loc. = LCCOMB_X23_Y21_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~31 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 125.797 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~33 306 COMB LCCOMB_X23_Y21_N2 2 " "Info: 306: + IC(0.000 ns) + CELL(0.080 ns) = 125.797 ns; Loc. = LCCOMB_X23_Y21_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~33 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 125.877 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~35 307 COMB LCCOMB_X23_Y21_N4 2 " "Info: 307: + IC(0.000 ns) + CELL(0.080 ns) = 125.877 ns; Loc. = LCCOMB_X23_Y21_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~33 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~35 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 125.957 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~37 308 COMB LCCOMB_X23_Y21_N6 2 " "Info: 308: + IC(0.000 ns) + CELL(0.080 ns) = 125.957 ns; Loc. = LCCOMB_X23_Y21_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~35 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~37 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 126.037 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~39 309 COMB LCCOMB_X23_Y21_N8 2 " "Info: 309: + IC(0.000 ns) + CELL(0.080 ns) = 126.037 ns; Loc. = LCCOMB_X23_Y21_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~37 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~39 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 126.117 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~41 310 COMB LCCOMB_X23_Y21_N10 2 " "Info: 310: + IC(0.000 ns) + CELL(0.080 ns) = 126.117 ns; Loc. = LCCOMB_X23_Y21_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~39 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~41 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 126.197 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~43 311 COMB LCCOMB_X23_Y21_N12 2 " "Info: 311: + IC(0.000 ns) + CELL(0.080 ns) = 126.197 ns; Loc. = LCCOMB_X23_Y21_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~41 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~43 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 126.371 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~45 312 COMB LCCOMB_X23_Y21_N14 2 " "Info: 312: + IC(0.000 ns) + CELL(0.174 ns) = 126.371 ns; Loc. = LCCOMB_X23_Y21_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~43 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~45 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 126.829 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~46 313 COMB LCCOMB_X23_Y21_N16 1 " "Info: 313: + IC(0.000 ns) + CELL(0.458 ns) = 126.829 ns; Loc. = LCCOMB_X23_Y21_N16; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~46'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~45 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~46 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.801 ns) + CELL(0.178 ns) 127.808 ns Arkanoid:inst\|Equal6~5 314 COMB LCCOMB_X22_Y21_N16 1 " "Info: 314: + IC(0.801 ns) + CELL(0.178 ns) = 127.808 ns; Loc. = LCCOMB_X22_Y21_N16; Fanout = 1; COMB Node = 'Arkanoid:inst\|Equal6~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.979 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~46 Arkanoid:inst|Equal6~5 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.318 ns) + CELL(0.545 ns) 128.671 ns Arkanoid:inst\|Equal6~6 315 COMB LCCOMB_X22_Y21_N26 2 " "Info: 315: + IC(0.318 ns) + CELL(0.545 ns) = 128.671 ns; Loc. = LCCOMB_X22_Y21_N26; Fanout = 2; COMB Node = 'Arkanoid:inst\|Equal6~6'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.863 ns" { Arkanoid:inst|Equal6~5 Arkanoid:inst|Equal6~6 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.302 ns) + CELL(0.491 ns) 129.464 ns Arkanoid:inst\|Equal6~7 316 COMB LCCOMB_X22_Y21_N20 1 " "Info: 316: + IC(0.302 ns) + CELL(0.491 ns) = 129.464 ns; Loc. = LCCOMB_X22_Y21_N20; Fanout = 1; COMB Node = 'Arkanoid:inst\|Equal6~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.793 ns" { Arkanoid:inst|Equal6~6 Arkanoid:inst|Equal6~7 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.810 ns) + CELL(0.521 ns) 130.795 ns Arkanoid:inst\|Equal6~24 317 COMB LCCOMB_X21_Y20_N22 5 " "Info: 317: + IC(0.810 ns) + CELL(0.521 ns) = 130.795 ns; Loc. = LCCOMB_X21_Y20_N22; Fanout = 5; COMB Node = 'Arkanoid:inst\|Equal6~24'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.331 ns" { Arkanoid:inst|Equal6~7 Arkanoid:inst|Equal6~24 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.178 ns) 131.316 ns Arkanoid:inst\|Equal7~0 318 COMB LCCOMB_X21_Y20_N8 2 " "Info: 318: + IC(0.343 ns) + CELL(0.178 ns) = 131.316 ns; Loc. = LCCOMB_X21_Y20_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|Equal7~0'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.521 ns" { Arkanoid:inst|Equal6~24 Arkanoid:inst|Equal7~0 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.308 ns) + CELL(0.322 ns) 131.946 ns Arkanoid:inst\|WideOr0~0 319 COMB LCCOMB_X21_Y20_N10 3 " "Info: 319: + IC(0.308 ns) + CELL(0.322 ns) = 131.946 ns; Loc. = LCCOMB_X21_Y20_N10; Fanout = 3; COMB Node = 'Arkanoid:inst\|WideOr0~0'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.630 ns" { Arkanoid:inst|Equal7~0 Arkanoid:inst|WideOr0~0 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.134 ns) + CELL(0.178 ns) 133.258 ns Arkanoid:inst\|high~8 320 COMB LCCOMB_X16_Y20_N26 1 " "Info: 320: + IC(1.134 ns) + CELL(0.178 ns) = 133.258 ns; Loc. = LCCOMB_X16_Y20_N26; Fanout = 1; COMB Node = 'Arkanoid:inst\|high~8'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.312 ns" { Arkanoid:inst|WideOr0~0 Arkanoid:inst|high~8 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 133.354 ns Arkanoid:inst\|hex3_\[5\] 321 REG LCFF_X16_Y20_N27 1 " "Info: 321: + IC(0.000 ns) + CELL(0.096 ns) = 133.354 ns; Loc. = LCFF_X16_Y20_N27; Fanout = 1; REG Node = 'Arkanoid:inst\|hex3_\[5\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { Arkanoid:inst|high~8 Arkanoid:inst|hex3_[5] } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "65.654 ns ( 49.23 % ) " "Info: Total cell delay = 65.654 ns ( 49.23 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "67.700 ns ( 50.77 % ) " "Info: Total interconnect delay = 67.700 ns ( 50.77 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "133.354 ns" { Arkanoid:inst|button1_state Arkanoid:inst|platform2_position~4 Arkanoid:inst|platform2_position~6 Arkanoid:inst|Add4~1 Arkanoid:inst|Add4~3 Arkanoid:inst|Add4~5 Arkanoid:inst|Add4~7 Arkanoid:inst|Add4~9 Arkanoid:inst|Add4~11 Arkanoid:inst|Add4~13 Arkanoid:inst|Add4~15 Arkanoid:inst|Add4~17 Arkanoid:inst|Add4~19 Arkanoid:inst|Add4~21 Arkanoid:inst|Add4~23 Arkanoid:inst|Add4~25 Arkanoid:inst|Add4~27 Arkanoid:inst|Add4~29 Arkanoid:inst|Add4~31 Arkanoid:inst|Add4~33 Arkanoid:inst|Add4~35 Arkanoid:inst|Add4~37 Arkanoid:inst|Add4~39 Arkanoid:inst|Add4~41 Arkanoid:inst|Add4~43 Arkanoid:inst|Add4~45 Arkanoid:inst|Add4~47 Arkanoid:inst|Add4~49 Arkanoid:inst|Add4~50 Arkanoid:inst|platform2_position~34 Arkanoid:inst|LessThan3~2 Arkanoid:inst|LessThan3~3 Arkanoid:inst|LessThan3~9 Arkanoid:inst|Add5~1 Arkanoid:inst|Add5~3 Arkanoid:inst|Add5~5 Arkanoid:inst|Add5~7 Arkanoid:inst|Add5~9 Arkanoid:inst|Add5~11 Arkanoid:inst|Add5~13 Arkanoid:inst|Add5~15 Arkanoid:inst|Add5~17 Arkanoid:inst|Add5~19 Arkanoid:inst|Add5~21 Arkanoid:inst|Add5~23 Arkanoid:inst|Add5~25 Arkanoid:inst|Add5~27 Arkanoid:inst|Add5~29 Arkanoid:inst|Add5~31 Arkanoid:inst|Add5~33 Arkanoid:inst|Add5~35 Arkanoid:inst|Add5~37 Arkanoid:inst|Add5~39 Arkanoid:inst|Add5~41 Arkanoid:inst|Add5~43 Arkanoid:inst|Add5~45 Arkanoid:inst|Add5~47 Arkanoid:inst|Add5~49 Arkanoid:inst|Add5~51 Arkanoid:inst|Add5~52 Arkanoid:inst|platform2_position~84 Arkanoid:inst|Add7~53 Arkanoid:inst|Add7~55 Arkanoid:inst|Add7~56 Arkanoid:inst|LessThan139~57 Arkanoid:inst|LessThan139~59 Arkanoid:inst|LessThan139~61 Arkanoid:inst|LessThan139~62 Arkanoid:inst|always2~4 Arkanoid:inst|Add9~1 Arkanoid:inst|Add9~3 Arkanoid:inst|Add9~5 Arkanoid:inst|Add9~7 Arkanoid:inst|Add9~9 Arkanoid:inst|Add9~11 Arkanoid:inst|Add9~13 Arkanoid:inst|Add9~15 Arkanoid:inst|Add9~17 Arkanoid:inst|Add9~19 Arkanoid:inst|Add9~21 Arkanoid:inst|Add9~23 Arkanoid:inst|Add9~25 Arkanoid:inst|Add9~27 Arkanoid:inst|Add9~29 Arkanoid:inst|Add9~31 Arkanoid:inst|Add9~33 Arkanoid:inst|Add9~35 Arkanoid:inst|Add9~37 Arkanoid:inst|Add9~39 Arkanoid:inst|Add9~41 Arkanoid:inst|Add9~43 Arkanoid:inst|Add9~45 Arkanoid:inst|Add9~47 Arkanoid:inst|Add9~49 Arkanoid:inst|Add9~51 Arkanoid:inst|Add9~53 Arkanoid:inst|Add9~55 Arkanoid:inst|Add9~57 Arkanoid:inst|Add9~59 Arkanoid:inst|Add9~61 Arkanoid:inst|Add9~63 Arkanoid:inst|Add9~65 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~56 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[20]~106 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[27]~115 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[30]~129 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~136 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[42]~144 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[48]~153 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[57]~339 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[60]~169 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[67]~174 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[75]~179 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[82]~186 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[85]~198 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[90]~208 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[96]~216 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~225 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[109]~231 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[116]~237 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~244 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[128]~252 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[134]~260 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[140]~268 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~276 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[150]~289 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[158]~292 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[164]~300 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[170]~308 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~316 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[182]~324 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~33 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~35 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~37 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~39 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~41 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~43 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~45 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~46 Arkanoid:inst|Equal6~5 Arkanoid:inst|Equal6~6 Arkanoid:inst|Equal6~7 Arkanoid:inst|Equal6~24 Arkanoid:inst|Equal7~0 Arkanoid:inst|WideOr0~0 Arkanoid:inst|high~8 Arkanoid:inst|hex3_[5] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "133.354 ns" { Arkanoid:inst|button1_state {} Arkanoid:inst|platform2_position~4 {} Arkanoid:inst|platform2_position~6 {} Arkanoid:inst|Add4~1 {} Arkanoid:inst|Add4~3 {} Arkanoid:inst|Add4~5 {} Arkanoid:inst|Add4~7 {} Arkanoid:inst|Add4~9 {} Arkanoid:inst|Add4~11 {} Arkanoid:inst|Add4~13 {} Arkanoid:inst|Add4~15 {} Arkanoid:inst|Add4~17 {} Arkanoid:inst|Add4~19 {} Arkanoid:inst|Add4~21 {} Arkanoid:inst|Add4~23 {} Arkanoid:inst|Add4~25 {} Arkanoid:inst|Add4~27 {} Arkanoid:inst|Add4~29 {} Arkanoid:inst|Add4~31 {} Arkanoid:inst|Add4~33 {} Arkanoid:inst|Add4~35 {} Arkanoid:inst|Add4~37 {} Arkanoid:inst|Add4~39 {} Arkanoid:inst|Add4~41 {} Arkanoid:inst|Add4~43 {} Arkanoid:inst|Add4~45 {} Arkanoid:inst|Add4~47 {} Arkanoid:inst|Add4~49 {} Arkanoid:inst|Add4~50 {} Arkanoid:inst|platform2_position~34 {} Arkanoid:inst|LessThan3~2 {} Arkanoid:inst|LessThan3~3 {} Arkanoid:inst|LessThan3~9 {} Arkanoid:inst|Add5~1 {} Arkanoid:inst|Add5~3 {} Arkanoid:inst|Add5~5 {} Arkanoid:inst|Add5~7 {} Arkanoid:inst|Add5~9 {} Arkanoid:inst|Add5~11 {} Arkanoid:inst|Add5~13 {} Arkanoid:inst|Add5~15 {} Arkanoid:inst|Add5~17 {} Arkanoid:inst|Add5~19 {} Arkanoid:inst|Add5~21 {} Arkanoid:inst|Add5~23 {} Arkanoid:inst|Add5~25 {} Arkanoid:inst|Add5~27 {} Arkanoid:inst|Add5~29 {} Arkanoid:inst|Add5~31 {} Arkanoid:inst|Add5~33 {} Arkanoid:inst|Add5~35 {} Arkanoid:inst|Add5~37 {} Arkanoid:inst|Add5~39 {} Arkanoid:inst|Add5~41 {} Arkanoid:inst|Add5~43 {} Arkanoid:inst|Add5~45 {} Arkanoid:inst|Add5~47 {} Arkanoid:inst|Add5~49 {} Arkanoid:inst|Add5~51 {} Arkanoid:inst|Add5~52 {} Arkanoid:inst|platform2_position~84 {} Arkanoid:inst|Add7~53 {} Arkanoid:inst|Add7~55 {} Arkanoid:inst|Add7~56 {} Arkanoid:inst|LessThan139~57 {} Arkanoid:inst|LessThan139~59 {} Arkanoid:inst|LessThan139~61 {} Arkanoid:inst|LessThan139~62 {} Arkanoid:inst|always2~4 {} Arkanoid:inst|Add9~1 {} Arkanoid:inst|Add9~3 {} Arkanoid:inst|Add9~5 {} Arkanoid:inst|Add9~7 {} Arkanoid:inst|Add9~9 {} Arkanoid:inst|Add9~11 {} Arkanoid:inst|Add9~13 {} Arkanoid:inst|Add9~15 {} Arkanoid:inst|Add9~17 {} Arkanoid:inst|Add9~19 {} Arkanoid:inst|Add9~21 {} Arkanoid:inst|Add9~23 {} Arkanoid:inst|Add9~25 {} Arkanoid:inst|Add9~27 {} Arkanoid:inst|Add9~29 {} Arkanoid:inst|Add9~31 {} Arkanoid:inst|Add9~33 {} Arkanoid:inst|Add9~35 {} Arkanoid:inst|Add9~37 {} Arkanoid:inst|Add9~39 {} Arkanoid:inst|Add9~41 {} Arkanoid:inst|Add9~43 {} Arkanoid:inst|Add9~45 {} Arkanoid:inst|Add9~47 {} Arkanoid:inst|Add9~49 {} Arkanoid:inst|Add9~51 {} Arkanoid:inst|Add9~53 {} Arkanoid:inst|Add9~55 {} Arkanoid:inst|Add9~57 {} Arkanoid:inst|Add9~59 {} Arkanoid:inst|Add9~61 {} Arkanoid:inst|Add9~63 {} Arkanoid:inst|Add9~65 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~56 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[20]~106 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[27]~115 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[30]~129 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~136 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[42]~144 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[48]~153 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[57]~339 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[60]~169 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[67]~174 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[75]~179 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[82]~186 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[85]~198 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[90]~208 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[96]~216 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~225 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[109]~231 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[116]~237 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~244 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[128]~252 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[134]~260 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[140]~268 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~276 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[150]~289 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[158]~292 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[164]~300 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[170]~308 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~316 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[182]~324 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~11 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~13 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~15 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~17 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~19 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~21 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~23 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~25 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~27 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~29 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~31 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~33 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~35 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~37 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~39 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~41 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~43 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~45 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~46 {} Arkanoid:inst|Equal6~5 {} Arkanoid:inst|Equal6~6 {} Arkanoid:inst|Equal6~7 {} Arkanoid:inst|Equal6~24 {} Arkanoid:inst|Equal7~0 {} Arkanoid:inst|WideOr0~0 {} Arkanoid:inst|high~8 {} Arkanoid:inst|hex3_[5] {} } { 0.000ns 0.400ns 0.941ns 0.961ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.527ns 0.595ns 0.821ns 0.534ns 0.825ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.890ns 1.381ns 0.000ns 0.000ns 0.548ns 0.000ns 0.000ns 0.000ns 1.730ns 1.404ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.193ns 1.291ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.497ns 0.000ns 0.000ns 0.000ns 0.583ns 0.558ns 0.000ns 0.000ns 1.066ns 0.939ns 0.000ns 0.000ns 0.936ns 0.939ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.948ns 0.540ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.836ns 0.818ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.220ns 0.927ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.837ns 1.183ns 0.000ns 0.000ns 0.896ns 1.180ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.184ns 0.856ns 0.000ns 0.000ns 0.000ns 0.000ns 0.901ns 0.484ns 0.000ns 0.000ns 1.174ns 0.835ns 0.000ns 0.924ns 0.546ns 0.000ns 0.000ns 0.000ns 0.000ns 0.632ns 0.319ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.646ns 0.537ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.632ns 0.319ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.919ns 0.485ns 0.000ns 0.000ns 0.000ns 0.000ns 0.564ns 0.581ns 0.000ns 0.000ns 0.000ns 0.564ns 0.807ns 0.000ns 0.000ns 0.000ns 0.519ns 0.930ns 0.000ns 0.000ns 0.000ns 0.919ns 0.899ns 0.000ns 0.000ns 0.000ns 0.581ns 0.849ns 0.000ns 0.000ns 0.000ns 0.584ns 0.851ns 0.000ns 0.000ns 0.000ns 0.917ns 0.537ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.914ns 1.207ns 0.000ns 0.000ns 0.000ns 0.842ns 1.384ns 0.000ns 0.000ns 0.000ns 1.106ns 1.058ns 0.000ns 0.000ns 0.000ns 0.572ns 0.943ns 0.000ns 0.000ns 0.000ns 0.981ns 1.243ns 0.000ns 0.000ns 0.000ns 1.995ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.801ns 0.318ns 0.302ns 0.810ns 0.343ns 0.308ns 1.134ns 0.000ns } { 0.000ns 0.545ns 0.178ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.161ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.458ns 0.178ns 0.455ns 0.322ns 0.521ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.161ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.458ns 0.544ns 0.495ns 0.080ns 0.458ns 0.495ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.161ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.161ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.620ns 0.080ns 0.080ns 0.458ns 0.319ns 0.517ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.458ns 0.177ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.177ns 0.517ns 0.080ns 0.080ns 0.174ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.458ns 0.177ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.322ns 0.495ns 0.080ns 0.080ns 0.080ns 0.458ns 0.322ns 0.620ns 0.080ns 0.458ns 0.322ns 0.495ns 0.458ns 0.178ns 0.517ns 0.080ns 0.174ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.174ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.080ns 0.174ns 0.458ns 0.177ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.458ns 0.322ns 0.495ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.458ns 0.322ns 0.495ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.174ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.080ns 0.080ns 0.458ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.161ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.458ns 0.178ns 0.545ns 0.491ns 0.521ns 0.178ns 0.322ns 0.178ns 0.096ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.033 ns - Smallest " "Info: - Smallest clock skew is -0.033 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz destination 4.577 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_50MHz\" to destination register is 4.577 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk_50MHz 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -168 -72 96 -152 "clk_50MHz" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.404 ns) + CELL(0.879 ns) 2.309 ns ClockDivider:inst1\|clk25MHz_ 2 REG LCFF_X1_Y13_N29 2 " "Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'ClockDivider:inst1\|clk25MHz_'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.283 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.703 ns) + CELL(0.000 ns) 3.012 ns ClockDivider:inst1\|clk25MHz_~clkctrl 3 COMB CLKCTRL_G0 1085 " "Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G0; Fanout = 1085; COMB Node = 'ClockDivider:inst1\|clk25MHz_~clkctrl'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.703 ns" { ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.963 ns) + CELL(0.602 ns) 4.577 ns Arkanoid:inst\|hex3_\[5\] 4 REG LCFF_X16_Y20_N27 1 " "Info: 4: + IC(0.963 ns) + CELL(0.602 ns) = 4.577 ns; Loc. = LCFF_X16_Y20_N27; Fanout = 1; REG Node = 'Arkanoid:inst\|hex3_\[5\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.565 ns" { ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|hex3_[5] } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 54.77 % ) " "Info: Total cell delay = 2.507 ns ( 54.77 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.070 ns ( 45.23 % ) " "Info: Total interconnect delay = 2.070 ns ( 45.23 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.577 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|hex3_[5] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.577 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|hex3_[5] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.963ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz source 4.610 ns - Longest register " "Info: - Longest clock path from clock \"clk_50MHz\" to source register is 4.610 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk_50MHz 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -168 -72 96 -152 "clk_50MHz" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.404 ns) + CELL(0.879 ns) 2.309 ns ClockDivider:inst1\|clk25MHz_ 2 REG LCFF_X1_Y13_N29 2 " "Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'ClockDivider:inst1\|clk25MHz_'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.283 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.703 ns) + CELL(0.000 ns) 3.012 ns ClockDivider:inst1\|clk25MHz_~clkctrl 3 COMB CLKCTRL_G0 1085 " "Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G0; Fanout = 1085; COMB Node = 'ClockDivider:inst1\|clk25MHz_~clkctrl'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.703 ns" { ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.996 ns) + CELL(0.602 ns) 4.610 ns Arkanoid:inst\|button1_state 4 REG LCFF_X24_Y14_N7 4 " "Info: 4: + IC(0.996 ns) + CELL(0.602 ns) = 4.610 ns; Loc. = LCFF_X24_Y14_N7; Fanout = 4; REG Node = 'Arkanoid:inst\|button1_state'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.598 ns" { ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|button1_state } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 107 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 54.38 % ) " "Info: Total cell delay = 2.507 ns ( 54.38 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.103 ns ( 45.62 % ) " "Info: Total interconnect delay = 2.103 ns ( 45.62 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.610 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|button1_state } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.610 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|button1_state {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.996ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.577 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|hex3_[5] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.577 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|hex3_[5] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.963ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.610 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|button1_state } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.610 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|button1_state {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.996ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" { } { { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 107 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" { } { { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 18 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "133.354 ns" { Arkanoid:inst|button1_state Arkanoid:inst|platform2_position~4 Arkanoid:inst|platform2_position~6 Arkanoid:inst|Add4~1 Arkanoid:inst|Add4~3 Arkanoid:inst|Add4~5 Arkanoid:inst|Add4~7 Arkanoid:inst|Add4~9 Arkanoid:inst|Add4~11 Arkanoid:inst|Add4~13 Arkanoid:inst|Add4~15 Arkanoid:inst|Add4~17 Arkanoid:inst|Add4~19 Arkanoid:inst|Add4~21 Arkanoid:inst|Add4~23 Arkanoid:inst|Add4~25 Arkanoid:inst|Add4~27 Arkanoid:inst|Add4~29 Arkanoid:inst|Add4~31 Arkanoid:inst|Add4~33 Arkanoid:inst|Add4~35 Arkanoid:inst|Add4~37 Arkanoid:inst|Add4~39 Arkanoid:inst|Add4~41 Arkanoid:inst|Add4~43 Arkanoid:inst|Add4~45 Arkanoid:inst|Add4~47 Arkanoid:inst|Add4~49 Arkanoid:inst|Add4~50 Arkanoid:inst|platform2_position~34 Arkanoid:inst|LessThan3~2 Arkanoid:inst|LessThan3~3 Arkanoid:inst|LessThan3~9 Arkanoid:inst|Add5~1 Arkanoid:inst|Add5~3 Arkanoid:inst|Add5~5 Arkanoid:inst|Add5~7 Arkanoid:inst|Add5~9 Arkanoid:inst|Add5~11 Arkanoid:inst|Add5~13 Arkanoid:inst|Add5~15 Arkanoid:inst|Add5~17 Arkanoid:inst|Add5~19 Arkanoid:inst|Add5~21 Arkanoid:inst|Add5~23 Arkanoid:inst|Add5~25 Arkanoid:inst|Add5~27 Arkanoid:inst|Add5~29 Arkanoid:inst|Add5~31 Arkanoid:inst|Add5~33 Arkanoid:inst|Add5~35 Arkanoid:inst|Add5~37 Arkanoid:inst|Add5~39 Arkanoid:inst|Add5~41 Arkanoid:inst|Add5~43 Arkanoid:inst|Add5~45 Arkanoid:inst|Add5~47 Arkanoid:inst|Add5~49 Arkanoid:inst|Add5~51 Arkanoid:inst|Add5~52 Arkanoid:inst|platform2_position~84 Arkanoid:inst|Add7~53 Arkanoid:inst|Add7~55 Arkanoid:inst|Add7~56 Arkanoid:inst|LessThan139~57 Arkanoid:inst|LessThan139~59 Arkanoid:inst|LessThan139~61 Arkanoid:inst|LessThan139~62 Arkanoid:inst|always2~4 Arkanoid:inst|Add9~1 Arkanoid:inst|Add9~3 Arkanoid:inst|Add9~5 Arkanoid:inst|Add9~7 Arkanoid:inst|Add9~9 Arkanoid:inst|Add9~11 Arkanoid:inst|Add9~13 Arkanoid:inst|Add9~15 Arkanoid:inst|Add9~17 Arkanoid:inst|Add9~19 Arkanoid:inst|Add9~21 Arkanoid:inst|Add9~23 Arkanoid:inst|Add9~25 Arkanoid:inst|Add9~27 Arkanoid:inst|Add9~29 Arkanoid:inst|Add9~31 Arkanoid:inst|Add9~33 Arkanoid:inst|Add9~35 Arkanoid:inst|Add9~37 Arkanoid:inst|Add9~39 Arkanoid:inst|Add9~41 Arkanoid:inst|Add9~43 Arkanoid:inst|Add9~45 Arkanoid:inst|Add9~47 Arkanoid:inst|Add9~49 Arkanoid:inst|Add9~51 Arkanoid:inst|Add9~53 Arkanoid:inst|Add9~55 Arkanoid:inst|Add9~57 Arkanoid:inst|Add9~59 Arkanoid:inst|Add9~61 Arkanoid:inst|Add9~63 Arkanoid:inst|Add9~65 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~56 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[20]~106 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[27]~115 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[30]~129 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~136 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[42]~144 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[48]~153 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[57]~339 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[60]~169 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[67]~174 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[75]~179 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[82]~186 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[85]~198 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[90]~208 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[96]~216 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~225 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[109]~231 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[116]~237 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~244 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[128]~252 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[134]~260 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[140]~268 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~276 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[150]~289 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[158]~292 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[164]~300 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[170]~308 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~316 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[182]~324 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~33 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~35 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~37 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~39 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~41 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~43 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~45 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~46 Arkanoid:inst|Equal6~5 Arkanoid:inst|Equal6~6 Arkanoid:inst|Equal6~7 Arkanoid:inst|Equal6~24 Arkanoid:inst|Equal7~0 Arkanoid:inst|WideOr0~0 Arkanoid:inst|high~8 Arkanoid:inst|hex3_[5] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "133.354 ns" { Arkanoid:inst|button1_state {} Arkanoid:inst|platform2_position~4 {} Arkanoid:inst|platform2_position~6 {} Arkanoid:inst|Add4~1 {} Arkanoid:inst|Add4~3 {} Arkanoid:inst|Add4~5 {} Arkanoid:inst|Add4~7 {} Arkanoid:inst|Add4~9 {} Arkanoid:inst|Add4~11 {} Arkanoid:inst|Add4~13 {} Arkanoid:inst|Add4~15 {} Arkanoid:inst|Add4~17 {} Arkanoid:inst|Add4~19 {} Arkanoid:inst|Add4~21 {} Arkanoid:inst|Add4~23 {} Arkanoid:inst|Add4~25 {} Arkanoid:inst|Add4~27 {} Arkanoid:inst|Add4~29 {} Arkanoid:inst|Add4~31 {} Arkanoid:inst|Add4~33 {} Arkanoid:inst|Add4~35 {} Arkanoid:inst|Add4~37 {} Arkanoid:inst|Add4~39 {} Arkanoid:inst|Add4~41 {} Arkanoid:inst|Add4~43 {} Arkanoid:inst|Add4~45 {} Arkanoid:inst|Add4~47 {} Arkanoid:inst|Add4~49 {} Arkanoid:inst|Add4~50 {} Arkanoid:inst|platform2_position~34 {} Arkanoid:inst|LessThan3~2 {} Arkanoid:inst|LessThan3~3 {} Arkanoid:inst|LessThan3~9 {} Arkanoid:inst|Add5~1 {} Arkanoid:inst|Add5~3 {} Arkanoid:inst|Add5~5 {} Arkanoid:inst|Add5~7 {} Arkanoid:inst|Add5~9 {} Arkanoid:inst|Add5~11 {} Arkanoid:inst|Add5~13 {} Arkanoid:inst|Add5~15 {} Arkanoid:inst|Add5~17 {} Arkanoid:inst|Add5~19 {} Arkanoid:inst|Add5~21 {} Arkanoid:inst|Add5~23 {} Arkanoid:inst|Add5~25 {} Arkanoid:inst|Add5~27 {} Arkanoid:inst|Add5~29 {} Arkanoid:inst|Add5~31 {} Arkanoid:inst|Add5~33 {} Arkanoid:inst|Add5~35 {} Arkanoid:inst|Add5~37 {} Arkanoid:inst|Add5~39 {} Arkanoid:inst|Add5~41 {} Arkanoid:inst|Add5~43 {} Arkanoid:inst|Add5~45 {} Arkanoid:inst|Add5~47 {} Arkanoid:inst|Add5~49 {} Arkanoid:inst|Add5~51 {} Arkanoid:inst|Add5~52 {} Arkanoid:inst|platform2_position~84 {} Arkanoid:inst|Add7~53 {} Arkanoid:inst|Add7~55 {} Arkanoid:inst|Add7~56 {} Arkanoid:inst|LessThan139~57 {} Arkanoid:inst|LessThan139~59 {} Arkanoid:inst|LessThan139~61 {} Arkanoid:inst|LessThan139~62 {} Arkanoid:inst|always2~4 {} Arkanoid:inst|Add9~1 {} Arkanoid:inst|Add9~3 {} Arkanoid:inst|Add9~5 {} Arkanoid:inst|Add9~7 {} Arkanoid:inst|Add9~9 {} Arkanoid:inst|Add9~11 {} Arkanoid:inst|Add9~13 {} Arkanoid:inst|Add9~15 {} Arkanoid:inst|Add9~17 {} Arkanoid:inst|Add9~19 {} Arkanoid:inst|Add9~21 {} Arkanoid:inst|Add9~23 {} Arkanoid:inst|Add9~25 {} Arkanoid:inst|Add9~27 {} Arkanoid:inst|Add9~29 {} Arkanoid:inst|Add9~31 {} Arkanoid:inst|Add9~33 {} Arkanoid:inst|Add9~35 {} Arkanoid:inst|Add9~37 {} Arkanoid:inst|Add9~39 {} Arkanoid:inst|Add9~41 {} Arkanoid:inst|Add9~43 {} Arkanoid:inst|Add9~45 {} Arkanoid:inst|Add9~47 {} Arkanoid:inst|Add9~49 {} Arkanoid:inst|Add9~51 {} Arkanoid:inst|Add9~53 {} Arkanoid:inst|Add9~55 {} Arkanoid:inst|Add9~57 {} Arkanoid:inst|Add9~59 {} Arkanoid:inst|Add9~61 {} Arkanoid:inst|Add9~63 {} Arkanoid:inst|Add9~65 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~56 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[20]~106 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[27]~115 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[30]~129 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~136 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[42]~144 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[48]~153 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[57]~339 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[60]~169 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[67]~174 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[75]~179 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[82]~186 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[85]~198 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[90]~208 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[96]~216 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~225 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[109]~231 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[116]~237 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~244 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[128]~252 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[134]~260 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[140]~268 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~276 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[150]~289 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[158]~292 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[164]~300 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[170]~308 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~316 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[182]~324 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~11 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~13 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~15 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~17 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~19 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~21 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~23 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~25 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~27 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~29 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~31 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~33 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~35 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~37 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~39 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~41 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~43 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~45 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~46 {} Arkanoid:inst|Equal6~5 {} Arkanoid:inst|Equal6~6 {} Arkanoid:inst|Equal6~7 {} Arkanoid:inst|Equal6~24 {} Arkanoid:inst|Equal7~0 {} Arkanoid:inst|WideOr0~0 {} Arkanoid:inst|high~8 {} Arkanoid:inst|hex3_[5] {} } { 0.000ns 0.400ns 0.941ns 0.961ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.527ns 0.595ns 0.821ns 0.534ns 0.825ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.890ns 1.381ns 0.000ns 0.000ns 0.548ns 0.000ns 0.000ns 0.000ns 1.730ns 1.404ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.193ns 1.291ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.497ns 0.000ns 0.000ns 0.000ns 0.583ns 0.558ns 0.000ns 0.000ns 1.066ns 0.939ns 0.000ns 0.000ns 0.936ns 0.939ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.948ns 0.540ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.836ns 0.818ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.220ns 0.927ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.837ns 1.183ns 0.000ns 0.000ns 0.896ns 1.180ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.184ns 0.856ns 0.000ns 0.000ns 0.000ns 0.000ns 0.901ns 0.484ns 0.000ns 0.000ns 1.174ns 0.835ns 0.000ns 0.924ns 0.546ns 0.000ns 0.000ns 0.000ns 0.000ns 0.632ns 0.319ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.646ns 0.537ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.632ns 0.319ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.919ns 0.485ns 0.000ns 0.000ns 0.000ns 0.000ns 0.564ns 0.581ns 0.000ns 0.000ns 0.000ns 0.564ns 0.807ns 0.000ns 0.000ns 0.000ns 0.519ns 0.930ns 0.000ns 0.000ns 0.000ns 0.919ns 0.899ns 0.000ns 0.000ns 0.000ns 0.581ns 0.849ns 0.000ns 0.000ns 0.000ns 0.584ns 0.851ns 0.000ns 0.000ns 0.000ns 0.917ns 0.537ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.914ns 1.207ns 0.000ns 0.000ns 0.000ns 0.842ns 1.384ns 0.000ns 0.000ns 0.000ns 1.106ns 1.058ns 0.000ns 0.000ns 0.000ns 0.572ns 0.943ns 0.000ns 0.000ns 0.000ns 0.981ns 1.243ns 0.000ns 0.000ns 0.000ns 1.995ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.801ns 0.318ns 0.302ns 0.810ns 0.343ns 0.308ns 1.134ns 0.000ns } { 0.000ns 0.545ns 0.178ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.161ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.458ns 0.178ns 0.455ns 0.322ns 0.521ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.161ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.458ns 0.544ns 0.495ns 0.080ns 0.458ns 0.495ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.161ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.161ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.620ns 0.080ns 0.080ns 0.458ns 0.319ns 0.517ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.458ns 0.177ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.177ns 0.517ns 0.080ns 0.080ns 0.174ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.458ns 0.177ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.322ns 0.495ns 0.080ns 0.080ns 0.080ns 0.458ns 0.322ns 0.620ns 0.080ns 0.458ns 0.322ns 0.495ns 0.458ns 0.178ns 0.517ns 0.080ns 0.174ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.174ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.080ns 0.174ns 0.458ns 0.177ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.458ns 0.322ns 0.495ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.458ns 0.322ns 0.495ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.174ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.080ns 0.080ns 0.458ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.161ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.458ns 0.178ns 0.545ns 0.491ns 0.521ns 0.178ns 0.322ns 0.178ns 0.096ns } "" } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.577 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|hex3_[5] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.577 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|hex3_[5] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.963ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.610 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|button1_state } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.610 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|button1_state {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.996ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
+{ "Info" "ITDB_TSU_RESULT" "Debouncer:inst2\|button_reg\[0\] button1 clk_50MHz 3.120 ns register " "Info: tsu for register \"Debouncer:inst2\|button_reg\[0\]\" (data pin = \"button1\", clock pin = \"clk_50MHz\") is 3.120 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.768 ns + Longest pin register " "Info: + Longest pin to register delay is 7.768 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.874 ns) 0.874 ns button1 1 PIN PIN_T21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.874 ns) = 0.874 ns; Loc. = PIN_T21; Fanout = 1; PIN Node = 'button1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { button1 } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -72 -72 96 -56 "button1" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.481 ns) + CELL(0.413 ns) 7.768 ns Debouncer:inst2\|button_reg\[0\] 2 REG LCFF_X24_Y14_N29 2 " "Info: 2: + IC(6.481 ns) + CELL(0.413 ns) = 7.768 ns; Loc. = LCFF_X24_Y14_N29; Fanout = 2; REG Node = 'Debouncer:inst2\|button_reg\[0\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.894 ns" { button1 Debouncer:inst2|button_reg[0] } "NODE_NAME" } } { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.287 ns ( 16.57 % ) " "Info: Total cell delay = 1.287 ns ( 16.57 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.481 ns ( 83.43 % ) " "Info: Total interconnect delay = 6.481 ns ( 83.43 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "7.768 ns" { button1 Debouncer:inst2|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "7.768 ns" { button1 {} button1~combout {} Debouncer:inst2|button_reg[0] {} } { 0.000ns 0.000ns 6.481ns } { 0.000ns 0.874ns 0.413ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" { } { { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 9 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz destination 4.610 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_50MHz\" to destination register is 4.610 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk_50MHz 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -168 -72 96 -152 "clk_50MHz" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.404 ns) + CELL(0.879 ns) 2.309 ns ClockDivider:inst1\|clk25MHz_ 2 REG LCFF_X1_Y13_N29 2 " "Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'ClockDivider:inst1\|clk25MHz_'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.283 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.703 ns) + CELL(0.000 ns) 3.012 ns ClockDivider:inst1\|clk25MHz_~clkctrl 3 COMB CLKCTRL_G0 1085 " "Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G0; Fanout = 1085; COMB Node = 'ClockDivider:inst1\|clk25MHz_~clkctrl'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.703 ns" { ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.996 ns) + CELL(0.602 ns) 4.610 ns Debouncer:inst2\|button_reg\[0\] 4 REG LCFF_X24_Y14_N29 2 " "Info: 4: + IC(0.996 ns) + CELL(0.602 ns) = 4.610 ns; Loc. = LCFF_X24_Y14_N29; Fanout = 2; REG Node = 'Debouncer:inst2\|button_reg\[0\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.598 ns" { ClockDivider:inst1|clk25MHz_~clkctrl Debouncer:inst2|button_reg[0] } "NODE_NAME" } } { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 54.38 % ) " "Info: Total cell delay = 2.507 ns ( 54.38 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.103 ns ( 45.62 % ) " "Info: Total interconnect delay = 2.103 ns ( 45.62 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.610 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Debouncer:inst2|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.610 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Debouncer:inst2|button_reg[0] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.996ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "7.768 ns" { button1 Debouncer:inst2|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "7.768 ns" { button1 {} button1~combout {} Debouncer:inst2|button_reg[0] {} } { 0.000ns 0.000ns 6.481ns } { 0.000ns 0.874ns 0.413ns } "" } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.610 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Debouncer:inst2|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.610 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Debouncer:inst2|button_reg[0] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.996ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TCO_RESULT" "clk_50MHz v_sync Arkanoid:inst\|v_counter\[10\] 15.478 ns register " "Info: tco from clock \"clk_50MHz\" to destination pin \"v_sync\" through register \"Arkanoid:inst\|v_counter\[10\]\" is 15.478 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz source 4.615 ns + Longest register " "Info: + Longest clock path from clock \"clk_50MHz\" to source register is 4.615 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk_50MHz 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -168 -72 96 -152 "clk_50MHz" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.404 ns) + CELL(0.879 ns) 2.309 ns ClockDivider:inst1\|clk25MHz_ 2 REG LCFF_X1_Y13_N29 2 " "Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'ClockDivider:inst1\|clk25MHz_'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.283 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.703 ns) + CELL(0.000 ns) 3.012 ns ClockDivider:inst1\|clk25MHz_~clkctrl 3 COMB CLKCTRL_G0 1085 " "Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G0; Fanout = 1085; COMB Node = 'ClockDivider:inst1\|clk25MHz_~clkctrl'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.703 ns" { ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.001 ns) + CELL(0.602 ns) 4.615 ns Arkanoid:inst\|v_counter\[10\] 4 REG LCFF_X45_Y15_N21 5 " "Info: 4: + IC(1.001 ns) + CELL(0.602 ns) = 4.615 ns; Loc. = LCFF_X45_Y15_N21; Fanout = 5; REG Node = 'Arkanoid:inst\|v_counter\[10\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.603 ns" { ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|v_counter[10] } "NODE_NAME" } } { "vga_sync.v" "" { Text "G:/Verilog/Arkanoid2PDE1/vga_sync.v" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 54.32 % ) " "Info: Total cell delay = 2.507 ns ( 54.32 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.108 ns ( 45.68 % ) " "Info: Total interconnect delay = 2.108 ns ( 45.68 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.615 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|v_counter[10] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.615 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|v_counter[10] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 1.001ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" { } { { "vga_sync.v" "" { Text "G:/Verilog/Arkanoid2PDE1/vga_sync.v" 17 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.586 ns + Longest register pin " "Info: + Longest register to pin delay is 10.586 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Arkanoid:inst\|v_counter\[10\] 1 REG LCFF_X45_Y15_N21 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X45_Y15_N21; Fanout = 5; REG Node = 'Arkanoid:inst\|v_counter\[10\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { Arkanoid:inst|v_counter[10] } "NODE_NAME" } } { "vga_sync.v" "" { Text "G:/Verilog/Arkanoid2PDE1/vga_sync.v" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.878 ns) + CELL(0.455 ns) 1.333 ns Arkanoid:inst\|Equal1~0 2 COMB LCCOMB_X44_Y15_N0 1 " "Info: 2: + IC(0.878 ns) + CELL(0.455 ns) = 1.333 ns; Loc. = LCCOMB_X44_Y15_N0; Fanout = 1; COMB Node = 'Arkanoid:inst\|Equal1~0'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.333 ns" { Arkanoid:inst|v_counter[10] Arkanoid:inst|Equal1~0 } "NODE_NAME" } } { "vga_sync.v" "" { Text "G:/Verilog/Arkanoid2PDE1/vga_sync.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.513 ns) + CELL(0.322 ns) 3.168 ns Arkanoid:inst\|Equal1~4 3 COMB LCCOMB_X46_Y14_N22 2 " "Info: 3: + IC(1.513 ns) + CELL(0.322 ns) = 3.168 ns; Loc. = LCCOMB_X46_Y14_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|Equal1~4'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.835 ns" { Arkanoid:inst|Equal1~0 Arkanoid:inst|Equal1~4 } "NODE_NAME" } } { "vga_sync.v" "" { Text "G:/Verilog/Arkanoid2PDE1/vga_sync.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.178 ns) 3.646 ns Arkanoid:inst\|Equal1~6 4 COMB LCCOMB_X46_Y14_N18 2 " "Info: 4: + IC(0.300 ns) + CELL(0.178 ns) = 3.646 ns; Loc. = LCCOMB_X46_Y14_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Equal1~6'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.478 ns" { Arkanoid:inst|Equal1~4 Arkanoid:inst|Equal1~6 } "NODE_NAME" } } { "vga_sync.v" "" { Text "G:/Verilog/Arkanoid2PDE1/vga_sync.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.309 ns) + CELL(0.178 ns) 4.133 ns Arkanoid:inst\|Equal46~1 5 COMB LCCOMB_X46_Y14_N10 1 " "Info: 5: + IC(0.309 ns) + CELL(0.178 ns) = 4.133 ns; Loc. = LCCOMB_X46_Y14_N10; Fanout = 1; COMB Node = 'Arkanoid:inst\|Equal46~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.487 ns" { Arkanoid:inst|Equal1~6 Arkanoid:inst|Equal46~1 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 384 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.477 ns) + CELL(2.976 ns) 10.586 ns v_sync 6 PIN PIN_B11 0 " "Info: 6: + IC(3.477 ns) + CELL(2.976 ns) = 10.586 ns; Loc. = PIN_B11; Fanout = 0; PIN Node = 'v_sync'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.453 ns" { Arkanoid:inst|Equal46~1 v_sync } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { 112 856 1032 128 "v_sync" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.109 ns ( 38.82 % ) " "Info: Total cell delay = 4.109 ns ( 38.82 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.477 ns ( 61.18 % ) " "Info: Total interconnect delay = 6.477 ns ( 61.18 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "10.586 ns" { Arkanoid:inst|v_counter[10] Arkanoid:inst|Equal1~0 Arkanoid:inst|Equal1~4 Arkanoid:inst|Equal1~6 Arkanoid:inst|Equal46~1 v_sync } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "10.586 ns" { Arkanoid:inst|v_counter[10] {} Arkanoid:inst|Equal1~0 {} Arkanoid:inst|Equal1~4 {} Arkanoid:inst|Equal1~6 {} Arkanoid:inst|Equal46~1 {} v_sync {} } { 0.000ns 0.878ns 1.513ns 0.300ns 0.309ns 3.477ns } { 0.000ns 0.455ns 0.322ns 0.178ns 0.178ns 2.976ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.615 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|v_counter[10] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.615 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|v_counter[10] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 1.001ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "10.586 ns" { Arkanoid:inst|v_counter[10] Arkanoid:inst|Equal1~0 Arkanoid:inst|Equal1~4 Arkanoid:inst|Equal1~6 Arkanoid:inst|Equal46~1 v_sync } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "10.586 ns" { Arkanoid:inst|v_counter[10] {} Arkanoid:inst|Equal1~0 {} Arkanoid:inst|Equal1~4 {} Arkanoid:inst|Equal1~6 {} Arkanoid:inst|Equal46~1 {} v_sync {} } { 0.000ns 0.878ns 1.513ns 0.300ns 0.309ns 3.477ns } { 0.000ns 0.455ns 0.322ns 0.178ns 0.178ns 2.976ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_TH_RESULT" "Debouncer:inst4\|button_reg\[0\] button3 clk_50MHz -1.775 ns register " "Info: th for register \"Debouncer:inst4\|button_reg\[0\]\" (data pin = \"button3\", clock pin = \"clk_50MHz\") is -1.775 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz destination 4.609 ns + Longest register " "Info: + Longest clock path from clock \"clk_50MHz\" to destination register is 4.609 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk_50MHz 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -168 -72 96 -152 "clk_50MHz" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.404 ns) + CELL(0.879 ns) 2.309 ns ClockDivider:inst1\|clk25MHz_ 2 REG LCFF_X1_Y13_N29 2 " "Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'ClockDivider:inst1\|clk25MHz_'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.283 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.703 ns) + CELL(0.000 ns) 3.012 ns ClockDivider:inst1\|clk25MHz_~clkctrl 3 COMB CLKCTRL_G0 1085 " "Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G0; Fanout = 1085; COMB Node = 'ClockDivider:inst1\|clk25MHz_~clkctrl'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.703 ns" { ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.995 ns) + CELL(0.602 ns) 4.609 ns Debouncer:inst4\|button_reg\[0\] 4 REG LCFF_X43_Y10_N29 2 " "Info: 4: + IC(0.995 ns) + CELL(0.602 ns) = 4.609 ns; Loc. = LCFF_X43_Y10_N29; Fanout = 2; REG Node = 'Debouncer:inst4\|button_reg\[0\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.597 ns" { ClockDivider:inst1|clk25MHz_~clkctrl Debouncer:inst4|button_reg[0] } "NODE_NAME" } } { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 54.39 % ) " "Info: Total cell delay = 2.507 ns ( 54.39 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.102 ns ( 45.61 % ) " "Info: Total interconnect delay = 2.102 ns ( 45.61 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.609 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Debouncer:inst4|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.609 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Debouncer:inst4|button_reg[0] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.995ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" { } { { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 9 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.670 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.670 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns button3 1 PIN PIN_R21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_R21; Fanout = 1; PIN Node = 'button3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { button3 } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { 120 -72 96 136 "button3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.393 ns) + CELL(0.413 ns) 6.670 ns Debouncer:inst4\|button_reg\[0\] 2 REG LCFF_X43_Y10_N29 2 " "Info: 2: + IC(5.393 ns) + CELL(0.413 ns) = 6.670 ns; Loc. = LCFF_X43_Y10_N29; Fanout = 2; REG Node = 'Debouncer:inst4\|button_reg\[0\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.806 ns" { button3 Debouncer:inst4|button_reg[0] } "NODE_NAME" } } { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.277 ns ( 19.15 % ) " "Info: Total cell delay = 1.277 ns ( 19.15 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.393 ns ( 80.85 % ) " "Info: Total interconnect delay = 5.393 ns ( 80.85 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.670 ns" { button3 Debouncer:inst4|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "6.670 ns" { button3 {} button3~combout {} Debouncer:inst4|button_reg[0] {} } { 0.000ns 0.000ns 5.393ns } { 0.000ns 0.864ns 0.413ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.609 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Debouncer:inst4|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "4.609 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Debouncer:inst4|button_reg[0] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.995ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.670 ns" { button3 Debouncer:inst4|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "6.670 ns" { button3 {} button3~combout {} Debouncer:inst4|button_reg[0] {} } { 0.000ns 0.000ns 5.393ns } { 0.000ns 0.864ns 0.413ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "199 " "Info: Peak virtual memory: 199 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 27 20:43:29 2012 " "Info: Processing ended: Sun May 27 20:43:29 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Info: Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 9 s " "Info: Quartus II Full Compilation was successful. 0 errors, 9 warnings" { } { } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/db/prev_cmp_myArkanoid.tan.qmsg b/db/prev_cmp_myArkanoid.tan.qmsg
new file mode 100644
index 0000000..1e74865
--- /dev/null
+++ b/db/prev_cmp_myArkanoid.tan.qmsg
@@ -0,0 +1,11 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 27 20:49:28 2012 " "Info: Processing started: Sun May 27 20:49:28 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_50MHz " "Info: Assuming node \"clk_50MHz\" is an undefined clock" { } { { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -168 -72 96 -152 "clk_50MHz" "" } } } } { "c:/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_50MHz" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
+{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "ClockDivider:inst1\|clk25MHz_ " "Info: Detected ripple clock \"ClockDivider:inst1\|clk25MHz_\" as buffer" { } { { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } { "c:/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "ClockDivider:inst1\|clk25MHz_" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_50MHz register Arkanoid:inst\|platform2_position\[8\] register Arkanoid:inst\|hex3_\[5\] 7.29 MHz 137.171 ns Internal " "Info: Clock \"clk_50MHz\" has Internal fmax of 7.29 MHz between source register \"Arkanoid:inst\|platform2_position\[8\]\" and destination register \"Arkanoid:inst\|hex3_\[5\]\" (period= 137.171 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "136.945 ns + Longest register register " "Info: + Longest register to register delay is 136.945 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Arkanoid:inst\|platform2_position\[8\] 1 REG LCFF_X27_Y16_N17 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y16_N17; Fanout = 4; REG Node = 'Arkanoid:inst\|platform2_position\[8\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { Arkanoid:inst|platform2_position[8] } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.735 ns) + CELL(0.455 ns) 2.190 ns Arkanoid:inst\|platform2_position~10 2 COMB LCCOMB_X26_Y16_N28 1 " "Info: 2: + IC(1.735 ns) + CELL(0.455 ns) = 2.190 ns; Loc. = LCCOMB_X26_Y16_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|platform2_position~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.190 ns" { Arkanoid:inst|platform2_position[8] Arkanoid:inst|platform2_position~10 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.289 ns) + CELL(0.491 ns) 2.970 ns Arkanoid:inst\|platform2_position~12 3 COMB LCCOMB_X26_Y16_N22 1 " "Info: 3: + IC(0.289 ns) + CELL(0.491 ns) = 2.970 ns; Loc. = LCCOMB_X26_Y16_N22; Fanout = 1; COMB Node = 'Arkanoid:inst\|platform2_position~12'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.780 ns" { Arkanoid:inst|platform2_position~10 Arkanoid:inst|platform2_position~12 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.340 ns) + CELL(0.319 ns) 4.629 ns Arkanoid:inst\|platform2_position~18 4 COMB LCCOMB_X27_Y11_N10 3 " "Info: 4: + IC(1.340 ns) + CELL(0.319 ns) = 4.629 ns; Loc. = LCCOMB_X27_Y11_N10; Fanout = 3; COMB Node = 'Arkanoid:inst\|platform2_position~18'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.659 ns" { Arkanoid:inst|platform2_position~12 Arkanoid:inst|platform2_position~18 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.840 ns) + CELL(0.178 ns) 5.647 ns Arkanoid:inst\|platform2_position~88 5 COMB LCCOMB_X27_Y12_N22 31 " "Info: 5: + IC(0.840 ns) + CELL(0.178 ns) = 5.647 ns; Loc. = LCCOMB_X27_Y12_N22; Fanout = 31; COMB Node = 'Arkanoid:inst\|platform2_position~88'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.018 ns" { Arkanoid:inst|platform2_position~18 Arkanoid:inst|platform2_position~88 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.373 ns) + CELL(0.322 ns) 7.342 ns Arkanoid:inst\|platform2_position~46 6 COMB LCCOMB_X26_Y14_N0 4 " "Info: 6: + IC(1.373 ns) + CELL(0.322 ns) = 7.342 ns; Loc. = LCCOMB_X26_Y14_N0; Fanout = 4; COMB Node = 'Arkanoid:inst\|platform2_position~46'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.695 ns" { Arkanoid:inst|platform2_position~88 Arkanoid:inst|platform2_position~46 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.933 ns) + CELL(0.455 ns) 8.730 ns Arkanoid:inst\|LessThan3~7 7 COMB LCCOMB_X26_Y14_N18 1 " "Info: 7: + IC(0.933 ns) + CELL(0.455 ns) = 8.730 ns; Loc. = LCCOMB_X26_Y14_N18; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan3~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.388 ns" { Arkanoid:inst|platform2_position~46 Arkanoid:inst|LessThan3~7 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 92 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.041 ns) + CELL(0.322 ns) 10.093 ns Arkanoid:inst\|LessThan3~9 8 COMB LCCOMB_X26_Y12_N28 1 " "Info: 8: + IC(1.041 ns) + CELL(0.322 ns) = 10.093 ns; Loc. = LCCOMB_X26_Y12_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan3~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.363 ns" { Arkanoid:inst|LessThan3~7 Arkanoid:inst|LessThan3~9 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 92 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.284 ns) + CELL(0.178 ns) 10.555 ns Arkanoid:inst\|LessThan3~10 9 COMB LCCOMB_X26_Y12_N30 2 " "Info: 9: + IC(0.284 ns) + CELL(0.178 ns) = 10.555 ns; Loc. = LCCOMB_X26_Y12_N30; Fanout = 2; COMB Node = 'Arkanoid:inst\|LessThan3~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.462 ns" { Arkanoid:inst|LessThan3~9 Arkanoid:inst|LessThan3~10 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 92 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.903 ns) + CELL(0.517 ns) 11.975 ns Arkanoid:inst\|Add5~1 10 COMB LCCOMB_X27_Y14_N0 2 " "Info: 10: + IC(0.903 ns) + CELL(0.517 ns) = 11.975 ns; Loc. = LCCOMB_X27_Y14_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.420 ns" { Arkanoid:inst|LessThan3~10 Arkanoid:inst|Add5~1 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.055 ns Arkanoid:inst\|Add5~3 11 COMB LCCOMB_X27_Y14_N2 2 " "Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 12.055 ns; Loc. = LCCOMB_X27_Y14_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~1 Arkanoid:inst|Add5~3 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.135 ns Arkanoid:inst\|Add5~5 12 COMB LCCOMB_X27_Y14_N4 2 " "Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 12.135 ns; Loc. = LCCOMB_X27_Y14_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~3 Arkanoid:inst|Add5~5 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.215 ns Arkanoid:inst\|Add5~7 13 COMB LCCOMB_X27_Y14_N6 2 " "Info: 13: + IC(0.000 ns) + CELL(0.080 ns) = 12.215 ns; Loc. = LCCOMB_X27_Y14_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~5 Arkanoid:inst|Add5~7 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.295 ns Arkanoid:inst\|Add5~9 14 COMB LCCOMB_X27_Y14_N8 2 " "Info: 14: + IC(0.000 ns) + CELL(0.080 ns) = 12.295 ns; Loc. = LCCOMB_X27_Y14_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~7 Arkanoid:inst|Add5~9 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.375 ns Arkanoid:inst\|Add5~11 15 COMB LCCOMB_X27_Y14_N10 2 " "Info: 15: + IC(0.000 ns) + CELL(0.080 ns) = 12.375 ns; Loc. = LCCOMB_X27_Y14_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~9 Arkanoid:inst|Add5~11 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.455 ns Arkanoid:inst\|Add5~13 16 COMB LCCOMB_X27_Y14_N12 2 " "Info: 16: + IC(0.000 ns) + CELL(0.080 ns) = 12.455 ns; Loc. = LCCOMB_X27_Y14_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~11 Arkanoid:inst|Add5~13 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 12.629 ns Arkanoid:inst\|Add5~15 17 COMB LCCOMB_X27_Y14_N14 2 " "Info: 17: + IC(0.000 ns) + CELL(0.174 ns) = 12.629 ns; Loc. = LCCOMB_X27_Y14_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|Add5~13 Arkanoid:inst|Add5~15 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.709 ns Arkanoid:inst\|Add5~17 18 COMB LCCOMB_X27_Y14_N16 2 " "Info: 18: + IC(0.000 ns) + CELL(0.080 ns) = 12.709 ns; Loc. = LCCOMB_X27_Y14_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~15 Arkanoid:inst|Add5~17 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.789 ns Arkanoid:inst\|Add5~19 19 COMB LCCOMB_X27_Y14_N18 2 " "Info: 19: + IC(0.000 ns) + CELL(0.080 ns) = 12.789 ns; Loc. = LCCOMB_X27_Y14_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~17 Arkanoid:inst|Add5~19 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.869 ns Arkanoid:inst\|Add5~21 20 COMB LCCOMB_X27_Y14_N20 2 " "Info: 20: + IC(0.000 ns) + CELL(0.080 ns) = 12.869 ns; Loc. = LCCOMB_X27_Y14_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~19 Arkanoid:inst|Add5~21 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.949 ns Arkanoid:inst\|Add5~23 21 COMB LCCOMB_X27_Y14_N22 2 " "Info: 21: + IC(0.000 ns) + CELL(0.080 ns) = 12.949 ns; Loc. = LCCOMB_X27_Y14_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~21 Arkanoid:inst|Add5~23 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 13.029 ns Arkanoid:inst\|Add5~25 22 COMB LCCOMB_X27_Y14_N24 2 " "Info: 22: + IC(0.000 ns) + CELL(0.080 ns) = 13.029 ns; Loc. = LCCOMB_X27_Y14_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~23 Arkanoid:inst|Add5~25 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 13.109 ns Arkanoid:inst\|Add5~27 23 COMB LCCOMB_X27_Y14_N26 2 " "Info: 23: + IC(0.000 ns) + CELL(0.080 ns) = 13.109 ns; Loc. = LCCOMB_X27_Y14_N26; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add5~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add5~25 Arkanoid:inst|Add5~27 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 13.567 ns Arkanoid:inst\|Add5~28 24 COMB LCCOMB_X27_Y14_N28 1 " "Info: 24: + IC(0.000 ns) + CELL(0.458 ns) = 13.567 ns; Loc. = LCCOMB_X27_Y14_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|Add5~28'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|Add5~27 Arkanoid:inst|Add5~28 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 93 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.320 ns) + CELL(0.178 ns) 15.065 ns Arkanoid:inst\|platform2_position~67 25 COMB LCCOMB_X26_Y12_N22 5 " "Info: 25: + IC(1.320 ns) + CELL(0.178 ns) = 15.065 ns; Loc. = LCCOMB_X26_Y12_N22; Fanout = 5; COMB Node = 'Arkanoid:inst\|platform2_position~67'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.498 ns" { Arkanoid:inst|Add5~28 Arkanoid:inst|platform2_position~67 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.359 ns) + CELL(0.517 ns) 16.941 ns Arkanoid:inst\|Add7~29 26 COMB LCCOMB_X27_Y18_N28 2 " "Info: 26: + IC(1.359 ns) + CELL(0.517 ns) = 16.941 ns; Loc. = LCCOMB_X27_Y18_N28; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add7~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.876 ns" { Arkanoid:inst|platform2_position~67 Arkanoid:inst|Add7~29 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 17.102 ns Arkanoid:inst\|Add7~31 27 COMB LCCOMB_X27_Y18_N30 2 " "Info: 27: + IC(0.000 ns) + CELL(0.161 ns) = 17.102 ns; Loc. = LCCOMB_X27_Y18_N30; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add7~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.161 ns" { Arkanoid:inst|Add7~29 Arkanoid:inst|Add7~31 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.182 ns Arkanoid:inst\|Add7~33 28 COMB LCCOMB_X27_Y17_N0 2 " "Info: 28: + IC(0.000 ns) + CELL(0.080 ns) = 17.182 ns; Loc. = LCCOMB_X27_Y17_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add7~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add7~31 Arkanoid:inst|Add7~33 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.262 ns Arkanoid:inst\|Add7~35 29 COMB LCCOMB_X27_Y17_N2 2 " "Info: 29: + IC(0.000 ns) + CELL(0.080 ns) = 17.262 ns; Loc. = LCCOMB_X27_Y17_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add7~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add7~33 Arkanoid:inst|Add7~35 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.342 ns Arkanoid:inst\|Add7~37 30 COMB LCCOMB_X27_Y17_N4 2 " "Info: 30: + IC(0.000 ns) + CELL(0.080 ns) = 17.342 ns; Loc. = LCCOMB_X27_Y17_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add7~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add7~35 Arkanoid:inst|Add7~37 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.422 ns Arkanoid:inst\|Add7~39 31 COMB LCCOMB_X27_Y17_N6 2 " "Info: 31: + IC(0.000 ns) + CELL(0.080 ns) = 17.422 ns; Loc. = LCCOMB_X27_Y17_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add7~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add7~37 Arkanoid:inst|Add7~39 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.502 ns Arkanoid:inst\|Add7~41 32 COMB LCCOMB_X27_Y17_N8 2 " "Info: 32: + IC(0.000 ns) + CELL(0.080 ns) = 17.502 ns; Loc. = LCCOMB_X27_Y17_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add7~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add7~39 Arkanoid:inst|Add7~41 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.582 ns Arkanoid:inst\|Add7~43 33 COMB LCCOMB_X27_Y17_N10 2 " "Info: 33: + IC(0.000 ns) + CELL(0.080 ns) = 17.582 ns; Loc. = LCCOMB_X27_Y17_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add7~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add7~41 Arkanoid:inst|Add7~43 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.662 ns Arkanoid:inst\|Add7~45 34 COMB LCCOMB_X27_Y17_N12 2 " "Info: 34: + IC(0.000 ns) + CELL(0.080 ns) = 17.662 ns; Loc. = LCCOMB_X27_Y17_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add7~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add7~43 Arkanoid:inst|Add7~45 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 17.836 ns Arkanoid:inst\|Add7~47 35 COMB LCCOMB_X27_Y17_N14 2 " "Info: 35: + IC(0.000 ns) + CELL(0.174 ns) = 17.836 ns; Loc. = LCCOMB_X27_Y17_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add7~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|Add7~45 Arkanoid:inst|Add7~47 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.916 ns Arkanoid:inst\|Add7~49 36 COMB LCCOMB_X27_Y17_N16 2 " "Info: 36: + IC(0.000 ns) + CELL(0.080 ns) = 17.916 ns; Loc. = LCCOMB_X27_Y17_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add7~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add7~47 Arkanoid:inst|Add7~49 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 17.996 ns Arkanoid:inst\|Add7~51 37 COMB LCCOMB_X27_Y17_N18 2 " "Info: 37: + IC(0.000 ns) + CELL(0.080 ns) = 17.996 ns; Loc. = LCCOMB_X27_Y17_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add7~51'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add7~49 Arkanoid:inst|Add7~51 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 18.454 ns Arkanoid:inst\|Add7~52 38 COMB LCCOMB_X27_Y17_N20 2 " "Info: 38: + IC(0.000 ns) + CELL(0.458 ns) = 18.454 ns; Loc. = LCCOMB_X27_Y17_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add7~52'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|Add7~51 Arkanoid:inst|Add7~52 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.822 ns) + CELL(0.517 ns) 19.793 ns Arkanoid:inst\|LessThan139~53 39 COMB LCCOMB_X26_Y17_N20 1 " "Info: 39: + IC(0.822 ns) + CELL(0.517 ns) = 19.793 ns; Loc. = LCCOMB_X26_Y17_N20; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~53'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.339 ns" { Arkanoid:inst|Add7~52 Arkanoid:inst|LessThan139~53 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.873 ns Arkanoid:inst\|LessThan139~55 40 COMB LCCOMB_X26_Y17_N22 1 " "Info: 40: + IC(0.000 ns) + CELL(0.080 ns) = 19.873 ns; Loc. = LCCOMB_X26_Y17_N22; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~55'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~53 Arkanoid:inst|LessThan139~55 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 19.953 ns Arkanoid:inst\|LessThan139~57 41 COMB LCCOMB_X26_Y17_N24 1 " "Info: 41: + IC(0.000 ns) + CELL(0.080 ns) = 19.953 ns; Loc. = LCCOMB_X26_Y17_N24; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~57'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~55 Arkanoid:inst|LessThan139~57 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 20.033 ns Arkanoid:inst\|LessThan139~59 42 COMB LCCOMB_X26_Y17_N26 1 " "Info: 42: + IC(0.000 ns) + CELL(0.080 ns) = 20.033 ns; Loc. = LCCOMB_X26_Y17_N26; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~59'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~57 Arkanoid:inst|LessThan139~59 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 20.113 ns Arkanoid:inst\|LessThan139~61 43 COMB LCCOMB_X26_Y17_N28 1 " "Info: 43: + IC(0.000 ns) + CELL(0.080 ns) = 20.113 ns; Loc. = LCCOMB_X26_Y17_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|LessThan139~61'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|LessThan139~59 Arkanoid:inst|LessThan139~61 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 20.571 ns Arkanoid:inst\|LessThan139~62 44 COMB LCCOMB_X26_Y17_N30 3 " "Info: 44: + IC(0.000 ns) + CELL(0.458 ns) = 20.571 ns; Loc. = LCCOMB_X26_Y17_N30; Fanout = 3; COMB Node = 'Arkanoid:inst\|LessThan139~62'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|LessThan139~61 Arkanoid:inst|LessThan139~62 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.527 ns) + CELL(0.178 ns) 21.276 ns Arkanoid:inst\|always2~4 45 COMB LCCOMB_X25_Y17_N10 2 " "Info: 45: + IC(0.527 ns) + CELL(0.178 ns) = 21.276 ns; Loc. = LCCOMB_X25_Y17_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|always2~4'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.705 ns" { Arkanoid:inst|LessThan139~62 Arkanoid:inst|always2~4 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.773 ns) + CELL(0.495 ns) 23.544 ns Arkanoid:inst\|Add9~1 46 COMB LCCOMB_X12_Y20_N0 2 " "Info: 46: + IC(1.773 ns) + CELL(0.495 ns) = 23.544 ns; Loc. = LCCOMB_X12_Y20_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.268 ns" { Arkanoid:inst|always2~4 Arkanoid:inst|Add9~1 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.624 ns Arkanoid:inst\|Add9~3 47 COMB LCCOMB_X12_Y20_N2 2 " "Info: 47: + IC(0.000 ns) + CELL(0.080 ns) = 23.624 ns; Loc. = LCCOMB_X12_Y20_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~1 Arkanoid:inst|Add9~3 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.704 ns Arkanoid:inst\|Add9~5 48 COMB LCCOMB_X12_Y20_N4 2 " "Info: 48: + IC(0.000 ns) + CELL(0.080 ns) = 23.704 ns; Loc. = LCCOMB_X12_Y20_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~3 Arkanoid:inst|Add9~5 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.784 ns Arkanoid:inst\|Add9~7 49 COMB LCCOMB_X12_Y20_N6 2 " "Info: 49: + IC(0.000 ns) + CELL(0.080 ns) = 23.784 ns; Loc. = LCCOMB_X12_Y20_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~5 Arkanoid:inst|Add9~7 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.864 ns Arkanoid:inst\|Add9~9 50 COMB LCCOMB_X12_Y20_N8 2 " "Info: 50: + IC(0.000 ns) + CELL(0.080 ns) = 23.864 ns; Loc. = LCCOMB_X12_Y20_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~7 Arkanoid:inst|Add9~9 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 23.944 ns Arkanoid:inst\|Add9~11 51 COMB LCCOMB_X12_Y20_N10 2 " "Info: 51: + IC(0.000 ns) + CELL(0.080 ns) = 23.944 ns; Loc. = LCCOMB_X12_Y20_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~9 Arkanoid:inst|Add9~11 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.024 ns Arkanoid:inst\|Add9~13 52 COMB LCCOMB_X12_Y20_N12 2 " "Info: 52: + IC(0.000 ns) + CELL(0.080 ns) = 24.024 ns; Loc. = LCCOMB_X12_Y20_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~11 Arkanoid:inst|Add9~13 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 24.198 ns Arkanoid:inst\|Add9~15 53 COMB LCCOMB_X12_Y20_N14 2 " "Info: 53: + IC(0.000 ns) + CELL(0.174 ns) = 24.198 ns; Loc. = LCCOMB_X12_Y20_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|Add9~13 Arkanoid:inst|Add9~15 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.278 ns Arkanoid:inst\|Add9~17 54 COMB LCCOMB_X12_Y20_N16 2 " "Info: 54: + IC(0.000 ns) + CELL(0.080 ns) = 24.278 ns; Loc. = LCCOMB_X12_Y20_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~15 Arkanoid:inst|Add9~17 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.358 ns Arkanoid:inst\|Add9~19 55 COMB LCCOMB_X12_Y20_N18 2 " "Info: 55: + IC(0.000 ns) + CELL(0.080 ns) = 24.358 ns; Loc. = LCCOMB_X12_Y20_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~17 Arkanoid:inst|Add9~19 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.438 ns Arkanoid:inst\|Add9~21 56 COMB LCCOMB_X12_Y20_N20 2 " "Info: 56: + IC(0.000 ns) + CELL(0.080 ns) = 24.438 ns; Loc. = LCCOMB_X12_Y20_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~19 Arkanoid:inst|Add9~21 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.518 ns Arkanoid:inst\|Add9~23 57 COMB LCCOMB_X12_Y20_N22 2 " "Info: 57: + IC(0.000 ns) + CELL(0.080 ns) = 24.518 ns; Loc. = LCCOMB_X12_Y20_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~21 Arkanoid:inst|Add9~23 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.598 ns Arkanoid:inst\|Add9~25 58 COMB LCCOMB_X12_Y20_N24 2 " "Info: 58: + IC(0.000 ns) + CELL(0.080 ns) = 24.598 ns; Loc. = LCCOMB_X12_Y20_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~23 Arkanoid:inst|Add9~25 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.678 ns Arkanoid:inst\|Add9~27 59 COMB LCCOMB_X12_Y20_N26 2 " "Info: 59: + IC(0.000 ns) + CELL(0.080 ns) = 24.678 ns; Loc. = LCCOMB_X12_Y20_N26; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~25 Arkanoid:inst|Add9~27 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.758 ns Arkanoid:inst\|Add9~29 60 COMB LCCOMB_X12_Y20_N28 2 " "Info: 60: + IC(0.000 ns) + CELL(0.080 ns) = 24.758 ns; Loc. = LCCOMB_X12_Y20_N28; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~27 Arkanoid:inst|Add9~29 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 24.919 ns Arkanoid:inst\|Add9~31 61 COMB LCCOMB_X12_Y20_N30 2 " "Info: 61: + IC(0.000 ns) + CELL(0.161 ns) = 24.919 ns; Loc. = LCCOMB_X12_Y20_N30; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.161 ns" { Arkanoid:inst|Add9~29 Arkanoid:inst|Add9~31 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 24.999 ns Arkanoid:inst\|Add9~33 62 COMB LCCOMB_X12_Y19_N0 2 " "Info: 62: + IC(0.000 ns) + CELL(0.080 ns) = 24.999 ns; Loc. = LCCOMB_X12_Y19_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~31 Arkanoid:inst|Add9~33 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.079 ns Arkanoid:inst\|Add9~35 63 COMB LCCOMB_X12_Y19_N2 2 " "Info: 63: + IC(0.000 ns) + CELL(0.080 ns) = 25.079 ns; Loc. = LCCOMB_X12_Y19_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~33 Arkanoid:inst|Add9~35 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.159 ns Arkanoid:inst\|Add9~37 64 COMB LCCOMB_X12_Y19_N4 2 " "Info: 64: + IC(0.000 ns) + CELL(0.080 ns) = 25.159 ns; Loc. = LCCOMB_X12_Y19_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~35 Arkanoid:inst|Add9~37 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.239 ns Arkanoid:inst\|Add9~39 65 COMB LCCOMB_X12_Y19_N6 2 " "Info: 65: + IC(0.000 ns) + CELL(0.080 ns) = 25.239 ns; Loc. = LCCOMB_X12_Y19_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~37 Arkanoid:inst|Add9~39 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.319 ns Arkanoid:inst\|Add9~41 66 COMB LCCOMB_X12_Y19_N8 2 " "Info: 66: + IC(0.000 ns) + CELL(0.080 ns) = 25.319 ns; Loc. = LCCOMB_X12_Y19_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~39 Arkanoid:inst|Add9~41 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.399 ns Arkanoid:inst\|Add9~43 67 COMB LCCOMB_X12_Y19_N10 2 " "Info: 67: + IC(0.000 ns) + CELL(0.080 ns) = 25.399 ns; Loc. = LCCOMB_X12_Y19_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~41 Arkanoid:inst|Add9~43 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.479 ns Arkanoid:inst\|Add9~45 68 COMB LCCOMB_X12_Y19_N12 2 " "Info: 68: + IC(0.000 ns) + CELL(0.080 ns) = 25.479 ns; Loc. = LCCOMB_X12_Y19_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~43 Arkanoid:inst|Add9~45 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 25.653 ns Arkanoid:inst\|Add9~47 69 COMB LCCOMB_X12_Y19_N14 2 " "Info: 69: + IC(0.000 ns) + CELL(0.174 ns) = 25.653 ns; Loc. = LCCOMB_X12_Y19_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|Add9~45 Arkanoid:inst|Add9~47 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.733 ns Arkanoid:inst\|Add9~49 70 COMB LCCOMB_X12_Y19_N16 2 " "Info: 70: + IC(0.000 ns) + CELL(0.080 ns) = 25.733 ns; Loc. = LCCOMB_X12_Y19_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~47 Arkanoid:inst|Add9~49 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.813 ns Arkanoid:inst\|Add9~51 71 COMB LCCOMB_X12_Y19_N18 2 " "Info: 71: + IC(0.000 ns) + CELL(0.080 ns) = 25.813 ns; Loc. = LCCOMB_X12_Y19_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~51'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~49 Arkanoid:inst|Add9~51 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.893 ns Arkanoid:inst\|Add9~53 72 COMB LCCOMB_X12_Y19_N20 2 " "Info: 72: + IC(0.000 ns) + CELL(0.080 ns) = 25.893 ns; Loc. = LCCOMB_X12_Y19_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~53'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~51 Arkanoid:inst|Add9~53 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 25.973 ns Arkanoid:inst\|Add9~55 73 COMB LCCOMB_X12_Y19_N22 2 " "Info: 73: + IC(0.000 ns) + CELL(0.080 ns) = 25.973 ns; Loc. = LCCOMB_X12_Y19_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~55'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~53 Arkanoid:inst|Add9~55 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 26.053 ns Arkanoid:inst\|Add9~57 74 COMB LCCOMB_X12_Y19_N24 2 " "Info: 74: + IC(0.000 ns) + CELL(0.080 ns) = 26.053 ns; Loc. = LCCOMB_X12_Y19_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~57'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~55 Arkanoid:inst|Add9~57 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 26.133 ns Arkanoid:inst\|Add9~59 75 COMB LCCOMB_X12_Y19_N26 2 " "Info: 75: + IC(0.000 ns) + CELL(0.080 ns) = 26.133 ns; Loc. = LCCOMB_X12_Y19_N26; Fanout = 2; COMB Node = 'Arkanoid:inst\|Add9~59'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~57 Arkanoid:inst|Add9~59 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 26.213 ns Arkanoid:inst\|Add9~61 76 COMB LCCOMB_X12_Y19_N28 1 " "Info: 76: + IC(0.000 ns) + CELL(0.080 ns) = 26.213 ns; Loc. = LCCOMB_X12_Y19_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|Add9~61'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|Add9~59 Arkanoid:inst|Add9~61 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 26.671 ns Arkanoid:inst\|Add9~63 77 COMB LCCOMB_X12_Y19_N30 3 " "Info: 77: + IC(0.000 ns) + CELL(0.458 ns) = 26.671 ns; Loc. = LCCOMB_X12_Y19_N30; Fanout = 3; COMB Node = 'Arkanoid:inst\|Add9~63'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|Add9~61 Arkanoid:inst|Add9~63 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.360 ns) + CELL(0.178 ns) 29.209 ns Arkanoid:inst\|Add9~65 78 COMB LCCOMB_X42_Y17_N28 147 " "Info: 78: + IC(2.360 ns) + CELL(0.178 ns) = 29.209 ns; Loc. = LCCOMB_X42_Y17_N28; Fanout = 147; COMB Node = 'Arkanoid:inst\|Add9~65'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.538 ns" { Arkanoid:inst|Add9~63 Arkanoid:inst|Add9~65 } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 149 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.221 ns) + CELL(0.495 ns) 31.925 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~3 79 COMB LCCOMB_X14_Y20_N4 2 " "Info: 79: + IC(2.221 ns) + CELL(0.495 ns) = 31.925 ns; Loc. = LCCOMB_X14_Y20_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.716 ns" { Arkanoid:inst|Add9~65 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.005 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~5 80 COMB LCCOMB_X14_Y20_N6 2 " "Info: 80: + IC(0.000 ns) + CELL(0.080 ns) = 32.005 ns; Loc. = LCCOMB_X14_Y20_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.085 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~7 81 COMB LCCOMB_X14_Y20_N8 2 " "Info: 81: + IC(0.000 ns) + CELL(0.080 ns) = 32.085 ns; Loc. = LCCOMB_X14_Y20_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.165 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~9 82 COMB LCCOMB_X14_Y20_N10 2 " "Info: 82: + IC(0.000 ns) + CELL(0.080 ns) = 32.165 ns; Loc. = LCCOMB_X14_Y20_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.245 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~11 83 COMB LCCOMB_X14_Y20_N12 2 " "Info: 83: + IC(0.000 ns) + CELL(0.080 ns) = 32.245 ns; Loc. = LCCOMB_X14_Y20_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 32.419 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~13 84 COMB LCCOMB_X14_Y20_N14 2 " "Info: 84: + IC(0.000 ns) + CELL(0.174 ns) = 32.419 ns; Loc. = LCCOMB_X14_Y20_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.499 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~15 85 COMB LCCOMB_X14_Y20_N16 2 " "Info: 85: + IC(0.000 ns) + CELL(0.080 ns) = 32.499 ns; Loc. = LCCOMB_X14_Y20_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.579 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~17 86 COMB LCCOMB_X14_Y20_N18 2 " "Info: 86: + IC(0.000 ns) + CELL(0.080 ns) = 32.579 ns; Loc. = LCCOMB_X14_Y20_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.659 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~19 87 COMB LCCOMB_X14_Y20_N20 2 " "Info: 87: + IC(0.000 ns) + CELL(0.080 ns) = 32.659 ns; Loc. = LCCOMB_X14_Y20_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.739 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~21 88 COMB LCCOMB_X14_Y20_N22 2 " "Info: 88: + IC(0.000 ns) + CELL(0.080 ns) = 32.739 ns; Loc. = LCCOMB_X14_Y20_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.819 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~23 89 COMB LCCOMB_X14_Y20_N24 2 " "Info: 89: + IC(0.000 ns) + CELL(0.080 ns) = 32.819 ns; Loc. = LCCOMB_X14_Y20_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.899 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~25 90 COMB LCCOMB_X14_Y20_N26 2 " "Info: 90: + IC(0.000 ns) + CELL(0.080 ns) = 32.899 ns; Loc. = LCCOMB_X14_Y20_N26; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 32.979 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~27 91 COMB LCCOMB_X14_Y20_N28 2 " "Info: 91: + IC(0.000 ns) + CELL(0.080 ns) = 32.979 ns; Loc. = LCCOMB_X14_Y20_N28; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 33.140 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~29 92 COMB LCCOMB_X14_Y20_N30 2 " "Info: 92: + IC(0.000 ns) + CELL(0.161 ns) = 33.140 ns; Loc. = LCCOMB_X14_Y20_N30; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.161 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 33.220 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~31 93 COMB LCCOMB_X14_Y19_N0 2 " "Info: 93: + IC(0.000 ns) + CELL(0.080 ns) = 33.220 ns; Loc. = LCCOMB_X14_Y19_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 33.300 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~33 94 COMB LCCOMB_X14_Y19_N2 2 " "Info: 94: + IC(0.000 ns) + CELL(0.080 ns) = 33.300 ns; Loc. = LCCOMB_X14_Y19_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~33'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 33.380 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~35 95 COMB LCCOMB_X14_Y19_N4 2 " "Info: 95: + IC(0.000 ns) + CELL(0.080 ns) = 33.380 ns; Loc. = LCCOMB_X14_Y19_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~35'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 33.460 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~37 96 COMB LCCOMB_X14_Y19_N6 2 " "Info: 96: + IC(0.000 ns) + CELL(0.080 ns) = 33.460 ns; Loc. = LCCOMB_X14_Y19_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~37'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 33.540 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~39 97 COMB LCCOMB_X14_Y19_N8 2 " "Info: 97: + IC(0.000 ns) + CELL(0.080 ns) = 33.540 ns; Loc. = LCCOMB_X14_Y19_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~39'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 33.620 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~41 98 COMB LCCOMB_X14_Y19_N10 2 " "Info: 98: + IC(0.000 ns) + CELL(0.080 ns) = 33.620 ns; Loc. = LCCOMB_X14_Y19_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~41'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 33.700 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~43 99 COMB LCCOMB_X14_Y19_N12 2 " "Info: 99: + IC(0.000 ns) + CELL(0.080 ns) = 33.700 ns; Loc. = LCCOMB_X14_Y19_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~43'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 33.874 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~45 100 COMB LCCOMB_X14_Y19_N14 2 " "Info: 100: + IC(0.000 ns) + CELL(0.174 ns) = 33.874 ns; Loc. = LCCOMB_X14_Y19_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~45'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 33.954 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~47 101 COMB LCCOMB_X14_Y19_N16 2 " "Info: 101: + IC(0.000 ns) + CELL(0.080 ns) = 33.954 ns; Loc. = LCCOMB_X14_Y19_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~47'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 34.034 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~49 102 COMB LCCOMB_X14_Y19_N18 2 " "Info: 102: + IC(0.000 ns) + CELL(0.080 ns) = 34.034 ns; Loc. = LCCOMB_X14_Y19_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~49'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 34.114 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~51 103 COMB LCCOMB_X14_Y19_N20 2 " "Info: 103: + IC(0.000 ns) + CELL(0.080 ns) = 34.114 ns; Loc. = LCCOMB_X14_Y19_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~51'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 34.194 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~53 104 COMB LCCOMB_X14_Y19_N22 2 " "Info: 104: + IC(0.000 ns) + CELL(0.080 ns) = 34.194 ns; Loc. = LCCOMB_X14_Y19_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~53'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 34.274 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~55 105 COMB LCCOMB_X14_Y19_N24 2 " "Info: 105: + IC(0.000 ns) + CELL(0.080 ns) = 34.274 ns; Loc. = LCCOMB_X14_Y19_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~55'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 34.354 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~57 106 COMB LCCOMB_X14_Y19_N26 2 " "Info: 106: + IC(0.000 ns) + CELL(0.080 ns) = 34.354 ns; Loc. = LCCOMB_X14_Y19_N26; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~57'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~57 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 34.434 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~59 107 COMB LCCOMB_X14_Y19_N28 1 " "Info: 107: + IC(0.000 ns) + CELL(0.080 ns) = 34.434 ns; Loc. = LCCOMB_X14_Y19_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~59'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~57 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~59 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 34.892 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~60 108 COMB LCCOMB_X14_Y19_N30 4 " "Info: 108: + IC(0.000 ns) + CELL(0.458 ns) = 34.892 ns; Loc. = LCCOMB_X14_Y19_N30; Fanout = 4; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|lpm_abs_0s9:my_abs_num\|cs2a\[1\]~60'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~59 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~60 } "NODE_NAME" } } { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 31 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.562 ns) + CELL(0.517 ns) 36.971 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[3\]~5 109 COMB LCCOMB_X18_Y15_N10 1 " "Info: 109: + IC(1.562 ns) + CELL(0.517 ns) = 36.971 ns; Loc. = LCCOMB_X18_Y15_N10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.079 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~60 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 141 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 37.429 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[4\]~6 110 COMB LCCOMB_X18_Y15_N12 14 " "Info: 110: + IC(0.000 ns) + CELL(0.458 ns) = 37.429 ns; Loc. = LCCOMB_X18_Y15_N12; Fanout = 14; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_3_result_int\[4\]~6'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 141 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.351 ns) + CELL(0.177 ns) 37.957 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[19\]~109 111 COMB LCCOMB_X18_Y15_N2 2 " "Info: 111: + IC(0.351 ns) + CELL(0.177 ns) = 37.957 ns; Loc. = LCCOMB_X18_Y15_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[19\]~109'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.528 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[19]~109 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.819 ns) + CELL(0.517 ns) 39.293 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[2\]~3 112 COMB LCCOMB_X19_Y15_N16 2 " "Info: 112: + IC(0.819 ns) + CELL(0.517 ns) = 39.293 ns; Loc. = LCCOMB_X19_Y15_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.336 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[19]~109 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 39.373 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[3\]~5 113 COMB LCCOMB_X19_Y15_N18 2 " "Info: 113: + IC(0.000 ns) + CELL(0.080 ns) = 39.373 ns; Loc. = LCCOMB_X19_Y15_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 39.453 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[4\]~7 114 COMB LCCOMB_X19_Y15_N20 1 " "Info: 114: + IC(0.000 ns) + CELL(0.080 ns) = 39.453 ns; Loc. = LCCOMB_X19_Y15_N20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 39.911 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[5\]~8 115 COMB LCCOMB_X19_Y15_N22 17 " "Info: 115: + IC(0.000 ns) + CELL(0.458 ns) = 39.911 ns; Loc. = LCCOMB_X19_Y15_N22; Fanout = 17; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_4_result_int\[5\]~8'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 156 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.892 ns) + CELL(0.177 ns) 40.980 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[24\]~121 116 COMB LCCOMB_X19_Y16_N2 2 " "Info: 116: + IC(0.892 ns) + CELL(0.177 ns) = 40.980 ns; Loc. = LCCOMB_X19_Y16_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[24\]~121'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.069 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[24]~121 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.867 ns) + CELL(0.495 ns) 42.342 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[1\]~1 117 COMB LCCOMB_X19_Y15_N2 2 " "Info: 117: + IC(0.867 ns) + CELL(0.495 ns) = 42.342 ns; Loc. = LCCOMB_X19_Y15_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.362 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[24]~121 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 42.422 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[2\]~3 118 COMB LCCOMB_X19_Y15_N4 2 " "Info: 118: + IC(0.000 ns) + CELL(0.080 ns) = 42.422 ns; Loc. = LCCOMB_X19_Y15_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 42.502 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[3\]~5 119 COMB LCCOMB_X19_Y15_N6 2 " "Info: 119: + IC(0.000 ns) + CELL(0.080 ns) = 42.502 ns; Loc. = LCCOMB_X19_Y15_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 42.582 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[4\]~7 120 COMB LCCOMB_X19_Y15_N8 1 " "Info: 120: + IC(0.000 ns) + CELL(0.080 ns) = 42.582 ns; Loc. = LCCOMB_X19_Y15_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 42.662 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[5\]~9 121 COMB LCCOMB_X19_Y15_N10 1 " "Info: 121: + IC(0.000 ns) + CELL(0.080 ns) = 42.662 ns; Loc. = LCCOMB_X19_Y15_N10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 43.120 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[6\]~10 122 COMB LCCOMB_X19_Y15_N12 16 " "Info: 122: + IC(0.000 ns) + CELL(0.458 ns) = 43.120 ns; Loc. = LCCOMB_X19_Y15_N12; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_5_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 161 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.926 ns) + CELL(0.322 ns) 44.368 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[30\]~128 123 COMB LCCOMB_X18_Y16_N16 2 " "Info: 123: + IC(0.926 ns) + CELL(0.322 ns) = 44.368 ns; Loc. = LCCOMB_X18_Y16_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[30\]~128'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.248 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[30]~128 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.516 ns) + CELL(0.495 ns) 45.379 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[1\]~1 124 COMB LCCOMB_X19_Y16_N20 2 " "Info: 124: + IC(0.516 ns) + CELL(0.495 ns) = 45.379 ns; Loc. = LCCOMB_X19_Y16_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.011 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[30]~128 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 45.459 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[2\]~3 125 COMB LCCOMB_X19_Y16_N22 2 " "Info: 125: + IC(0.000 ns) + CELL(0.080 ns) = 45.459 ns; Loc. = LCCOMB_X19_Y16_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 45.539 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[3\]~5 126 COMB LCCOMB_X19_Y16_N24 2 " "Info: 126: + IC(0.000 ns) + CELL(0.080 ns) = 45.539 ns; Loc. = LCCOMB_X19_Y16_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 45.619 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[4\]~7 127 COMB LCCOMB_X19_Y16_N26 1 " "Info: 127: + IC(0.000 ns) + CELL(0.080 ns) = 45.619 ns; Loc. = LCCOMB_X19_Y16_N26; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 45.699 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[5\]~9 128 COMB LCCOMB_X19_Y16_N28 1 " "Info: 128: + IC(0.000 ns) + CELL(0.080 ns) = 45.699 ns; Loc. = LCCOMB_X19_Y16_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 46.157 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[6\]~10 129 COMB LCCOMB_X19_Y16_N30 16 " "Info: 129: + IC(0.000 ns) + CELL(0.458 ns) = 46.157 ns; Loc. = LCCOMB_X19_Y16_N30; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_6_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 166 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.796 ns) + CELL(0.178 ns) 48.131 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[36\]~136 130 COMB LCCOMB_X36_Y13_N8 2 " "Info: 130: + IC(1.796 ns) + CELL(0.178 ns) = 48.131 ns; Loc. = LCCOMB_X36_Y13_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[36\]~136'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.974 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~136 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.784 ns) + CELL(0.495 ns) 50.410 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[1\]~1 131 COMB LCCOMB_X18_Y16_N2 2 " "Info: 131: + IC(1.784 ns) + CELL(0.495 ns) = 50.410 ns; Loc. = LCCOMB_X18_Y16_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~136 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 50.490 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[2\]~3 132 COMB LCCOMB_X18_Y16_N4 2 " "Info: 132: + IC(0.000 ns) + CELL(0.080 ns) = 50.490 ns; Loc. = LCCOMB_X18_Y16_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 50.570 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[3\]~5 133 COMB LCCOMB_X18_Y16_N6 2 " "Info: 133: + IC(0.000 ns) + CELL(0.080 ns) = 50.570 ns; Loc. = LCCOMB_X18_Y16_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 50.650 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[4\]~7 134 COMB LCCOMB_X18_Y16_N8 1 " "Info: 134: + IC(0.000 ns) + CELL(0.080 ns) = 50.650 ns; Loc. = LCCOMB_X18_Y16_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 50.730 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[5\]~9 135 COMB LCCOMB_X18_Y16_N10 1 " "Info: 135: + IC(0.000 ns) + CELL(0.080 ns) = 50.730 ns; Loc. = LCCOMB_X18_Y16_N10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 51.188 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[6\]~10 136 COMB LCCOMB_X18_Y16_N12 16 " "Info: 136: + IC(0.000 ns) + CELL(0.458 ns) = 51.188 ns; Loc. = LCCOMB_X18_Y16_N12; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_7_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 171 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.099 ns) + CELL(0.319 ns) 53.606 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[42\]~144 137 COMB LCCOMB_X35_Y13_N8 2 " "Info: 137: + IC(2.099 ns) + CELL(0.319 ns) = 53.606 ns; Loc. = LCCOMB_X35_Y13_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[42\]~144'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.418 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[42]~144 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.567 ns) + CELL(0.517 ns) 54.690 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[1\]~1 138 COMB LCCOMB_X36_Y13_N18 2 " "Info: 138: + IC(0.567 ns) + CELL(0.517 ns) = 54.690 ns; Loc. = LCCOMB_X36_Y13_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.084 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[42]~144 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 54.770 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[2\]~3 139 COMB LCCOMB_X36_Y13_N20 2 " "Info: 139: + IC(0.000 ns) + CELL(0.080 ns) = 54.770 ns; Loc. = LCCOMB_X36_Y13_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 54.850 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[3\]~5 140 COMB LCCOMB_X36_Y13_N22 2 " "Info: 140: + IC(0.000 ns) + CELL(0.080 ns) = 54.850 ns; Loc. = LCCOMB_X36_Y13_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 54.930 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[4\]~7 141 COMB LCCOMB_X36_Y13_N24 1 " "Info: 141: + IC(0.000 ns) + CELL(0.080 ns) = 54.930 ns; Loc. = LCCOMB_X36_Y13_N24; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 55.010 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[5\]~9 142 COMB LCCOMB_X36_Y13_N26 1 " "Info: 142: + IC(0.000 ns) + CELL(0.080 ns) = 55.010 ns; Loc. = LCCOMB_X36_Y13_N26; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 55.468 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[6\]~10 143 COMB LCCOMB_X36_Y13_N28 16 " "Info: 143: + IC(0.000 ns) + CELL(0.458 ns) = 55.468 ns; Loc. = LCCOMB_X36_Y13_N28; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_8_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 176 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.027 ns) + CELL(0.178 ns) 57.673 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[51\]~337 144 COMB LCCOMB_X18_Y16_N22 3 " "Info: 144: + IC(2.027 ns) + CELL(0.178 ns) = 57.673 ns; Loc. = LCCOMB_X18_Y16_N22; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[51\]~337'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.205 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[51]~337 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.072 ns) + CELL(0.517 ns) 60.262 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[4\]~7 145 COMB LCCOMB_X35_Y13_N26 1 " "Info: 145: + IC(2.072 ns) + CELL(0.517 ns) = 60.262 ns; Loc. = LCCOMB_X35_Y13_N26; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.589 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[51]~337 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 60.342 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[5\]~9 146 COMB LCCOMB_X35_Y13_N28 1 " "Info: 146: + IC(0.000 ns) + CELL(0.080 ns) = 60.342 ns; Loc. = LCCOMB_X35_Y13_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 60.800 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[6\]~10 147 COMB LCCOMB_X35_Y13_N30 16 " "Info: 147: + IC(0.000 ns) + CELL(0.458 ns) = 60.800 ns; Loc. = LCCOMB_X35_Y13_N30; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_9_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 181 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.954 ns) + CELL(0.319 ns) 62.073 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[55\]~158 148 COMB LCCOMB_X34_Y14_N20 2 " "Info: 148: + IC(0.954 ns) + CELL(0.319 ns) = 62.073 ns; Loc. = LCCOMB_X34_Y14_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[55\]~158'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.273 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[55]~158 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.815 ns) + CELL(0.517 ns) 63.405 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[2\]~3 149 COMB LCCOMB_X36_Y14_N8 2 " "Info: 149: + IC(0.815 ns) + CELL(0.517 ns) = 63.405 ns; Loc. = LCCOMB_X36_Y14_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.332 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[55]~158 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 36 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 63.485 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[3\]~5 150 COMB LCCOMB_X36_Y14_N10 2 " "Info: 150: + IC(0.000 ns) + CELL(0.080 ns) = 63.485 ns; Loc. = LCCOMB_X36_Y14_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 36 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 63.565 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[4\]~7 151 COMB LCCOMB_X36_Y14_N12 1 " "Info: 151: + IC(0.000 ns) + CELL(0.080 ns) = 63.565 ns; Loc. = LCCOMB_X36_Y14_N12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 36 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 63.739 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[5\]~9 152 COMB LCCOMB_X36_Y14_N14 1 " "Info: 152: + IC(0.000 ns) + CELL(0.174 ns) = 63.739 ns; Loc. = LCCOMB_X36_Y14_N14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 36 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 64.197 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[6\]~10 153 COMB LCCOMB_X36_Y14_N16 16 " "Info: 153: + IC(0.000 ns) + CELL(0.458 ns) = 64.197 ns; Loc. = LCCOMB_X36_Y14_N16; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_10_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 36 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.874 ns) + CELL(0.178 ns) 65.249 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[63\]~341 154 COMB LCCOMB_X35_Y13_N10 3 " "Info: 154: + IC(0.874 ns) + CELL(0.178 ns) = 65.249 ns; Loc. = LCCOMB_X35_Y13_N10; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[63\]~341'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.052 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[63]~341 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(0.495 ns) 66.637 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[4\]~7 155 COMB LCCOMB_X34_Y14_N12 1 " "Info: 155: + IC(0.893 ns) + CELL(0.495 ns) = 66.637 ns; Loc. = LCCOMB_X34_Y14_N12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.388 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[63]~341 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 66.811 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[5\]~9 156 COMB LCCOMB_X34_Y14_N14 1 " "Info: 156: + IC(0.000 ns) + CELL(0.174 ns) = 66.811 ns; Loc. = LCCOMB_X34_Y14_N14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 67.269 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[6\]~10 157 COMB LCCOMB_X34_Y14_N16 16 " "Info: 157: + IC(0.000 ns) + CELL(0.458 ns) = 67.269 ns; Loc. = LCCOMB_X34_Y14_N16; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_11_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 41 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.219 ns) + CELL(0.177 ns) 68.665 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[66\]~177 158 COMB LCCOMB_X36_Y18_N26 2 " "Info: 158: + IC(1.219 ns) + CELL(0.177 ns) = 68.665 ns; Loc. = LCCOMB_X36_Y18_N26; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[66\]~177'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.396 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[66]~177 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.918 ns) + CELL(0.517 ns) 70.100 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[1\]~1 159 COMB LCCOMB_X36_Y14_N20 2 " "Info: 159: + IC(0.918 ns) + CELL(0.517 ns) = 70.100 ns; Loc. = LCCOMB_X36_Y14_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.435 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[66]~177 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 70.180 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[2\]~3 160 COMB LCCOMB_X36_Y14_N22 2 " "Info: 160: + IC(0.000 ns) + CELL(0.080 ns) = 70.180 ns; Loc. = LCCOMB_X36_Y14_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 70.260 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[3\]~5 161 COMB LCCOMB_X36_Y14_N24 2 " "Info: 161: + IC(0.000 ns) + CELL(0.080 ns) = 70.260 ns; Loc. = LCCOMB_X36_Y14_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 70.340 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[4\]~7 162 COMB LCCOMB_X36_Y14_N26 1 " "Info: 162: + IC(0.000 ns) + CELL(0.080 ns) = 70.340 ns; Loc. = LCCOMB_X36_Y14_N26; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 70.420 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[5\]~9 163 COMB LCCOMB_X36_Y14_N28 1 " "Info: 163: + IC(0.000 ns) + CELL(0.080 ns) = 70.420 ns; Loc. = LCCOMB_X36_Y14_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 70.878 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[6\]~10 164 COMB LCCOMB_X36_Y14_N30 16 " "Info: 164: + IC(0.000 ns) + CELL(0.458 ns) = 70.878 ns; Loc. = LCCOMB_X36_Y14_N30; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_12_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 46 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.823 ns) + CELL(0.178 ns) 71.879 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[76\]~344 165 COMB LCCOMB_X34_Y14_N30 1 " "Info: 165: + IC(0.823 ns) + CELL(0.178 ns) = 71.879 ns; Loc. = LCCOMB_X34_Y14_N30; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[76\]~344'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.001 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[76]~344 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.802 ns) + CELL(0.495 ns) 73.176 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[5\]~9 166 COMB LCCOMB_X37_Y14_N28 1 " "Info: 166: + IC(0.802 ns) + CELL(0.495 ns) = 73.176 ns; Loc. = LCCOMB_X37_Y14_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.297 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[76]~344 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 51 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 73.634 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[6\]~10 167 COMB LCCOMB_X37_Y14_N30 16 " "Info: 167: + IC(0.000 ns) + CELL(0.458 ns) = 73.634 ns; Loc. = LCCOMB_X37_Y14_N30; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_13_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 51 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.995 ns) + CELL(0.178 ns) 74.807 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[78\]~192 168 COMB LCCOMB_X36_Y18_N2 2 " "Info: 168: + IC(0.995 ns) + CELL(0.178 ns) = 74.807 ns; Loc. = LCCOMB_X36_Y18_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[78\]~192'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.173 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[78]~192 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.517 ns) 75.887 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[1\]~1 169 COMB LCCOMB_X36_Y18_N8 2 " "Info: 169: + IC(0.563 ns) + CELL(0.517 ns) = 75.887 ns; Loc. = LCCOMB_X36_Y18_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[78]~192 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 56 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 75.967 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[2\]~3 170 COMB LCCOMB_X36_Y18_N10 2 " "Info: 170: + IC(0.000 ns) + CELL(0.080 ns) = 75.967 ns; Loc. = LCCOMB_X36_Y18_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 56 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 76.047 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[3\]~5 171 COMB LCCOMB_X36_Y18_N12 2 " "Info: 171: + IC(0.000 ns) + CELL(0.080 ns) = 76.047 ns; Loc. = LCCOMB_X36_Y18_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 56 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 76.221 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[4\]~7 172 COMB LCCOMB_X36_Y18_N14 1 " "Info: 172: + IC(0.000 ns) + CELL(0.174 ns) = 76.221 ns; Loc. = LCCOMB_X36_Y18_N14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 56 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 76.301 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[5\]~9 173 COMB LCCOMB_X36_Y18_N16 1 " "Info: 173: + IC(0.000 ns) + CELL(0.080 ns) = 76.301 ns; Loc. = LCCOMB_X36_Y18_N16; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 56 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 76.759 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[6\]~10 174 COMB LCCOMB_X36_Y18_N18 16 " "Info: 174: + IC(0.000 ns) + CELL(0.458 ns) = 76.759 ns; Loc. = LCCOMB_X36_Y18_N18; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_14_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 56 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.930 ns) + CELL(0.177 ns) 77.866 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[88\]~194 175 COMB LCCOMB_X35_Y14_N0 1 " "Info: 175: + IC(0.930 ns) + CELL(0.177 ns) = 77.866 ns; Loc. = LCCOMB_X35_Y14_N0; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[88\]~194'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.107 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[88]~194 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.280 ns) + CELL(0.517 ns) 79.663 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[5\]~9 176 COMB LCCOMB_X36_Y22_N18 1 " "Info: 176: + IC(1.280 ns) + CELL(0.517 ns) = 79.663 ns; Loc. = LCCOMB_X36_Y22_N18; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.797 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[88]~194 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 61 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 80.121 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[6\]~10 177 COMB LCCOMB_X36_Y22_N20 16 " "Info: 177: + IC(0.000 ns) + CELL(0.458 ns) = 80.121 ns; Loc. = LCCOMB_X36_Y22_N20; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_15_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 61 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.625 ns) + CELL(0.178 ns) 80.924 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[90\]~208 178 COMB LCCOMB_X35_Y22_N20 2 " "Info: 178: + IC(0.625 ns) + CELL(0.178 ns) = 80.924 ns; Loc. = LCCOMB_X35_Y22_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[90\]~208'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.803 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[90]~208 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.314 ns) + CELL(0.517 ns) 81.755 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[1\]~1 179 COMB LCCOMB_X35_Y22_N8 2 " "Info: 179: + IC(0.314 ns) + CELL(0.517 ns) = 81.755 ns; Loc. = LCCOMB_X35_Y22_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.831 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[90]~208 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 81.835 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[2\]~3 180 COMB LCCOMB_X35_Y22_N10 2 " "Info: 180: + IC(0.000 ns) + CELL(0.080 ns) = 81.835 ns; Loc. = LCCOMB_X35_Y22_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 81.915 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[3\]~5 181 COMB LCCOMB_X35_Y22_N12 2 " "Info: 181: + IC(0.000 ns) + CELL(0.080 ns) = 81.915 ns; Loc. = LCCOMB_X35_Y22_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 82.089 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[4\]~7 182 COMB LCCOMB_X35_Y22_N14 1 " "Info: 182: + IC(0.000 ns) + CELL(0.174 ns) = 82.089 ns; Loc. = LCCOMB_X35_Y22_N14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 82.169 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[5\]~9 183 COMB LCCOMB_X35_Y22_N16 1 " "Info: 183: + IC(0.000 ns) + CELL(0.080 ns) = 82.169 ns; Loc. = LCCOMB_X35_Y22_N16; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 82.627 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[6\]~10 184 COMB LCCOMB_X35_Y22_N18 16 " "Info: 184: + IC(0.000 ns) + CELL(0.458 ns) = 82.627 ns; Loc. = LCCOMB_X35_Y22_N18; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_16_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 66 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.923 ns) + CELL(0.178 ns) 83.728 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[98\]~212 185 COMB LCCOMB_X35_Y23_N28 3 " "Info: 185: + IC(0.923 ns) + CELL(0.178 ns) = 83.728 ns; Loc. = LCCOMB_X35_Y23_N28; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[98\]~212'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.101 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[98]~212 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.552 ns) + CELL(0.620 ns) 84.900 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[3\]~5 186 COMB LCCOMB_X35_Y23_N14 2 " "Info: 186: + IC(0.552 ns) + CELL(0.620 ns) = 84.900 ns; Loc. = LCCOMB_X35_Y23_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.172 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[98]~212 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 84.980 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[4\]~7 187 COMB LCCOMB_X35_Y23_N16 1 " "Info: 187: + IC(0.000 ns) + CELL(0.080 ns) = 84.980 ns; Loc. = LCCOMB_X35_Y23_N16; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 85.060 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[5\]~9 188 COMB LCCOMB_X35_Y23_N18 1 " "Info: 188: + IC(0.000 ns) + CELL(0.080 ns) = 85.060 ns; Loc. = LCCOMB_X35_Y23_N18; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 85.518 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[6\]~10 189 COMB LCCOMB_X35_Y23_N20 16 " "Info: 189: + IC(0.000 ns) + CELL(0.458 ns) = 85.518 ns; Loc. = LCCOMB_X35_Y23_N20; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_17_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 71 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.640 ns) + CELL(0.178 ns) 86.336 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[102\]~224 190 COMB LCCOMB_X34_Y23_N30 2 " "Info: 190: + IC(0.640 ns) + CELL(0.178 ns) = 86.336 ns; Loc. = LCCOMB_X34_Y23_N30; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[102\]~224'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.818 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~224 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.517 ns) 87.351 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[1\]~1 191 COMB LCCOMB_X34_Y23_N6 2 " "Info: 191: + IC(0.498 ns) + CELL(0.517 ns) = 87.351 ns; Loc. = LCCOMB_X34_Y23_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.015 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~224 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 87.431 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[2\]~3 192 COMB LCCOMB_X34_Y23_N8 2 " "Info: 192: + IC(0.000 ns) + CELL(0.080 ns) = 87.431 ns; Loc. = LCCOMB_X34_Y23_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 87.511 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[3\]~5 193 COMB LCCOMB_X34_Y23_N10 2 " "Info: 193: + IC(0.000 ns) + CELL(0.080 ns) = 87.511 ns; Loc. = LCCOMB_X34_Y23_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 87.591 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[4\]~7 194 COMB LCCOMB_X34_Y23_N12 1 " "Info: 194: + IC(0.000 ns) + CELL(0.080 ns) = 87.591 ns; Loc. = LCCOMB_X34_Y23_N12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 87.765 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[5\]~9 195 COMB LCCOMB_X34_Y23_N14 1 " "Info: 195: + IC(0.000 ns) + CELL(0.174 ns) = 87.765 ns; Loc. = LCCOMB_X34_Y23_N14; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 88.223 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[6\]~10 196 COMB LCCOMB_X34_Y23_N16 16 " "Info: 196: + IC(0.000 ns) + CELL(0.458 ns) = 88.223 ns; Loc. = LCCOMB_X34_Y23_N16; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_18_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 76 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.590 ns) + CELL(0.319 ns) 89.132 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[109\]~230 197 COMB LCCOMB_X33_Y23_N4 2 " "Info: 197: + IC(0.590 ns) + CELL(0.319 ns) = 89.132 ns; Loc. = LCCOMB_X33_Y23_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[109\]~230'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[109]~230 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.534 ns) + CELL(0.517 ns) 90.183 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[2\]~3 198 COMB LCCOMB_X32_Y23_N4 2 " "Info: 198: + IC(0.534 ns) + CELL(0.517 ns) = 90.183 ns; Loc. = LCCOMB_X32_Y23_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.051 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[109]~230 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 90.263 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[3\]~5 199 COMB LCCOMB_X32_Y23_N6 2 " "Info: 199: + IC(0.000 ns) + CELL(0.080 ns) = 90.263 ns; Loc. = LCCOMB_X32_Y23_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 90.721 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[4\]~6 200 COMB LCCOMB_X32_Y23_N8 1 " "Info: 200: + IC(0.000 ns) + CELL(0.458 ns) = 90.721 ns; Loc. = LCCOMB_X32_Y23_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_19_result_int\[4\]~6'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~6 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 81 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.554 ns) + CELL(0.545 ns) 91.820 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[118\]~234 201 COMB LCCOMB_X33_Y23_N0 1 " "Info: 201: + IC(0.554 ns) + CELL(0.545 ns) = 91.820 ns; Loc. = LCCOMB_X33_Y23_N0; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[118\]~234'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.099 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~6 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[118]~234 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.788 ns) + CELL(0.495 ns) 93.103 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[5\]~9 202 COMB LCCOMB_X31_Y23_N28 1 " "Info: 202: + IC(0.788 ns) + CELL(0.495 ns) = 93.103 ns; Loc. = LCCOMB_X31_Y23_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.283 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[118]~234 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 91 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 93.561 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[6\]~10 203 COMB LCCOMB_X31_Y23_N30 16 " "Info: 203: + IC(0.000 ns) + CELL(0.458 ns) = 93.561 ns; Loc. = LCCOMB_X31_Y23_N30; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_20_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 91 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.501 ns) + CELL(0.322 ns) 94.384 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[122\]~244 204 COMB LCCOMB_X32_Y23_N18 3 " "Info: 204: + IC(0.501 ns) + CELL(0.322 ns) = 94.384 ns; Loc. = LCCOMB_X32_Y23_N18; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[122\]~244'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.823 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~244 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.149 ns) + CELL(0.517 ns) 96.050 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[3\]~5 205 COMB LCCOMB_X31_Y22_N18 2 " "Info: 205: + IC(1.149 ns) + CELL(0.517 ns) = 96.050 ns; Loc. = LCCOMB_X31_Y22_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.666 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~244 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 96.130 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[4\]~7 206 COMB LCCOMB_X31_Y22_N20 1 " "Info: 206: + IC(0.000 ns) + CELL(0.080 ns) = 96.130 ns; Loc. = LCCOMB_X31_Y22_N20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 96.210 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[5\]~9 207 COMB LCCOMB_X31_Y22_N22 1 " "Info: 207: + IC(0.000 ns) + CELL(0.080 ns) = 96.210 ns; Loc. = LCCOMB_X31_Y22_N22; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 96.668 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[6\]~10 208 COMB LCCOMB_X31_Y22_N24 16 " "Info: 208: + IC(0.000 ns) + CELL(0.458 ns) = 96.668 ns; Loc. = LCCOMB_X31_Y22_N24; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_21_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 96 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.912 ns) + CELL(0.178 ns) 97.758 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[128\]~252 209 COMB LCCOMB_X31_Y23_N14 3 " "Info: 209: + IC(0.912 ns) + CELL(0.178 ns) = 97.758 ns; Loc. = LCCOMB_X31_Y23_N14; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[128\]~252'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.090 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[128]~252 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.901 ns) + CELL(0.495 ns) 99.154 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[3\]~5 210 COMB LCCOMB_X30_Y22_N8 2 " "Info: 210: + IC(0.901 ns) + CELL(0.495 ns) = 99.154 ns; Loc. = LCCOMB_X30_Y22_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.396 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[128]~252 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 99.234 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[4\]~7 211 COMB LCCOMB_X30_Y22_N10 1 " "Info: 211: + IC(0.000 ns) + CELL(0.080 ns) = 99.234 ns; Loc. = LCCOMB_X30_Y22_N10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 99.314 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[5\]~9 212 COMB LCCOMB_X30_Y22_N12 1 " "Info: 212: + IC(0.000 ns) + CELL(0.080 ns) = 99.314 ns; Loc. = LCCOMB_X30_Y22_N12; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 99.772 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[6\]~10 213 COMB LCCOMB_X30_Y22_N14 16 " "Info: 213: + IC(0.000 ns) + CELL(0.458 ns) = 99.772 ns; Loc. = LCCOMB_X30_Y22_N14; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_22_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 101 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.501 ns) + CELL(0.178 ns) 100.451 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[134\]~260 214 COMB LCCOMB_X31_Y22_N10 3 " "Info: 214: + IC(0.501 ns) + CELL(0.178 ns) = 100.451 ns; Loc. = LCCOMB_X31_Y22_N10; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[134\]~260'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.679 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[134]~260 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.830 ns) + CELL(0.517 ns) 101.798 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[3\]~5 215 COMB LCCOMB_X29_Y22_N22 2 " "Info: 215: + IC(0.830 ns) + CELL(0.517 ns) = 101.798 ns; Loc. = LCCOMB_X29_Y22_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.347 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[134]~260 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 101.878 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[4\]~7 216 COMB LCCOMB_X29_Y22_N24 1 " "Info: 216: + IC(0.000 ns) + CELL(0.080 ns) = 101.878 ns; Loc. = LCCOMB_X29_Y22_N24; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 101.958 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[5\]~9 217 COMB LCCOMB_X29_Y22_N26 1 " "Info: 217: + IC(0.000 ns) + CELL(0.080 ns) = 101.958 ns; Loc. = LCCOMB_X29_Y22_N26; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 102.416 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[6\]~10 218 COMB LCCOMB_X29_Y22_N28 16 " "Info: 218: + IC(0.000 ns) + CELL(0.458 ns) = 102.416 ns; Loc. = LCCOMB_X29_Y22_N28; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_23_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 106 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.322 ns) 103.638 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[138\]~273 219 COMB LCCOMB_X30_Y20_N12 2 " "Info: 219: + IC(0.900 ns) + CELL(0.322 ns) = 103.638 ns; Loc. = LCCOMB_X30_Y20_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[138\]~273'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.222 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[138]~273 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.307 ns) + CELL(0.620 ns) 104.565 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[1\]~1 220 COMB LCCOMB_X30_Y20_N14 2 " "Info: 220: + IC(0.307 ns) + CELL(0.620 ns) = 104.565 ns; Loc. = LCCOMB_X30_Y20_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[1\]~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.927 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[138]~273 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[1]~1 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 104.645 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[2\]~3 221 COMB LCCOMB_X30_Y20_N16 2 " "Info: 221: + IC(0.000 ns) + CELL(0.080 ns) = 104.645 ns; Loc. = LCCOMB_X30_Y20_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[2\]~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[2]~3 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 104.725 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[3\]~5 222 COMB LCCOMB_X30_Y20_N18 2 " "Info: 222: + IC(0.000 ns) + CELL(0.080 ns) = 104.725 ns; Loc. = LCCOMB_X30_Y20_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 104.805 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[4\]~7 223 COMB LCCOMB_X30_Y20_N20 1 " "Info: 223: + IC(0.000 ns) + CELL(0.080 ns) = 104.805 ns; Loc. = LCCOMB_X30_Y20_N20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 104.885 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[5\]~9 224 COMB LCCOMB_X30_Y20_N22 1 " "Info: 224: + IC(0.000 ns) + CELL(0.080 ns) = 104.885 ns; Loc. = LCCOMB_X30_Y20_N22; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 105.343 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[6\]~10 225 COMB LCCOMB_X30_Y20_N24 16 " "Info: 225: + IC(0.000 ns) + CELL(0.458 ns) = 105.343 ns; Loc. = LCCOMB_X30_Y20_N24; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_24_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 111 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.919 ns) + CELL(0.322 ns) 106.584 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[146\]~276 226 COMB LCCOMB_X29_Y22_N14 3 " "Info: 226: + IC(0.919 ns) + CELL(0.322 ns) = 106.584 ns; Loc. = LCCOMB_X29_Y22_N14; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[146\]~276'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.241 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~276 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.183 ns) + CELL(0.517 ns) 108.284 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[3\]~5 227 COMB LCCOMB_X31_Y20_N6 2 " "Info: 227: + IC(1.183 ns) + CELL(0.517 ns) = 108.284 ns; Loc. = LCCOMB_X31_Y20_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~276 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 108.364 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[4\]~7 228 COMB LCCOMB_X31_Y20_N8 1 " "Info: 228: + IC(0.000 ns) + CELL(0.080 ns) = 108.364 ns; Loc. = LCCOMB_X31_Y20_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 108.444 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[5\]~9 229 COMB LCCOMB_X31_Y20_N10 1 " "Info: 229: + IC(0.000 ns) + CELL(0.080 ns) = 108.444 ns; Loc. = LCCOMB_X31_Y20_N10; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 108.902 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[6\]~10 230 COMB LCCOMB_X31_Y20_N12 16 " "Info: 230: + IC(0.000 ns) + CELL(0.458 ns) = 108.902 ns; Loc. = LCCOMB_X31_Y20_N12; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_25_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 116 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.556 ns) + CELL(0.322 ns) 109.780 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[152\]~284 231 COMB LCCOMB_X30_Y20_N10 3 " "Info: 231: + IC(0.556 ns) + CELL(0.322 ns) = 109.780 ns; Loc. = LCCOMB_X30_Y20_N10; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[152\]~284'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.878 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[152]~284 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.819 ns) + CELL(0.495 ns) 111.094 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[3\]~5 232 COMB LCCOMB_X32_Y20_N16 2 " "Info: 232: + IC(0.819 ns) + CELL(0.495 ns) = 111.094 ns; Loc. = LCCOMB_X32_Y20_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.314 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[152]~284 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 111.174 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[4\]~7 233 COMB LCCOMB_X32_Y20_N18 1 " "Info: 233: + IC(0.000 ns) + CELL(0.080 ns) = 111.174 ns; Loc. = LCCOMB_X32_Y20_N18; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 111.254 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[5\]~9 234 COMB LCCOMB_X32_Y20_N20 1 " "Info: 234: + IC(0.000 ns) + CELL(0.080 ns) = 111.254 ns; Loc. = LCCOMB_X32_Y20_N20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 111.712 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[6\]~10 235 COMB LCCOMB_X32_Y20_N22 16 " "Info: 235: + IC(0.000 ns) + CELL(0.458 ns) = 111.712 ns; Loc. = LCCOMB_X32_Y20_N22; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_26_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 121 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.545 ns) + CELL(0.178 ns) 112.435 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[158\]~292 236 COMB LCCOMB_X31_Y20_N26 3 " "Info: 236: + IC(0.545 ns) + CELL(0.178 ns) = 112.435 ns; Loc. = LCCOMB_X31_Y20_N26; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[158\]~292'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.723 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[158]~292 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.097 ns) + CELL(0.596 ns) 114.128 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[3\]~5 237 COMB LCCOMB_X36_Y20_N14 2 " "Info: 237: + IC(1.097 ns) + CELL(0.596 ns) = 114.128 ns; Loc. = LCCOMB_X36_Y20_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.693 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[158]~292 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 114.208 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[4\]~7 238 COMB LCCOMB_X36_Y20_N16 1 " "Info: 238: + IC(0.000 ns) + CELL(0.080 ns) = 114.208 ns; Loc. = LCCOMB_X36_Y20_N16; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 114.288 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[5\]~9 239 COMB LCCOMB_X36_Y20_N18 1 " "Info: 239: + IC(0.000 ns) + CELL(0.080 ns) = 114.288 ns; Loc. = LCCOMB_X36_Y20_N18; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 114.746 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[6\]~10 240 COMB LCCOMB_X36_Y20_N20 16 " "Info: 240: + IC(0.000 ns) + CELL(0.458 ns) = 114.746 ns; Loc. = LCCOMB_X36_Y20_N20; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_27_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 126 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.821 ns) + CELL(0.178 ns) 115.745 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[164\]~300 241 COMB LCCOMB_X32_Y20_N2 3 " "Info: 241: + IC(0.821 ns) + CELL(0.178 ns) = 115.745 ns; Loc. = LCCOMB_X32_Y20_N2; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[164\]~300'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.999 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[164]~300 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.088 ns) + CELL(0.517 ns) 117.350 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[3\]~5 242 COMB LCCOMB_X37_Y20_N20 2 " "Info: 242: + IC(1.088 ns) + CELL(0.517 ns) = 117.350 ns; Loc. = LCCOMB_X37_Y20_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.605 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[164]~300 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 117.430 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[4\]~7 243 COMB LCCOMB_X37_Y20_N22 1 " "Info: 243: + IC(0.000 ns) + CELL(0.080 ns) = 117.430 ns; Loc. = LCCOMB_X37_Y20_N22; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 117.510 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[5\]~9 244 COMB LCCOMB_X37_Y20_N24 1 " "Info: 244: + IC(0.000 ns) + CELL(0.080 ns) = 117.510 ns; Loc. = LCCOMB_X37_Y20_N24; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 117.968 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[6\]~10 245 COMB LCCOMB_X37_Y20_N26 16 " "Info: 245: + IC(0.000 ns) + CELL(0.458 ns) = 117.968 ns; Loc. = LCCOMB_X37_Y20_N26; Fanout = 16; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_28_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 131 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.570 ns) + CELL(0.322 ns) 118.860 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[170\]~308 246 COMB LCCOMB_X36_Y20_N2 3 " "Info: 246: + IC(0.570 ns) + CELL(0.322 ns) = 118.860 ns; Loc. = LCCOMB_X36_Y20_N2; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[170\]~308'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.892 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[170]~308 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.830 ns) + CELL(0.495 ns) 120.185 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[3\]~5 247 COMB LCCOMB_X38_Y20_N16 2 " "Info: 247: + IC(0.830 ns) + CELL(0.495 ns) = 120.185 ns; Loc. = LCCOMB_X38_Y20_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.325 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[170]~308 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 120.265 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[4\]~7 248 COMB LCCOMB_X38_Y20_N18 1 " "Info: 248: + IC(0.000 ns) + CELL(0.080 ns) = 120.265 ns; Loc. = LCCOMB_X38_Y20_N18; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 120.345 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[5\]~9 249 COMB LCCOMB_X38_Y20_N20 1 " "Info: 249: + IC(0.000 ns) + CELL(0.080 ns) = 120.345 ns; Loc. = LCCOMB_X38_Y20_N20; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 120.803 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[6\]~10 250 COMB LCCOMB_X38_Y20_N22 17 " "Info: 250: + IC(0.000 ns) + CELL(0.458 ns) = 120.803 ns; Loc. = LCCOMB_X38_Y20_N22; Fanout = 17; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_29_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 136 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.569 ns) + CELL(0.178 ns) 121.550 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[176\]~316 251 COMB LCCOMB_X37_Y20_N6 3 " "Info: 251: + IC(0.569 ns) + CELL(0.178 ns) = 121.550 ns; Loc. = LCCOMB_X37_Y20_N6; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[176\]~316'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.747 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~316 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.825 ns) + CELL(0.495 ns) 122.870 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[3\]~5 252 COMB LCCOMB_X39_Y20_N4 2 " "Info: 252: + IC(0.825 ns) + CELL(0.495 ns) = 122.870 ns; Loc. = LCCOMB_X39_Y20_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.320 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~316 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 122.950 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[4\]~7 253 COMB LCCOMB_X39_Y20_N6 1 " "Info: 253: + IC(0.000 ns) + CELL(0.080 ns) = 122.950 ns; Loc. = LCCOMB_X39_Y20_N6; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 123.030 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[5\]~9 254 COMB LCCOMB_X39_Y20_N8 1 " "Info: 254: + IC(0.000 ns) + CELL(0.080 ns) = 123.030 ns; Loc. = LCCOMB_X39_Y20_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 123.488 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[6\]~10 255 COMB LCCOMB_X39_Y20_N10 13 " "Info: 255: + IC(0.000 ns) + CELL(0.458 ns) = 123.488 ns; Loc. = LCCOMB_X39_Y20_N10; Fanout = 13; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_30_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 146 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.322 ns) 124.368 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[182\]~324 256 COMB LCCOMB_X38_Y20_N2 1 " "Info: 256: + IC(0.558 ns) + CELL(0.322 ns) = 124.368 ns; Loc. = LCCOMB_X38_Y20_N2; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|StageOut\[182\]~324'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.880 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[182]~324 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 198 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.848 ns) + CELL(0.495 ns) 125.711 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[3\]~5 257 COMB LCCOMB_X40_Y20_N4 1 " "Info: 257: + IC(0.848 ns) + CELL(0.495 ns) = 125.711 ns; Loc. = LCCOMB_X40_Y20_N4; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[3\]~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.343 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[182]~324 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 125.791 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[4\]~7 258 COMB LCCOMB_X40_Y20_N6 1 " "Info: 258: + IC(0.000 ns) + CELL(0.080 ns) = 125.791 ns; Loc. = LCCOMB_X40_Y20_N6; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[4\]~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 125.871 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[5\]~9 259 COMB LCCOMB_X40_Y20_N8 1 " "Info: 259: + IC(0.000 ns) + CELL(0.080 ns) = 125.871 ns; Loc. = LCCOMB_X40_Y20_N8; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[5\]~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 126.329 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[6\]~10 260 COMB LCCOMB_X40_Y20_N10 3 " "Info: 260: + IC(0.000 ns) + CELL(0.458 ns) = 126.329 ns; Loc. = LCCOMB_X40_Y20_N10; Fanout = 3; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|alt_u_div_k2f:divider\|add_sub_31_result_int\[6\]~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 } "NODE_NAME" } } { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 151 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.439 ns) + CELL(0.517 ns) 128.285 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~1 261 COMB LCCOMB_X32_Y22_N2 2 " "Info: 261: + IC(1.439 ns) + CELL(0.517 ns) = 128.285 ns; Loc. = LCCOMB_X32_Y22_N2; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.956 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~1 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 128.365 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~3 262 COMB LCCOMB_X32_Y22_N4 2 " "Info: 262: + IC(0.000 ns) + CELL(0.080 ns) = 128.365 ns; Loc. = LCCOMB_X32_Y22_N4; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~3'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~3 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 128.445 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~5 263 COMB LCCOMB_X32_Y22_N6 2 " "Info: 263: + IC(0.000 ns) + CELL(0.080 ns) = 128.445 ns; Loc. = LCCOMB_X32_Y22_N6; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 128.525 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~7 264 COMB LCCOMB_X32_Y22_N8 2 " "Info: 264: + IC(0.000 ns) + CELL(0.080 ns) = 128.525 ns; Loc. = LCCOMB_X32_Y22_N8; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~7 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 128.605 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~9 265 COMB LCCOMB_X32_Y22_N10 2 " "Info: 265: + IC(0.000 ns) + CELL(0.080 ns) = 128.605 ns; Loc. = LCCOMB_X32_Y22_N10; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~9 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 128.685 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~11 266 COMB LCCOMB_X32_Y22_N12 2 " "Info: 266: + IC(0.000 ns) + CELL(0.080 ns) = 128.685 ns; Loc. = LCCOMB_X32_Y22_N12; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~11'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~11 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 128.859 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~13 267 COMB LCCOMB_X32_Y22_N14 2 " "Info: 267: + IC(0.000 ns) + CELL(0.174 ns) = 128.859 ns; Loc. = LCCOMB_X32_Y22_N14; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~13 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 128.939 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~15 268 COMB LCCOMB_X32_Y22_N16 2 " "Info: 268: + IC(0.000 ns) + CELL(0.080 ns) = 128.939 ns; Loc. = LCCOMB_X32_Y22_N16; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~15'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~15 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 129.019 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~17 269 COMB LCCOMB_X32_Y22_N18 2 " "Info: 269: + IC(0.000 ns) + CELL(0.080 ns) = 129.019 ns; Loc. = LCCOMB_X32_Y22_N18; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~17'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~17 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 129.099 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~19 270 COMB LCCOMB_X32_Y22_N20 2 " "Info: 270: + IC(0.000 ns) + CELL(0.080 ns) = 129.099 ns; Loc. = LCCOMB_X32_Y22_N20; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~19'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~19 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 129.179 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~21 271 COMB LCCOMB_X32_Y22_N22 2 " "Info: 271: + IC(0.000 ns) + CELL(0.080 ns) = 129.179 ns; Loc. = LCCOMB_X32_Y22_N22; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~21'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~21 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 129.259 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~23 272 COMB LCCOMB_X32_Y22_N24 2 " "Info: 272: + IC(0.000 ns) + CELL(0.080 ns) = 129.259 ns; Loc. = LCCOMB_X32_Y22_N24; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~23'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~23 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 129.339 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~25 273 COMB LCCOMB_X32_Y22_N26 2 " "Info: 273: + IC(0.000 ns) + CELL(0.080 ns) = 129.339 ns; Loc. = LCCOMB_X32_Y22_N26; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~25'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~25 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 129.419 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~27 274 COMB LCCOMB_X32_Y22_N28 2 " "Info: 274: + IC(0.000 ns) + CELL(0.080 ns) = 129.419 ns; Loc. = LCCOMB_X32_Y22_N28; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~27 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 129.580 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~29 275 COMB LCCOMB_X32_Y22_N30 2 " "Info: 275: + IC(0.000 ns) + CELL(0.161 ns) = 129.580 ns; Loc. = LCCOMB_X32_Y22_N30; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~29'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.161 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~29 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 129.660 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~31 276 COMB LCCOMB_X32_Y21_N0 2 " "Info: 276: + IC(0.000 ns) + CELL(0.080 ns) = 129.660 ns; Loc. = LCCOMB_X32_Y21_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~31'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~31 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 130.118 ns Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~32 277 COMB LCCOMB_X32_Y21_N2 1 " "Info: 277: + IC(0.000 ns) + CELL(0.458 ns) = 130.118 ns; Loc. = LCCOMB_X32_Y21_N2; Fanout = 1; COMB Node = 'Arkanoid:inst\|lpm_divide:Div0\|lpm_divide_7so:auto_generated\|abs_divider_kbg:divider\|op_1~32'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~32 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.473 ns) + CELL(0.178 ns) 131.769 ns Arkanoid:inst\|Equal6~9 278 COMB LCCOMB_X31_Y21_N16 1 " "Info: 278: + IC(1.473 ns) + CELL(0.178 ns) = 131.769 ns; Loc. = LCCOMB_X31_Y21_N16; Fanout = 1; COMB Node = 'Arkanoid:inst\|Equal6~9'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.651 ns" { Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~32 Arkanoid:inst|Equal6~9 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.322 ns) 132.391 ns Arkanoid:inst\|Equal6~10 279 COMB LCCOMB_X31_Y21_N2 1 " "Info: 279: + IC(0.300 ns) + CELL(0.322 ns) = 132.391 ns; Loc. = LCCOMB_X31_Y21_N2; Fanout = 1; COMB Node = 'Arkanoid:inst\|Equal6~10'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.622 ns" { Arkanoid:inst|Equal6~9 Arkanoid:inst|Equal6~10 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.292 ns) + CELL(0.178 ns) 132.861 ns Arkanoid:inst\|Equal6~13 280 COMB LCCOMB_X31_Y21_N0 2 " "Info: 280: + IC(0.292 ns) + CELL(0.178 ns) = 132.861 ns; Loc. = LCCOMB_X31_Y21_N0; Fanout = 2; COMB Node = 'Arkanoid:inst\|Equal6~13'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.470 ns" { Arkanoid:inst|Equal6~10 Arkanoid:inst|Equal6~13 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.141 ns) + CELL(0.491 ns) 134.493 ns Arkanoid:inst\|Equal6~27 281 COMB LCCOMB_X39_Y21_N0 5 " "Info: 281: + IC(1.141 ns) + CELL(0.491 ns) = 134.493 ns; Loc. = LCCOMB_X39_Y21_N0; Fanout = 5; COMB Node = 'Arkanoid:inst\|Equal6~27'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.632 ns" { Arkanoid:inst|Equal6~13 Arkanoid:inst|Equal6~27 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.322 ns) + CELL(0.521 ns) 135.336 ns Arkanoid:inst\|WideNor0~4 282 COMB LCCOMB_X39_Y21_N12 4 " "Info: 282: + IC(0.322 ns) + CELL(0.521 ns) = 135.336 ns; Loc. = LCCOMB_X39_Y21_N12; Fanout = 4; COMB Node = 'Arkanoid:inst\|WideNor0~4'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.843 ns" { Arkanoid:inst|Equal6~27 Arkanoid:inst|WideNor0~4 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.313 ns) + CELL(0.178 ns) 135.827 ns Arkanoid:inst\|WideOr0~0 283 COMB LCCOMB_X39_Y21_N10 3 " "Info: 283: + IC(0.313 ns) + CELL(0.178 ns) = 135.827 ns; Loc. = LCCOMB_X39_Y21_N10; Fanout = 3; COMB Node = 'Arkanoid:inst\|WideOr0~0'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.491 ns" { Arkanoid:inst|WideNor0~4 Arkanoid:inst|WideOr0~0 } "NODE_NAME" } } { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.844 ns) + CELL(0.178 ns) 136.849 ns Arkanoid:inst\|high~8 284 COMB LCCOMB_X42_Y21_N10 1 " "Info: 284: + IC(0.844 ns) + CELL(0.178 ns) = 136.849 ns; Loc. = LCCOMB_X42_Y21_N10; Fanout = 1; COMB Node = 'Arkanoid:inst\|high~8'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.022 ns" { Arkanoid:inst|WideOr0~0 Arkanoid:inst|high~8 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 136.945 ns Arkanoid:inst\|hex3_\[5\] 285 REG LCFF_X42_Y21_N11 1 " "Info: 285: + IC(0.000 ns) + CELL(0.096 ns) = 136.945 ns; Loc. = LCFF_X42_Y21_N11; Fanout = 1; REG Node = 'Arkanoid:inst\|hex3_\[5\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { Arkanoid:inst|high~8 Arkanoid:inst|hex3_[5] } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "61.110 ns ( 44.62 % ) " "Info: Total cell delay = 61.110 ns ( 44.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "75.835 ns ( 55.38 % ) " "Info: Total interconnect delay = 75.835 ns ( 55.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "136.945 ns" { Arkanoid:inst|platform2_position[8] Arkanoid:inst|platform2_position~10 Arkanoid:inst|platform2_position~12 Arkanoid:inst|platform2_position~18 Arkanoid:inst|platform2_position~88 Arkanoid:inst|platform2_position~46 Arkanoid:inst|LessThan3~7 Arkanoid:inst|LessThan3~9 Arkanoid:inst|LessThan3~10 Arkanoid:inst|Add5~1 Arkanoid:inst|Add5~3 Arkanoid:inst|Add5~5 Arkanoid:inst|Add5~7 Arkanoid:inst|Add5~9 Arkanoid:inst|Add5~11 Arkanoid:inst|Add5~13 Arkanoid:inst|Add5~15 Arkanoid:inst|Add5~17 Arkanoid:inst|Add5~19 Arkanoid:inst|Add5~21 Arkanoid:inst|Add5~23 Arkanoid:inst|Add5~25 Arkanoid:inst|Add5~27 Arkanoid:inst|Add5~28 Arkanoid:inst|platform2_position~67 Arkanoid:inst|Add7~29 Arkanoid:inst|Add7~31 Arkanoid:inst|Add7~33 Arkanoid:inst|Add7~35 Arkanoid:inst|Add7~37 Arkanoid:inst|Add7~39 Arkanoid:inst|Add7~41 Arkanoid:inst|Add7~43 Arkanoid:inst|Add7~45 Arkanoid:inst|Add7~47 Arkanoid:inst|Add7~49 Arkanoid:inst|Add7~51 Arkanoid:inst|Add7~52 Arkanoid:inst|LessThan139~53 Arkanoid:inst|LessThan139~55 Arkanoid:inst|LessThan139~57 Arkanoid:inst|LessThan139~59 Arkanoid:inst|LessThan139~61 Arkanoid:inst|LessThan139~62 Arkanoid:inst|always2~4 Arkanoid:inst|Add9~1 Arkanoid:inst|Add9~3 Arkanoid:inst|Add9~5 Arkanoid:inst|Add9~7 Arkanoid:inst|Add9~9 Arkanoid:inst|Add9~11 Arkanoid:inst|Add9~13 Arkanoid:inst|Add9~15 Arkanoid:inst|Add9~17 Arkanoid:inst|Add9~19 Arkanoid:inst|Add9~21 Arkanoid:inst|Add9~23 Arkanoid:inst|Add9~25 Arkanoid:inst|Add9~27 Arkanoid:inst|Add9~29 Arkanoid:inst|Add9~31 Arkanoid:inst|Add9~33 Arkanoid:inst|Add9~35 Arkanoid:inst|Add9~37 Arkanoid:inst|Add9~39 Arkanoid:inst|Add9~41 Arkanoid:inst|Add9~43 Arkanoid:inst|Add9~45 Arkanoid:inst|Add9~47 Arkanoid:inst|Add9~49 Arkanoid:inst|Add9~51 Arkanoid:inst|Add9~53 Arkanoid:inst|Add9~55 Arkanoid:inst|Add9~57 Arkanoid:inst|Add9~59 Arkanoid:inst|Add9~61 Arkanoid:inst|Add9~63 Arkanoid:inst|Add9~65 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~57 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~59 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~60 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[19]~109 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[24]~121 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[30]~128 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~136 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[42]~144 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[51]~337 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[55]~158 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[63]~341 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[66]~177 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[76]~344 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[78]~192 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[88]~194 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[90]~208 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[98]~212 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~224 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[109]~230 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~6 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[118]~234 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~244 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[128]~252 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[134]~260 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[138]~273 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~276 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[152]~284 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[158]~292 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[164]~300 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[170]~308 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~316 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[182]~324 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~32 Arkanoid:inst|Equal6~9 Arkanoid:inst|Equal6~10 Arkanoid:inst|Equal6~13 Arkanoid:inst|Equal6~27 Arkanoid:inst|WideNor0~4 Arkanoid:inst|WideOr0~0 Arkanoid:inst|high~8 Arkanoid:inst|hex3_[5] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "136.945 ns" { Arkanoid:inst|platform2_position[8] {} Arkanoid:inst|platform2_position~10 {} Arkanoid:inst|platform2_position~12 {} Arkanoid:inst|platform2_position~18 {} Arkanoid:inst|platform2_position~88 {} Arkanoid:inst|platform2_position~46 {} Arkanoid:inst|LessThan3~7 {} Arkanoid:inst|LessThan3~9 {} Arkanoid:inst|LessThan3~10 {} Arkanoid:inst|Add5~1 {} Arkanoid:inst|Add5~3 {} Arkanoid:inst|Add5~5 {} Arkanoid:inst|Add5~7 {} Arkanoid:inst|Add5~9 {} Arkanoid:inst|Add5~11 {} Arkanoid:inst|Add5~13 {} Arkanoid:inst|Add5~15 {} Arkanoid:inst|Add5~17 {} Arkanoid:inst|Add5~19 {} Arkanoid:inst|Add5~21 {} Arkanoid:inst|Add5~23 {} Arkanoid:inst|Add5~25 {} Arkanoid:inst|Add5~27 {} Arkanoid:inst|Add5~28 {} Arkanoid:inst|platform2_position~67 {} Arkanoid:inst|Add7~29 {} Arkanoid:inst|Add7~31 {} Arkanoid:inst|Add7~33 {} Arkanoid:inst|Add7~35 {} Arkanoid:inst|Add7~37 {} Arkanoid:inst|Add7~39 {} Arkanoid:inst|Add7~41 {} Arkanoid:inst|Add7~43 {} Arkanoid:inst|Add7~45 {} Arkanoid:inst|Add7~47 {} Arkanoid:inst|Add7~49 {} Arkanoid:inst|Add7~51 {} Arkanoid:inst|Add7~52 {} Arkanoid:inst|LessThan139~53 {} Arkanoid:inst|LessThan139~55 {} Arkanoid:inst|LessThan139~57 {} Arkanoid:inst|LessThan139~59 {} Arkanoid:inst|LessThan139~61 {} Arkanoid:inst|LessThan139~62 {} Arkanoid:inst|always2~4 {} Arkanoid:inst|Add9~1 {} Arkanoid:inst|Add9~3 {} Arkanoid:inst|Add9~5 {} Arkanoid:inst|Add9~7 {} Arkanoid:inst|Add9~9 {} Arkanoid:inst|Add9~11 {} Arkanoid:inst|Add9~13 {} Arkanoid:inst|Add9~15 {} Arkanoid:inst|Add9~17 {} Arkanoid:inst|Add9~19 {} Arkanoid:inst|Add9~21 {} Arkanoid:inst|Add9~23 {} Arkanoid:inst|Add9~25 {} Arkanoid:inst|Add9~27 {} Arkanoid:inst|Add9~29 {} Arkanoid:inst|Add9~31 {} Arkanoid:inst|Add9~33 {} Arkanoid:inst|Add9~35 {} Arkanoid:inst|Add9~37 {} Arkanoid:inst|Add9~39 {} Arkanoid:inst|Add9~41 {} Arkanoid:inst|Add9~43 {} Arkanoid:inst|Add9~45 {} Arkanoid:inst|Add9~47 {} Arkanoid:inst|Add9~49 {} Arkanoid:inst|Add9~51 {} Arkanoid:inst|Add9~53 {} Arkanoid:inst|Add9~55 {} Arkanoid:inst|Add9~57 {} Arkanoid:inst|Add9~59 {} Arkanoid:inst|Add9~61 {} Arkanoid:inst|Add9~63 {} Arkanoid:inst|Add9~65 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~57 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~59 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~60 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[19]~109 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[24]~121 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[30]~128 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~136 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[42]~144 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[51]~337 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[55]~158 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[63]~341 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[66]~177 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[76]~344 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[78]~192 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[88]~194 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[90]~208 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[98]~212 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~224 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[109]~230 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~6 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[118]~234 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~244 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[128]~252 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[134]~260 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[138]~273 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~276 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[152]~284 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[158]~292 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[164]~300 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[170]~308 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~316 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[182]~324 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~11 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~13 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~15 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~17 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~19 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~21 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~23 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~25 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~27 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~29 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~31 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~32 {} Arkanoid:inst|Equal6~9 {} Arkanoid:inst|Equal6~10 {} Arkanoid:inst|Equal6~13 {} Arkanoid:inst|Equal6~27 {} Arkanoid:inst|WideNor0~4 {} Arkanoid:inst|WideOr0~0 {} Arkanoid:inst|high~8 {} Arkanoid:inst|hex3_[5] {} } { 0.000ns 1.735ns 0.289ns 1.340ns 0.840ns 1.373ns 0.933ns 1.041ns 0.284ns 0.903ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.320ns 1.359ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.822ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.527ns 1.773ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 2.360ns 2.221ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.562ns 0.000ns 0.351ns 0.819ns 0.000ns 0.000ns 0.000ns 0.892ns 0.867ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.926ns 0.516ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.796ns 1.784ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 2.099ns 0.567ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 2.027ns 2.072ns 0.000ns 0.000ns 0.954ns 0.815ns 0.000ns 0.000ns 0.000ns 0.000ns 0.874ns 0.893ns 0.000ns 0.000ns 1.219ns 0.918ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.823ns 0.802ns 0.000ns 0.995ns 0.563ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.930ns 1.280ns 0.000ns 0.625ns 0.314ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.923ns 0.552ns 0.000ns 0.000ns 0.000ns 0.640ns 0.498ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.590ns 0.534ns 0.000ns 0.000ns 0.554ns 0.788ns 0.000ns 0.501ns 1.149ns 0.000ns 0.000ns 0.000ns 0.912ns 0.901ns 0.000ns 0.000ns 0.000ns 0.501ns 0.830ns 0.000ns 0.000ns 0.000ns 0.900ns 0.307ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.919ns 1.183ns 0.000ns 0.000ns 0.000ns 0.556ns 0.819ns 0.000ns 0.000ns 0.000ns 0.545ns 1.097ns 0.000ns 0.000ns 0.000ns 0.821ns 1.088ns 0.000ns 0.000ns 0.000ns 0.570ns 0.830ns 0.000ns 0.000ns 0.000ns 0.569ns 0.825ns 0.000ns 0.000ns 0.000ns 0.558ns 0.848ns 0.000ns 0.000ns 0.000ns 1.439ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.473ns 0.300ns 0.292ns 1.141ns 0.322ns 0.313ns 0.844ns 0.000ns } { 0.000ns 0.455ns 0.491ns 0.319ns 0.178ns 0.322ns 0.455ns 0.322ns 0.178ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.161ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.458ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.161ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.161ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.517ns 0.458ns 0.177ns 0.517ns 0.080ns 0.080ns 0.458ns 0.177ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.322ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.319ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.458ns 0.319ns 0.517ns 0.080ns 0.080ns 0.174ns 0.458ns 0.178ns 0.495ns 0.174ns 0.458ns 0.177ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.174ns 0.080ns 0.458ns 0.177ns 0.517ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.174ns 0.080ns 0.458ns 0.178ns 0.620ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.080ns 0.174ns 0.458ns 0.319ns 0.517ns 0.080ns 0.458ns 0.545ns 0.495ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.458ns 0.322ns 0.620ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.458ns 0.322ns 0.495ns 0.080ns 0.080ns 0.458ns 0.178ns 0.596ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.458ns 0.322ns 0.495ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.080ns 0.080ns 0.458ns 0.322ns 0.495ns 0.080ns 0.080ns 0.458ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.161ns 0.080ns 0.458ns 0.178ns 0.322ns 0.178ns 0.491ns 0.521ns 0.178ns 0.178ns 0.096ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.013 ns - Smallest " "Info: - Smallest clock skew is 0.013 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz destination 6.643 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_50MHz\" to destination register is 6.643 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk_50MHz 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -168 -72 96 -152 "clk_50MHz" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.937 ns) + CELL(0.879 ns) 3.842 ns ClockDivider:inst1\|clk25MHz_ 2 REG LCFF_X25_Y2_N1 2 " "Info: 2: + IC(1.937 ns) + CELL(0.879 ns) = 3.842 ns; Loc. = LCFF_X25_Y2_N1; Fanout = 2; REG Node = 'ClockDivider:inst1\|clk25MHz_'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.816 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.215 ns) + CELL(0.000 ns) 5.057 ns ClockDivider:inst1\|clk25MHz_~clkctrl 3 COMB CLKCTRL_G12 1085 " "Info: 3: + IC(1.215 ns) + CELL(0.000 ns) = 5.057 ns; Loc. = CLKCTRL_G12; Fanout = 1085; COMB Node = 'ClockDivider:inst1\|clk25MHz_~clkctrl'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.215 ns" { ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.984 ns) + CELL(0.602 ns) 6.643 ns Arkanoid:inst\|hex3_\[5\] 4 REG LCFF_X42_Y21_N11 1 " "Info: 4: + IC(0.984 ns) + CELL(0.602 ns) = 6.643 ns; Loc. = LCFF_X42_Y21_N11; Fanout = 1; REG Node = 'Arkanoid:inst\|hex3_\[5\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.586 ns" { ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|hex3_[5] } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 37.74 % ) " "Info: Total cell delay = 2.507 ns ( 37.74 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.136 ns ( 62.26 % ) " "Info: Total interconnect delay = 4.136 ns ( 62.26 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.643 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|hex3_[5] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "6.643 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|hex3_[5] {} } { 0.000ns 0.000ns 1.937ns 1.215ns 0.984ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz source 6.630 ns - Longest register " "Info: - Longest clock path from clock \"clk_50MHz\" to source register is 6.630 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk_50MHz 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -168 -72 96 -152 "clk_50MHz" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.937 ns) + CELL(0.879 ns) 3.842 ns ClockDivider:inst1\|clk25MHz_ 2 REG LCFF_X25_Y2_N1 2 " "Info: 2: + IC(1.937 ns) + CELL(0.879 ns) = 3.842 ns; Loc. = LCFF_X25_Y2_N1; Fanout = 2; REG Node = 'ClockDivider:inst1\|clk25MHz_'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.816 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.215 ns) + CELL(0.000 ns) 5.057 ns ClockDivider:inst1\|clk25MHz_~clkctrl 3 COMB CLKCTRL_G12 1085 " "Info: 3: + IC(1.215 ns) + CELL(0.000 ns) = 5.057 ns; Loc. = CLKCTRL_G12; Fanout = 1085; COMB Node = 'ClockDivider:inst1\|clk25MHz_~clkctrl'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.215 ns" { ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.971 ns) + CELL(0.602 ns) 6.630 ns Arkanoid:inst\|platform2_position\[8\] 4 REG LCFF_X27_Y16_N17 4 " "Info: 4: + IC(0.971 ns) + CELL(0.602 ns) = 6.630 ns; Loc. = LCFF_X27_Y16_N17; Fanout = 4; REG Node = 'Arkanoid:inst\|platform2_position\[8\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|platform2_position[8] } "NODE_NAME" } } { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 37.81 % ) " "Info: Total cell delay = 2.507 ns ( 37.81 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.123 ns ( 62.19 % ) " "Info: Total interconnect delay = 4.123 ns ( 62.19 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.630 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|platform2_position[8] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "6.630 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|platform2_position[8] {} } { 0.000ns 0.000ns 1.937ns 1.215ns 0.971ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.643 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|hex3_[5] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "6.643 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|hex3_[5] {} } { 0.000ns 0.000ns 1.937ns 1.215ns 0.984ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.630 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|platform2_position[8] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "6.630 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|platform2_position[8] {} } { 0.000ns 0.000ns 1.937ns 1.215ns 0.971ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" { } { { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 18 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" { } { { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 18 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "136.945 ns" { Arkanoid:inst|platform2_position[8] Arkanoid:inst|platform2_position~10 Arkanoid:inst|platform2_position~12 Arkanoid:inst|platform2_position~18 Arkanoid:inst|platform2_position~88 Arkanoid:inst|platform2_position~46 Arkanoid:inst|LessThan3~7 Arkanoid:inst|LessThan3~9 Arkanoid:inst|LessThan3~10 Arkanoid:inst|Add5~1 Arkanoid:inst|Add5~3 Arkanoid:inst|Add5~5 Arkanoid:inst|Add5~7 Arkanoid:inst|Add5~9 Arkanoid:inst|Add5~11 Arkanoid:inst|Add5~13 Arkanoid:inst|Add5~15 Arkanoid:inst|Add5~17 Arkanoid:inst|Add5~19 Arkanoid:inst|Add5~21 Arkanoid:inst|Add5~23 Arkanoid:inst|Add5~25 Arkanoid:inst|Add5~27 Arkanoid:inst|Add5~28 Arkanoid:inst|platform2_position~67 Arkanoid:inst|Add7~29 Arkanoid:inst|Add7~31 Arkanoid:inst|Add7~33 Arkanoid:inst|Add7~35 Arkanoid:inst|Add7~37 Arkanoid:inst|Add7~39 Arkanoid:inst|Add7~41 Arkanoid:inst|Add7~43 Arkanoid:inst|Add7~45 Arkanoid:inst|Add7~47 Arkanoid:inst|Add7~49 Arkanoid:inst|Add7~51 Arkanoid:inst|Add7~52 Arkanoid:inst|LessThan139~53 Arkanoid:inst|LessThan139~55 Arkanoid:inst|LessThan139~57 Arkanoid:inst|LessThan139~59 Arkanoid:inst|LessThan139~61 Arkanoid:inst|LessThan139~62 Arkanoid:inst|always2~4 Arkanoid:inst|Add9~1 Arkanoid:inst|Add9~3 Arkanoid:inst|Add9~5 Arkanoid:inst|Add9~7 Arkanoid:inst|Add9~9 Arkanoid:inst|Add9~11 Arkanoid:inst|Add9~13 Arkanoid:inst|Add9~15 Arkanoid:inst|Add9~17 Arkanoid:inst|Add9~19 Arkanoid:inst|Add9~21 Arkanoid:inst|Add9~23 Arkanoid:inst|Add9~25 Arkanoid:inst|Add9~27 Arkanoid:inst|Add9~29 Arkanoid:inst|Add9~31 Arkanoid:inst|Add9~33 Arkanoid:inst|Add9~35 Arkanoid:inst|Add9~37 Arkanoid:inst|Add9~39 Arkanoid:inst|Add9~41 Arkanoid:inst|Add9~43 Arkanoid:inst|Add9~45 Arkanoid:inst|Add9~47 Arkanoid:inst|Add9~49 Arkanoid:inst|Add9~51 Arkanoid:inst|Add9~53 Arkanoid:inst|Add9~55 Arkanoid:inst|Add9~57 Arkanoid:inst|Add9~59 Arkanoid:inst|Add9~61 Arkanoid:inst|Add9~63 Arkanoid:inst|Add9~65 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~57 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~59 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~60 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[19]~109 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[24]~121 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[30]~128 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~136 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[42]~144 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[51]~337 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[55]~158 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[63]~341 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[66]~177 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[76]~344 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[78]~192 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[88]~194 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[90]~208 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[98]~212 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~224 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[109]~230 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~6 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[118]~234 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~244 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[128]~252 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[134]~260 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[138]~273 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[1]~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[2]~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~276 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[152]~284 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[158]~292 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[164]~300 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[170]~308 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~316 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[182]~324 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~1 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~3 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~5 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~7 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~9 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~11 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~13 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~15 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~17 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~19 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~21 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~23 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~25 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~27 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~29 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~31 Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~32 Arkanoid:inst|Equal6~9 Arkanoid:inst|Equal6~10 Arkanoid:inst|Equal6~13 Arkanoid:inst|Equal6~27 Arkanoid:inst|WideNor0~4 Arkanoid:inst|WideOr0~0 Arkanoid:inst|high~8 Arkanoid:inst|hex3_[5] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "136.945 ns" { Arkanoid:inst|platform2_position[8] {} Arkanoid:inst|platform2_position~10 {} Arkanoid:inst|platform2_position~12 {} Arkanoid:inst|platform2_position~18 {} Arkanoid:inst|platform2_position~88 {} Arkanoid:inst|platform2_position~46 {} Arkanoid:inst|LessThan3~7 {} Arkanoid:inst|LessThan3~9 {} Arkanoid:inst|LessThan3~10 {} Arkanoid:inst|Add5~1 {} Arkanoid:inst|Add5~3 {} Arkanoid:inst|Add5~5 {} Arkanoid:inst|Add5~7 {} Arkanoid:inst|Add5~9 {} Arkanoid:inst|Add5~11 {} Arkanoid:inst|Add5~13 {} Arkanoid:inst|Add5~15 {} Arkanoid:inst|Add5~17 {} Arkanoid:inst|Add5~19 {} Arkanoid:inst|Add5~21 {} Arkanoid:inst|Add5~23 {} Arkanoid:inst|Add5~25 {} Arkanoid:inst|Add5~27 {} Arkanoid:inst|Add5~28 {} Arkanoid:inst|platform2_position~67 {} Arkanoid:inst|Add7~29 {} Arkanoid:inst|Add7~31 {} Arkanoid:inst|Add7~33 {} Arkanoid:inst|Add7~35 {} Arkanoid:inst|Add7~37 {} Arkanoid:inst|Add7~39 {} Arkanoid:inst|Add7~41 {} Arkanoid:inst|Add7~43 {} Arkanoid:inst|Add7~45 {} Arkanoid:inst|Add7~47 {} Arkanoid:inst|Add7~49 {} Arkanoid:inst|Add7~51 {} Arkanoid:inst|Add7~52 {} Arkanoid:inst|LessThan139~53 {} Arkanoid:inst|LessThan139~55 {} Arkanoid:inst|LessThan139~57 {} Arkanoid:inst|LessThan139~59 {} Arkanoid:inst|LessThan139~61 {} Arkanoid:inst|LessThan139~62 {} Arkanoid:inst|always2~4 {} Arkanoid:inst|Add9~1 {} Arkanoid:inst|Add9~3 {} Arkanoid:inst|Add9~5 {} Arkanoid:inst|Add9~7 {} Arkanoid:inst|Add9~9 {} Arkanoid:inst|Add9~11 {} Arkanoid:inst|Add9~13 {} Arkanoid:inst|Add9~15 {} Arkanoid:inst|Add9~17 {} Arkanoid:inst|Add9~19 {} Arkanoid:inst|Add9~21 {} Arkanoid:inst|Add9~23 {} Arkanoid:inst|Add9~25 {} Arkanoid:inst|Add9~27 {} Arkanoid:inst|Add9~29 {} Arkanoid:inst|Add9~31 {} Arkanoid:inst|Add9~33 {} Arkanoid:inst|Add9~35 {} Arkanoid:inst|Add9~37 {} Arkanoid:inst|Add9~39 {} Arkanoid:inst|Add9~41 {} Arkanoid:inst|Add9~43 {} Arkanoid:inst|Add9~45 {} Arkanoid:inst|Add9~47 {} Arkanoid:inst|Add9~49 {} Arkanoid:inst|Add9~51 {} Arkanoid:inst|Add9~53 {} Arkanoid:inst|Add9~55 {} Arkanoid:inst|Add9~57 {} Arkanoid:inst|Add9~59 {} Arkanoid:inst|Add9~61 {} Arkanoid:inst|Add9~63 {} Arkanoid:inst|Add9~65 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~57 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~59 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~60 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[19]~109 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[24]~121 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[30]~128 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~136 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[42]~144 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[51]~337 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[55]~158 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[63]~341 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[66]~177 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[76]~344 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[78]~192 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[88]~194 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[90]~208 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[98]~212 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~224 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[109]~230 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~6 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[118]~234 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~244 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[128]~252 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[134]~260 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[138]~273 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[1]~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[2]~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~276 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[152]~284 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[158]~292 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[164]~300 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[170]~308 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~316 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[182]~324 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~1 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~3 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~5 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~7 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~9 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~11 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~13 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~15 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~17 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~19 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~21 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~23 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~25 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~27 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~29 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~31 {} Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~32 {} Arkanoid:inst|Equal6~9 {} Arkanoid:inst|Equal6~10 {} Arkanoid:inst|Equal6~13 {} Arkanoid:inst|Equal6~27 {} Arkanoid:inst|WideNor0~4 {} Arkanoid:inst|WideOr0~0 {} Arkanoid:inst|high~8 {} Arkanoid:inst|hex3_[5] {} } { 0.000ns 1.735ns 0.289ns 1.340ns 0.840ns 1.373ns 0.933ns 1.041ns 0.284ns 0.903ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.320ns 1.359ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.822ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.527ns 1.773ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 2.360ns 2.221ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.562ns 0.000ns 0.351ns 0.819ns 0.000ns 0.000ns 0.000ns 0.892ns 0.867ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.926ns 0.516ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.796ns 1.784ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 2.099ns 0.567ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 2.027ns 2.072ns 0.000ns 0.000ns 0.954ns 0.815ns 0.000ns 0.000ns 0.000ns 0.000ns 0.874ns 0.893ns 0.000ns 0.000ns 1.219ns 0.918ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.823ns 0.802ns 0.000ns 0.995ns 0.563ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.930ns 1.280ns 0.000ns 0.625ns 0.314ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.923ns 0.552ns 0.000ns 0.000ns 0.000ns 0.640ns 0.498ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.590ns 0.534ns 0.000ns 0.000ns 0.554ns 0.788ns 0.000ns 0.501ns 1.149ns 0.000ns 0.000ns 0.000ns 0.912ns 0.901ns 0.000ns 0.000ns 0.000ns 0.501ns 0.830ns 0.000ns 0.000ns 0.000ns 0.900ns 0.307ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.919ns 1.183ns 0.000ns 0.000ns 0.000ns 0.556ns 0.819ns 0.000ns 0.000ns 0.000ns 0.545ns 1.097ns 0.000ns 0.000ns 0.000ns 0.821ns 1.088ns 0.000ns 0.000ns 0.000ns 0.570ns 0.830ns 0.000ns 0.000ns 0.000ns 0.569ns 0.825ns 0.000ns 0.000ns 0.000ns 0.558ns 0.848ns 0.000ns 0.000ns 0.000ns 1.439ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.473ns 0.300ns 0.292ns 1.141ns 0.322ns 0.313ns 0.844ns 0.000ns } { 0.000ns 0.455ns 0.491ns 0.319ns 0.178ns 0.322ns 0.455ns 0.322ns 0.178ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.161ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.458ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.161ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.161ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.517ns 0.458ns 0.177ns 0.517ns 0.080ns 0.080ns 0.458ns 0.177ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.322ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.319ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.458ns 0.319ns 0.517ns 0.080ns 0.080ns 0.174ns 0.458ns 0.178ns 0.495ns 0.174ns 0.458ns 0.177ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.174ns 0.080ns 0.458ns 0.177ns 0.517ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.174ns 0.080ns 0.458ns 0.178ns 0.620ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.080ns 0.174ns 0.458ns 0.319ns 0.517ns 0.080ns 0.458ns 0.545ns 0.495ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.458ns 0.322ns 0.620ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.322ns 0.517ns 0.080ns 0.080ns 0.458ns 0.322ns 0.495ns 0.080ns 0.080ns 0.458ns 0.178ns 0.596ns 0.080ns 0.080ns 0.458ns 0.178ns 0.517ns 0.080ns 0.080ns 0.458ns 0.322ns 0.495ns 0.080ns 0.080ns 0.458ns 0.178ns 0.495ns 0.080ns 0.080ns 0.458ns 0.322ns 0.495ns 0.080ns 0.080ns 0.458ns 0.517ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.161ns 0.080ns 0.458ns 0.178ns 0.322ns 0.178ns 0.491ns 0.521ns 0.178ns 0.178ns 0.096ns } "" } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.643 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|hex3_[5] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "6.643 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|hex3_[5] {} } { 0.000ns 0.000ns 1.937ns 1.215ns 0.984ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.630 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|platform2_position[8] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "6.630 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|platform2_position[8] {} } { 0.000ns 0.000ns 1.937ns 1.215ns 0.971ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
+{ "Info" "ITDB_TSU_RESULT" "Debouncer:inst2\|button_reg\[0\] button1 clk_50MHz 0.191 ns register " "Info: tsu for register \"Debouncer:inst2\|button_reg\[0\]\" (data pin = \"button1\", clock pin = \"clk_50MHz\") is 0.191 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.872 ns + Longest pin register " "Info: + Longest pin to register delay is 6.872 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.874 ns) 0.874 ns button1 1 PIN PIN_T21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.874 ns) = 0.874 ns; Loc. = PIN_T21; Fanout = 1; PIN Node = 'button1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { button1 } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -72 -72 96 -56 "button1" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.585 ns) + CELL(0.413 ns) 6.872 ns Debouncer:inst2\|button_reg\[0\] 2 REG LCFF_X44_Y12_N17 2 " "Info: 2: + IC(5.585 ns) + CELL(0.413 ns) = 6.872 ns; Loc. = LCFF_X44_Y12_N17; Fanout = 2; REG Node = 'Debouncer:inst2\|button_reg\[0\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.998 ns" { button1 Debouncer:inst2|button_reg[0] } "NODE_NAME" } } { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.287 ns ( 18.73 % ) " "Info: Total cell delay = 1.287 ns ( 18.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.585 ns ( 81.27 % ) " "Info: Total interconnect delay = 5.585 ns ( 81.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.872 ns" { button1 Debouncer:inst2|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "6.872 ns" { button1 {} button1~combout {} Debouncer:inst2|button_reg[0] {} } { 0.000ns 0.000ns 5.585ns } { 0.000ns 0.874ns 0.413ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" { } { { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 9 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz destination 6.643 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_50MHz\" to destination register is 6.643 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk_50MHz 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -168 -72 96 -152 "clk_50MHz" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.937 ns) + CELL(0.879 ns) 3.842 ns ClockDivider:inst1\|clk25MHz_ 2 REG LCFF_X25_Y2_N1 2 " "Info: 2: + IC(1.937 ns) + CELL(0.879 ns) = 3.842 ns; Loc. = LCFF_X25_Y2_N1; Fanout = 2; REG Node = 'ClockDivider:inst1\|clk25MHz_'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.816 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.215 ns) + CELL(0.000 ns) 5.057 ns ClockDivider:inst1\|clk25MHz_~clkctrl 3 COMB CLKCTRL_G12 1085 " "Info: 3: + IC(1.215 ns) + CELL(0.000 ns) = 5.057 ns; Loc. = CLKCTRL_G12; Fanout = 1085; COMB Node = 'ClockDivider:inst1\|clk25MHz_~clkctrl'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.215 ns" { ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.984 ns) + CELL(0.602 ns) 6.643 ns Debouncer:inst2\|button_reg\[0\] 4 REG LCFF_X44_Y12_N17 2 " "Info: 4: + IC(0.984 ns) + CELL(0.602 ns) = 6.643 ns; Loc. = LCFF_X44_Y12_N17; Fanout = 2; REG Node = 'Debouncer:inst2\|button_reg\[0\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.586 ns" { ClockDivider:inst1|clk25MHz_~clkctrl Debouncer:inst2|button_reg[0] } "NODE_NAME" } } { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 37.74 % ) " "Info: Total cell delay = 2.507 ns ( 37.74 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.136 ns ( 62.26 % ) " "Info: Total interconnect delay = 4.136 ns ( 62.26 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.643 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Debouncer:inst2|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "6.643 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Debouncer:inst2|button_reg[0] {} } { 0.000ns 0.000ns 1.937ns 1.215ns 0.984ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.872 ns" { button1 Debouncer:inst2|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "6.872 ns" { button1 {} button1~combout {} Debouncer:inst2|button_reg[0] {} } { 0.000ns 0.000ns 5.585ns } { 0.000ns 0.874ns 0.413ns } "" } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.643 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Debouncer:inst2|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "6.643 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Debouncer:inst2|button_reg[0] {} } { 0.000ns 0.000ns 1.937ns 1.215ns 0.984ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TCO_RESULT" "clk_50MHz h_sync Arkanoid:inst\|h_counter\[12\] 16.438 ns register " "Info: tco from clock \"clk_50MHz\" to destination pin \"h_sync\" through register \"Arkanoid:inst\|h_counter\[12\]\" is 16.438 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz source 6.621 ns + Longest register " "Info: + Longest clock path from clock \"clk_50MHz\" to source register is 6.621 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk_50MHz 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -168 -72 96 -152 "clk_50MHz" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.937 ns) + CELL(0.879 ns) 3.842 ns ClockDivider:inst1\|clk25MHz_ 2 REG LCFF_X25_Y2_N1 2 " "Info: 2: + IC(1.937 ns) + CELL(0.879 ns) = 3.842 ns; Loc. = LCFF_X25_Y2_N1; Fanout = 2; REG Node = 'ClockDivider:inst1\|clk25MHz_'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.816 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.215 ns) + CELL(0.000 ns) 5.057 ns ClockDivider:inst1\|clk25MHz_~clkctrl 3 COMB CLKCTRL_G12 1085 " "Info: 3: + IC(1.215 ns) + CELL(0.000 ns) = 5.057 ns; Loc. = CLKCTRL_G12; Fanout = 1085; COMB Node = 'ClockDivider:inst1\|clk25MHz_~clkctrl'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.215 ns" { ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.962 ns) + CELL(0.602 ns) 6.621 ns Arkanoid:inst\|h_counter\[12\] 4 REG LCFF_X21_Y8_N25 5 " "Info: 4: + IC(0.962 ns) + CELL(0.602 ns) = 6.621 ns; Loc. = LCFF_X21_Y8_N25; Fanout = 5; REG Node = 'Arkanoid:inst\|h_counter\[12\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.564 ns" { ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|h_counter[12] } "NODE_NAME" } } { "vga_sync.v" "" { Text "G:/Verilog/Arkanoid2PDE1/vga_sync.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 37.86 % ) " "Info: Total cell delay = 2.507 ns ( 37.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.114 ns ( 62.14 % ) " "Info: Total interconnect delay = 4.114 ns ( 62.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.621 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|h_counter[12] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "6.621 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|h_counter[12] {} } { 0.000ns 0.000ns 1.937ns 1.215ns 0.962ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" { } { { "vga_sync.v" "" { Text "G:/Verilog/Arkanoid2PDE1/vga_sync.v" 9 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.540 ns + Longest register pin " "Info: + Longest register to pin delay is 9.540 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Arkanoid:inst\|h_counter\[12\] 1 REG LCFF_X21_Y8_N25 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y8_N25; Fanout = 5; REG Node = 'Arkanoid:inst\|h_counter\[12\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { Arkanoid:inst|h_counter[12] } "NODE_NAME" } } { "vga_sync.v" "" { Text "G:/Verilog/Arkanoid2PDE1/vga_sync.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.898 ns) + CELL(0.455 ns) 1.353 ns Arkanoid:inst\|Equal0~1 2 COMB LCCOMB_X22_Y8_N0 1 " "Info: 2: + IC(0.898 ns) + CELL(0.455 ns) = 1.353 ns; Loc. = LCCOMB_X22_Y8_N0; Fanout = 1; COMB Node = 'Arkanoid:inst\|Equal0~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.353 ns" { Arkanoid:inst|h_counter[12] Arkanoid:inst|Equal0~1 } "NODE_NAME" } } { "vga_sync.v" "" { Text "G:/Verilog/Arkanoid2PDE1/vga_sync.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.409 ns) + CELL(0.322 ns) 3.084 ns Arkanoid:inst\|Equal0~5 3 COMB LCCOMB_X20_Y7_N22 1 " "Info: 3: + IC(1.409 ns) + CELL(0.322 ns) = 3.084 ns; Loc. = LCCOMB_X20_Y7_N22; Fanout = 1; COMB Node = 'Arkanoid:inst\|Equal0~5'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.731 ns" { Arkanoid:inst|Equal0~1 Arkanoid:inst|Equal0~5 } "NODE_NAME" } } { "vga_sync.v" "" { Text "G:/Verilog/Arkanoid2PDE1/vga_sync.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.298 ns) + CELL(0.178 ns) 3.560 ns Arkanoid:inst\|Equal0~7 4 COMB LCCOMB_X20_Y7_N26 6 " "Info: 4: + IC(0.298 ns) + CELL(0.178 ns) = 3.560 ns; Loc. = LCCOMB_X20_Y7_N26; Fanout = 6; COMB Node = 'Arkanoid:inst\|Equal0~7'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.476 ns" { Arkanoid:inst|Equal0~5 Arkanoid:inst|Equal0~7 } "NODE_NAME" } } { "vga_sync.v" "" { Text "G:/Verilog/Arkanoid2PDE1/vga_sync.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.297 ns) + CELL(0.178 ns) 4.035 ns Arkanoid:inst\|h_sync~1 5 COMB LCCOMB_X20_Y7_N28 1 " "Info: 5: + IC(0.297 ns) + CELL(0.178 ns) = 4.035 ns; Loc. = LCCOMB_X20_Y7_N28; Fanout = 1; COMB Node = 'Arkanoid:inst\|h_sync~1'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.475 ns" { Arkanoid:inst|Equal0~7 Arkanoid:inst|h_sync~1 } "NODE_NAME" } } { "arkanoid_header.v" "" { Text "G:/Verilog/Arkanoid2PDE1/arkanoid_header.v" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.499 ns) + CELL(3.006 ns) 9.540 ns h_sync 6 PIN PIN_A11 0 " "Info: 6: + IC(2.499 ns) + CELL(3.006 ns) = 9.540 ns; Loc. = PIN_A11; Fanout = 0; PIN Node = 'h_sync'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.505 ns" { Arkanoid:inst|h_sync~1 h_sync } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { 96 856 1032 112 "h_sync" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.139 ns ( 43.39 % ) " "Info: Total cell delay = 4.139 ns ( 43.39 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.401 ns ( 56.61 % ) " "Info: Total interconnect delay = 5.401 ns ( 56.61 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "9.540 ns" { Arkanoid:inst|h_counter[12] Arkanoid:inst|Equal0~1 Arkanoid:inst|Equal0~5 Arkanoid:inst|Equal0~7 Arkanoid:inst|h_sync~1 h_sync } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "9.540 ns" { Arkanoid:inst|h_counter[12] {} Arkanoid:inst|Equal0~1 {} Arkanoid:inst|Equal0~5 {} Arkanoid:inst|Equal0~7 {} Arkanoid:inst|h_sync~1 {} h_sync {} } { 0.000ns 0.898ns 1.409ns 0.298ns 0.297ns 2.499ns } { 0.000ns 0.455ns 0.322ns 0.178ns 0.178ns 3.006ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.621 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Arkanoid:inst|h_counter[12] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "6.621 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Arkanoid:inst|h_counter[12] {} } { 0.000ns 0.000ns 1.937ns 1.215ns 0.962ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "9.540 ns" { Arkanoid:inst|h_counter[12] Arkanoid:inst|Equal0~1 Arkanoid:inst|Equal0~5 Arkanoid:inst|Equal0~7 Arkanoid:inst|h_sync~1 h_sync } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "9.540 ns" { Arkanoid:inst|h_counter[12] {} Arkanoid:inst|Equal0~1 {} Arkanoid:inst|Equal0~5 {} Arkanoid:inst|Equal0~7 {} Arkanoid:inst|h_sync~1 {} h_sync {} } { 0.000ns 0.898ns 1.409ns 0.298ns 0.297ns 2.499ns } { 0.000ns 0.455ns 0.322ns 0.178ns 0.178ns 3.006ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_TH_RESULT" "Debouncer:inst3\|button_reg\[0\] button2 clk_50MHz 0.227 ns register " "Info: th for register \"Debouncer:inst3\|button_reg\[0\]\" (data pin = \"button2\", clock pin = \"clk_50MHz\") is 0.227 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz destination 6.632 ns + Longest register " "Info: + Longest clock path from clock \"clk_50MHz\" to destination register is 6.632 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk_50MHz 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -168 -72 96 -152 "clk_50MHz" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.937 ns) + CELL(0.879 ns) 3.842 ns ClockDivider:inst1\|clk25MHz_ 2 REG LCFF_X25_Y2_N1 2 " "Info: 2: + IC(1.937 ns) + CELL(0.879 ns) = 3.842 ns; Loc. = LCFF_X25_Y2_N1; Fanout = 2; REG Node = 'ClockDivider:inst1\|clk25MHz_'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.816 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.215 ns) + CELL(0.000 ns) 5.057 ns ClockDivider:inst1\|clk25MHz_~clkctrl 3 COMB CLKCTRL_G12 1085 " "Info: 3: + IC(1.215 ns) + CELL(0.000 ns) = 5.057 ns; Loc. = CLKCTRL_G12; Fanout = 1085; COMB Node = 'ClockDivider:inst1\|clk25MHz_~clkctrl'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.215 ns" { ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl } "NODE_NAME" } } { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.973 ns) + CELL(0.602 ns) 6.632 ns Debouncer:inst3\|button_reg\[0\] 4 REG LCFF_X36_Y9_N21 2 " "Info: 4: + IC(0.973 ns) + CELL(0.602 ns) = 6.632 ns; Loc. = LCFF_X36_Y9_N21; Fanout = 2; REG Node = 'Debouncer:inst3\|button_reg\[0\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.575 ns" { ClockDivider:inst1|clk25MHz_~clkctrl Debouncer:inst3|button_reg[0] } "NODE_NAME" } } { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 37.80 % ) " "Info: Total cell delay = 2.507 ns ( 37.80 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.125 ns ( 62.20 % ) " "Info: Total interconnect delay = 4.125 ns ( 62.20 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.632 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Debouncer:inst3|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "6.632 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Debouncer:inst3|button_reg[0] {} } { 0.000ns 0.000ns 1.937ns 1.215ns 0.973ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" { } { { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 9 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.691 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.691 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.874 ns) 0.874 ns button2 1 PIN PIN_T22 1 " "Info: 1: + IC(0.000 ns) + CELL(0.874 ns) = 0.874 ns; Loc. = PIN_T22; Fanout = 1; PIN Node = 'button2'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { button2 } "NODE_NAME" } } { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { 24 -72 96 40 "button2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.543 ns) + CELL(0.178 ns) 6.595 ns Debouncer:inst3\|button_reg\[0\]~feeder 2 COMB LCCOMB_X36_Y9_N20 1 " "Info: 2: + IC(5.543 ns) + CELL(0.178 ns) = 6.595 ns; Loc. = LCCOMB_X36_Y9_N20; Fanout = 1; COMB Node = 'Debouncer:inst3\|button_reg\[0\]~feeder'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.721 ns" { button2 Debouncer:inst3|button_reg[0]~feeder } "NODE_NAME" } } { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 6.691 ns Debouncer:inst3\|button_reg\[0\] 3 REG LCFF_X36_Y9_N21 2 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 6.691 ns; Loc. = LCFF_X36_Y9_N21; Fanout = 2; REG Node = 'Debouncer:inst3\|button_reg\[0\]'" { } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { Debouncer:inst3|button_reg[0]~feeder Debouncer:inst3|button_reg[0] } "NODE_NAME" } } { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.148 ns ( 17.16 % ) " "Info: Total cell delay = 1.148 ns ( 17.16 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.543 ns ( 82.84 % ) " "Info: Total interconnect delay = 5.543 ns ( 82.84 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.691 ns" { button2 Debouncer:inst3|button_reg[0]~feeder Debouncer:inst3|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "6.691 ns" { button2 {} button2~combout {} Debouncer:inst3|button_reg[0]~feeder {} Debouncer:inst3|button_reg[0] {} } { 0.000ns 0.000ns 5.543ns 0.000ns } { 0.000ns 0.874ns 0.178ns 0.096ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.632 ns" { clk_50MHz ClockDivider:inst1|clk25MHz_ ClockDivider:inst1|clk25MHz_~clkctrl Debouncer:inst3|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "6.632 ns" { clk_50MHz {} clk_50MHz~combout {} ClockDivider:inst1|clk25MHz_ {} ClockDivider:inst1|clk25MHz_~clkctrl {} Debouncer:inst3|button_reg[0] {} } { 0.000ns 0.000ns 1.937ns 1.215ns 0.973ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.691 ns" { button2 Debouncer:inst3|button_reg[0]~feeder Debouncer:inst3|button_reg[0] } "NODE_NAME" } } { "c:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/quartus/bin/Technology_Viewer.qrui" "6.691 ns" { button2 {} button2~combout {} Debouncer:inst3|button_reg[0]~feeder {} Debouncer:inst3|button_reg[0] {} } { 0.000ns 0.000ns 5.543ns 0.000ns } { 0.000ns 0.874ns 0.178ns 0.096ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "200 " "Info: Peak virtual memory: 200 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 27 20:49:34 2012 " "Info: Processing ended: Sun May 27 20:49:34 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Info: Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/incremental_db/README b/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used. To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/incremental_db/compiled_partitions/myArkanoid.root_partition.cmp.cdb b/incremental_db/compiled_partitions/myArkanoid.root_partition.cmp.cdb
new file mode 100644
index 0000000..a3c9879
Binary files /dev/null and b/incremental_db/compiled_partitions/myArkanoid.root_partition.cmp.cdb differ
diff --git a/incremental_db/compiled_partitions/myArkanoid.root_partition.cmp.dfp b/incremental_db/compiled_partitions/myArkanoid.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
Binary files /dev/null and b/incremental_db/compiled_partitions/myArkanoid.root_partition.cmp.dfp differ
diff --git a/incremental_db/compiled_partitions/myArkanoid.root_partition.cmp.hdb b/incremental_db/compiled_partitions/myArkanoid.root_partition.cmp.hdb
new file mode 100644
index 0000000..a83e1e6
Binary files /dev/null and b/incremental_db/compiled_partitions/myArkanoid.root_partition.cmp.hdb differ
diff --git a/incremental_db/compiled_partitions/myArkanoid.root_partition.cmp.kpt b/incremental_db/compiled_partitions/myArkanoid.root_partition.cmp.kpt
new file mode 100644
index 0000000..eb12639
Binary files /dev/null and b/incremental_db/compiled_partitions/myArkanoid.root_partition.cmp.kpt differ
diff --git a/incremental_db/compiled_partitions/myArkanoid.root_partition.cmp.logdb b/incremental_db/compiled_partitions/myArkanoid.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/incremental_db/compiled_partitions/myArkanoid.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/incremental_db/compiled_partitions/myArkanoid.root_partition.cmp.rcfdb b/incremental_db/compiled_partitions/myArkanoid.root_partition.cmp.rcfdb
new file mode 100644
index 0000000..91c379a
Binary files /dev/null and b/incremental_db/compiled_partitions/myArkanoid.root_partition.cmp.rcfdb differ
diff --git a/incremental_db/compiled_partitions/myArkanoid.root_partition.cmp.re.rcfdb b/incremental_db/compiled_partitions/myArkanoid.root_partition.cmp.re.rcfdb
new file mode 100644
index 0000000..eb4285c
Binary files /dev/null and b/incremental_db/compiled_partitions/myArkanoid.root_partition.cmp.re.rcfdb differ
diff --git a/incremental_db/compiled_partitions/myArkanoid.root_partition.map.cdb b/incremental_db/compiled_partitions/myArkanoid.root_partition.map.cdb
new file mode 100644
index 0000000..84817ec
Binary files /dev/null and b/incremental_db/compiled_partitions/myArkanoid.root_partition.map.cdb differ
diff --git a/incremental_db/compiled_partitions/myArkanoid.root_partition.map.dpi b/incremental_db/compiled_partitions/myArkanoid.root_partition.map.dpi
new file mode 100644
index 0000000..8f22416
Binary files /dev/null and b/incremental_db/compiled_partitions/myArkanoid.root_partition.map.dpi differ
diff --git a/incremental_db/compiled_partitions/myArkanoid.root_partition.map.hdb b/incremental_db/compiled_partitions/myArkanoid.root_partition.map.hdb
new file mode 100644
index 0000000..747b566
Binary files /dev/null and b/incremental_db/compiled_partitions/myArkanoid.root_partition.map.hdb differ
diff --git a/incremental_db/compiled_partitions/myArkanoid.root_partition.map.kpt b/incremental_db/compiled_partitions/myArkanoid.root_partition.map.kpt
new file mode 100644
index 0000000..df78e2e
Binary files /dev/null and b/incremental_db/compiled_partitions/myArkanoid.root_partition.map.kpt differ
diff --git a/int_to_digital.v b/int_to_digital.v
new file mode 100644
index 0000000..635e5d9
--- /dev/null
+++ b/int_to_digital.v
@@ -0,0 +1,51 @@
+`ifndef _int_to_digital_
+`define _int_to_digital_
+
+ task IntToDigital
+ (
+ input integer n,
+ output [7:0] high,
+ output [7:0] low
+ );
+ integer n1, n0;
+ begin
+ if (n > 99)
+ begin
+ high = 7'b1101111; high = 7'b1101111; // 99 any way
+ end
+ else
+ begin
+ n1 = n / 10;
+ n0 = n % 10;
+
+ case (n1)
+ 0: high = 7'b0111111; // 0x
+ 1: high = 7'b0000110; // 1x
+ 2: high = 7'b1011011; // 2x
+ 3: high = 7'b1001111; // 3x
+ 4: high = 7'b1100110; // 4x
+ 5: high = 7'b1101101; // 5x
+ 6: high = 7'b1111101; // 6x
+ 7: high = 7'b0000111; // 7x
+ 8: high = 7'b1111111; // 8x
+ 9: high = 7'b1101111; // 9x
+ default: high = 7'b0000000;
+ endcase
+ case (n0)
+ 0: low = 7'b0111111; // x0
+ 1: low = 7'b0000110; // x1
+ 2: low = 7'b1011011; // x2
+ 3: low = 7'b1001111; // x3
+ 4: low = 7'b1100110; // x4
+ 5: low = 7'b1101101; // x5
+ 6: low = 7'b1111101; // x6
+ 7: low = 7'b0000111; // x7
+ 8: low = 7'b1111111; // x8
+ 9: low = 7'b1101111; // x9
+ default: low = 7'b0000000;
+ endcase
+ end
+ end
+ endtask
+
+`endif // _int_to_digital_
\ No newline at end of file
diff --git a/myArkanoid.asm.rpt b/myArkanoid.asm.rpt
index f4b3807..d6ffb6c 100644
--- a/myArkanoid.asm.rpt
+++ b/myArkanoid.asm.rpt
@@ -1,5 +1,5 @@
Assembler report for myArkanoid
-Mon May 21 19:54:38 2012
+Mon May 28 14:22:31 2012
Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version
@@ -10,8 +10,8 @@ Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
- 5. Assembler Device Options: C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/myArkanoid.sof
- 6. Assembler Device Options: C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/myArkanoid.pof
+ 5. Assembler Device Options: G:/Verilog/Arkanoid2PDE1/myArkanoid.sof
+ 6. Assembler Device Options: G:/Verilog/Arkanoid2PDE1/myArkanoid.pof
7. Assembler Messages
@@ -38,7 +38,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Mon May 21 19:54:38 2012 ;
+; Assembler Status ; Successful - Mon May 28 14:22:31 2012 ;
; Revision Name ; myArkanoid ;
; Top-level Entity Name ; TotalScheme ;
; Family ; Cyclone II ;
@@ -78,37 +78,37 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+----------+---------------+
-+---------------------------------------------------------------------+
-; Assembler Generated Files ;
-+---------------------------------------------------------------------+
-; File Name ;
-+---------------------------------------------------------------------+
-; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/myArkanoid.sof ;
-; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/myArkanoid.pof ;
-+---------------------------------------------------------------------+
++-----------------------------------------+
+; Assembler Generated Files ;
++-----------------------------------------+
+; File Name ;
++-----------------------------------------+
+; G:/Verilog/Arkanoid2PDE1/myArkanoid.sof ;
+; G:/Verilog/Arkanoid2PDE1/myArkanoid.pof ;
++-----------------------------------------+
-+-----------------------------------------------------------------------------------------------+
-; Assembler Device Options: C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/myArkanoid.sof ;
-+----------------+------------------------------------------------------------------------------+
-; Option ; Setting ;
-+----------------+------------------------------------------------------------------------------+
-; Device ; EP2C20F484C7 ;
-; JTAG usercode ; 0xFFFFFFFF ;
-; Checksum ; 0x002DEAD6 ;
-+----------------+------------------------------------------------------------------------------+
++-------------------------------------------------------------------+
+; Assembler Device Options: G:/Verilog/Arkanoid2PDE1/myArkanoid.sof ;
++----------------+--------------------------------------------------+
+; Option ; Setting ;
++----------------+--------------------------------------------------+
+; Device ; EP2C20F484C7 ;
+; JTAG usercode ; 0xFFFFFFFF ;
+; Checksum ; 0x006B4B07 ;
++----------------+--------------------------------------------------+
-+-----------------------------------------------------------------------------------------------+
-; Assembler Device Options: C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/myArkanoid.pof ;
-+--------------------+--------------------------------------------------------------------------+
-; Option ; Setting ;
-+--------------------+--------------------------------------------------------------------------+
-; Device ; EPCS16 ;
-; JTAG usercode ; 0x00000000 ;
-; Checksum ; 0x1DBBF76B ;
-; Compression Ratio ; 2 ;
-+--------------------+--------------------------------------------------------------------------+
++-------------------------------------------------------------------+
+; Assembler Device Options: G:/Verilog/Arkanoid2PDE1/myArkanoid.pof ;
++--------------------+----------------------------------------------+
+; Option ; Setting ;
++--------------------+----------------------------------------------+
+; Device ; EPCS16 ;
+; JTAG usercode ; 0x00000000 ;
+; Checksum ; 0x1D6A557A ;
+; Compression Ratio ; 2 ;
++--------------------+----------------------------------------------+
+--------------------+
@@ -117,14 +117,14 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 9.1 Build 222 10/21/2009 SJ Full Version
- Info: Processing started: Mon May 21 19:54:35 2012
+ Info: Processing started: Mon May 28 14:22:29 2012
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
- Info: Peak virtual memory: 207 megabytes
- Info: Processing ended: Mon May 21 19:54:38 2012
- Info: Elapsed time: 00:00:03
- Info: Total CPU time (on all processors): 00:00:03
+ Info: Peak virtual memory: 219 megabytes
+ Info: Processing ended: Mon May 28 14:22:31 2012
+ Info: Elapsed time: 00:00:02
+ Info: Total CPU time (on all processors): 00:00:02
diff --git a/myArkanoid.cdf b/myArkanoid.cdf
index 9a9c1e5..9cd6ea0 100644
--- a/myArkanoid.cdf
+++ b/myArkanoid.cdf
@@ -4,7 +4,7 @@ JedecChain;
DefaultMfr(6E);
P ActionCode(Cfg)
- Device PartName(EP2C20F484) Path("C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/") File("myArkanoid.sof") MfrSpec(OpMask(1));
+ Device PartName(EP2C20F484) Path("G:/Verilog/Arkanoid2PDE1/") File("myArkanoid.sof") MfrSpec(OpMask(1));
ChainEnd;
diff --git a/myArkanoid.done b/myArkanoid.done
index 7f10ffb..892c9a0 100644
--- a/myArkanoid.done
+++ b/myArkanoid.done
@@ -1 +1 @@
-Mon May 21 19:54:46 2012
+Mon May 28 14:22:40 2012
diff --git a/myArkanoid.fit.rpt b/myArkanoid.fit.rpt
index 8ef6182..5c5217f 100644
--- a/myArkanoid.fit.rpt
+++ b/myArkanoid.fit.rpt
@@ -1,5 +1,5 @@
Fitter report for myArkanoid
-Mon May 21 19:54:33 2012
+Mon May 28 14:22:25 2012
Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version
@@ -62,17 +62,17 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+------------------------------------------+
-; Fitter Status ; Successful - Mon May 21 19:54:32 2012 ;
+; Fitter Status ; Successful - Mon May 28 14:22:24 2012 ;
; Quartus II Version ; 9.1 Build 222 10/21/2009 SJ Full Version ;
; Revision Name ; myArkanoid ;
; Top-level Entity Name ; TotalScheme ;
; Family ; Cyclone II ;
; Device ; EP2C20F484C7 ;
; Timing Models ; Final ;
-; Total logic elements ; 1,806 / 18,752 ( 10 % ) ;
-; Total combinational functions ; 1,793 / 18,752 ( 10 % ) ;
-; Dedicated logic registers ; 151 / 18,752 ( < 1 % ) ;
-; Total registers ; 151 ;
+; Total logic elements ; 7,148 / 18,752 ( 38 % ) ;
+; Total combinational functions ; 7,096 / 18,752 ( 38 % ) ;
+; Dedicated logic registers ; 1,086 / 18,752 ( 6 % ) ;
+; Total registers ; 1086 ;
; Total pins ; 55 / 315 ( 17 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 239,616 ( 0 % ) ;
@@ -142,12 +142,12 @@ applicable agreement for further details.
; Number detected on machine ; 2 ;
; Maximum allowed ; 2 ;
; ; ;
-; Average used ; 1.17 ;
+; Average used ; 1.20 ;
; Maximum used ; 2 ;
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
-; 2 processors ; 9.1% ;
+; 2 processors ; 11.1% ;
+----------------------------+-------------+
@@ -157,8 +157,8 @@ applicable agreement for further details.
; Type ; Value ;
+-------------------------+---------------------+
; Placement ; ;
-; -- Requested ; 0 / 2004 ( 0.00 % ) ;
-; -- Achieved ; 0 / 2004 ( 0.00 % ) ;
+; -- Requested ; 0 / 8242 ( 0.00 % ) ;
+; -- Achieved ; 0 / 8242 ( 0.00 % ) ;
; ; ;
; Routing (by Connection) ; ;
; -- Requested ; 0 / 0 ( 0.00 % ) ;
@@ -180,64 +180,64 @@ applicable agreement for further details.
+----------------+---------+-------------------+-------------------------+-------------------+
; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
+----------------+---------+-------------------+-------------------------+-------------------+
-; Top ; 2004 ; 0 ; N/A ; Source File ;
+; Top ; 8242 ; 0 ; N/A ; Source File ;
+----------------+---------+-------------------+-------------------------+-------------------+
+--------------+
; Pin-Out File ;
+--------------+
-The pin-out file can be found in C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/myArkanoid.pin.
+The pin-out file can be found in G:/Verilog/Arkanoid2PDE1/myArkanoid.pin.
-+-------------------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+---------------------------------+
-; Resource ; Usage ;
-+---------------------------------------------+---------------------------------+
-; Total logic elements ; 1,806 / 18,752 ( 10 % ) ;
-; -- Combinational with no register ; 1655 ;
-; -- Register only ; 13 ;
-; -- Combinational with a register ; 138 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 561 ;
-; -- 3 input functions ; 452 ;
-; -- <=2 input functions ; 780 ;
-; -- Register only ; 13 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 1147 ;
-; -- arithmetic mode ; 646 ;
-; ; ;
-; Total registers* ; 151 / 19,649 ( < 1 % ) ;
-; -- Dedicated logic registers ; 151 / 18,752 ( < 1 % ) ;
-; -- I/O registers ; 0 / 897 ( 0 % ) ;
-; ; ;
-; Total LABs: partially or completely used ; 135 / 1,172 ( 12 % ) ;
-; User inserted logic elements ; 0 ;
-; Virtual pins ; 0 ;
-; I/O pins ; 55 / 315 ( 17 % ) ;
-; -- Clock pins ; 1 / 8 ( 13 % ) ;
-; Global signals ; 1 ;
-; M4Ks ; 0 / 52 ( 0 % ) ;
-; Total block memory bits ; 0 / 239,616 ( 0 % ) ;
-; Total block memory implementation bits ; 0 / 239,616 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ;
-; PLLs ; 0 / 4 ( 0 % ) ;
-; Global clocks ; 1 / 16 ( 6 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; ASMI blocks ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 2% / 2% / 2% ;
-; Peak interconnect usage (total/H/V) ; 10% / 9% / 11% ;
-; Maximum fan-out node ; Arkanoid:inst|clk25MHz_~clkctrl ;
-; Maximum fan-out ; 150 ;
-; Highest non-global fan-out signal ; Arkanoid:inst|Add8~60 ;
-; Highest non-global fan-out ; 36 ;
-; Total fan-out ; 5404 ;
-; Average fan-out ; 2.69 ;
-+---------------------------------------------+---------------------------------+
++-------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++---------------------------------------------+---------------------------------------------------------------------------------------------------+
+; Resource ; Usage ;
++---------------------------------------------+---------------------------------------------------------------------------------------------------+
+; Total logic elements ; 7,148 / 18,752 ( 38 % ) ;
+; -- Combinational with no register ; 6062 ;
+; -- Register only ; 52 ;
+; -- Combinational with a register ; 1034 ;
+; ; ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 2860 ;
+; -- 3 input functions ; 2246 ;
+; -- <=2 input functions ; 1990 ;
+; -- Register only ; 52 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 5409 ;
+; -- arithmetic mode ; 1687 ;
+; ; ;
+; Total registers* ; 1,086 / 19,649 ( 6 % ) ;
+; -- Dedicated logic registers ; 1,086 / 18,752 ( 6 % ) ;
+; -- I/O registers ; 0 / 897 ( 0 % ) ;
+; ; ;
+; Total LABs: partially or completely used ; 521 / 1,172 ( 44 % ) ;
+; User inserted logic elements ; 0 ;
+; Virtual pins ; 0 ;
+; I/O pins ; 55 / 315 ( 17 % ) ;
+; -- Clock pins ; 1 / 8 ( 13 % ) ;
+; Global signals ; 1 ;
+; M4Ks ; 0 / 52 ( 0 % ) ;
+; Total block memory bits ; 0 / 239,616 ( 0 % ) ;
+; Total block memory implementation bits ; 0 / 239,616 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ;
+; PLLs ; 0 / 4 ( 0 % ) ;
+; Global clocks ; 1 / 16 ( 6 % ) ;
+; JTAGs ; 0 / 1 ( 0 % ) ;
+; ASMI blocks ; 0 / 1 ( 0 % ) ;
+; CRC blocks ; 0 / 1 ( 0 % ) ;
+; Average interconnect usage (total/H/V) ; 15% / 15% / 16% ;
+; Peak interconnect usage (total/H/V) ; 31% / 31% / 31% ;
+; Maximum fan-out node ; ClockDivider:inst1|clk25MHz_~clkctrl ;
+; Maximum fan-out ; 1085 ;
+; Highest non-global fan-out signal ; Arkanoid:inst|lpm_divide:Div2|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|quotient[1]~0 ;
+; Highest non-global fan-out ; 197 ;
+; Total fan-out ; 24145 ;
+; Average fan-out ; 2.92 ;
++---------------------------------------------+---------------------------------------------------------------------------------------------------+
* Register count does not include registers inside RAM blocks or DSP blocks.
@@ -247,10 +247,10 @@ The pin-out file can be found in C:/Users/ProGOLD/Desktop/
+-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
-; button1 ; T21 ; 6 ; 50 ; 9 ; 1 ; 5 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
-; button2 ; T22 ; 6 ; 50 ; 9 ; 0 ; 36 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
-; button3 ; R21 ; 6 ; 50 ; 10 ; 2 ; 5 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
-; button4 ; R22 ; 6 ; 50 ; 10 ; 1 ; 36 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; button1 ; T21 ; 6 ; 50 ; 9 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; button2 ; T22 ; 6 ; 50 ; 9 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; button3 ; R21 ; 6 ; 50 ; 10 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; button4 ; R22 ; 6 ; 50 ; 10 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
; clk_50MHz ; L1 ; 2 ; 0 ; 13 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
@@ -269,34 +269,34 @@ The pin-out file can be found in C:/Users/ProGOLD/Desktop/
; green[2] ; B9 ; 3 ; 15 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
; green[3] ; A8 ; 3 ; 13 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
; h_sync ; A11 ; 3 ; 22 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led1[0] ; J2 ; 2 ; 0 ; 18 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led1[1] ; J1 ; 2 ; 0 ; 18 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led1[2] ; H2 ; 2 ; 0 ; 19 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led1[3] ; H1 ; 2 ; 0 ; 19 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led1[4] ; F2 ; 2 ; 0 ; 20 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led1[5] ; F1 ; 2 ; 0 ; 20 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led1[6] ; E2 ; 2 ; 0 ; 20 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led2[0] ; E1 ; 2 ; 0 ; 20 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led2[1] ; H6 ; 2 ; 0 ; 21 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led2[2] ; H5 ; 2 ; 0 ; 21 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led2[3] ; H4 ; 2 ; 0 ; 21 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led2[4] ; G3 ; 2 ; 0 ; 21 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led2[5] ; D2 ; 2 ; 0 ; 22 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led2[6] ; D1 ; 2 ; 0 ; 22 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led3[0] ; G5 ; 2 ; 0 ; 22 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led3[1] ; G6 ; 2 ; 0 ; 23 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led3[2] ; C2 ; 2 ; 0 ; 23 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led3[3] ; C1 ; 2 ; 0 ; 23 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led3[4] ; E3 ; 2 ; 0 ; 24 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led3[5] ; E4 ; 2 ; 0 ; 24 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led3[6] ; D3 ; 2 ; 0 ; 25 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led4[0] ; F4 ; 2 ; 0 ; 23 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led4[1] ; D5 ; 2 ; 0 ; 24 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led4[2] ; D6 ; 2 ; 0 ; 24 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led4[3] ; J4 ; 2 ; 0 ; 18 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led4[4] ; L8 ; 2 ; 0 ; 19 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led4[5] ; F3 ; 2 ; 0 ; 22 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
-; led4[6] ; D4 ; 2 ; 0 ; 25 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex0[0] ; J2 ; 2 ; 0 ; 18 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex0[1] ; J1 ; 2 ; 0 ; 18 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex0[2] ; H2 ; 2 ; 0 ; 19 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex0[3] ; H1 ; 2 ; 0 ; 19 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex0[4] ; F2 ; 2 ; 0 ; 20 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex0[5] ; F1 ; 2 ; 0 ; 20 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex0[6] ; E2 ; 2 ; 0 ; 20 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex1[0] ; E1 ; 2 ; 0 ; 20 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex1[1] ; H6 ; 2 ; 0 ; 21 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex1[2] ; H5 ; 2 ; 0 ; 21 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex1[3] ; H4 ; 2 ; 0 ; 21 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex1[4] ; G3 ; 2 ; 0 ; 21 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex1[5] ; D2 ; 2 ; 0 ; 22 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex1[6] ; D1 ; 2 ; 0 ; 22 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex2[0] ; G5 ; 2 ; 0 ; 22 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex2[1] ; G6 ; 2 ; 0 ; 23 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex2[2] ; C2 ; 2 ; 0 ; 23 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex2[3] ; C1 ; 2 ; 0 ; 23 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex2[4] ; E3 ; 2 ; 0 ; 24 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex2[5] ; E4 ; 2 ; 0 ; 24 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex2[6] ; D3 ; 2 ; 0 ; 25 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex3[0] ; F4 ; 2 ; 0 ; 23 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex3[1] ; D5 ; 2 ; 0 ; 24 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex3[2] ; D6 ; 2 ; 0 ; 24 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex3[3] ; J4 ; 2 ; 0 ; 18 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex3[4] ; L8 ; 2 ; 0 ; 19 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex3[5] ; F3 ; 2 ; 0 ; 22 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
+; hex3[6] ; D4 ; 2 ; 0 ; 25 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
; led[0] ; U22 ; 6 ; 50 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
; led[1] ; U21 ; 6 ; 50 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
; led[2] ; V22 ; 6 ; 50 ; 7 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ;
@@ -422,8 +422,8 @@ The pin-out file can be found in C:/Users/ProGOLD/Desktop/
; B20 ; 246 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; B21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; B22 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; C1 ; 8 ; 2 ; led3[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; C2 ; 9 ; 2 ; led3[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; C1 ; 8 ; 2 ; hex2[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; C2 ; 9 ; 2 ; hex2[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; C3 ; 1 ; 2 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
; C4 ; 0 ; 2 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
@@ -444,12 +444,12 @@ The pin-out file can be found in C:/Users/ProGOLD/Desktop/
; C20 ; 239 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; C21 ; 236 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; C22 ; 237 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; D1 ; 14 ; 2 ; led2[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; D2 ; 15 ; 2 ; led2[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; D3 ; 2 ; 2 ; led3[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; D4 ; 3 ; 2 ; led4[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; D5 ; 4 ; 2 ; led4[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; D6 ; 5 ; 2 ; led4[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; D1 ; 14 ; 2 ; hex1[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; D2 ; 15 ; 2 ; hex1[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; D3 ; 2 ; 2 ; hex2[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; D4 ; 3 ; 2 ; hex3[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; D5 ; 4 ; 2 ; hex3[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; D6 ; 5 ; 2 ; hex3[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; D7 ; 311 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; D8 ; 309 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; D9 ; 302 ; 3 ; red[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
@@ -466,10 +466,10 @@ The pin-out file can be found in C:/Users/ProGOLD/Desktop/
; D20 ; 241 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; D21 ; 229 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; D22 ; 230 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; E1 ; 20 ; 2 ; led2[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; E2 ; 21 ; 2 ; led1[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; E3 ; 6 ; 2 ; led3[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; E4 ; 7 ; 2 ; led3[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; E1 ; 20 ; 2 ; hex1[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; E2 ; 21 ; 2 ; hex0[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; E3 ; 6 ; 2 ; hex2[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; E4 ; 7 ; 2 ; hex2[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; E5 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; E6 ; ; ; VCCA_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; E7 ; 316 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
@@ -488,10 +488,10 @@ The pin-out file can be found in C:/Users/ProGOLD/Desktop/
; E20 ; 234 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; E21 ; 227 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; E22 ; 228 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; F1 ; 22 ; 2 ; led1[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; F2 ; 23 ; 2 ; led1[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; F3 ; 13 ; 2 ; led4[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; F4 ; 10 ; 2 ; led4[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; F1 ; 22 ; 2 ; hex0[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; F2 ; 23 ; 2 ; hex0[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; F3 ; 13 ; 2 ; hex3[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; F4 ; 10 ; 2 ; hex3[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; F5 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ;
; F6 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ;
; F7 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ;
@@ -512,10 +512,10 @@ The pin-out file can be found in C:/Users/ProGOLD/Desktop/
; F22 ; 224 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; G1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
; G2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
-; G3 ; 16 ; 2 ; led2[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; G3 ; 16 ; 2 ; hex1[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; G5 ; 12 ; 2 ; led3[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; G6 ; 11 ; 2 ; led3[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; G5 ; 12 ; 2 ; hex2[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; G6 ; 11 ; 2 ; hex2[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; G7 ; 317 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; G8 ; 313 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; G9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
@@ -532,12 +532,12 @@ The pin-out file can be found in C:/Users/ProGOLD/Desktop/
; G20 ; 233 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; G21 ; 221 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; G22 ; 222 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; H1 ; 24 ; 2 ; led1[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; H2 ; 25 ; 2 ; led1[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; H1 ; 24 ; 2 ; hex0[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; H2 ; 25 ; 2 ; hex0[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; H3 ; 27 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; H4 ; 17 ; 2 ; led2[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; H5 ; 18 ; 2 ; led2[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; H6 ; 19 ; 2 ; led2[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; H4 ; 17 ; 2 ; hex1[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; H5 ; 18 ; 2 ; hex1[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; H6 ; 19 ; 2 ; hex1[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; H7 ; 318 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; H8 ; 314 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; H9 ; 300 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
@@ -554,10 +554,10 @@ The pin-out file can be found in C:/Users/ProGOLD/Desktop/
; H20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; H21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
; H22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
-; J1 ; 29 ; 2 ; led1[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; J2 ; 30 ; 2 ; led1[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; J1 ; 29 ; 2 ; hex0[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; J2 ; 30 ; 2 ; hex0[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; J3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
-; J4 ; 28 ; 2 ; led4[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; J4 ; 28 ; 2 ; hex3[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; J5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
; J6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
; J7 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
@@ -605,7 +605,7 @@ The pin-out file can be found in C:/Users/ProGOLD/Desktop/
; L5 ; 34 ; 2 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
; L6 ; 35 ; 2 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ;
; L7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
-; L8 ; 26 ; 2 ; led4[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; L8 ; 26 ; 2 ; hex3[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
@@ -864,18 +864,43 @@ Note: User assignments will override these defaults. The user specified values a
+------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
+------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------+--------------+
-; |TotalScheme ; 1806 (0) ; 151 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 55 ; 0 ; 1655 (0) ; 13 (0) ; 138 (0) ; |TotalScheme ; work ;
-; |Arkanoid:inst| ; 1806 (779) ; 151 (151) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1655 (628) ; 13 (13) ; 138 (137) ; |TotalScheme|Arkanoid:inst ; ;
-; |lpm_divide:Div0| ; 475 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 475 (0) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0 ; ;
-; |lpm_divide_8so:auto_generated| ; 475 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 475 (0) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated ; ;
-; |abs_divider_lbg:divider| ; 475 (10) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 475 (10) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider ; ;
-; |alt_u_div_m2f:divider| ; 433 (433) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 433 (433) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider ; ;
-; |lpm_abs_0s9:my_abs_num| ; 32 (32) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (32) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num ; ;
-; |lpm_divide:Div1| ; 553 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 552 (0) ; 0 (0) ; 1 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1 ; ;
-; |lpm_divide_8so:auto_generated| ; 553 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 552 (0) ; 0 (0) ; 1 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated ; ;
-; |abs_divider_lbg:divider| ; 553 (10) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 552 (10) ; 0 (0) ; 1 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider ; ;
-; |alt_u_div_m2f:divider| ; 511 (511) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 511 (511) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider ; ;
-; |lpm_abs_0s9:my_abs_num| ; 32 (32) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 (31) ; 0 (0) ; 1 (1) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num ; ;
+; |TotalScheme ; 7148 (0) ; 1086 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 55 ; 0 ; 6062 (0) ; 52 (0) ; 1034 (0) ; |TotalScheme ; work ;
+; |Arkanoid:inst| ; 7110 (3971) ; 1049 (1049) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6059 (2920) ; 31 (31) ; 1020 (1020) ; |TotalScheme|Arkanoid:inst ; ;
+; |lpm_divide:Div0| ; 515 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 515 (0) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0 ; ;
+; |lpm_divide_7so:auto_generated| ; 515 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 515 (0) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated ; ;
+; |abs_divider_kbg:divider| ; 515 (35) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 515 (35) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider ; ;
+; |alt_u_div_k2f:divider| ; 449 (449) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 449 (449) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider ; ;
+; |lpm_abs_0s9:my_abs_num| ; 31 (31) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 (31) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num ; ;
+; |lpm_divide:Div1| ; 515 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 515 (0) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1 ; ;
+; |lpm_divide_7so:auto_generated| ; 515 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 515 (0) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_7so:auto_generated ; ;
+; |abs_divider_kbg:divider| ; 515 (35) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 515 (35) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_7so:auto_generated|abs_divider_kbg:divider ; ;
+; |alt_u_div_k2f:divider| ; 449 (449) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 449 (449) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider ; ;
+; |lpm_abs_0s9:my_abs_num| ; 31 (31) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 (31) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num ; ;
+; |lpm_divide:Div2| ; 553 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 553 (0) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div2 ; ;
+; |lpm_divide_8so:auto_generated| ; 553 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 553 (0) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div2|lpm_divide_8so:auto_generated ; ;
+; |abs_divider_lbg:divider| ; 553 (10) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 553 (10) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div2|lpm_divide_8so:auto_generated|abs_divider_lbg:divider ; ;
+; |alt_u_div_m2f:divider| ; 511 (511) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 511 (511) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div2|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider ; ;
+; |lpm_abs_0s9:my_abs_num| ; 32 (32) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (32) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div2|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num ; ;
+; |lpm_divide:Div3| ; 553 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 553 (0) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div3 ; ;
+; |lpm_divide_8so:auto_generated| ; 553 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 553 (0) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div3|lpm_divide_8so:auto_generated ; ;
+; |abs_divider_lbg:divider| ; 553 (10) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 553 (10) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div3|lpm_divide_8so:auto_generated|abs_divider_lbg:divider ; ;
+; |alt_u_div_m2f:divider| ; 511 (511) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 511 (511) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div3|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider ; ;
+; |lpm_abs_0s9:my_abs_num| ; 32 (32) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (32) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div3|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num ; ;
+; |lpm_divide:Mod0| ; 502 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 502 (0) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Mod0 ; ;
+; |lpm_divide_ako:auto_generated| ; 502 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 502 (0) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Mod0|lpm_divide_ako:auto_generated ; ;
+; |abs_divider_kbg:divider| ; 502 (10) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 502 (10) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Mod0|lpm_divide_ako:auto_generated|abs_divider_kbg:divider ; ;
+; |alt_u_div_k2f:divider| ; 459 (459) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 459 (459) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Mod0|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider ; ;
+; |lpm_abs_0s9:my_abs_num| ; 33 (33) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 33 (33) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Mod0|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num ; ;
+; |lpm_divide:Mod1| ; 501 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 501 (0) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Mod1 ; ;
+; |lpm_divide_ako:auto_generated| ; 501 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 501 (0) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated ; ;
+; |abs_divider_kbg:divider| ; 501 (9) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 501 (9) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider ; ;
+; |alt_u_div_k2f:divider| ; 459 (459) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 459 (459) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider ; ;
+; |lpm_abs_0s9:my_abs_num| ; 33 (33) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 33 (33) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num ; ;
+; |ClockDivider:inst1| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |TotalScheme|ClockDivider:inst1 ; ;
+; |Debouncer:inst2| ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 5 (5) ; 4 (4) ; |TotalScheme|Debouncer:inst2 ; ;
+; |Debouncer:inst3| ; 10 (10) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 6 (6) ; 3 (3) ; |TotalScheme|Debouncer:inst3 ; ;
+; |Debouncer:inst4| ; 10 (10) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 5 (5) ; 4 (4) ; |TotalScheme|Debouncer:inst4 ; ;
+; |Debouncer:inst5| ; 10 (10) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 5 (5) ; 4 (4) ; |TotalScheme|Debouncer:inst5 ; ;
+------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@@ -895,6 +920,34 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; green[2] ; Output ; -- ; -- ; -- ; -- ;
; green[1] ; Output ; -- ; -- ; -- ; -- ;
; green[0] ; Output ; -- ; -- ; -- ; -- ;
+; hex0[6] ; Output ; -- ; -- ; -- ; -- ;
+; hex0[5] ; Output ; -- ; -- ; -- ; -- ;
+; hex0[4] ; Output ; -- ; -- ; -- ; -- ;
+; hex0[3] ; Output ; -- ; -- ; -- ; -- ;
+; hex0[2] ; Output ; -- ; -- ; -- ; -- ;
+; hex0[1] ; Output ; -- ; -- ; -- ; -- ;
+; hex0[0] ; Output ; -- ; -- ; -- ; -- ;
+; hex1[6] ; Output ; -- ; -- ; -- ; -- ;
+; hex1[5] ; Output ; -- ; -- ; -- ; -- ;
+; hex1[4] ; Output ; -- ; -- ; -- ; -- ;
+; hex1[3] ; Output ; -- ; -- ; -- ; -- ;
+; hex1[2] ; Output ; -- ; -- ; -- ; -- ;
+; hex1[1] ; Output ; -- ; -- ; -- ; -- ;
+; hex1[0] ; Output ; -- ; -- ; -- ; -- ;
+; hex2[6] ; Output ; -- ; -- ; -- ; -- ;
+; hex2[5] ; Output ; -- ; -- ; -- ; -- ;
+; hex2[4] ; Output ; -- ; -- ; -- ; -- ;
+; hex2[3] ; Output ; -- ; -- ; -- ; -- ;
+; hex2[2] ; Output ; -- ; -- ; -- ; -- ;
+; hex2[1] ; Output ; -- ; -- ; -- ; -- ;
+; hex2[0] ; Output ; -- ; -- ; -- ; -- ;
+; hex3[6] ; Output ; -- ; -- ; -- ; -- ;
+; hex3[5] ; Output ; -- ; -- ; -- ; -- ;
+; hex3[4] ; Output ; -- ; -- ; -- ; -- ;
+; hex3[3] ; Output ; -- ; -- ; -- ; -- ;
+; hex3[2] ; Output ; -- ; -- ; -- ; -- ;
+; hex3[1] ; Output ; -- ; -- ; -- ; -- ;
+; hex3[0] ; Output ; -- ; -- ; -- ; -- ;
; led[7] ; Output ; -- ; -- ; -- ; -- ;
; led[6] ; Output ; -- ; -- ; -- ; -- ;
; led[5] ; Output ; -- ; -- ; -- ; -- ;
@@ -903,392 +956,289 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; led[2] ; Output ; -- ; -- ; -- ; -- ;
; led[1] ; Output ; -- ; -- ; -- ; -- ;
; led[0] ; Output ; -- ; -- ; -- ; -- ;
-; led1[6] ; Output ; -- ; -- ; -- ; -- ;
-; led1[5] ; Output ; -- ; -- ; -- ; -- ;
-; led1[4] ; Output ; -- ; -- ; -- ; -- ;
-; led1[3] ; Output ; -- ; -- ; -- ; -- ;
-; led1[2] ; Output ; -- ; -- ; -- ; -- ;
-; led1[1] ; Output ; -- ; -- ; -- ; -- ;
-; led1[0] ; Output ; -- ; -- ; -- ; -- ;
-; led2[6] ; Output ; -- ; -- ; -- ; -- ;
-; led2[5] ; Output ; -- ; -- ; -- ; -- ;
-; led2[4] ; Output ; -- ; -- ; -- ; -- ;
-; led2[3] ; Output ; -- ; -- ; -- ; -- ;
-; led2[2] ; Output ; -- ; -- ; -- ; -- ;
-; led2[1] ; Output ; -- ; -- ; -- ; -- ;
-; led2[0] ; Output ; -- ; -- ; -- ; -- ;
-; led3[6] ; Output ; -- ; -- ; -- ; -- ;
-; led3[5] ; Output ; -- ; -- ; -- ; -- ;
-; led3[4] ; Output ; -- ; -- ; -- ; -- ;
-; led3[3] ; Output ; -- ; -- ; -- ; -- ;
-; led3[2] ; Output ; -- ; -- ; -- ; -- ;
-; led3[1] ; Output ; -- ; -- ; -- ; -- ;
-; led3[0] ; Output ; -- ; -- ; -- ; -- ;
-; led4[6] ; Output ; -- ; -- ; -- ; -- ;
-; led4[5] ; Output ; -- ; -- ; -- ; -- ;
-; led4[4] ; Output ; -- ; -- ; -- ; -- ;
-; led4[3] ; Output ; -- ; -- ; -- ; -- ;
-; led4[2] ; Output ; -- ; -- ; -- ; -- ;
-; led4[1] ; Output ; -- ; -- ; -- ; -- ;
-; led4[0] ; Output ; -- ; -- ; -- ; -- ;
; red[3] ; Output ; -- ; -- ; -- ; -- ;
; red[2] ; Output ; -- ; -- ; -- ; -- ;
; red[1] ; Output ; -- ; -- ; -- ; -- ;
; red[0] ; Output ; -- ; -- ; -- ; -- ;
-; button3 ; Input ; (6) 4358 ps ; (6) 4358 ps ; -- ; -- ;
-; button4 ; Input ; (6) 4358 ps ; (6) 4358 ps ; -- ; -- ;
+; clk_50MHz ; Input ; (0) 325 ps ; (0) 325 ps ; -- ; -- ;
; button1 ; Input ; (6) 4358 ps ; (6) 4358 ps ; -- ; -- ;
; button2 ; Input ; (6) 4358 ps ; (6) 4358 ps ; -- ; -- ;
-; clk_50MHz ; Input ; (0) 325 ps ; (0) 325 ps ; -- ; -- ;
+; button3 ; Input ; (6) 4358 ps ; (6) 4358 ps ; -- ; -- ;
+; button4 ; Input ; (6) 4358 ps ; (6) 4358 ps ; -- ; -- ;
+-----------+----------+---------------+---------------+-----------------------+-----+
-+-------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+-------------------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+-------------------------------------------+-------------------+---------+
-; button3 ; ; ;
-; - Arkanoid:inst|button3_state ; 0 ; 6 ;
-; - Arkanoid:inst|platform2_position~0 ; 0 ; 6 ;
-; - Arkanoid:inst|always3~95 ; 0 ; 6 ;
-; - Arkanoid:inst|led_[2]~feeder ; 0 ; 6 ;
-; - Arkanoid:inst|led_[3]~feeder ; 0 ; 6 ;
-; button4 ; ; ;
-; - Arkanoid:inst|led_[0] ; 1 ; 6 ;
-; - Arkanoid:inst|led_[1] ; 1 ; 6 ;
-; - Arkanoid:inst|button4_state ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~20 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~21 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~22 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~25 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~28 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~31 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~34 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~37 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~40 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~43 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~46 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~49 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~52 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~55 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~58 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~61 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~64 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~67 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~86 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~87 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~88 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~89 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~90 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~91 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~92 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~93 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~94 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~97 ; 1 ; 6 ;
-; - Arkanoid:inst|always3~3 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~100 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~101 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~102 ; 1 ; 6 ;
-; - Arkanoid:inst|Add5~103 ; 1 ; 6 ;
-; button1 ; ; ;
-; - Arkanoid:inst|button1_state ; 1 ; 6 ;
-; - Arkanoid:inst|led_[6] ; 1 ; 6 ;
-; - Arkanoid:inst|led_[7] ; 1 ; 6 ;
-; - Arkanoid:inst|platform1_position~0 ; 1 ; 6 ;
-; - Arkanoid:inst|always3~94 ; 1 ; 6 ;
-; button2 ; ; ;
-; - Arkanoid:inst|led_[4] ; 0 ; 6 ;
-; - Arkanoid:inst|led_[5] ; 0 ; 6 ;
-; - Arkanoid:inst|button2_state ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~70 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~71 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~72 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~73 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~74 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~75 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~76 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~77 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~78 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~79 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~80 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~81 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~82 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~83 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~84 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~85 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~86 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~87 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~88 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~89 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~90 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~91 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~92 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~93 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~94 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~95 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~96 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~97 ; 0 ; 6 ;
-; - Arkanoid:inst|always3~51 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~100 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~101 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~102 ; 0 ; 6 ;
-; - Arkanoid:inst|Add3~103 ; 0 ; 6 ;
-; clk_50MHz ; ; ;
-+-------------------------------------------+-------------------+---------+
++--------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++--------------------------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++--------------------------------------+-------------------+---------+
+; clk_50MHz ; ; ;
+; button1 ; ; ;
+; - Debouncer:inst2|button_reg[0] ; 0 ; 6 ;
+; button2 ; ; ;
+; - Debouncer:inst3|button_reg[0] ; 0 ; 6 ;
+; button3 ; ; ;
+; - Debouncer:inst4|button_reg[0] ; 0 ; 6 ;
+; button4 ; ; ;
+; - Debouncer:inst5|button_reg[0] ; 1 ; 6 ;
++--------------------------------------+-------------------+---------+
-+-------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals ;
-+--------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
-; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+--------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
-; Arkanoid:inst|Equal1~10 ; LCCOMB_X18_Y11_N6 ; 32 ; Sync. clear ; no ; -- ; -- ; -- ;
-; Arkanoid:inst|always3~3 ; LCCOMB_X34_Y17_N26 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
-; Arkanoid:inst|always3~51 ; LCCOMB_X29_Y13_N22 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
-; Arkanoid:inst|always3~94 ; LCCOMB_X34_Y12_N14 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
-; Arkanoid:inst|always3~95 ; LCCOMB_X34_Y21_N14 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
-; Arkanoid:inst|clk25MHz_ ; LCFF_X1_Y13_N29 ; 150 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ;
-; clk_50MHz ; PIN_L1 ; 1 ; Clock ; no ; -- ; -- ; -- ;
-+--------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals ;
++------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+
+; Arkanoid:inst|Equal1~10 ; LCCOMB_X21_Y13_N0 ; 32 ; Sync. clear ; no ; -- ; -- ; -- ;
+; Arkanoid:inst|LessThan132~10 ; LCCOMB_X32_Y19_N22 ; 36 ; Sync. clear ; no ; -- ; -- ; -- ;
+; Arkanoid:inst|always2~10 ; LCCOMB_X32_Y11_N6 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
+; Arkanoid:inst|always2~11 ; LCCOMB_X32_Y10_N30 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
+; Arkanoid:inst|always2~12 ; LCCOMB_X31_Y13_N18 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
+; Arkanoid:inst|always2~9 ; LCCOMB_X33_Y13_N30 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
+; Arkanoid:inst|game_state~4 ; LCCOMB_X31_Y13_N4 ; 37 ; Clock enable, Sync. clear ; no ; -- ; -- ; -- ;
+; ClockDivider:inst1|clk25MHz_ ; LCFF_X1_Y13_N29 ; 1085 ; Clock ; yes ; Global Clock ; GCLK0 ; -- ;
+; clk_50MHz ; PIN_L1 ; 1 ; Clock ; no ; -- ; -- ; -- ;
++------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+
-+---------------------------------------------------------------------------------------------------------------------------+
-; Global & Other Fast Signals ;
-+-------------------------+-----------------+---------+----------------------+------------------+---------------------------+
-; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+-------------------------+-----------------+---------+----------------------+------------------+---------------------------+
-; Arkanoid:inst|clk25MHz_ ; LCFF_X1_Y13_N29 ; 150 ; Global Clock ; GCLK2 ; -- ;
-+-------------------------+-----------------+---------+----------------------+------------------+---------------------------+
++--------------------------------------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals ;
++------------------------------+-----------------+---------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++------------------------------+-----------------+---------+----------------------+------------------+---------------------------+
+; ClockDivider:inst1|clk25MHz_ ; LCFF_X1_Y13_N29 ; 1085 ; Global Clock ; GCLK0 ; -- ;
++------------------------------+-----------------+---------+----------------------+------------------+---------------------------+
-+-------------------------------------------------------------------------------------------------------------------------------------------------+
-; Non-Global High Fan-Out Signals ;
-+---------------------------------------------------------------------------------------------------------------------------------------+---------+
-; Name ; Fan-Out ;
-+---------------------------------------------------------------------------------------------------------------------------------------+---------+
-; button2 ; 36 ;
-; button4 ; 36 ;
-; Arkanoid:inst|Add9~60 ; 36 ;
-; Arkanoid:inst|Add8~60 ; 36 ;
-; Arkanoid:inst|Add5~103 ; 34 ;
-; Arkanoid:inst|Add3~102 ; 33 ;
-; Arkanoid:inst|Add3~101 ; 33 ;
-; Arkanoid:inst|button2_state ; 33 ;
-; Arkanoid:inst|button4_state ; 33 ;
-; Arkanoid:inst|platform1_position~0 ; 32 ;
-; Arkanoid:inst|platform2_position~0 ; 32 ;
-; Arkanoid:inst|Equal1~10 ; 32 ;
-; Arkanoid:inst|Add6~56 ; 32 ;
-; Arkanoid:inst|Add7~56 ; 31 ;
-; Arkanoid:inst|Add7~0 ; 30 ;
-; Arkanoid:inst|Add6~0 ; 29 ;
-; Arkanoid:inst|Add3~100 ; 26 ;
-; Arkanoid:inst|Add5~102 ; 25 ;
-; Arkanoid:inst|Add3~97 ; 23 ;
-; Arkanoid:inst|Add5~22 ; 20 ;
-; Arkanoid:inst|Add3~96 ; 19 ;
-; Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|quotient[0]~4 ; 19 ;
-; Arkanoid:inst|Add5~100 ; 18 ;
-; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[7]~10 ; 18 ;
-; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_28_result_int[7]~10 ; 18 ;
-; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[7]~10 ; 18 ;
-; Arkanoid:inst|Add5~21 ; 17 ;
-; Arkanoid:inst|LessThan31~9 ; 16 ;
-; Arkanoid:inst|LessThan29~10 ; 16 ;
-; Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|quotient[1]~3 ; 16 ;
-; Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|quotient[2]~2 ; 16 ;
-; Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|quotient[3]~1 ; 16 ;
-; Arkanoid:inst|Add7~2 ; 16 ;
-; Arkanoid:inst|Add6~2 ; 16 ;
-; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_26_result_int[7]~10 ; 16 ;
-; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[7]~10 ; 16 ;
-; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_24_result_int[7]~10 ; 16 ;
-; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[7]~10 ; 16 ;
-; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_22_result_int[7]~10 ; 16 ;
-; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[7]~10 ; 16 ;
-; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[7]~10 ; 16 ;
-; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_19_result_int[7]~10 ; 16 ;
-; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_18_result_int[7]~10 ; 16 ;
-; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[7]~10 ; 16 ;
-; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[7]~10 ; 16 ;
-; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[7]~10 ; 16 ;
-; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[7]~10 ; 16 ;
-; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_13_result_int[7]~10 ; 16 ;
-; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_12_result_int[7]~10 ; 16 ;
-; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_11_result_int[7]~10 ; 16 ;
-+---------------------------------------------------------------------------------------------------------------------------------------+---------+
++-------------------------------------------------------------------------------------------------------------+
+; Non-Global High Fan-Out Signals ;
++---------------------------------------------------------------------------------------------------+---------+
+; Name ; Fan-Out ;
++---------------------------------------------------------------------------------------------------+---------+
+; Arkanoid:inst|lpm_divide:Div2|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|quotient[3]~3 ; 197 ;
+; Arkanoid:inst|lpm_divide:Div2|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|quotient[2]~2 ; 197 ;
+; Arkanoid:inst|lpm_divide:Div2|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|quotient[0]~1 ; 197 ;
+; Arkanoid:inst|lpm_divide:Div2|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|quotient[1]~0 ; 197 ;
+; Arkanoid:inst|ball_direction~17 ; 142 ;
+; Arkanoid:inst|Decoder3~1 ; 131 ;
+; Arkanoid:inst|Decoder2~12 ; 129 ;
+; Arkanoid:inst|Decoder3~33 ; 124 ;
+; Arkanoid:inst|Decoder2~13 ; 122 ;
+; Arkanoid:inst|game_state ; 110 ;
+; Arkanoid:inst|Decoder2~8 ; 100 ;
+; Arkanoid:inst|field~885 ; 96 ;
+; Arkanoid:inst|field~1017 ; 94 ;
+; Arkanoid:inst|Add14~65 ; 93 ;
+; Arkanoid:inst|field~819 ; 92 ;
+; Arkanoid:inst|Add9~65 ; 89 ;
+; Arkanoid:inst|Selector37~3 ; 83 ;
+; Arkanoid:inst|platform1_position~61 ; 79 ;
+; Arkanoid:inst|platform2_position~4 ; 73 ;
+; Arkanoid:inst|Decoder2~11 ; 72 ;
+; Arkanoid:inst|platform1_position~60 ; 69 ;
+; Arkanoid:inst|field~1451 ; 65 ;
+; Arkanoid:inst|field~951 ; 64 ;
+; Arkanoid:inst|platform1_position~75 ; 56 ;
+; Arkanoid:inst|ball_y~25 ; 55 ;
+; Arkanoid:inst|LessThan137~0 ; 43 ;
+; Arkanoid:inst|ball_x~28 ; 43 ;
+; Debouncer:inst3|debounced ; 42 ;
+; Arkanoid:inst|Decoder2~14 ; 41 ;
+; Arkanoid:inst|player2_score~2 ; 37 ;
+; Arkanoid:inst|game_state~4 ; 37 ;
+; Arkanoid:inst|player1_score~1 ; 36 ;
+; Arkanoid:inst|LessThan132~10 ; 36 ;
+; Arkanoid:inst|Decoder2~9 ; 36 ;
+; Arkanoid:inst|button2_state ; 36 ;
+; Arkanoid:inst|Add15~60 ; 36 ;
+; Arkanoid:inst|Add16~60 ; 36 ;
+; Arkanoid:inst|ball_y~27 ; 35 ;
+; Arkanoid:inst|platform2_position~84 ; 35 ;
+; Arkanoid:inst|field~710 ; 34 ;
+; Arkanoid:inst|game_state~3 ; 34 ;
+; Arkanoid:inst|platform1_position~76 ; 33 ;
+; Arkanoid:inst|Add13~62 ; 33 ;
+; Arkanoid:inst|Add7~62 ; 33 ;
+; Arkanoid:inst|field~1820 ; 32 ;
+; Arkanoid:inst|field~1755 ; 32 ;
+; Arkanoid:inst|field~1658 ; 32 ;
+; Arkanoid:inst|field~1656 ; 32 ;
+; Arkanoid:inst|field~1591 ; 32 ;
+; Arkanoid:inst|field~1551 ; 32 ;
++---------------------------------------------------------------------------------------------------+---------+
-+-----------------------------------------------------+
-; Interconnect Usage Summary ;
-+----------------------------+------------------------+
-; Interconnect Resource Type ; Usage ;
-+----------------------------+------------------------+
-; Block interconnects ; 2,288 / 54,004 ( 4 % ) ;
-; C16 interconnects ; 6 / 2,100 ( < 1 % ) ;
-; C4 interconnects ; 1,077 / 36,000 ( 3 % ) ;
-; Direct links ; 690 / 54,004 ( 1 % ) ;
-; Global clocks ; 1 / 16 ( 6 % ) ;
-; Local interconnects ; 583 / 18,752 ( 3 % ) ;
-; R24 interconnects ; 24 / 1,900 ( 1 % ) ;
-; R4 interconnects ; 1,279 / 46,920 ( 3 % ) ;
-+----------------------------+------------------------+
++------------------------------------------------------+
+; Interconnect Usage Summary ;
++----------------------------+-------------------------+
+; Interconnect Resource Type ; Usage ;
++----------------------------+-------------------------+
+; Block interconnects ; 9,680 / 54,004 ( 18 % ) ;
+; C16 interconnects ; 106 / 2,100 ( 5 % ) ;
+; C4 interconnects ; 5,746 / 36,000 ( 16 % ) ;
+; Direct links ; 2,159 / 54,004 ( 4 % ) ;
+; Global clocks ; 1 / 16 ( 6 % ) ;
+; Local interconnects ; 3,489 / 18,752 ( 19 % ) ;
+; R24 interconnects ; 197 / 1,900 ( 10 % ) ;
+; R4 interconnects ; 6,847 / 46,920 ( 15 % ) ;
++----------------------------+-------------------------+
+-----------------------------------------------------------------------------+
; LAB Logic Elements ;
+---------------------------------------------+-------------------------------+
-; Number of Logic Elements (Average = 13.38) ; Number of LABs (Total = 135) ;
+; Number of Logic Elements (Average = 13.72) ; Number of LABs (Total = 521) ;
+---------------------------------------------+-------------------------------+
-; 1 ; 13 ;
-; 2 ; 3 ;
-; 3 ; 3 ;
-; 4 ; 1 ;
-; 5 ; 3 ;
-; 6 ; 2 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 1 ;
+; 1 ; 22 ;
+; 2 ; 16 ;
+; 3 ; 32 ;
+; 4 ; 7 ;
+; 5 ; 1 ;
+; 6 ; 4 ;
+; 7 ; 2 ;
+; 8 ; 1 ;
+; 9 ; 3 ;
; 10 ; 0 ;
-; 11 ; 1 ;
-; 12 ; 0 ;
+; 11 ; 3 ;
+; 12 ; 1 ;
; 13 ; 0 ;
-; 14 ; 0 ;
-; 15 ; 1 ;
-; 16 ; 107 ;
+; 14 ; 7 ;
+; 15 ; 3 ;
+; 16 ; 419 ;
+---------------------------------------------+-------------------------------+
+--------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-------------------------------+
-; LAB-wide Signals (Average = 0.19) ; Number of LABs (Total = 135) ;
+; LAB-wide Signals (Average = 0.38) ; Number of LABs (Total = 521) ;
+------------------------------------+-------------------------------+
-; 1 Clock ; 21 ;
-; 1 Clock enable ; 2 ;
-; 1 Sync. clear ; 3 ;
+; 1 Clock ; 189 ;
+; 1 Clock enable ; 5 ;
+; 1 Sync. clear ; 4 ;
+------------------------------------+-------------------------------+
+------------------------------------------------------------------------------+
; LAB Signals Sourced ;
+----------------------------------------------+-------------------------------+
-; Number of Signals Sourced (Average = 13.96) ; Number of LABs (Total = 135) ;
+; Number of Signals Sourced (Average = 15.18) ; Number of LABs (Total = 521) ;
+----------------------------------------------+-------------------------------+
-; 0 ; 0 ;
-; 1 ; 11 ;
-; 2 ; 5 ;
-; 3 ; 3 ;
-; 4 ; 1 ;
-; 5 ; 2 ;
-; 6 ; 2 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 1 ;
-; 10 ; 0 ;
-; 11 ; 3 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 18 ;
-; 15 ; 20 ;
-; 16 ; 53 ;
-; 17 ; 2 ;
-; 18 ; 0 ;
-; 19 ; 1 ;
-; 20 ; 0 ;
-; 21 ; 2 ;
-; 22 ; 1 ;
-; 23 ; 1 ;
-; 24 ; 3 ;
-; 25 ; 2 ;
-; 26 ; 0 ;
-; 27 ; 0 ;
-; 28 ; 0 ;
-; 29 ; 0 ;
-; 30 ; 1 ;
-; 31 ; 1 ;
-; 32 ; 2 ;
+; 0 ; 4 ;
+; 1 ; 24 ;
+; 2 ; 17 ;
+; 3 ; 31 ;
+; 4 ; 7 ;
+; 5 ; 1 ;
+; 6 ; 3 ;
+; 7 ; 4 ;
+; 8 ; 1 ;
+; 9 ; 0 ;
+; 10 ; 1 ;
+; 11 ; 5 ;
+; 12 ; 1 ;
+; 13 ; 1 ;
+; 14 ; 43 ;
+; 15 ; 91 ;
+; 16 ; 110 ;
+; 17 ; 19 ;
+; 18 ; 10 ;
+; 19 ; 14 ;
+; 20 ; 16 ;
+; 21 ; 10 ;
+; 22 ; 61 ;
+; 23 ; 13 ;
+; 24 ; 10 ;
+; 25 ; 3 ;
+; 26 ; 3 ;
+; 27 ; 6 ;
+; 28 ; 2 ;
+; 29 ; 4 ;
+; 30 ; 2 ;
+; 31 ; 0 ;
+; 32 ; 4 ;
+----------------------------------------------+-------------------------------+
-+----------------------------------------------------------------------------------+
-; LAB Signals Sourced Out ;
-+--------------------------------------------------+-------------------------------+
-; Number of Signals Sourced Out (Average = 10.92) ; Number of LABs (Total = 135) ;
-+--------------------------------------------------+-------------------------------+
-; 0 ; 0 ;
-; 1 ; 16 ;
-; 2 ; 5 ;
-; 3 ; 4 ;
-; 4 ; 6 ;
-; 5 ; 3 ;
-; 6 ; 0 ;
-; 7 ; 1 ;
-; 8 ; 2 ;
-; 9 ; 15 ;
-; 10 ; 5 ;
-; 11 ; 20 ;
-; 12 ; 6 ;
-; 13 ; 5 ;
-; 14 ; 5 ;
-; 15 ; 1 ;
-; 16 ; 30 ;
-; 17 ; 1 ;
-; 18 ; 0 ;
-; 19 ; 2 ;
-; 20 ; 1 ;
-; 21 ; 1 ;
-; 22 ; 1 ;
-; 23 ; 0 ;
-; 24 ; 1 ;
-; 25 ; 0 ;
-; 26 ; 0 ;
-; 27 ; 0 ;
-; 28 ; 0 ;
-; 29 ; 0 ;
-; 30 ; 1 ;
-; 31 ; 1 ;
-; 32 ; 2 ;
-+--------------------------------------------------+-------------------------------+
++---------------------------------------------------------------------------------+
+; LAB Signals Sourced Out ;
++-------------------------------------------------+-------------------------------+
+; Number of Signals Sourced Out (Average = 8.48) ; Number of LABs (Total = 521) ;
++-------------------------------------------------+-------------------------------+
+; 0 ; 4 ;
+; 1 ; 74 ;
+; 2 ; 79 ;
+; 3 ; 12 ;
+; 4 ; 8 ;
+; 5 ; 5 ;
+; 6 ; 14 ;
+; 7 ; 4 ;
+; 8 ; 17 ;
+; 9 ; 53 ;
+; 10 ; 47 ;
+; 11 ; 52 ;
+; 12 ; 19 ;
+; 13 ; 31 ;
+; 14 ; 17 ;
+; 15 ; 5 ;
+; 16 ; 65 ;
+; 17 ; 4 ;
+; 18 ; 1 ;
+; 19 ; 0 ;
+; 20 ; 1 ;
+; 21 ; 1 ;
+; 22 ; 0 ;
+; 23 ; 1 ;
+; 24 ; 1 ;
+; 25 ; 0 ;
+; 26 ; 0 ;
+; 27 ; 2 ;
+; 28 ; 1 ;
+; 29 ; 2 ;
+; 30 ; 1 ;
++-------------------------------------------------+-------------------------------+
+------------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+-------------------------------+
-; Number of Distinct Inputs (Average = 15.07) ; Number of LABs (Total = 135) ;
+; Number of Distinct Inputs (Average = 16.41) ; Number of LABs (Total = 521) ;
+----------------------------------------------+-------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
-; 2 ; 4 ;
-; 3 ; 6 ;
-; 4 ; 7 ;
-; 5 ; 3 ;
-; 6 ; 1 ;
-; 7 ; 2 ;
+; 2 ; 40 ;
+; 3 ; 20 ;
+; 4 ; 16 ;
+; 5 ; 7 ;
+; 6 ; 2 ;
+; 7 ; 8 ;
; 8 ; 1 ;
-; 9 ; 0 ;
+; 9 ; 4 ;
; 10 ; 1 ;
-; 11 ; 3 ;
-; 12 ; 3 ;
-; 13 ; 10 ;
-; 14 ; 14 ;
-; 15 ; 4 ;
-; 16 ; 11 ;
-; 17 ; 20 ;
-; 18 ; 4 ;
-; 19 ; 7 ;
-; 20 ; 15 ;
-; 21 ; 3 ;
-; 22 ; 2 ;
-; 23 ; 2 ;
-; 24 ; 3 ;
-; 25 ; 1 ;
-; 26 ; 0 ;
-; 27 ; 2 ;
-; 28 ; 2 ;
-; 29 ; 0 ;
-; 30 ; 3 ;
+; 11 ; 23 ;
+; 12 ; 12 ;
+; 13 ; 27 ;
+; 14 ; 41 ;
+; 15 ; 21 ;
+; 16 ; 25 ;
+; 17 ; 28 ;
+; 18 ; 24 ;
+; 19 ; 14 ;
+; 20 ; 42 ;
+; 21 ; 6 ;
+; 22 ; 56 ;
+; 23 ; 13 ;
+; 24 ; 9 ;
+; 25 ; 14 ;
+; 26 ; 7 ;
+; 27 ; 11 ;
+; 28 ; 9 ;
+; 29 ; 8 ;
+; 30 ; 20 ;
+; 31 ; 3 ;
+; 32 ; 4 ;
+; 33 ; 4 ;
+----------------------------------------------+-------------------------------+
@@ -1334,7 +1284,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 9.1 Build 222 10/21/2009 SJ Full Version
- Info: Processing started: Mon May 21 19:54:21 2012
+ Info: Processing started: Mon May 28 14:21:59 2012
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Selected device EP2C20F484C7 for design "myArkanoid"
@@ -1351,281 +1301,353 @@ Info: Fitter converted 3 user pins into dedicated programming pins
Info: Pin ~LVDS91p/nCEO~ is reserved at location W20
Info: Timing-driven compilation is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
-Info: Automatically promoted node Arkanoid:inst|clk25MHz_
+Info: Automatically promoted node ClockDivider:inst1|clk25MHz_
Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Following destination nodes may be non-global or may not use global or regional clocks
- Info: Destination node Arkanoid:inst|clk25MHz_~0
+ Info: Destination node ClockDivider:inst1|clk25MHz_~0
Info: Starting register packing
Info: Finished register packing
Extra Info: No registers were packed into other blocks
-Info: Fitter preparation operations ending: elapsed time is 00:00:01
+Info: Fitter preparation operations ending: elapsed time is 00:00:03
Info: Fitter placement preparation operations beginning
-Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info: Fitter placement preparation operations ending: elapsed time is 00:00:01
Info: Fitter placement operations beginning
Info: Fitter placement was successful
-Info: Fitter placement operations ending: elapsed time is 00:00:01
-Info: Estimated most critical path is register to register delay of 110.730 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X14_Y11; Fanout = 6; REG Node = 'Arkanoid:inst|h_counter[1]'
- Info: 2: + IC(0.781 ns) + CELL(0.517 ns) = 1.298 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~1'
- Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.378 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~3'
- Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.458 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~5'
- Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.538 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~7'
- Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 1.618 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~9'
- Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 1.698 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~11'
- Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 1.778 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~13'
- Info: 9: + IC(0.000 ns) + CELL(0.080 ns) = 1.858 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~15'
- Info: 10: + IC(0.000 ns) + CELL(0.080 ns) = 1.938 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~17'
- Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 2.018 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~19'
- Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 2.098 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~21'
- Info: 13: + IC(0.000 ns) + CELL(0.080 ns) = 2.178 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~23'
- Info: 14: + IC(0.000 ns) + CELL(0.080 ns) = 2.258 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~25'
- Info: 15: + IC(0.000 ns) + CELL(0.080 ns) = 2.338 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~27'
- Info: 16: + IC(0.000 ns) + CELL(0.080 ns) = 2.418 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~29'
- Info: 17: + IC(0.098 ns) + CELL(0.080 ns) = 2.596 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~31'
- Info: 18: + IC(0.000 ns) + CELL(0.080 ns) = 2.676 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~33'
- Info: 19: + IC(0.000 ns) + CELL(0.080 ns) = 2.756 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~35'
- Info: 20: + IC(0.000 ns) + CELL(0.080 ns) = 2.836 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~37'
- Info: 21: + IC(0.000 ns) + CELL(0.080 ns) = 2.916 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~39'
- Info: 22: + IC(0.000 ns) + CELL(0.080 ns) = 2.996 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~41'
- Info: 23: + IC(0.000 ns) + CELL(0.080 ns) = 3.076 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~43'
- Info: 24: + IC(0.000 ns) + CELL(0.080 ns) = 3.156 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~45'
- Info: 25: + IC(0.000 ns) + CELL(0.080 ns) = 3.236 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~47'
- Info: 26: + IC(0.000 ns) + CELL(0.080 ns) = 3.316 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~49'
- Info: 27: + IC(0.000 ns) + CELL(0.080 ns) = 3.396 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~51'
- Info: 28: + IC(0.000 ns) + CELL(0.080 ns) = 3.476 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~53'
- Info: 29: + IC(0.000 ns) + CELL(0.080 ns) = 3.556 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~55'
- Info: 30: + IC(0.000 ns) + CELL(0.080 ns) = 3.636 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~57'
- Info: 31: + IC(0.000 ns) + CELL(0.080 ns) = 3.716 ns; Loc. = LAB_X15_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst|Add8~59'
- Info: 32: + IC(0.000 ns) + CELL(0.458 ns) = 4.174 ns; Loc. = LAB_X15_Y10; Fanout = 65; COMB Node = 'Arkanoid:inst|Add8~60'
- Info: 33: + IC(1.060 ns) + CELL(0.517 ns) = 5.751 ns; Loc. = LAB_X16_Y11; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~1'
- Info: 34: + IC(0.000 ns) + CELL(0.080 ns) = 5.831 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3'
- Info: 35: + IC(0.000 ns) + CELL(0.080 ns) = 5.911 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5'
- Info: 36: + IC(0.000 ns) + CELL(0.080 ns) = 5.991 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7'
- Info: 37: + IC(0.000 ns) + CELL(0.080 ns) = 6.071 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9'
- Info: 38: + IC(0.000 ns) + CELL(0.080 ns) = 6.151 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11'
- Info: 39: + IC(0.000 ns) + CELL(0.080 ns) = 6.231 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13'
- Info: 40: + IC(0.000 ns) + CELL(0.080 ns) = 6.311 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15'
- Info: 41: + IC(0.000 ns) + CELL(0.080 ns) = 6.391 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17'
- Info: 42: + IC(0.000 ns) + CELL(0.080 ns) = 6.471 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19'
- Info: 43: + IC(0.000 ns) + CELL(0.080 ns) = 6.551 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21'
- Info: 44: + IC(0.000 ns) + CELL(0.080 ns) = 6.631 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23'
- Info: 45: + IC(0.000 ns) + CELL(0.080 ns) = 6.711 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25'
- Info: 46: + IC(0.000 ns) + CELL(0.080 ns) = 6.791 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27'
- Info: 47: + IC(0.000 ns) + CELL(0.080 ns) = 6.871 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29'
- Info: 48: + IC(0.000 ns) + CELL(0.080 ns) = 6.951 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31'
- Info: 49: + IC(0.098 ns) + CELL(0.080 ns) = 7.129 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33'
- Info: 50: + IC(0.000 ns) + CELL(0.080 ns) = 7.209 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35'
- Info: 51: + IC(0.000 ns) + CELL(0.080 ns) = 7.289 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37'
- Info: 52: + IC(0.000 ns) + CELL(0.080 ns) = 7.369 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39'
- Info: 53: + IC(0.000 ns) + CELL(0.080 ns) = 7.449 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41'
- Info: 54: + IC(0.000 ns) + CELL(0.080 ns) = 7.529 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43'
- Info: 55: + IC(0.000 ns) + CELL(0.080 ns) = 7.609 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45'
- Info: 56: + IC(0.000 ns) + CELL(0.080 ns) = 7.689 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47'
- Info: 57: + IC(0.000 ns) + CELL(0.080 ns) = 7.769 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49'
- Info: 58: + IC(0.000 ns) + CELL(0.080 ns) = 7.849 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51'
- Info: 59: + IC(0.000 ns) + CELL(0.080 ns) = 7.929 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53'
- Info: 60: + IC(0.000 ns) + CELL(0.080 ns) = 8.009 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55'
- Info: 61: + IC(0.000 ns) + CELL(0.080 ns) = 8.089 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~57'
- Info: 62: + IC(0.000 ns) + CELL(0.458 ns) = 8.547 ns; Loc. = LAB_X16_Y10; Fanout = 4; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~58'
- Info: 63: + IC(1.405 ns) + CELL(0.517 ns) = 10.469 ns; Loc. = LAB_X16_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_4_result_int[2]~1'
- Info: 64: + IC(0.000 ns) + CELL(0.080 ns) = 10.549 ns; Loc. = LAB_X16_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_4_result_int[3]~3'
- Info: 65: + IC(0.000 ns) + CELL(0.080 ns) = 10.629 ns; Loc. = LAB_X16_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_4_result_int[4]~5'
- Info: 66: + IC(0.000 ns) + CELL(0.458 ns) = 11.087 ns; Loc. = LAB_X16_Y15; Fanout = 11; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_4_result_int[5]~6'
- Info: 67: + IC(1.037 ns) + CELL(0.177 ns) = 12.301 ns; Loc. = LAB_X18_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[29]~435'
- Info: 68: + IC(1.037 ns) + CELL(0.495 ns) = 13.833 ns; Loc. = LAB_X16_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_5_result_int[2]~1'
- Info: 69: + IC(0.000 ns) + CELL(0.080 ns) = 13.913 ns; Loc. = LAB_X16_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_5_result_int[3]~3'
- Info: 70: + IC(0.000 ns) + CELL(0.080 ns) = 13.993 ns; Loc. = LAB_X16_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_5_result_int[4]~5'
- Info: 71: + IC(0.000 ns) + CELL(0.080 ns) = 14.073 ns; Loc. = LAB_X16_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_5_result_int[5]~7'
- Info: 72: + IC(0.000 ns) + CELL(0.458 ns) = 14.531 ns; Loc. = LAB_X16_Y15; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_5_result_int[6]~8'
- Info: 73: + IC(0.693 ns) + CELL(0.521 ns) = 15.745 ns; Loc. = LAB_X18_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[36]~441'
- Info: 74: + IC(0.709 ns) + CELL(0.517 ns) = 16.971 ns; Loc. = LAB_X19_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[2]~1'
- Info: 75: + IC(0.000 ns) + CELL(0.080 ns) = 17.051 ns; Loc. = LAB_X19_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[3]~3'
- Info: 76: + IC(0.000 ns) + CELL(0.080 ns) = 17.131 ns; Loc. = LAB_X19_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[4]~5'
- Info: 77: + IC(0.000 ns) + CELL(0.080 ns) = 17.211 ns; Loc. = LAB_X19_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[5]~7'
- Info: 78: + IC(0.000 ns) + CELL(0.080 ns) = 17.291 ns; Loc. = LAB_X19_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[6]~9'
- Info: 79: + IC(0.000 ns) + CELL(0.458 ns) = 17.749 ns; Loc. = LAB_X19_Y15; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[7]~10'
- Info: 80: + IC(0.745 ns) + CELL(0.521 ns) = 19.015 ns; Loc. = LAB_X20_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[43]~447'
- Info: 81: + IC(1.066 ns) + CELL(0.517 ns) = 20.598 ns; Loc. = LAB_X19_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[2]~1'
- Info: 82: + IC(0.000 ns) + CELL(0.080 ns) = 20.678 ns; Loc. = LAB_X19_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[3]~3'
- Info: 83: + IC(0.000 ns) + CELL(0.080 ns) = 20.758 ns; Loc. = LAB_X19_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[4]~5'
- Info: 84: + IC(0.000 ns) + CELL(0.080 ns) = 20.838 ns; Loc. = LAB_X19_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[5]~7'
- Info: 85: + IC(0.000 ns) + CELL(0.080 ns) = 20.918 ns; Loc. = LAB_X19_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[6]~9'
- Info: 86: + IC(0.000 ns) + CELL(0.458 ns) = 21.376 ns; Loc. = LAB_X19_Y15; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[7]~10'
- Info: 87: + IC(0.745 ns) + CELL(0.521 ns) = 22.642 ns; Loc. = LAB_X20_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[50]~453'
- Info: 88: + IC(0.709 ns) + CELL(0.517 ns) = 23.868 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[2]~1'
- Info: 89: + IC(0.000 ns) + CELL(0.080 ns) = 23.948 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[3]~3'
- Info: 90: + IC(0.000 ns) + CELL(0.080 ns) = 24.028 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[4]~5'
- Info: 91: + IC(0.000 ns) + CELL(0.080 ns) = 24.108 ns; Loc. = LAB_X19_Y18; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[5]~7'
- Info: 92: + IC(0.000 ns) + CELL(0.080 ns) = 24.188 ns; Loc. = LAB_X19_Y18; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[6]~9'
- Info: 93: + IC(0.000 ns) + CELL(0.458 ns) = 24.646 ns; Loc. = LAB_X19_Y18; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[7]~10'
- Info: 94: + IC(0.745 ns) + CELL(0.521 ns) = 25.912 ns; Loc. = LAB_X19_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[57]~459'
- Info: 95: + IC(1.066 ns) + CELL(0.517 ns) = 27.495 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[2]~1'
- Info: 96: + IC(0.000 ns) + CELL(0.080 ns) = 27.575 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[3]~3'
- Info: 97: + IC(0.000 ns) + CELL(0.080 ns) = 27.655 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[4]~5'
- Info: 98: + IC(0.000 ns) + CELL(0.080 ns) = 27.735 ns; Loc. = LAB_X19_Y18; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[5]~7'
- Info: 99: + IC(0.000 ns) + CELL(0.080 ns) = 27.815 ns; Loc. = LAB_X19_Y18; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[6]~9'
- Info: 100: + IC(0.000 ns) + CELL(0.458 ns) = 28.273 ns; Loc. = LAB_X19_Y18; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[7]~10'
- Info: 101: + IC(0.745 ns) + CELL(0.521 ns) = 29.539 ns; Loc. = LAB_X19_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[64]~465'
- Info: 102: + IC(0.709 ns) + CELL(0.517 ns) = 30.765 ns; Loc. = LAB_X20_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_10_result_int[2]~1'
- Info: 103: + IC(0.000 ns) + CELL(0.080 ns) = 30.845 ns; Loc. = LAB_X20_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_10_result_int[3]~3'
- Info: 104: + IC(0.000 ns) + CELL(0.080 ns) = 30.925 ns; Loc. = LAB_X20_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_10_result_int[4]~5'
- Info: 105: + IC(0.000 ns) + CELL(0.080 ns) = 31.005 ns; Loc. = LAB_X20_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_10_result_int[5]~7'
- Info: 106: + IC(0.000 ns) + CELL(0.080 ns) = 31.085 ns; Loc. = LAB_X20_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_10_result_int[6]~9'
- Info: 107: + IC(0.000 ns) + CELL(0.458 ns) = 31.543 ns; Loc. = LAB_X20_Y22; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_10_result_int[7]~10'
- Info: 108: + IC(0.729 ns) + CELL(0.521 ns) = 32.793 ns; Loc. = LAB_X20_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[71]~471'
- Info: 109: + IC(1.050 ns) + CELL(0.517 ns) = 34.360 ns; Loc. = LAB_X20_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_11_result_int[2]~1'
- Info: 110: + IC(0.000 ns) + CELL(0.080 ns) = 34.440 ns; Loc. = LAB_X20_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_11_result_int[3]~3'
- Info: 111: + IC(0.000 ns) + CELL(0.080 ns) = 34.520 ns; Loc. = LAB_X20_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_11_result_int[4]~5'
- Info: 112: + IC(0.000 ns) + CELL(0.080 ns) = 34.600 ns; Loc. = LAB_X20_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_11_result_int[5]~7'
- Info: 113: + IC(0.000 ns) + CELL(0.080 ns) = 34.680 ns; Loc. = LAB_X20_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_11_result_int[6]~9'
- Info: 114: + IC(0.000 ns) + CELL(0.458 ns) = 35.138 ns; Loc. = LAB_X20_Y22; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_11_result_int[7]~10'
- Info: 115: + IC(0.729 ns) + CELL(0.521 ns) = 36.388 ns; Loc. = LAB_X20_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[78]~477'
- Info: 116: + IC(0.709 ns) + CELL(0.517 ns) = 37.614 ns; Loc. = LAB_X19_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_12_result_int[2]~1'
- Info: 117: + IC(0.000 ns) + CELL(0.080 ns) = 37.694 ns; Loc. = LAB_X19_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_12_result_int[3]~3'
- Info: 118: + IC(0.000 ns) + CELL(0.080 ns) = 37.774 ns; Loc. = LAB_X19_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_12_result_int[4]~5'
- Info: 119: + IC(0.000 ns) + CELL(0.080 ns) = 37.854 ns; Loc. = LAB_X19_Y21; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_12_result_int[5]~7'
- Info: 120: + IC(0.000 ns) + CELL(0.080 ns) = 37.934 ns; Loc. = LAB_X19_Y21; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_12_result_int[6]~9'
- Info: 121: + IC(0.000 ns) + CELL(0.458 ns) = 38.392 ns; Loc. = LAB_X19_Y21; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_12_result_int[7]~10'
- Info: 122: + IC(0.388 ns) + CELL(0.521 ns) = 39.301 ns; Loc. = LAB_X18_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[85]~483'
- Info: 123: + IC(0.709 ns) + CELL(0.517 ns) = 40.527 ns; Loc. = LAB_X19_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_13_result_int[2]~1'
- Info: 124: + IC(0.000 ns) + CELL(0.080 ns) = 40.607 ns; Loc. = LAB_X19_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_13_result_int[3]~3'
- Info: 125: + IC(0.000 ns) + CELL(0.080 ns) = 40.687 ns; Loc. = LAB_X19_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_13_result_int[4]~5'
- Info: 126: + IC(0.000 ns) + CELL(0.080 ns) = 40.767 ns; Loc. = LAB_X19_Y21; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_13_result_int[5]~7'
- Info: 127: + IC(0.000 ns) + CELL(0.080 ns) = 40.847 ns; Loc. = LAB_X19_Y21; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_13_result_int[6]~9'
- Info: 128: + IC(0.000 ns) + CELL(0.458 ns) = 41.305 ns; Loc. = LAB_X19_Y21; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_13_result_int[7]~10'
- Info: 129: + IC(0.388 ns) + CELL(0.521 ns) = 42.214 ns; Loc. = LAB_X18_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[92]~489'
- Info: 130: + IC(1.050 ns) + CELL(0.517 ns) = 43.781 ns; Loc. = LAB_X19_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[2]~1'
- Info: 131: + IC(0.000 ns) + CELL(0.080 ns) = 43.861 ns; Loc. = LAB_X19_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[3]~3'
- Info: 132: + IC(0.000 ns) + CELL(0.080 ns) = 43.941 ns; Loc. = LAB_X19_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[4]~5'
- Info: 133: + IC(0.000 ns) + CELL(0.080 ns) = 44.021 ns; Loc. = LAB_X19_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[5]~7'
- Info: 134: + IC(0.000 ns) + CELL(0.080 ns) = 44.101 ns; Loc. = LAB_X19_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[6]~9'
- Info: 135: + IC(0.000 ns) + CELL(0.458 ns) = 44.559 ns; Loc. = LAB_X19_Y20; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[7]~10'
- Info: 136: + IC(0.729 ns) + CELL(0.521 ns) = 45.809 ns; Loc. = LAB_X18_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[99]~495'
- Info: 137: + IC(1.050 ns) + CELL(0.517 ns) = 47.376 ns; Loc. = LAB_X18_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[2]~1'
- Info: 138: + IC(0.000 ns) + CELL(0.080 ns) = 47.456 ns; Loc. = LAB_X18_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[3]~3'
- Info: 139: + IC(0.000 ns) + CELL(0.080 ns) = 47.536 ns; Loc. = LAB_X18_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[4]~5'
- Info: 140: + IC(0.000 ns) + CELL(0.080 ns) = 47.616 ns; Loc. = LAB_X18_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[5]~7'
- Info: 141: + IC(0.000 ns) + CELL(0.080 ns) = 47.696 ns; Loc. = LAB_X18_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[6]~9'
- Info: 142: + IC(0.000 ns) + CELL(0.458 ns) = 48.154 ns; Loc. = LAB_X18_Y20; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[7]~10'
- Info: 143: + IC(0.729 ns) + CELL(0.521 ns) = 49.404 ns; Loc. = LAB_X19_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[106]~501'
- Info: 144: + IC(1.050 ns) + CELL(0.517 ns) = 50.971 ns; Loc. = LAB_X19_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[2]~1'
- Info: 145: + IC(0.000 ns) + CELL(0.080 ns) = 51.051 ns; Loc. = LAB_X19_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[3]~3'
- Info: 146: + IC(0.000 ns) + CELL(0.080 ns) = 51.131 ns; Loc. = LAB_X19_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[4]~5'
- Info: 147: + IC(0.000 ns) + CELL(0.080 ns) = 51.211 ns; Loc. = LAB_X19_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[5]~7'
- Info: 148: + IC(0.000 ns) + CELL(0.080 ns) = 51.291 ns; Loc. = LAB_X19_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[6]~9'
- Info: 149: + IC(0.000 ns) + CELL(0.458 ns) = 51.749 ns; Loc. = LAB_X19_Y20; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[7]~10'
- Info: 150: + IC(0.929 ns) + CELL(0.322 ns) = 53.000 ns; Loc. = LAB_X19_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[114]~657'
- Info: 151: + IC(0.709 ns) + CELL(0.517 ns) = 54.226 ns; Loc. = LAB_X18_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[3]~3'
- Info: 152: + IC(0.000 ns) + CELL(0.080 ns) = 54.306 ns; Loc. = LAB_X18_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[4]~5'
- Info: 153: + IC(0.000 ns) + CELL(0.080 ns) = 54.386 ns; Loc. = LAB_X18_Y19; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[5]~7'
- Info: 154: + IC(0.000 ns) + CELL(0.080 ns) = 54.466 ns; Loc. = LAB_X18_Y19; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[6]~9'
- Info: 155: + IC(0.000 ns) + CELL(0.458 ns) = 54.924 ns; Loc. = LAB_X18_Y19; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[7]~10'
- Info: 156: + IC(0.154 ns) + CELL(0.521 ns) = 55.599 ns; Loc. = LAB_X18_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[120]~513'
- Info: 157: + IC(0.709 ns) + CELL(0.517 ns) = 56.825 ns; Loc. = LAB_X19_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_18_result_int[2]~1'
- Info: 158: + IC(0.000 ns) + CELL(0.080 ns) = 56.905 ns; Loc. = LAB_X19_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_18_result_int[3]~3'
- Info: 159: + IC(0.000 ns) + CELL(0.080 ns) = 56.985 ns; Loc. = LAB_X19_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_18_result_int[4]~5'
- Info: 160: + IC(0.000 ns) + CELL(0.080 ns) = 57.065 ns; Loc. = LAB_X19_Y19; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_18_result_int[5]~7'
- Info: 161: + IC(0.000 ns) + CELL(0.080 ns) = 57.145 ns; Loc. = LAB_X19_Y19; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_18_result_int[6]~9'
- Info: 162: + IC(0.000 ns) + CELL(0.458 ns) = 57.603 ns; Loc. = LAB_X19_Y19; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_18_result_int[7]~10'
- Info: 163: + IC(0.388 ns) + CELL(0.521 ns) = 58.512 ns; Loc. = LAB_X20_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[127]~519'
- Info: 164: + IC(0.475 ns) + CELL(0.517 ns) = 59.504 ns; Loc. = LAB_X20_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_19_result_int[2]~1'
- Info: 165: + IC(0.000 ns) + CELL(0.080 ns) = 59.584 ns; Loc. = LAB_X20_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_19_result_int[3]~3'
- Info: 166: + IC(0.000 ns) + CELL(0.080 ns) = 59.664 ns; Loc. = LAB_X20_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_19_result_int[4]~5'
- Info: 167: + IC(0.000 ns) + CELL(0.080 ns) = 59.744 ns; Loc. = LAB_X20_Y19; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_19_result_int[5]~7'
- Info: 168: + IC(0.000 ns) + CELL(0.080 ns) = 59.824 ns; Loc. = LAB_X20_Y19; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_19_result_int[6]~9'
- Info: 169: + IC(0.000 ns) + CELL(0.458 ns) = 60.282 ns; Loc. = LAB_X20_Y19; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_19_result_int[7]~10'
- Info: 170: + IC(0.388 ns) + CELL(0.521 ns) = 61.191 ns; Loc. = LAB_X21_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[134]~525'
- Info: 171: + IC(0.709 ns) + CELL(0.517 ns) = 62.417 ns; Loc. = LAB_X22_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[2]~1'
- Info: 172: + IC(0.000 ns) + CELL(0.080 ns) = 62.497 ns; Loc. = LAB_X22_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[3]~3'
- Info: 173: + IC(0.000 ns) + CELL(0.080 ns) = 62.577 ns; Loc. = LAB_X22_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[4]~5'
- Info: 174: + IC(0.000 ns) + CELL(0.080 ns) = 62.657 ns; Loc. = LAB_X22_Y19; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[5]~7'
- Info: 175: + IC(0.000 ns) + CELL(0.080 ns) = 62.737 ns; Loc. = LAB_X22_Y19; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[6]~9'
- Info: 176: + IC(0.000 ns) + CELL(0.458 ns) = 63.195 ns; Loc. = LAB_X22_Y19; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[7]~10'
- Info: 177: + IC(0.745 ns) + CELL(0.521 ns) = 64.461 ns; Loc. = LAB_X22_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[141]~531'
- Info: 178: + IC(1.066 ns) + CELL(0.517 ns) = 66.044 ns; Loc. = LAB_X22_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[2]~1'
- Info: 179: + IC(0.000 ns) + CELL(0.080 ns) = 66.124 ns; Loc. = LAB_X22_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[3]~3'
- Info: 180: + IC(0.000 ns) + CELL(0.080 ns) = 66.204 ns; Loc. = LAB_X22_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[4]~5'
- Info: 181: + IC(0.000 ns) + CELL(0.080 ns) = 66.284 ns; Loc. = LAB_X22_Y19; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[5]~7'
- Info: 182: + IC(0.000 ns) + CELL(0.080 ns) = 66.364 ns; Loc. = LAB_X22_Y19; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[6]~9'
- Info: 183: + IC(0.000 ns) + CELL(0.458 ns) = 66.822 ns; Loc. = LAB_X22_Y19; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[7]~10'
- Info: 184: + IC(0.732 ns) + CELL(0.177 ns) = 67.731 ns; Loc. = LAB_X21_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[150]~535'
- Info: 185: + IC(1.397 ns) + CELL(0.495 ns) = 69.623 ns; Loc. = LAB_X23_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_22_result_int[4]~5'
- Info: 186: + IC(0.000 ns) + CELL(0.080 ns) = 69.703 ns; Loc. = LAB_X23_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_22_result_int[5]~7'
- Info: 187: + IC(0.000 ns) + CELL(0.080 ns) = 69.783 ns; Loc. = LAB_X23_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_22_result_int[6]~9'
- Info: 188: + IC(0.000 ns) + CELL(0.458 ns) = 70.241 ns; Loc. = LAB_X23_Y22; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_22_result_int[7]~10'
- Info: 189: + IC(0.388 ns) + CELL(0.521 ns) = 71.150 ns; Loc. = LAB_X24_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[155]~543'
- Info: 190: + IC(0.709 ns) + CELL(0.517 ns) = 72.376 ns; Loc. = LAB_X23_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[2]~1'
- Info: 191: + IC(0.000 ns) + CELL(0.080 ns) = 72.456 ns; Loc. = LAB_X23_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[3]~3'
- Info: 192: + IC(0.000 ns) + CELL(0.080 ns) = 72.536 ns; Loc. = LAB_X23_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[4]~5'
- Info: 193: + IC(0.000 ns) + CELL(0.080 ns) = 72.616 ns; Loc. = LAB_X23_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[5]~7'
- Info: 194: + IC(0.000 ns) + CELL(0.080 ns) = 72.696 ns; Loc. = LAB_X23_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[6]~9'
- Info: 195: + IC(0.000 ns) + CELL(0.458 ns) = 73.154 ns; Loc. = LAB_X23_Y22; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[7]~10'
- Info: 196: + IC(0.732 ns) + CELL(0.177 ns) = 74.063 ns; Loc. = LAB_X22_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[164]~547'
- Info: 197: + IC(1.039 ns) + CELL(0.495 ns) = 75.597 ns; Loc. = LAB_X25_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_24_result_int[4]~5'
- Info: 198: + IC(0.000 ns) + CELL(0.080 ns) = 75.677 ns; Loc. = LAB_X25_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_24_result_int[5]~7'
- Info: 199: + IC(0.000 ns) + CELL(0.080 ns) = 75.757 ns; Loc. = LAB_X25_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_24_result_int[6]~9'
- Info: 200: + IC(0.000 ns) + CELL(0.458 ns) = 76.215 ns; Loc. = LAB_X25_Y22; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_24_result_int[7]~10'
- Info: 201: + IC(0.737 ns) + CELL(0.521 ns) = 77.473 ns; Loc. = LAB_X30_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[169]~555'
- Info: 202: + IC(1.035 ns) + CELL(0.517 ns) = 79.025 ns; Loc. = LAB_X25_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[2]~1'
- Info: 203: + IC(0.000 ns) + CELL(0.080 ns) = 79.105 ns; Loc. = LAB_X25_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[3]~3'
- Info: 204: + IC(0.000 ns) + CELL(0.080 ns) = 79.185 ns; Loc. = LAB_X25_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[4]~5'
- Info: 205: + IC(0.000 ns) + CELL(0.080 ns) = 79.265 ns; Loc. = LAB_X25_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[5]~7'
- Info: 206: + IC(0.000 ns) + CELL(0.080 ns) = 79.345 ns; Loc. = LAB_X25_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[6]~9'
- Info: 207: + IC(0.000 ns) + CELL(0.458 ns) = 79.803 ns; Loc. = LAB_X25_Y22; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[7]~10'
- Info: 208: + IC(0.755 ns) + CELL(0.177 ns) = 80.735 ns; Loc. = LAB_X24_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[178]~559'
- Info: 209: + IC(1.351 ns) + CELL(0.495 ns) = 82.581 ns; Loc. = LAB_X31_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_26_result_int[4]~5'
- Info: 210: + IC(0.000 ns) + CELL(0.080 ns) = 82.661 ns; Loc. = LAB_X31_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_26_result_int[5]~7'
- Info: 211: + IC(0.000 ns) + CELL(0.080 ns) = 82.741 ns; Loc. = LAB_X31_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_26_result_int[6]~9'
- Info: 212: + IC(0.000 ns) + CELL(0.458 ns) = 83.199 ns; Loc. = LAB_X31_Y22; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_26_result_int[7]~10'
- Info: 213: + IC(1.049 ns) + CELL(0.521 ns) = 84.769 ns; Loc. = LAB_X34_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[183]~567'
- Info: 214: + IC(1.370 ns) + CELL(0.517 ns) = 86.656 ns; Loc. = LAB_X31_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[2]~1'
- Info: 215: + IC(0.000 ns) + CELL(0.080 ns) = 86.736 ns; Loc. = LAB_X31_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[3]~3'
- Info: 216: + IC(0.000 ns) + CELL(0.080 ns) = 86.816 ns; Loc. = LAB_X31_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[4]~5'
- Info: 217: + IC(0.000 ns) + CELL(0.080 ns) = 86.896 ns; Loc. = LAB_X31_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[5]~7'
- Info: 218: + IC(0.000 ns) + CELL(0.080 ns) = 86.976 ns; Loc. = LAB_X31_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[6]~9'
- Info: 219: + IC(0.000 ns) + CELL(0.458 ns) = 87.434 ns; Loc. = LAB_X31_Y22; Fanout = 15; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[7]~10'
- Info: 220: + IC(0.732 ns) + CELL(0.177 ns) = 88.343 ns; Loc. = LAB_X30_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[192]~571'
- Info: 221: + IC(1.703 ns) + CELL(0.495 ns) = 90.541 ns; Loc. = LAB_X35_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_28_result_int[4]~5'
- Info: 222: + IC(0.000 ns) + CELL(0.080 ns) = 90.621 ns; Loc. = LAB_X35_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_28_result_int[5]~7'
- Info: 223: + IC(0.000 ns) + CELL(0.080 ns) = 90.701 ns; Loc. = LAB_X35_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_28_result_int[6]~9'
- Info: 224: + IC(0.000 ns) + CELL(0.458 ns) = 91.159 ns; Loc. = LAB_X35_Y20; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_28_result_int[7]~10'
- Info: 225: + IC(0.388 ns) + CELL(0.521 ns) = 92.068 ns; Loc. = LAB_X34_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[197]~579'
- Info: 226: + IC(0.709 ns) + CELL(0.517 ns) = 93.294 ns; Loc. = LAB_X35_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[2]~1'
- Info: 227: + IC(0.000 ns) + CELL(0.080 ns) = 93.374 ns; Loc. = LAB_X35_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[3]~3'
- Info: 228: + IC(0.000 ns) + CELL(0.080 ns) = 93.454 ns; Loc. = LAB_X35_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[4]~5'
- Info: 229: + IC(0.000 ns) + CELL(0.080 ns) = 93.534 ns; Loc. = LAB_X35_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[5]~7'
- Info: 230: + IC(0.000 ns) + CELL(0.080 ns) = 93.614 ns; Loc. = LAB_X35_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[6]~9'
- Info: 231: + IC(0.000 ns) + CELL(0.458 ns) = 94.072 ns; Loc. = LAB_X35_Y20; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[7]~10'
- Info: 232: + IC(1.084 ns) + CELL(0.177 ns) = 95.333 ns; Loc. = LAB_X36_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[205]~584'
- Info: 233: + IC(0.732 ns) + CELL(0.495 ns) = 96.560 ns; Loc. = LAB_X35_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_30_result_int[3]~3'
- Info: 234: + IC(0.000 ns) + CELL(0.080 ns) = 96.640 ns; Loc. = LAB_X35_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_30_result_int[4]~5'
- Info: 235: + IC(0.000 ns) + CELL(0.080 ns) = 96.720 ns; Loc. = LAB_X35_Y18; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_30_result_int[5]~7'
- Info: 236: + IC(0.000 ns) + CELL(0.080 ns) = 96.800 ns; Loc. = LAB_X35_Y18; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_30_result_int[6]~9'
- Info: 237: + IC(0.000 ns) + CELL(0.458 ns) = 97.258 ns; Loc. = LAB_X35_Y18; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_30_result_int[7]~10'
- Info: 238: + IC(0.740 ns) + CELL(0.521 ns) = 98.519 ns; Loc. = LAB_X35_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[211]~591'
- Info: 239: + IC(0.475 ns) + CELL(0.517 ns) = 99.511 ns; Loc. = LAB_X35_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[2]~1'
- Info: 240: + IC(0.000 ns) + CELL(0.080 ns) = 99.591 ns; Loc. = LAB_X35_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[3]~3'
- Info: 241: + IC(0.000 ns) + CELL(0.080 ns) = 99.671 ns; Loc. = LAB_X35_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[4]~5'
- Info: 242: + IC(0.000 ns) + CELL(0.080 ns) = 99.751 ns; Loc. = LAB_X35_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[5]~7'
- Info: 243: + IC(0.000 ns) + CELL(0.080 ns) = 99.831 ns; Loc. = LAB_X35_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[6]~9'
- Info: 244: + IC(0.000 ns) + CELL(0.458 ns) = 100.289 ns; Loc. = LAB_X35_Y16; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[7]~10'
- Info: 245: + IC(1.017 ns) + CELL(0.545 ns) = 101.851 ns; Loc. = LAB_X31_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|op_1~0'
- Info: 246: + IC(0.673 ns) + CELL(0.545 ns) = 103.069 ns; Loc. = LAB_X35_Y16; Fanout = 19; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|quotient[0]~4'
- Info: 247: + IC(0.498 ns) + CELL(0.178 ns) = 103.745 ns; Loc. = LAB_X35_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~15'
- Info: 248: + IC(0.498 ns) + CELL(0.178 ns) = 104.421 ns; Loc. = LAB_X35_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~16'
- Info: 249: + IC(1.058 ns) + CELL(0.178 ns) = 105.657 ns; Loc. = LAB_X30_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~17'
- Info: 250: + IC(0.354 ns) + CELL(0.322 ns) = 106.333 ns; Loc. = LAB_X30_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~18'
- Info: 251: + IC(0.498 ns) + CELL(0.178 ns) = 107.009 ns; Loc. = LAB_X30_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~19'
- Info: 252: + IC(0.354 ns) + CELL(0.319 ns) = 107.682 ns; Loc. = LAB_X30_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~22'
- Info: 253: + IC(1.249 ns) + CELL(0.322 ns) = 109.253 ns; Loc. = LAB_X27_Y18; Fanout = 4; COMB Node = 'Arkanoid:inst|Mux3~3'
- Info: 254: + IC(0.354 ns) + CELL(0.322 ns) = 109.929 ns; Loc. = LAB_X27_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|blue_~1'
- Info: 255: + IC(0.705 ns) + CELL(0.096 ns) = 110.730 ns; Loc. = LAB_X26_Y18; Fanout = 1; REG Node = 'Arkanoid:inst|blue_[0]'
- Info: Total cell delay = 56.585 ns ( 51.10 % )
- Info: Total interconnect delay = 54.145 ns ( 48.90 % )
+Info: Fitter placement operations ending: elapsed time is 00:00:03
+Info: Estimated most critical path is register to register delay of 139.129 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X32_Y11; Fanout = 36; REG Node = 'Arkanoid:inst|button2_state'
+ Info: 2: + IC(0.779 ns) + CELL(0.544 ns) = 1.323 ns; Loc. = LAB_X33_Y13; Fanout = 73; COMB Node = 'Arkanoid:inst|platform2_position~4'
+ Info: 3: + IC(0.740 ns) + CELL(0.521 ns) = 2.584 ns; Loc. = LAB_X33_Y15; Fanout = 63; COMB Node = 'Arkanoid:inst|platform2_position~5'
+ Info: 4: + IC(1.073 ns) + CELL(0.495 ns) = 4.152 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~1'
+ Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 4.232 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~3'
+ Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 4.312 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~5'
+ Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 4.392 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~7'
+ Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 4.472 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~9'
+ Info: 9: + IC(0.000 ns) + CELL(0.080 ns) = 4.552 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~11'
+ Info: 10: + IC(0.000 ns) + CELL(0.080 ns) = 4.632 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~13'
+ Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 4.712 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~15'
+ Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 4.792 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~17'
+ Info: 13: + IC(0.000 ns) + CELL(0.080 ns) = 4.872 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~19'
+ Info: 14: + IC(0.000 ns) + CELL(0.080 ns) = 4.952 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~21'
+ Info: 15: + IC(0.000 ns) + CELL(0.080 ns) = 5.032 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~23'
+ Info: 16: + IC(0.000 ns) + CELL(0.080 ns) = 5.112 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~25'
+ Info: 17: + IC(0.000 ns) + CELL(0.080 ns) = 5.192 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~27'
+ Info: 18: + IC(0.000 ns) + CELL(0.080 ns) = 5.272 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~29'
+ Info: 19: + IC(0.000 ns) + CELL(0.080 ns) = 5.352 ns; Loc. = LAB_X32_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~31'
+ Info: 20: + IC(0.098 ns) + CELL(0.080 ns) = 5.530 ns; Loc. = LAB_X32_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~33'
+ Info: 21: + IC(0.000 ns) + CELL(0.080 ns) = 5.610 ns; Loc. = LAB_X32_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~35'
+ Info: 22: + IC(0.000 ns) + CELL(0.080 ns) = 5.690 ns; Loc. = LAB_X32_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~37'
+ Info: 23: + IC(0.000 ns) + CELL(0.080 ns) = 5.770 ns; Loc. = LAB_X32_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~39'
+ Info: 24: + IC(0.000 ns) + CELL(0.080 ns) = 5.850 ns; Loc. = LAB_X32_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~41'
+ Info: 25: + IC(0.000 ns) + CELL(0.080 ns) = 5.930 ns; Loc. = LAB_X32_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~43'
+ Info: 26: + IC(0.000 ns) + CELL(0.080 ns) = 6.010 ns; Loc. = LAB_X32_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~45'
+ Info: 27: + IC(0.000 ns) + CELL(0.080 ns) = 6.090 ns; Loc. = LAB_X32_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~47'
+ Info: 28: + IC(0.000 ns) + CELL(0.080 ns) = 6.170 ns; Loc. = LAB_X32_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~49'
+ Info: 29: + IC(0.000 ns) + CELL(0.080 ns) = 6.250 ns; Loc. = LAB_X32_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~51'
+ Info: 30: + IC(0.000 ns) + CELL(0.080 ns) = 6.330 ns; Loc. = LAB_X32_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~53'
+ Info: 31: + IC(0.000 ns) + CELL(0.458 ns) = 6.788 ns; Loc. = LAB_X32_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|Add4~54'
+ Info: 32: + IC(0.388 ns) + CELL(0.521 ns) = 7.697 ns; Loc. = LAB_X33_Y15; Fanout = 4; COMB Node = 'Arkanoid:inst|platform2_position~29'
+ Info: 33: + IC(0.498 ns) + CELL(0.177 ns) = 8.372 ns; Loc. = LAB_X33_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan3~3'
+ Info: 34: + IC(0.498 ns) + CELL(0.178 ns) = 9.048 ns; Loc. = LAB_X33_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan3~4'
+ Info: 35: + IC(1.237 ns) + CELL(0.322 ns) = 10.607 ns; Loc. = LAB_X31_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst|LessThan3~10'
+ Info: 36: + IC(0.732 ns) + CELL(0.495 ns) = 11.834 ns; Loc. = LAB_X30_Y16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~1'
+ Info: 37: + IC(0.000 ns) + CELL(0.458 ns) = 12.292 ns; Loc. = LAB_X30_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|Add5~2'
+ Info: 38: + IC(0.745 ns) + CELL(0.521 ns) = 13.558 ns; Loc. = LAB_X31_Y13; Fanout = 16; COMB Node = 'Arkanoid:inst|platform2_position~48'
+ Info: 39: + IC(1.362 ns) + CELL(0.517 ns) = 15.437 ns; Loc. = LAB_X27_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst|Add7~3'
+ Info: 40: + IC(0.000 ns) + CELL(0.458 ns) = 15.895 ns; Loc. = LAB_X27_Y14; Fanout = 15; COMB Node = 'Arkanoid:inst|Add7~4'
+ Info: 41: + IC(0.709 ns) + CELL(0.517 ns) = 17.121 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~5'
+ Info: 42: + IC(0.000 ns) + CELL(0.080 ns) = 17.201 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~7'
+ Info: 43: + IC(0.000 ns) + CELL(0.080 ns) = 17.281 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~9'
+ Info: 44: + IC(0.000 ns) + CELL(0.080 ns) = 17.361 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~11'
+ Info: 45: + IC(0.000 ns) + CELL(0.080 ns) = 17.441 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~13'
+ Info: 46: + IC(0.000 ns) + CELL(0.080 ns) = 17.521 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~15'
+ Info: 47: + IC(0.000 ns) + CELL(0.080 ns) = 17.601 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~17'
+ Info: 48: + IC(0.000 ns) + CELL(0.080 ns) = 17.681 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~19'
+ Info: 49: + IC(0.000 ns) + CELL(0.080 ns) = 17.761 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~21'
+ Info: 50: + IC(0.000 ns) + CELL(0.080 ns) = 17.841 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~23'
+ Info: 51: + IC(0.000 ns) + CELL(0.080 ns) = 17.921 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~25'
+ Info: 52: + IC(0.000 ns) + CELL(0.080 ns) = 18.001 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~27'
+ Info: 53: + IC(0.000 ns) + CELL(0.080 ns) = 18.081 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~29'
+ Info: 54: + IC(0.000 ns) + CELL(0.080 ns) = 18.161 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~31'
+ Info: 55: + IC(0.098 ns) + CELL(0.080 ns) = 18.339 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~33'
+ Info: 56: + IC(0.000 ns) + CELL(0.080 ns) = 18.419 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~35'
+ Info: 57: + IC(0.000 ns) + CELL(0.080 ns) = 18.499 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~37'
+ Info: 58: + IC(0.000 ns) + CELL(0.080 ns) = 18.579 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~39'
+ Info: 59: + IC(0.000 ns) + CELL(0.080 ns) = 18.659 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~41'
+ Info: 60: + IC(0.000 ns) + CELL(0.080 ns) = 18.739 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~43'
+ Info: 61: + IC(0.000 ns) + CELL(0.080 ns) = 18.819 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~45'
+ Info: 62: + IC(0.000 ns) + CELL(0.080 ns) = 18.899 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~47'
+ Info: 63: + IC(0.000 ns) + CELL(0.080 ns) = 18.979 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~49'
+ Info: 64: + IC(0.000 ns) + CELL(0.080 ns) = 19.059 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~51'
+ Info: 65: + IC(0.000 ns) + CELL(0.080 ns) = 19.139 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~53'
+ Info: 66: + IC(0.000 ns) + CELL(0.080 ns) = 19.219 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~55'
+ Info: 67: + IC(0.000 ns) + CELL(0.080 ns) = 19.299 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~57'
+ Info: 68: + IC(0.000 ns) + CELL(0.080 ns) = 19.379 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~59'
+ Info: 69: + IC(0.000 ns) + CELL(0.080 ns) = 19.459 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan139~61'
+ Info: 70: + IC(0.000 ns) + CELL(0.458 ns) = 19.917 ns; Loc. = LAB_X26_Y13; Fanout = 3; COMB Node = 'Arkanoid:inst|LessThan139~62'
+ Info: 71: + IC(0.763 ns) + CELL(0.521 ns) = 21.201 ns; Loc. = LAB_X26_Y11; Fanout = 9; COMB Node = 'Arkanoid:inst|always2~5'
+ Info: 72: + IC(1.739 ns) + CELL(0.495 ns) = 23.435 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~1'
+ Info: 73: + IC(0.000 ns) + CELL(0.080 ns) = 23.515 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~3'
+ Info: 74: + IC(0.000 ns) + CELL(0.080 ns) = 23.595 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~5'
+ Info: 75: + IC(0.000 ns) + CELL(0.080 ns) = 23.675 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~7'
+ Info: 76: + IC(0.000 ns) + CELL(0.080 ns) = 23.755 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~9'
+ Info: 77: + IC(0.000 ns) + CELL(0.080 ns) = 23.835 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~11'
+ Info: 78: + IC(0.000 ns) + CELL(0.080 ns) = 23.915 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~13'
+ Info: 79: + IC(0.000 ns) + CELL(0.080 ns) = 23.995 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~15'
+ Info: 80: + IC(0.000 ns) + CELL(0.080 ns) = 24.075 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~17'
+ Info: 81: + IC(0.000 ns) + CELL(0.080 ns) = 24.155 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~19'
+ Info: 82: + IC(0.000 ns) + CELL(0.080 ns) = 24.235 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~21'
+ Info: 83: + IC(0.000 ns) + CELL(0.080 ns) = 24.315 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~23'
+ Info: 84: + IC(0.000 ns) + CELL(0.080 ns) = 24.395 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~25'
+ Info: 85: + IC(0.000 ns) + CELL(0.080 ns) = 24.475 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~27'
+ Info: 86: + IC(0.000 ns) + CELL(0.080 ns) = 24.555 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~29'
+ Info: 87: + IC(0.000 ns) + CELL(0.080 ns) = 24.635 ns; Loc. = LAB_X13_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~31'
+ Info: 88: + IC(0.098 ns) + CELL(0.080 ns) = 24.813 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~33'
+ Info: 89: + IC(0.000 ns) + CELL(0.080 ns) = 24.893 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~35'
+ Info: 90: + IC(0.000 ns) + CELL(0.080 ns) = 24.973 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~37'
+ Info: 91: + IC(0.000 ns) + CELL(0.080 ns) = 25.053 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~39'
+ Info: 92: + IC(0.000 ns) + CELL(0.080 ns) = 25.133 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~41'
+ Info: 93: + IC(0.000 ns) + CELL(0.080 ns) = 25.213 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~43'
+ Info: 94: + IC(0.000 ns) + CELL(0.080 ns) = 25.293 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~45'
+ Info: 95: + IC(0.000 ns) + CELL(0.080 ns) = 25.373 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~47'
+ Info: 96: + IC(0.000 ns) + CELL(0.080 ns) = 25.453 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~49'
+ Info: 97: + IC(0.000 ns) + CELL(0.080 ns) = 25.533 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~51'
+ Info: 98: + IC(0.000 ns) + CELL(0.080 ns) = 25.613 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~53'
+ Info: 99: + IC(0.000 ns) + CELL(0.080 ns) = 25.693 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~55'
+ Info: 100: + IC(0.000 ns) + CELL(0.080 ns) = 25.773 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~57'
+ Info: 101: + IC(0.000 ns) + CELL(0.080 ns) = 25.853 ns; Loc. = LAB_X13_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add9~59'
+ Info: 102: + IC(0.000 ns) + CELL(0.080 ns) = 25.933 ns; Loc. = LAB_X13_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst|Add9~61'
+ Info: 103: + IC(0.000 ns) + CELL(0.458 ns) = 26.391 ns; Loc. = LAB_X13_Y10; Fanout = 3; COMB Node = 'Arkanoid:inst|Add9~63'
+ Info: 104: + IC(0.745 ns) + CELL(0.521 ns) = 27.657 ns; Loc. = LAB_X12_Y13; Fanout = 4; COMB Node = 'Arkanoid:inst|lpm_divide:Mod0|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[0]~0'
+ Info: 105: + IC(1.381 ns) + CELL(0.495 ns) = 29.533 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~1'
+ Info: 106: + IC(0.000 ns) + CELL(0.080 ns) = 29.613 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3'
+ Info: 107: + IC(0.000 ns) + CELL(0.080 ns) = 29.693 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5'
+ Info: 108: + IC(0.000 ns) + CELL(0.080 ns) = 29.773 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7'
+ Info: 109: + IC(0.000 ns) + CELL(0.080 ns) = 29.853 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9'
+ Info: 110: + IC(0.000 ns) + CELL(0.080 ns) = 29.933 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11'
+ Info: 111: + IC(0.000 ns) + CELL(0.080 ns) = 30.013 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13'
+ Info: 112: + IC(0.000 ns) + CELL(0.080 ns) = 30.093 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15'
+ Info: 113: + IC(0.000 ns) + CELL(0.080 ns) = 30.173 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17'
+ Info: 114: + IC(0.000 ns) + CELL(0.080 ns) = 30.253 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19'
+ Info: 115: + IC(0.000 ns) + CELL(0.080 ns) = 30.333 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21'
+ Info: 116: + IC(0.000 ns) + CELL(0.080 ns) = 30.413 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23'
+ Info: 117: + IC(0.000 ns) + CELL(0.080 ns) = 30.493 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25'
+ Info: 118: + IC(0.000 ns) + CELL(0.080 ns) = 30.573 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27'
+ Info: 119: + IC(0.000 ns) + CELL(0.080 ns) = 30.653 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29'
+ Info: 120: + IC(0.098 ns) + CELL(0.080 ns) = 30.831 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31'
+ Info: 121: + IC(0.000 ns) + CELL(0.080 ns) = 30.911 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33'
+ Info: 122: + IC(0.000 ns) + CELL(0.080 ns) = 30.991 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35'
+ Info: 123: + IC(0.000 ns) + CELL(0.080 ns) = 31.071 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37'
+ Info: 124: + IC(0.000 ns) + CELL(0.080 ns) = 31.151 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39'
+ Info: 125: + IC(0.000 ns) + CELL(0.080 ns) = 31.231 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41'
+ Info: 126: + IC(0.000 ns) + CELL(0.080 ns) = 31.311 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43'
+ Info: 127: + IC(0.000 ns) + CELL(0.080 ns) = 31.391 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45'
+ Info: 128: + IC(0.000 ns) + CELL(0.080 ns) = 31.471 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47'
+ Info: 129: + IC(0.000 ns) + CELL(0.080 ns) = 31.551 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49'
+ Info: 130: + IC(0.000 ns) + CELL(0.080 ns) = 31.631 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51'
+ Info: 131: + IC(0.000 ns) + CELL(0.080 ns) = 31.711 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53'
+ Info: 132: + IC(0.000 ns) + CELL(0.080 ns) = 31.791 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55'
+ Info: 133: + IC(0.000 ns) + CELL(0.458 ns) = 32.249 ns; Loc. = LAB_X14_Y13; Fanout = 4; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~56'
+ Info: 134: + IC(1.984 ns) + CELL(0.517 ns) = 34.750 ns; Loc. = LAB_X21_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[1]~1'
+ Info: 135: + IC(0.000 ns) + CELL(0.080 ns) = 34.830 ns; Loc. = LAB_X21_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[2]~3'
+ Info: 136: + IC(0.000 ns) + CELL(0.080 ns) = 34.910 ns; Loc. = LAB_X21_Y21; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5'
+ Info: 137: + IC(0.000 ns) + CELL(0.458 ns) = 35.368 ns; Loc. = LAB_X21_Y21; Fanout = 14; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6'
+ Info: 138: + IC(0.732 ns) + CELL(0.177 ns) = 36.277 ns; Loc. = LAB_X22_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[18]~111'
+ Info: 139: + IC(0.498 ns) + CELL(0.495 ns) = 37.270 ns; Loc. = LAB_X22_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[1]~1'
+ Info: 140: + IC(0.000 ns) + CELL(0.080 ns) = 37.350 ns; Loc. = LAB_X22_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[2]~3'
+ Info: 141: + IC(0.000 ns) + CELL(0.080 ns) = 37.430 ns; Loc. = LAB_X22_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5'
+ Info: 142: + IC(0.000 ns) + CELL(0.080 ns) = 37.510 ns; Loc. = LAB_X22_Y21; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7'
+ Info: 143: + IC(0.000 ns) + CELL(0.458 ns) = 37.968 ns; Loc. = LAB_X22_Y21; Fanout = 17; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8'
+ Info: 144: + IC(1.089 ns) + CELL(0.177 ns) = 39.234 ns; Loc. = LAB_X21_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[24]~121'
+ Info: 145: + IC(1.089 ns) + CELL(0.495 ns) = 40.818 ns; Loc. = LAB_X22_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[1]~1'
+ Info: 146: + IC(0.000 ns) + CELL(0.080 ns) = 40.898 ns; Loc. = LAB_X22_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[2]~3'
+ Info: 147: + IC(0.000 ns) + CELL(0.080 ns) = 40.978 ns; Loc. = LAB_X22_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[3]~5'
+ Info: 148: + IC(0.000 ns) + CELL(0.080 ns) = 41.058 ns; Loc. = LAB_X22_Y21; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7'
+ Info: 149: + IC(0.000 ns) + CELL(0.080 ns) = 41.138 ns; Loc. = LAB_X22_Y21; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9'
+ Info: 150: + IC(0.000 ns) + CELL(0.458 ns) = 41.596 ns; Loc. = LAB_X22_Y21; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10'
+ Info: 151: + IC(1.397 ns) + CELL(0.177 ns) = 43.170 ns; Loc. = LAB_X20_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[30]~129'
+ Info: 152: + IC(0.732 ns) + CELL(0.495 ns) = 44.397 ns; Loc. = LAB_X21_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[1]~1'
+ Info: 153: + IC(0.000 ns) + CELL(0.080 ns) = 44.477 ns; Loc. = LAB_X21_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[2]~3'
+ Info: 154: + IC(0.000 ns) + CELL(0.080 ns) = 44.557 ns; Loc. = LAB_X21_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5'
+ Info: 155: + IC(0.000 ns) + CELL(0.080 ns) = 44.637 ns; Loc. = LAB_X21_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7'
+ Info: 156: + IC(0.000 ns) + CELL(0.080 ns) = 44.717 ns; Loc. = LAB_X21_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9'
+ Info: 157: + IC(0.000 ns) + CELL(0.458 ns) = 45.175 ns; Loc. = LAB_X21_Y17; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10'
+ Info: 158: + IC(1.058 ns) + CELL(0.177 ns) = 46.410 ns; Loc. = LAB_X16_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~137'
+ Info: 159: + IC(1.039 ns) + CELL(0.495 ns) = 47.944 ns; Loc. = LAB_X20_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1'
+ Info: 160: + IC(0.000 ns) + CELL(0.080 ns) = 48.024 ns; Loc. = LAB_X20_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3'
+ Info: 161: + IC(0.000 ns) + CELL(0.080 ns) = 48.104 ns; Loc. = LAB_X20_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5'
+ Info: 162: + IC(0.000 ns) + CELL(0.080 ns) = 48.184 ns; Loc. = LAB_X20_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7'
+ Info: 163: + IC(0.000 ns) + CELL(0.080 ns) = 48.264 ns; Loc. = LAB_X20_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9'
+ Info: 164: + IC(0.000 ns) + CELL(0.458 ns) = 48.722 ns; Loc. = LAB_X20_Y17; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10'
+ Info: 165: + IC(1.396 ns) + CELL(0.177 ns) = 50.295 ns; Loc. = LAB_X16_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[42]~145'
+ Info: 166: + IC(1.084 ns) + CELL(0.495 ns) = 51.874 ns; Loc. = LAB_X16_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[1]~1'
+ Info: 167: + IC(0.000 ns) + CELL(0.080 ns) = 51.954 ns; Loc. = LAB_X16_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[2]~3'
+ Info: 168: + IC(0.000 ns) + CELL(0.080 ns) = 52.034 ns; Loc. = LAB_X16_Y17; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5'
+ Info: 169: + IC(0.000 ns) + CELL(0.080 ns) = 52.114 ns; Loc. = LAB_X16_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7'
+ Info: 170: + IC(0.000 ns) + CELL(0.080 ns) = 52.194 ns; Loc. = LAB_X16_Y17; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9'
+ Info: 171: + IC(0.000 ns) + CELL(0.458 ns) = 52.652 ns; Loc. = LAB_X16_Y17; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10'
+ Info: 172: + IC(1.393 ns) + CELL(0.177 ns) = 54.222 ns; Loc. = LAB_X13_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[48]~153'
+ Info: 173: + IC(1.039 ns) + CELL(0.495 ns) = 55.756 ns; Loc. = LAB_X16_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[1]~1'
+ Info: 174: + IC(0.000 ns) + CELL(0.080 ns) = 55.836 ns; Loc. = LAB_X16_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[2]~3'
+ Info: 175: + IC(0.000 ns) + CELL(0.080 ns) = 55.916 ns; Loc. = LAB_X16_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[3]~5'
+ Info: 176: + IC(0.000 ns) + CELL(0.080 ns) = 55.996 ns; Loc. = LAB_X16_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7'
+ Info: 177: + IC(0.000 ns) + CELL(0.080 ns) = 56.076 ns; Loc. = LAB_X16_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9'
+ Info: 178: + IC(0.000 ns) + CELL(0.458 ns) = 56.534 ns; Loc. = LAB_X16_Y15; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10'
+ Info: 179: + IC(0.940 ns) + CELL(0.319 ns) = 57.793 ns; Loc. = LAB_X16_Y17; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[57]~339'
+ Info: 180: + IC(1.680 ns) + CELL(0.517 ns) = 59.990 ns; Loc. = LAB_X11_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7'
+ Info: 181: + IC(0.000 ns) + CELL(0.080 ns) = 60.070 ns; Loc. = LAB_X11_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9'
+ Info: 182: + IC(0.000 ns) + CELL(0.458 ns) = 60.528 ns; Loc. = LAB_X11_Y15; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10'
+ Info: 183: + IC(0.914 ns) + CELL(0.319 ns) = 61.761 ns; Loc. = LAB_X16_Y15; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[63]~341'
+ Info: 184: + IC(1.015 ns) + CELL(0.517 ns) = 63.293 ns; Loc. = LAB_X13_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7'
+ Info: 185: + IC(0.000 ns) + CELL(0.080 ns) = 63.373 ns; Loc. = LAB_X13_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9'
+ Info: 186: + IC(0.000 ns) + CELL(0.458 ns) = 63.831 ns; Loc. = LAB_X13_Y15; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10'
+ Info: 187: + IC(1.040 ns) + CELL(0.177 ns) = 65.048 ns; Loc. = LAB_X9_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[66]~177'
+ Info: 188: + IC(1.038 ns) + CELL(0.495 ns) = 66.581 ns; Loc. = LAB_X11_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[1]~1'
+ Info: 189: + IC(0.000 ns) + CELL(0.080 ns) = 66.661 ns; Loc. = LAB_X11_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3'
+ Info: 190: + IC(0.000 ns) + CELL(0.080 ns) = 66.741 ns; Loc. = LAB_X11_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5'
+ Info: 191: + IC(0.000 ns) + CELL(0.080 ns) = 66.821 ns; Loc. = LAB_X11_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7'
+ Info: 192: + IC(0.000 ns) + CELL(0.080 ns) = 66.901 ns; Loc. = LAB_X11_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9'
+ Info: 193: + IC(0.000 ns) + CELL(0.458 ns) = 67.359 ns; Loc. = LAB_X11_Y15; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10'
+ Info: 194: + IC(0.894 ns) + CELL(0.319 ns) = 68.572 ns; Loc. = LAB_X13_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[76]~344'
+ Info: 195: + IC(1.016 ns) + CELL(0.517 ns) = 70.105 ns; Loc. = LAB_X10_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[5]~9'
+ Info: 196: + IC(0.000 ns) + CELL(0.458 ns) = 70.563 ns; Loc. = LAB_X10_Y15; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[6]~10'
+ Info: 197: + IC(1.038 ns) + CELL(0.177 ns) = 71.778 ns; Loc. = LAB_X12_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[82]~186'
+ Info: 198: + IC(1.039 ns) + CELL(0.495 ns) = 73.312 ns; Loc. = LAB_X9_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9'
+ Info: 199: + IC(0.000 ns) + CELL(0.458 ns) = 73.770 ns; Loc. = LAB_X9_Y15; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10'
+ Info: 200: + IC(1.039 ns) + CELL(0.177 ns) = 74.986 ns; Loc. = LAB_X12_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[88]~194'
+ Info: 201: + IC(1.382 ns) + CELL(0.495 ns) = 76.863 ns; Loc. = LAB_X9_Y14; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9'
+ Info: 202: + IC(0.000 ns) + CELL(0.458 ns) = 77.321 ns; Loc. = LAB_X9_Y14; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10'
+ Info: 203: + IC(1.089 ns) + CELL(0.177 ns) = 78.587 ns; Loc. = LAB_X9_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[90]~209'
+ Info: 204: + IC(0.498 ns) + CELL(0.495 ns) = 79.580 ns; Loc. = LAB_X9_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[1]~1'
+ Info: 205: + IC(0.000 ns) + CELL(0.080 ns) = 79.660 ns; Loc. = LAB_X9_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[2]~3'
+ Info: 206: + IC(0.000 ns) + CELL(0.080 ns) = 79.740 ns; Loc. = LAB_X9_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5'
+ Info: 207: + IC(0.000 ns) + CELL(0.080 ns) = 79.820 ns; Loc. = LAB_X9_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7'
+ Info: 208: + IC(0.000 ns) + CELL(0.080 ns) = 79.900 ns; Loc. = LAB_X9_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9'
+ Info: 209: + IC(0.000 ns) + CELL(0.458 ns) = 80.358 ns; Loc. = LAB_X9_Y10; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10'
+ Info: 210: + IC(0.732 ns) + CELL(0.177 ns) = 81.267 ns; Loc. = LAB_X10_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[96]~217'
+ Info: 211: + IC(0.498 ns) + CELL(0.495 ns) = 82.260 ns; Loc. = LAB_X10_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[1]~1'
+ Info: 212: + IC(0.000 ns) + CELL(0.080 ns) = 82.340 ns; Loc. = LAB_X10_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[2]~3'
+ Info: 213: + IC(0.000 ns) + CELL(0.080 ns) = 82.420 ns; Loc. = LAB_X10_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5'
+ Info: 214: + IC(0.000 ns) + CELL(0.080 ns) = 82.500 ns; Loc. = LAB_X10_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7'
+ Info: 215: + IC(0.000 ns) + CELL(0.080 ns) = 82.580 ns; Loc. = LAB_X10_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9'
+ Info: 216: + IC(0.000 ns) + CELL(0.458 ns) = 83.038 ns; Loc. = LAB_X10_Y10; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10'
+ Info: 217: + IC(1.084 ns) + CELL(0.177 ns) = 84.299 ns; Loc. = LAB_X9_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~225'
+ Info: 218: + IC(0.498 ns) + CELL(0.495 ns) = 85.292 ns; Loc. = LAB_X9_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1'
+ Info: 219: + IC(0.000 ns) + CELL(0.080 ns) = 85.372 ns; Loc. = LAB_X9_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3'
+ Info: 220: + IC(0.000 ns) + CELL(0.080 ns) = 85.452 ns; Loc. = LAB_X9_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5'
+ Info: 221: + IC(0.000 ns) + CELL(0.080 ns) = 85.532 ns; Loc. = LAB_X9_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7'
+ Info: 222: + IC(0.000 ns) + CELL(0.080 ns) = 85.612 ns; Loc. = LAB_X9_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9'
+ Info: 223: + IC(0.000 ns) + CELL(0.458 ns) = 86.070 ns; Loc. = LAB_X9_Y12; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10'
+ Info: 224: + IC(1.038 ns) + CELL(0.177 ns) = 87.285 ns; Loc. = LAB_X11_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[108]~233'
+ Info: 225: + IC(0.498 ns) + CELL(0.495 ns) = 88.278 ns; Loc. = LAB_X11_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[1]~1'
+ Info: 226: + IC(0.000 ns) + CELL(0.080 ns) = 88.358 ns; Loc. = LAB_X11_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3'
+ Info: 227: + IC(0.000 ns) + CELL(0.080 ns) = 88.438 ns; Loc. = LAB_X11_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5'
+ Info: 228: + IC(0.000 ns) + CELL(0.080 ns) = 88.518 ns; Loc. = LAB_X11_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~7'
+ Info: 229: + IC(0.000 ns) + CELL(0.080 ns) = 88.598 ns; Loc. = LAB_X11_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[5]~9'
+ Info: 230: + IC(0.000 ns) + CELL(0.458 ns) = 89.056 ns; Loc. = LAB_X11_Y12; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[6]~10'
+ Info: 231: + IC(1.089 ns) + CELL(0.177 ns) = 90.322 ns; Loc. = LAB_X10_Y9; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[114]~241'
+ Info: 232: + IC(0.498 ns) + CELL(0.495 ns) = 91.315 ns; Loc. = LAB_X10_Y9; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[1]~1'
+ Info: 233: + IC(0.000 ns) + CELL(0.080 ns) = 91.395 ns; Loc. = LAB_X10_Y9; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[2]~3'
+ Info: 234: + IC(0.000 ns) + CELL(0.080 ns) = 91.475 ns; Loc. = LAB_X10_Y9; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[3]~5'
+ Info: 235: + IC(0.000 ns) + CELL(0.080 ns) = 91.555 ns; Loc. = LAB_X10_Y9; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[4]~7'
+ Info: 236: + IC(0.000 ns) + CELL(0.080 ns) = 91.635 ns; Loc. = LAB_X10_Y9; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9'
+ Info: 237: + IC(0.000 ns) + CELL(0.458 ns) = 92.093 ns; Loc. = LAB_X10_Y9; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10'
+ Info: 238: + IC(0.722 ns) + CELL(0.544 ns) = 93.359 ns; Loc. = LAB_X11_Y12; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~244'
+ Info: 239: + IC(1.066 ns) + CELL(0.517 ns) = 94.942 ns; Loc. = LAB_X11_Y9; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5'
+ Info: 240: + IC(0.000 ns) + CELL(0.080 ns) = 95.022 ns; Loc. = LAB_X11_Y9; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7'
+ Info: 241: + IC(0.000 ns) + CELL(0.080 ns) = 95.102 ns; Loc. = LAB_X11_Y9; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9'
+ Info: 242: + IC(0.000 ns) + CELL(0.458 ns) = 95.560 ns; Loc. = LAB_X11_Y9; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10'
+ Info: 243: + IC(0.365 ns) + CELL(0.544 ns) = 96.469 ns; Loc. = LAB_X10_Y9; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[128]~252'
+ Info: 244: + IC(1.017 ns) + CELL(0.517 ns) = 98.003 ns; Loc. = LAB_X14_Y9; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5'
+ Info: 245: + IC(0.000 ns) + CELL(0.080 ns) = 98.083 ns; Loc. = LAB_X14_Y9; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7'
+ Info: 246: + IC(0.000 ns) + CELL(0.080 ns) = 98.163 ns; Loc. = LAB_X14_Y9; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9'
+ Info: 247: + IC(0.000 ns) + CELL(0.458 ns) = 98.621 ns; Loc. = LAB_X14_Y9; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10'
+ Info: 248: + IC(0.681 ns) + CELL(0.544 ns) = 99.846 ns; Loc. = LAB_X11_Y9; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[134]~260'
+ Info: 249: + IC(1.017 ns) + CELL(0.517 ns) = 101.380 ns; Loc. = LAB_X15_Y9; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5'
+ Info: 250: + IC(0.000 ns) + CELL(0.080 ns) = 101.460 ns; Loc. = LAB_X15_Y9; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7'
+ Info: 251: + IC(0.000 ns) + CELL(0.080 ns) = 101.540 ns; Loc. = LAB_X15_Y9; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9'
+ Info: 252: + IC(0.000 ns) + CELL(0.458 ns) = 101.998 ns; Loc. = LAB_X15_Y9; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10'
+ Info: 253: + IC(0.375 ns) + CELL(0.544 ns) = 102.917 ns; Loc. = LAB_X14_Y9; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[140]~268'
+ Info: 254: + IC(1.060 ns) + CELL(0.517 ns) = 104.494 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5'
+ Info: 255: + IC(0.000 ns) + CELL(0.080 ns) = 104.574 ns; Loc. = LAB_X15_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7'
+ Info: 256: + IC(0.000 ns) + CELL(0.080 ns) = 104.654 ns; Loc. = LAB_X15_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9'
+ Info: 257: + IC(0.000 ns) + CELL(0.458 ns) = 105.112 ns; Loc. = LAB_X15_Y10; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10'
+ Info: 258: + IC(0.716 ns) + CELL(0.544 ns) = 106.372 ns; Loc. = LAB_X15_Y9; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~276'
+ Info: 259: + IC(1.060 ns) + CELL(0.517 ns) = 107.949 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5'
+ Info: 260: + IC(0.000 ns) + CELL(0.080 ns) = 108.029 ns; Loc. = LAB_X16_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7'
+ Info: 261: + IC(0.000 ns) + CELL(0.080 ns) = 108.109 ns; Loc. = LAB_X16_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9'
+ Info: 262: + IC(0.000 ns) + CELL(0.458 ns) = 108.567 ns; Loc. = LAB_X16_Y10; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10'
+ Info: 263: + IC(0.365 ns) + CELL(0.544 ns) = 109.476 ns; Loc. = LAB_X15_Y10; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[152]~284'
+ Info: 264: + IC(1.060 ns) + CELL(0.517 ns) = 111.053 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5'
+ Info: 265: + IC(0.000 ns) + CELL(0.080 ns) = 111.133 ns; Loc. = LAB_X16_Y11; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7'
+ Info: 266: + IC(0.000 ns) + CELL(0.080 ns) = 111.213 ns; Loc. = LAB_X16_Y11; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9'
+ Info: 267: + IC(0.000 ns) + CELL(0.458 ns) = 111.671 ns; Loc. = LAB_X16_Y11; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10'
+ Info: 268: + IC(0.706 ns) + CELL(0.544 ns) = 112.921 ns; Loc. = LAB_X16_Y10; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[158]~292'
+ Info: 269: + IC(1.050 ns) + CELL(0.517 ns) = 114.488 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5'
+ Info: 270: + IC(0.000 ns) + CELL(0.080 ns) = 114.568 ns; Loc. = LAB_X15_Y11; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7'
+ Info: 271: + IC(0.000 ns) + CELL(0.080 ns) = 114.648 ns; Loc. = LAB_X15_Y11; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9'
+ Info: 272: + IC(0.000 ns) + CELL(0.458 ns) = 115.106 ns; Loc. = LAB_X15_Y11; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10'
+ Info: 273: + IC(0.375 ns) + CELL(0.544 ns) = 116.025 ns; Loc. = LAB_X16_Y11; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[164]~300'
+ Info: 274: + IC(1.358 ns) + CELL(0.517 ns) = 117.900 ns; Loc. = LAB_X14_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5'
+ Info: 275: + IC(0.000 ns) + CELL(0.080 ns) = 117.980 ns; Loc. = LAB_X14_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7'
+ Info: 276: + IC(0.000 ns) + CELL(0.080 ns) = 118.060 ns; Loc. = LAB_X14_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9'
+ Info: 277: + IC(0.000 ns) + CELL(0.458 ns) = 118.518 ns; Loc. = LAB_X14_Y12; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10'
+ Info: 278: + IC(0.716 ns) + CELL(0.544 ns) = 119.778 ns; Loc. = LAB_X15_Y11; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[170]~308'
+ Info: 279: + IC(1.060 ns) + CELL(0.517 ns) = 121.355 ns; Loc. = LAB_X15_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5'
+ Info: 280: + IC(0.000 ns) + CELL(0.080 ns) = 121.435 ns; Loc. = LAB_X15_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7'
+ Info: 281: + IC(0.000 ns) + CELL(0.080 ns) = 121.515 ns; Loc. = LAB_X15_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9'
+ Info: 282: + IC(0.000 ns) + CELL(0.458 ns) = 121.973 ns; Loc. = LAB_X15_Y12; Fanout = 17; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10'
+ Info: 283: + IC(0.375 ns) + CELL(0.544 ns) = 122.892 ns; Loc. = LAB_X14_Y12; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~316'
+ Info: 284: + IC(1.024 ns) + CELL(0.517 ns) = 124.433 ns; Loc. = LAB_X16_Y12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5'
+ Info: 285: + IC(0.000 ns) + CELL(0.080 ns) = 124.513 ns; Loc. = LAB_X16_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7'
+ Info: 286: + IC(0.000 ns) + CELL(0.080 ns) = 124.593 ns; Loc. = LAB_X16_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9'
+ Info: 287: + IC(0.000 ns) + CELL(0.458 ns) = 125.051 ns; Loc. = LAB_X16_Y12; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10'
+ Info: 288: + IC(0.365 ns) + CELL(0.544 ns) = 125.960 ns; Loc. = LAB_X15_Y12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[182]~324'
+ Info: 289: + IC(1.060 ns) + CELL(0.517 ns) = 127.537 ns; Loc. = LAB_X16_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5'
+ Info: 290: + IC(0.000 ns) + CELL(0.080 ns) = 127.617 ns; Loc. = LAB_X16_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7'
+ Info: 291: + IC(0.000 ns) + CELL(0.080 ns) = 127.697 ns; Loc. = LAB_X16_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9'
+ Info: 292: + IC(0.000 ns) + CELL(0.458 ns) = 128.155 ns; Loc. = LAB_X16_Y13; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10'
+ Info: 293: + IC(1.369 ns) + CELL(0.517 ns) = 130.041 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~1'
+ Info: 294: + IC(0.000 ns) + CELL(0.080 ns) = 130.121 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~3'
+ Info: 295: + IC(0.000 ns) + CELL(0.080 ns) = 130.201 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~5'
+ Info: 296: + IC(0.000 ns) + CELL(0.080 ns) = 130.281 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~7'
+ Info: 297: + IC(0.000 ns) + CELL(0.080 ns) = 130.361 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~9'
+ Info: 298: + IC(0.000 ns) + CELL(0.080 ns) = 130.441 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~11'
+ Info: 299: + IC(0.000 ns) + CELL(0.080 ns) = 130.521 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~13'
+ Info: 300: + IC(0.000 ns) + CELL(0.080 ns) = 130.601 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~15'
+ Info: 301: + IC(0.000 ns) + CELL(0.080 ns) = 130.681 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~17'
+ Info: 302: + IC(0.000 ns) + CELL(0.080 ns) = 130.761 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~19'
+ Info: 303: + IC(0.000 ns) + CELL(0.080 ns) = 130.841 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~21'
+ Info: 304: + IC(0.000 ns) + CELL(0.080 ns) = 130.921 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~23'
+ Info: 305: + IC(0.000 ns) + CELL(0.080 ns) = 131.001 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~25'
+ Info: 306: + IC(0.000 ns) + CELL(0.080 ns) = 131.081 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~27'
+ Info: 307: + IC(0.000 ns) + CELL(0.080 ns) = 131.161 ns; Loc. = LAB_X18_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~29'
+ Info: 308: + IC(0.098 ns) + CELL(0.080 ns) = 131.339 ns; Loc. = LAB_X18_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~31'
+ Info: 309: + IC(0.000 ns) + CELL(0.080 ns) = 131.419 ns; Loc. = LAB_X18_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~33'
+ Info: 310: + IC(0.000 ns) + CELL(0.080 ns) = 131.499 ns; Loc. = LAB_X18_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~35'
+ Info: 311: + IC(0.000 ns) + CELL(0.080 ns) = 131.579 ns; Loc. = LAB_X18_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~37'
+ Info: 312: + IC(0.000 ns) + CELL(0.080 ns) = 131.659 ns; Loc. = LAB_X18_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~39'
+ Info: 313: + IC(0.000 ns) + CELL(0.080 ns) = 131.739 ns; Loc. = LAB_X18_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~41'
+ Info: 314: + IC(0.000 ns) + CELL(0.080 ns) = 131.819 ns; Loc. = LAB_X18_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~43'
+ Info: 315: + IC(0.000 ns) + CELL(0.080 ns) = 131.899 ns; Loc. = LAB_X18_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~45'
+ Info: 316: + IC(0.000 ns) + CELL(0.080 ns) = 131.979 ns; Loc. = LAB_X18_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~47'
+ Info: 317: + IC(0.000 ns) + CELL(0.080 ns) = 132.059 ns; Loc. = LAB_X18_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~49'
+ Info: 318: + IC(0.000 ns) + CELL(0.080 ns) = 132.139 ns; Loc. = LAB_X18_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~51'
+ Info: 319: + IC(0.000 ns) + CELL(0.458 ns) = 132.597 ns; Loc. = LAB_X18_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|op_1~52'
+ Info: 320: + IC(0.732 ns) + CELL(0.178 ns) = 133.507 ns; Loc. = LAB_X19_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Equal6~2'
+ Info: 321: + IC(0.131 ns) + CELL(0.545 ns) = 134.183 ns; Loc. = LAB_X19_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst|Equal6~3'
+ Info: 322: + IC(0.354 ns) + CELL(0.322 ns) = 134.859 ns; Loc. = LAB_X19_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst|Equal6~7'
+ Info: 323: + IC(1.034 ns) + CELL(0.544 ns) = 136.437 ns; Loc. = LAB_X15_Y13; Fanout = 5; COMB Node = 'Arkanoid:inst|Equal6~24'
+ Info: 324: + IC(0.131 ns) + CELL(0.545 ns) = 137.113 ns; Loc. = LAB_X15_Y13; Fanout = 4; COMB Node = 'Arkanoid:inst|WideNor0~4'
+ Info: 325: + IC(0.131 ns) + CELL(0.545 ns) = 137.789 ns; Loc. = LAB_X15_Y13; Fanout = 3; COMB Node = 'Arkanoid:inst|WideOr0~0'
+ Info: 326: + IC(0.723 ns) + CELL(0.521 ns) = 139.033 ns; Loc. = LAB_X10_Y13; Fanout = 1; COMB Node = 'Arkanoid:inst|high~8'
+ Info: 327: + IC(0.000 ns) + CELL(0.096 ns) = 139.129 ns; Loc. = LAB_X10_Y13; Fanout = 1; REG Node = 'Arkanoid:inst|hex3_[5]'
+ Info: Total cell delay = 67.965 ns ( 48.85 % )
+ Info: Total interconnect delay = 71.164 ns ( 51.15 % )
Info: Fitter routing operations beginning
-Info: Average interconnect usage is 2% of the available device resources
- Info: Peak interconnect usage is 9% of the available device resources in the region that extends from location X25_Y14 to location X37_Y27
-Info: Fitter routing operations ending: elapsed time is 00:00:02
+Info: Average interconnect usage is 13% of the available device resources
+ Info: Peak interconnect usage is 26% of the available device resources in the region that extends from location X25_Y14 to location X37_Y27
+Info: Fitter routing operations ending: elapsed time is 00:00:08
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
@@ -1641,6 +1663,34 @@ Warning: Found 50 output pins without output pin load capacitance assignment
Info: Pin "green[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "green[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "green[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex0[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex0[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex0[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex0[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex0[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex0[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex0[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex1[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex1[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex1[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex1[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex1[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex1[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex1[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex2[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex2[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex2[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex2[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex2[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex2[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex2[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex3[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex3[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex3[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex3[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex3[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex3[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "hex3[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "led[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "led[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "led[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
@@ -1649,51 +1699,23 @@ Warning: Found 50 output pins without output pin load capacitance assignment
Info: Pin "led[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "led[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "led[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led1[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led1[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led1[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led1[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led1[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led1[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led1[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led2[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led2[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led2[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led2[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led2[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led2[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led2[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led3[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led3[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led3[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led3[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led3[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led3[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led3[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led4[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led4[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led4[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led4[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led4[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led4[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "led4[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "red[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "red[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "red[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "red[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
-Info: Generated suppressed messages file C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/myArkanoid.fit.smsg
+Info: Generated suppressed messages file G:/Verilog/Arkanoid2PDE1/myArkanoid.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
- Info: Peak virtual memory: 237 megabytes
- Info: Processing ended: Mon May 21 19:54:33 2012
- Info: Elapsed time: 00:00:12
- Info: Total CPU time (on all processors): 00:00:14
+ Info: Peak virtual memory: 266 megabytes
+ Info: Processing ended: Mon May 28 14:22:27 2012
+ Info: Elapsed time: 00:00:28
+ Info: Total CPU time (on all processors): 00:00:31
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
-The suppressed messages can be found in C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/myArkanoid.fit.smsg.
+The suppressed messages can be found in G:/Verilog/Arkanoid2PDE1/myArkanoid.fit.smsg.
diff --git a/myArkanoid.fit.summary b/myArkanoid.fit.summary
index 6819d17..d26dca0 100644
--- a/myArkanoid.fit.summary
+++ b/myArkanoid.fit.summary
@@ -1,14 +1,14 @@
-Fitter Status : Successful - Mon May 21 19:54:32 2012
+Fitter Status : Successful - Mon May 28 14:22:24 2012
Quartus II Version : 9.1 Build 222 10/21/2009 SJ Full Version
Revision Name : myArkanoid
Top-level Entity Name : TotalScheme
Family : Cyclone II
Device : EP2C20F484C7
Timing Models : Final
-Total logic elements : 1,806 / 18,752 ( 10 % )
- Total combinational functions : 1,793 / 18,752 ( 10 % )
- Dedicated logic registers : 151 / 18,752 ( < 1 % )
-Total registers : 151
+Total logic elements : 7,148 / 18,752 ( 38 % )
+ Total combinational functions : 7,096 / 18,752 ( 38 % )
+ Dedicated logic registers : 1,086 / 18,752 ( 6 % )
+Total registers : 1086
Total pins : 55 / 315 ( 17 % )
Total virtual pins : 0
Total memory bits : 0 / 239,616 ( 0 % )
diff --git a/myArkanoid.flow.rpt b/myArkanoid.flow.rpt
index 6a08c48..52c6d7b 100644
--- a/myArkanoid.flow.rpt
+++ b/myArkanoid.flow.rpt
@@ -1,5 +1,5 @@
Flow report for myArkanoid
-Mon May 21 19:54:43 2012
+Mon May 28 14:22:37 2012
Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version
@@ -38,7 +38,7 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+------------------------------------------+
-; Flow Status ; Successful - Mon May 21 19:54:41 2012 ;
+; Flow Status ; Successful - Mon May 28 14:22:35 2012 ;
; Quartus II Version ; 9.1 Build 222 10/21/2009 SJ Full Version ;
; Revision Name ; myArkanoid ;
; Top-level Entity Name ; TotalScheme ;
@@ -46,10 +46,10 @@ applicable agreement for further details.
; Device ; EP2C20F484C7 ;
; Timing Models ; Final ;
; Met timing requirements ; Yes ;
-; Total logic elements ; 1,806 / 18,752 ( 10 % ) ;
-; Total combinational functions ; 1,793 / 18,752 ( 10 % ) ;
-; Dedicated logic registers ; 151 / 18,752 ( < 1 % ) ;
-; Total registers ; 151 ;
+; Total logic elements ; 7,148 / 18,752 ( 38 % ) ;
+; Total combinational functions ; 7,096 / 18,752 ( 38 % ) ;
+; Dedicated logic registers ; 1,086 / 18,752 ( 6 % ) ;
+; Total registers ; 1086 ;
; Total pins ; 55 / 315 ( 17 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 239,616 ( 0 % ) ;
@@ -63,7 +63,7 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
-; Start date & time ; 05/21/2012 19:54:04 ;
+; Start date & time ; 05/28/2012 14:18:58 ;
; Main task ; Compilation ;
; Revision Name ; myArkanoid ;
+-------------------+---------------------+
@@ -74,7 +74,7 @@ applicable agreement for further details.
+------------------------+-----------------------------------------------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+------------------------+-----------------------------------------------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID ; 1097476773127.133761564404376 ; -- ; -- ; -- ;
+; COMPILER_SIGNATURE_ID ; 1097476773127.133820033707144 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; MISC_FILE ; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/myArkanoid/myArkanoid.dpf ; -- ; -- ; -- ;
@@ -90,11 +90,11 @@ applicable agreement for further details.
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:15 ; 1.0 ; 204 MB ; 00:00:16 ;
-; Fitter ; 00:00:11 ; 1.2 ; 237 MB ; 00:00:13 ;
-; Assembler ; 00:00:03 ; 1.0 ; 207 MB ; 00:00:04 ;
-; Classic Timing Analyzer ; 00:00:02 ; 1.0 ; 151 MB ; 00:00:02 ;
-; Total ; 00:00:31 ; -- ; -- ; 00:00:35 ;
+; Analysis & Synthesis ; 00:03:01 ; 1.0 ; 227 MB ; 00:03:05 ;
+; Fitter ; 00:00:25 ; 1.2 ; 266 MB ; 00:00:28 ;
+; Assembler ; 00:00:03 ; 1.0 ; 219 MB ; 00:00:02 ;
+; Classic Timing Analyzer ; 00:00:03 ; 1.0 ; 195 MB ; 00:00:04 ;
+; Total ; 00:03:32 ; -- ; -- ; 00:03:39 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
diff --git a/myArkanoid.map.rpt b/myArkanoid.map.rpt
index 7e1d33b..e2a184b 100644
--- a/myArkanoid.map.rpt
+++ b/myArkanoid.map.rpt
@@ -1,5 +1,5 @@
Analysis & Synthesis report for myArkanoid
-Mon May 21 19:54:20 2012
+Mon May 28 14:21:58 2012
Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version
@@ -13,14 +13,19 @@ Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
- 8. Registers Removed During Synthesis
- 9. General Register Statistics
- 10. Inverted Register Statistics
- 11. Multiplexer Restructuring Statistics (Restructuring Performed)
- 12. Parameter Settings for User Entity Instance: Arkanoid:inst
- 13. Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Div0
- 14. Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Div1
- 15. Analysis & Synthesis Messages
+ 8. State Machine - |TotalScheme|Arkanoid:inst|ball_direction
+ 9. Registers Removed During Synthesis
+ 10. General Register Statistics
+ 11. Inverted Register Statistics
+ 12. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 13. Parameter Settings for User Entity Instance: Arkanoid:inst
+ 14. Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Div3
+ 15. Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Div2
+ 16. Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Mod1
+ 17. Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Div1
+ 18. Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Mod0
+ 19. Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Div0
+ 20. Analysis & Synthesis Messages
@@ -46,15 +51,15 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Mon May 21 19:54:20 2012 ;
+; Analysis & Synthesis Status ; Successful - Mon May 28 14:21:58 2012 ;
; Quartus II Version ; 9.1 Build 222 10/21/2009 SJ Full Version ;
; Revision Name ; myArkanoid ;
; Top-level Entity Name ; TotalScheme ;
; Family ; Cyclone II ;
-; Total logic elements ; 1,810 ;
-; Total combinational functions ; 1,793 ;
-; Dedicated logic registers ; 151 ;
-; Total registers ; 151 ;
+; Total logic elements ; 7,146 ;
+; Total combinational functions ; 7,096 ;
+; Dedicated logic registers ; 1,086 ;
+; Total registers ; 1086 ;
; Total pins ; 55 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
@@ -158,51 +163,61 @@ applicable agreement for further details.
+----------------------------+-------------+
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
-+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------+
-; TotalScheme.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/TotalScheme.bdf ;
-; Arkanoid.v ; yes ; User Verilog HDL File ; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/Arkanoid.v ;
-; lpm_divide.tdf ; yes ; Megafunction ; c:/quartus/quartus/libraries/megafunctions/lpm_divide.tdf ;
-; db/lpm_divide_8so.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/db/lpm_divide_8so.tdf ;
-; db/abs_divider_lbg.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/db/abs_divider_lbg.tdf ;
-; db/alt_u_div_m2f.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/db/alt_u_div_m2f.tdf ;
-; db/add_sub_lkc.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/db/add_sub_lkc.tdf ;
-; db/add_sub_mkc.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/db/add_sub_mkc.tdf ;
-; db/lpm_abs_hq9.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/db/lpm_abs_hq9.tdf ;
-; db/lpm_abs_0s9.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/db/lpm_abs_0s9.tdf ;
-+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------+
++-----------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+
+; debouncer.v ; yes ; User Verilog HDL File ; G:/Verilog/Arkanoid2PDE1/debouncer.v ;
+; TotalScheme.bdf ; yes ; User Block Diagram/Schematic File ; G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf ;
+; Arkanoid.v ; yes ; User Verilog HDL File ; G:/Verilog/Arkanoid2PDE1/Arkanoid.v ;
+; arkanoid_header.v ; yes ; User Verilog HDL File ; G:/Verilog/Arkanoid2PDE1/arkanoid_header.v ;
+; int_to_digital.v ; yes ; User Verilog HDL File ; G:/Verilog/Arkanoid2PDE1/int_to_digital.v ;
+; vga_sync.v ; yes ; User Verilog HDL File ; G:/Verilog/Arkanoid2PDE1/vga_sync.v ;
+; ClockDivider.v ; yes ; User Verilog HDL File ; G:/Verilog/Arkanoid2PDE1/ClockDivider.v ;
+; lpm_divide.tdf ; yes ; Megafunction ; c:/quartus/quartus/libraries/megafunctions/lpm_divide.tdf ;
+; db/lpm_divide_8so.tdf ; yes ; Auto-Generated Megafunction ; G:/Verilog/Arkanoid2PDE1/db/lpm_divide_8so.tdf ;
+; db/abs_divider_lbg.tdf ; yes ; Auto-Generated Megafunction ; G:/Verilog/Arkanoid2PDE1/db/abs_divider_lbg.tdf ;
+; db/alt_u_div_m2f.tdf ; yes ; Auto-Generated Megafunction ; G:/Verilog/Arkanoid2PDE1/db/alt_u_div_m2f.tdf ;
+; db/add_sub_lkc.tdf ; yes ; Auto-Generated Megafunction ; G:/Verilog/Arkanoid2PDE1/db/add_sub_lkc.tdf ;
+; db/add_sub_mkc.tdf ; yes ; Auto-Generated Megafunction ; G:/Verilog/Arkanoid2PDE1/db/add_sub_mkc.tdf ;
+; db/lpm_abs_hq9.tdf ; yes ; Auto-Generated Megafunction ; G:/Verilog/Arkanoid2PDE1/db/lpm_abs_hq9.tdf ;
+; db/lpm_abs_0s9.tdf ; yes ; Auto-Generated Megafunction ; G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf ;
+; db/lpm_divide_ako.tdf ; yes ; Auto-Generated Megafunction ; G:/Verilog/Arkanoid2PDE1/db/lpm_divide_ako.tdf ;
+; db/abs_divider_kbg.tdf ; yes ; Auto-Generated Megafunction ; G:/Verilog/Arkanoid2PDE1/db/abs_divider_kbg.tdf ;
+; db/alt_u_div_k2f.tdf ; yes ; Auto-Generated Megafunction ; G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf ;
+; db/lpm_abs_gq9.tdf ; yes ; Auto-Generated Megafunction ; G:/Verilog/Arkanoid2PDE1/db/lpm_abs_gq9.tdf ;
+; db/lpm_divide_7so.tdf ; yes ; Auto-Generated Megafunction ; G:/Verilog/Arkanoid2PDE1/db/lpm_divide_7so.tdf ;
++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+
-+-----------------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+-------------------------+
-; Resource ; Usage ;
-+---------------------------------------------+-------------------------+
-; Estimated Total logic elements ; 1,810 ;
-; ; ;
-; Total combinational functions ; 1793 ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 561 ;
-; -- 3 input functions ; 452 ;
-; -- <=2 input functions ; 780 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 1147 ;
-; -- arithmetic mode ; 646 ;
-; ; ;
-; Total registers ; 151 ;
-; -- Dedicated logic registers ; 151 ;
-; -- I/O registers ; 0 ;
-; ; ;
-; I/O pins ; 55 ;
-; Maximum fan-out node ; Arkanoid:inst|clk25MHz_ ;
-; Maximum fan-out ; 151 ;
-; Total fan-out ; 5397 ;
-; Average fan-out ; 2.70 ;
-+---------------------------------------------+-------------------------+
++----------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++---------------------------------------------+------------------------------+
+; Resource ; Usage ;
++---------------------------------------------+------------------------------+
+; Estimated Total logic elements ; 7,146 ;
+; ; ;
+; Total combinational functions ; 7096 ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 2860 ;
+; -- 3 input functions ; 2246 ;
+; -- <=2 input functions ; 1990 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 5409 ;
+; -- arithmetic mode ; 1687 ;
+; ; ;
+; Total registers ; 1086 ;
+; -- Dedicated logic registers ; 1086 ;
+; -- I/O registers ; 0 ;
+; ; ;
+; I/O pins ; 55 ;
+; Maximum fan-out node ; ClockDivider:inst1|clk25MHz_ ;
+; Maximum fan-out ; 1086 ;
+; Total fan-out ; 24111 ;
+; Average fan-out ; 2.93 ;
++---------------------------------------------+------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -210,30 +225,168 @@ applicable agreement for further details.
+------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------+--------------+
-; |TotalScheme ; 1793 (0) ; 151 (0) ; 0 ; 0 ; 0 ; 0 ; 55 ; 0 ; |TotalScheme ; work ;
-; |Arkanoid:inst| ; 1793 (765) ; 151 (151) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst ; ;
-; |lpm_divide:Div0| ; 475 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0 ; ;
-; |lpm_divide_8so:auto_generated| ; 475 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated ; ;
-; |abs_divider_lbg:divider| ; 475 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider ; ;
-; |alt_u_div_m2f:divider| ; 433 (433) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider ; ;
-; |lpm_abs_0s9:my_abs_num| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num ; ;
-; |lpm_divide:Div1| ; 553 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1 ; ;
-; |lpm_divide_8so:auto_generated| ; 553 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated ; ;
-; |abs_divider_lbg:divider| ; 553 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider ; ;
-; |alt_u_div_m2f:divider| ; 511 (511) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider ; ;
-; |lpm_abs_0s9:my_abs_num| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num ; ;
+; |TotalScheme ; 7096 (0) ; 1086 (0) ; 0 ; 0 ; 0 ; 0 ; 55 ; 0 ; |TotalScheme ; work ;
+; |Arkanoid:inst| ; 7079 (3940) ; 1049 (1049) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst ; ;
+; |lpm_divide:Div0| ; 515 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0 ; ;
+; |lpm_divide_7so:auto_generated| ; 515 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated ; ;
+; |abs_divider_kbg:divider| ; 515 (35) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider ; ;
+; |alt_u_div_k2f:divider| ; 449 (449) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider ; ;
+; |lpm_abs_0s9:my_abs_num| ; 31 (31) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num ; ;
+; |lpm_divide:Div1| ; 515 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1 ; ;
+; |lpm_divide_7so:auto_generated| ; 515 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_7so:auto_generated ; ;
+; |abs_divider_kbg:divider| ; 515 (35) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_7so:auto_generated|abs_divider_kbg:divider ; ;
+; |alt_u_div_k2f:divider| ; 449 (449) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider ; ;
+; |lpm_abs_0s9:my_abs_num| ; 31 (31) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_7so:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num ; ;
+; |lpm_divide:Div2| ; 553 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div2 ; ;
+; |lpm_divide_8so:auto_generated| ; 553 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div2|lpm_divide_8so:auto_generated ; ;
+; |abs_divider_lbg:divider| ; 553 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div2|lpm_divide_8so:auto_generated|abs_divider_lbg:divider ; ;
+; |alt_u_div_m2f:divider| ; 511 (511) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div2|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider ; ;
+; |lpm_abs_0s9:my_abs_num| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div2|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num ; ;
+; |lpm_divide:Div3| ; 553 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div3 ; ;
+; |lpm_divide_8so:auto_generated| ; 553 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div3|lpm_divide_8so:auto_generated ; ;
+; |abs_divider_lbg:divider| ; 553 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div3|lpm_divide_8so:auto_generated|abs_divider_lbg:divider ; ;
+; |alt_u_div_m2f:divider| ; 511 (511) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div3|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider ; ;
+; |lpm_abs_0s9:my_abs_num| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div3|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num ; ;
+; |lpm_divide:Mod0| ; 502 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Mod0 ; ;
+; |lpm_divide_ako:auto_generated| ; 502 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Mod0|lpm_divide_ako:auto_generated ; ;
+; |abs_divider_kbg:divider| ; 502 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Mod0|lpm_divide_ako:auto_generated|abs_divider_kbg:divider ; ;
+; |alt_u_div_k2f:divider| ; 459 (459) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Mod0|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider ; ;
+; |lpm_abs_0s9:my_abs_num| ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Mod0|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num ; ;
+; |lpm_divide:Mod1| ; 501 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Mod1 ; ;
+; |lpm_divide_ako:auto_generated| ; 501 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated ; ;
+; |abs_divider_kbg:divider| ; 501 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider ; ;
+; |alt_u_div_k2f:divider| ; 459 (459) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider ; ;
+; |lpm_abs_0s9:my_abs_num| ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num ; ;
+; |ClockDivider:inst1| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|ClockDivider:inst1 ; ;
+; |Debouncer:inst2| ; 4 (4) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Debouncer:inst2 ; ;
+; |Debouncer:inst3| ; 4 (4) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Debouncer:inst3 ; ;
+; |Debouncer:inst4| ; 4 (4) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Debouncer:inst4 ; ;
+; |Debouncer:inst5| ; 4 (4) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Debouncer:inst5 ; ;
+------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-+--------------------------------------------------------------------------------+
-; Registers Removed During Synthesis ;
-+---------------------------------------+----------------------------------------+
-; Register name ; Reason for Removal ;
-+---------------------------------------+----------------------------------------+
-; Arkanoid:inst|green_[0..1] ; Stuck at GND due to stuck port data_in ;
-; Total Number of Removed Registers = 2 ; ;
-+---------------------------------------+----------------------------------------+
+Encoding Type: One-Hot
++-------------------------------------------------------------------------------------------------------------------------------------+
+; State Machine - |TotalScheme|Arkanoid:inst|ball_direction ;
++---------------------------+---------------------------+--------------------------+-------------------------+------------------------+
+; Name ; ball_direction.RIGHT_DOWN ; ball_direction.LEFT_DOWN ; ball_direction.RIGHT_UP ; ball_direction.LEFT_UP ;
++---------------------------+---------------------------+--------------------------+-------------------------+------------------------+
+; ball_direction.LEFT_UP ; 0 ; 0 ; 0 ; 0 ;
+; ball_direction.RIGHT_UP ; 0 ; 0 ; 1 ; 1 ;
+; ball_direction.LEFT_DOWN ; 0 ; 1 ; 0 ; 1 ;
+; ball_direction.RIGHT_DOWN ; 1 ; 0 ; 0 ; 1 ;
++---------------------------+---------------------------+--------------------------+-------------------------+------------------------+
+
+
++----------------------------------------------------------------------------------+
+; Registers Removed During Synthesis ;
++-----------------------------------------+----------------------------------------+
+; Register name ; Reason for Removal ;
++-----------------------------------------+----------------------------------------+
+; Arkanoid:inst|field[22][0][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][1][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][2][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][3][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][4][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][5][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][6][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][7][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][8][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][9][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][10][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][11][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][12][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][13][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][14][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][15][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][16][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][17][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][18][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][19][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][20][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][21][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][22][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][23][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][24][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][25][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][26][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][27][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][28][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][29][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][30][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[22][31][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][0][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][1][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][2][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][3][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][4][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][5][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][6][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][7][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][8][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][9][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][10][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][11][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][12][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][13][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][14][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][15][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][16][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][17][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][18][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][19][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][20][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][21][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][22][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][23][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][24][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][25][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][26][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][27][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][28][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][29][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][30][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[21][31][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][0][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][1][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][2][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][3][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][4][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][5][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][6][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][7][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][8][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][9][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][10][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][11][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][12][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][13][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][14][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][15][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][16][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][17][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][18][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][19][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][20][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][21][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][22][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][23][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][24][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][25][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][26][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][27][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][28][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][29][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][30][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[20][31][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[19][0][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[19][1][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[19][2][1] ; Stuck at GND due to stuck port data_in ;
+; Arkanoid:inst|field[19][3][1] ; Stuck at GND due to stuck port data_in ;
+; Total Number of Removed Registers = 706 ; ;
++-----------------------------------------+----------------------------------------+
+* Table truncated at 100 items. To change the number of removed registers reported, set the "Number of Removed Registers Reported" option under Assignments->Settings->Analysis and Synthesis Settings->More Settings
+------------------------------------------------------+
@@ -241,12 +394,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
-; Total registers ; 151 ;
-; Number of registers using Synchronous Clear ; 32 ;
+; Total registers ; 1086 ;
+; Number of registers using Synchronous Clear ; 65 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 12 ;
+; Number of registers using Clock Enable ; 44 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
@@ -256,11 +409,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
-; Arkanoid:inst|platform2_position[3] ; 2 ;
-; Arkanoid:inst|platform2_position[2] ; 2 ;
-; Arkanoid:inst|platform1_position[2] ; 2 ;
-; Arkanoid:inst|platform1_position[3] ; 2 ;
-; Total number of inverted registers = 4 ; ;
+; Arkanoid:inst|platform2_position[3] ; 3 ;
+; Arkanoid:inst|platform2_position[2] ; 3 ;
+; Arkanoid:inst|ball_x[4] ; 2 ;
+; Arkanoid:inst|platform1_position[3] ; 3 ;
+; Arkanoid:inst|platform1_position[2] ; 3 ;
+; Arkanoid:inst|ball_y[2] ; 3 ;
+; Arkanoid:inst|ball_y[4] ; 4 ;
+; Arkanoid:inst|ball_y[1] ; 2 ;
+; Arkanoid:inst|ball_y[0] ; 2 ;
+; Total number of inverted registers = 9 ; ;
+----------------------------------------+---------+
@@ -269,10 +427,722 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+
-; 3:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; No ; |TotalScheme|Arkanoid:inst|platform1_position ;
-; 3:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; No ; |TotalScheme|Arkanoid:inst|platform2_position ;
-; 4:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; No ; |TotalScheme|Arkanoid:inst|platform1_position ;
-; 4:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; No ; |TotalScheme|Arkanoid:inst|platform2_position ;
+; 3:1 ; 59 bits ; 118 LEs ; 59 LEs ; 59 LEs ; Yes ; |TotalScheme|Arkanoid:inst|ball_y[22] ;
+; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |TotalScheme|Arkanoid:inst|ball_y[4] ;
+; 4:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; No ; |TotalScheme|Arkanoid:inst|platform2_position ;
+; 5:1 ; 32 bits ; 96 LEs ; 64 LEs ; 32 LEs ; No ; |TotalScheme|Arkanoid:inst|platform2_position ;
+; 5:1 ; 32 bits ; 96 LEs ; 64 LEs ; 32 LEs ; No ; |TotalScheme|Arkanoid:inst|platform1_position ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |TotalScheme|Arkanoid:inst|field ;
+; 5:1 ; 32 bits ; 96 LEs ; 32 LEs ; 64 LEs ; No ; |TotalScheme|Arkanoid:inst|platform2_position ;
+; 9:1 ; 32 bits ; 192 LEs ; 32 LEs ; 160 LEs ; No ; |TotalScheme|Arkanoid:inst|player1_score ;
+; 9:1 ; 32 bits ; 192 LEs ; 32 LEs ; 160 LEs ; No ; |TotalScheme|Arkanoid:inst|player2_score ;
+; 6:1 ; 32 bits ; 128 LEs ; 64 LEs ; 64 LEs ; No ; |TotalScheme|Arkanoid:inst|platform1_position ;
+; 7:1 ; 68 bits ; 272 LEs ; 68 LEs ; 204 LEs ; No ; |TotalScheme|Arkanoid:inst|ball_x ;
+; 12:1 ; 32 bits ; 256 LEs ; 32 LEs ; 224 LEs ; No ; |TotalScheme|Arkanoid:inst|Selector37 ;
+; 12:1 ; 32 bits ; 256 LEs ; 32 LEs ; 224 LEs ; No ; |TotalScheme|Arkanoid:inst|Selector3 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+
@@ -281,16 +1151,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+------------------+-------+---------------------------------+
; Parameter Name ; Value ; Type ;
+------------------+-------+---------------------------------+
-; SCREEN_WIDTH ; 640 ; Signed Integer ;
-; SCREEN_HEIGHT ; 480 ; Signed Integer ;
; CELL_SIZE ; 20 ; Signed Integer ;
; BALL_SIZE ; 1 ; Signed Integer ;
-; BALL_SPEED ; 2 ; Signed Integer ;
-; PLATFORM_WIDTH ; 8 ; Signed Integer ;
-; PLATFORM_SPEED ; 1 ; Signed Integer ;
-; BK_COLOR_R ; 0000 ; Unsigned Binary ;
-; BK_COLOR_G ; 0000 ; Unsigned Binary ;
-; BK_COLOR_B ; 0000 ; Unsigned Binary ;
+; BALL_SPEED ; 3 ; Signed Integer ;
+; PLATFORM_WIDTH ; 7 ; Signed Integer ;
+; BK_COLOR_R ; 1111 ; Unsigned Binary ;
+; BK_COLOR_G ; 1111 ; Unsigned Binary ;
+; BK_COLOR_B ; 1111 ; Unsigned Binary ;
; STABLE_COLOR_R ; 0011 ; Unsigned Binary ;
; STABLE_COLOR_G ; 1100 ; Unsigned Binary ;
; STABLE_COLOR_B ; 0110 ; Unsigned Binary ;
@@ -305,7 +1172,7 @@ Note: In order to hide this table in the UI and the text report file, please set
+--------------------------------------------------------------------------------+
-; Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Div0 ;
+; Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Div3 ;
+------------------------+----------------+--------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+----------------+--------------------------------------+
@@ -327,19 +1194,111 @@ Note: In order to hide this table in the UI and the text report file, please set
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
++--------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Div2 ;
++------------------------+----------------+--------------------------------------+
+; Parameter Name ; Value ; Type ;
++------------------------+----------------+--------------------------------------+
+; LPM_WIDTHN ; 32 ; Untyped ;
+; LPM_WIDTHD ; 6 ; Untyped ;
+; LPM_NREPRESENTATION ; SIGNED ; Untyped ;
+; LPM_DREPRESENTATION ; SIGNED ; Untyped ;
+; LPM_PIPELINE ; 0 ; Untyped ;
+; LPM_REMAINDERPOSITIVE ; FALSE ; Untyped ;
+; MAXIMIZE_SPEED ; 5 ; Untyped ;
+; CBXI_PARAMETER ; lpm_divide_8so ; Untyped ;
+; CARRY_CHAIN ; MANUAL ; Untyped ;
+; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
+; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
+; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
+; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
+; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
++------------------------+----------------+--------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Mod1 ;
++------------------------+----------------+--------------------------------------+
+; Parameter Name ; Value ; Type ;
++------------------------+----------------+--------------------------------------+
+; LPM_WIDTHN ; 32 ; Untyped ;
+; LPM_WIDTHD ; 5 ; Untyped ;
+; LPM_NREPRESENTATION ; SIGNED ; Untyped ;
+; LPM_DREPRESENTATION ; SIGNED ; Untyped ;
+; LPM_PIPELINE ; 0 ; Untyped ;
+; LPM_REMAINDERPOSITIVE ; FALSE ; Untyped ;
+; MAXIMIZE_SPEED ; 5 ; Untyped ;
+; CBXI_PARAMETER ; lpm_divide_ako ; Untyped ;
+; CARRY_CHAIN ; MANUAL ; Untyped ;
+; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
+; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
+; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
+; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
+; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
++------------------------+----------------+--------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
+--------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Div1 ;
+------------------------+----------------+--------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+----------------+--------------------------------------+
; LPM_WIDTHN ; 32 ; Untyped ;
-; LPM_WIDTHD ; 6 ; Untyped ;
+; LPM_WIDTHD ; 5 ; Untyped ;
; LPM_NREPRESENTATION ; SIGNED ; Untyped ;
; LPM_DREPRESENTATION ; SIGNED ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; LPM_REMAINDERPOSITIVE ; FALSE ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
-; CBXI_PARAMETER ; lpm_divide_8so ; Untyped ;
+; CBXI_PARAMETER ; lpm_divide_7so ; Untyped ;
+; CARRY_CHAIN ; MANUAL ; Untyped ;
+; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
+; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
+; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
+; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
+; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
++------------------------+----------------+--------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Mod0 ;
++------------------------+----------------+--------------------------------------+
+; Parameter Name ; Value ; Type ;
++------------------------+----------------+--------------------------------------+
+; LPM_WIDTHN ; 32 ; Untyped ;
+; LPM_WIDTHD ; 5 ; Untyped ;
+; LPM_NREPRESENTATION ; SIGNED ; Untyped ;
+; LPM_DREPRESENTATION ; SIGNED ; Untyped ;
+; LPM_PIPELINE ; 0 ; Untyped ;
+; LPM_REMAINDERPOSITIVE ; FALSE ; Untyped ;
+; MAXIMIZE_SPEED ; 5 ; Untyped ;
+; CBXI_PARAMETER ; lpm_divide_ako ; Untyped ;
+; CARRY_CHAIN ; MANUAL ; Untyped ;
+; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
+; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
+; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
+; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
+; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
++------------------------+----------------+--------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Div0 ;
++------------------------+----------------+--------------------------------------+
+; Parameter Name ; Value ; Type ;
++------------------------+----------------+--------------------------------------+
+; LPM_WIDTHN ; 32 ; Untyped ;
+; LPM_WIDTHD ; 5 ; Untyped ;
+; LPM_NREPRESENTATION ; SIGNED ; Untyped ;
+; LPM_DREPRESENTATION ; SIGNED ; Untyped ;
+; LPM_PIPELINE ; 0 ; Untyped ;
+; LPM_REMAINDERPOSITIVE ; FALSE ; Untyped ;
+; MAXIMIZE_SPEED ; 5 ; Untyped ;
+; CBXI_PARAMETER ; lpm_divide_7so ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
@@ -356,22 +1315,39 @@ Note: In order to hide this table in the UI and the text report file, please set
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.1 Build 222 10/21/2009 SJ Full Version
- Info: Processing started: Mon May 21 19:54:04 2012
+ Info: Processing started: Mon May 28 14:18:56 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
+Info: Found 1 design units, including 1 entities, in source file debouncer.v
+ Info: Found entity 1: Debouncer
Info: Found 1 design units, including 1 entities, in source file totalscheme.bdf
Info: Found entity 1: TotalScheme
Info: Found 1 design units, including 1 entities, in source file arkanoid.v
Info: Found entity 1: Arkanoid
+Info: Found 0 design units, including 0 entities, in source file arkanoid_header.v
+Info: Found 0 design units, including 0 entities, in source file int_to_digital.v
+Info: Found 0 design units, including 0 entities, in source file vga_sync.v
+Info: Found 1 design units, including 1 entities, in source file clockdivider.v
+ Info: Found entity 1: ClockDivider
Info: Elaborating entity "TotalScheme" for the top level hierarchy
Info: Elaborating entity "Arkanoid" for hierarchy "Arkanoid:inst"
-Warning (10036): Verilog HDL or VHDL warning at Arkanoid.v(82): object "ball_state" assigned a value but never read
+Warning (10762): Verilog HDL Case Statement warning at int_to_digital.v(21): can't check case statement for completeness because the case expression has too many possible states
+Warning (10776): Verilog HDL warning at int_to_digital.v(10): variable n1 in static task or function IntToDigital may have unintended latch behavior
+Warning (10776): Verilog HDL warning at int_to_digital.v(10): variable n0 in static task or function IntToDigital may have unintended latch behavior
+Warning (10776): Verilog HDL warning at int_to_digital.v(9): variable low in static task or function IntToDigital may have unintended latch behavior
+Warning (10030): Net "IntToDigital.low[6..0]" at int_to_digital.v(9) has no driver or initial value, using a default initial value '0'
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "field" into its bus
-Info: Inferred 2 megafunctions from design logic
- Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Arkanoid:inst|Div0"
+Info: Elaborating entity "ClockDivider" for hierarchy "ClockDivider:inst1"
+Info: Elaborating entity "Debouncer" for hierarchy "Debouncer:inst2"
+Info: Inferred 6 megafunctions from design logic
+ Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Arkanoid:inst|Div3"
+ Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Arkanoid:inst|Div2"
+ Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Arkanoid:inst|Mod1"
Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Arkanoid:inst|Div1"
-Info: Elaborated megafunction instantiation "Arkanoid:inst|lpm_divide:Div0"
-Info: Instantiated megafunction "Arkanoid:inst|lpm_divide:Div0" with the following parameter:
+ Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Arkanoid:inst|Mod0"
+ Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Arkanoid:inst|Div0"
+Info: Elaborated megafunction instantiation "Arkanoid:inst|lpm_divide:Div3"
+Info: Instantiated megafunction "Arkanoid:inst|lpm_divide:Div3" with the following parameter:
Info: Parameter "LPM_WIDTHN" = "32"
Info: Parameter "LPM_WIDTHD" = "6"
Info: Parameter "LPM_NREPRESENTATION" = "SIGNED"
@@ -391,45 +1367,41 @@ Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_hq9.
Info: Found entity 1: lpm_abs_hq9
Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_0s9.tdf
Info: Found entity 1: lpm_abs_0s9
-Warning: Output pins are stuck at VCC or GND
- Warning (13410): Pin "green[1]" is stuck at GND
- Warning (13410): Pin "green[0]" is stuck at GND
- Warning (13410): Pin "led1[6]" is stuck at GND
- Warning (13410): Pin "led1[5]" is stuck at GND
- Warning (13410): Pin "led1[4]" is stuck at GND
- Warning (13410): Pin "led1[3]" is stuck at GND
- Warning (13410): Pin "led1[2]" is stuck at GND
- Warning (13410): Pin "led1[1]" is stuck at GND
- Warning (13410): Pin "led1[0]" is stuck at GND
- Warning (13410): Pin "led2[6]" is stuck at GND
- Warning (13410): Pin "led2[5]" is stuck at GND
- Warning (13410): Pin "led2[4]" is stuck at GND
- Warning (13410): Pin "led2[3]" is stuck at GND
- Warning (13410): Pin "led2[2]" is stuck at GND
- Warning (13410): Pin "led2[1]" is stuck at GND
- Warning (13410): Pin "led2[0]" is stuck at GND
- Warning (13410): Pin "led3[6]" is stuck at GND
- Warning (13410): Pin "led3[5]" is stuck at GND
- Warning (13410): Pin "led3[4]" is stuck at GND
- Warning (13410): Pin "led3[3]" is stuck at GND
- Warning (13410): Pin "led3[2]" is stuck at GND
- Warning (13410): Pin "led3[1]" is stuck at GND
- Warning (13410): Pin "led3[0]" is stuck at GND
- Warning (13410): Pin "led4[6]" is stuck at GND
- Warning (13410): Pin "led4[5]" is stuck at GND
- Warning (13410): Pin "led4[4]" is stuck at GND
- Warning (13410): Pin "led4[3]" is stuck at GND
- Warning (13410): Pin "led4[2]" is stuck at GND
- Warning (13410): Pin "led4[1]" is stuck at GND
- Warning (13410): Pin "led4[0]" is stuck at GND
-Info: Implemented 1932 device resources after synthesis - the final resource count might be different
+Info: Elaborated megafunction instantiation "Arkanoid:inst|lpm_divide:Mod1"
+Info: Instantiated megafunction "Arkanoid:inst|lpm_divide:Mod1" with the following parameter:
+ Info: Parameter "LPM_WIDTHN" = "32"
+ Info: Parameter "LPM_WIDTHD" = "5"
+ Info: Parameter "LPM_NREPRESENTATION" = "SIGNED"
+ Info: Parameter "LPM_DREPRESENTATION" = "SIGNED"
+ Info: Parameter "LPM_HINT" = "LPM_REMAINDERPOSITIVE=FALSE"
+Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_ako.tdf
+ Info: Found entity 1: lpm_divide_ako
+Info: Found 1 design units, including 1 entities, in source file db/abs_divider_kbg.tdf
+ Info: Found entity 1: abs_divider_kbg
+Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_k2f.tdf
+ Info: Found entity 1: alt_u_div_k2f
+Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_gq9.tdf
+ Info: Found entity 1: lpm_abs_gq9
+Info: Elaborated megafunction instantiation "Arkanoid:inst|lpm_divide:Div1"
+Info: Instantiated megafunction "Arkanoid:inst|lpm_divide:Div1" with the following parameter:
+ Info: Parameter "LPM_WIDTHN" = "32"
+ Info: Parameter "LPM_WIDTHD" = "5"
+ Info: Parameter "LPM_NREPRESENTATION" = "SIGNED"
+ Info: Parameter "LPM_DREPRESENTATION" = "SIGNED"
+ Info: Parameter "LPM_HINT" = "LPM_REMAINDERPOSITIVE=FALSE"
+Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_7so.tdf
+ Info: Found entity 1: lpm_divide_7so
+Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below.
+ Info: Register "Arkanoid:inst|ball_direction~6" lost all its fanouts during netlist optimizations.
+ Info: Register "Arkanoid:inst|ball_direction~7" lost all its fanouts during netlist optimizations.
+Info: Implemented 8037 device resources after synthesis - the final resource count might be different
Info: Implemented 5 input pins
Info: Implemented 50 output pins
- Info: Implemented 1877 logic cells
-Info: Quartus II Analysis & Synthesis was successful. 0 errors, 32 warnings
- Info: Peak virtual memory: 204 megabytes
- Info: Processing ended: Mon May 21 19:54:20 2012
- Info: Elapsed time: 00:00:16
- Info: Total CPU time (on all processors): 00:00:17
+ Info: Implemented 7982 logic cells
+Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
+ Info: Peak virtual memory: 227 megabytes
+ Info: Processing ended: Mon May 28 14:21:58 2012
+ Info: Elapsed time: 00:03:02
+ Info: Total CPU time (on all processors): 00:03:06
diff --git a/myArkanoid.map.summary b/myArkanoid.map.summary
index aa2c8eb..212759d 100644
--- a/myArkanoid.map.summary
+++ b/myArkanoid.map.summary
@@ -1,12 +1,12 @@
-Analysis & Synthesis Status : Successful - Mon May 21 19:54:20 2012
+Analysis & Synthesis Status : Successful - Mon May 28 14:21:58 2012
Quartus II Version : 9.1 Build 222 10/21/2009 SJ Full Version
Revision Name : myArkanoid
Top-level Entity Name : TotalScheme
Family : Cyclone II
-Total logic elements : 1,810
- Total combinational functions : 1,793
- Dedicated logic registers : 151
-Total registers : 151
+Total logic elements : 7,146
+ Total combinational functions : 7,096
+ Dedicated logic registers : 1,086
+Total registers : 1086
Total pins : 55
Total virtual pins : 0
Total memory bits : 0
diff --git a/myArkanoid.pin b/myArkanoid.pin
index 6903afe..a91ffaf 100644
--- a/myArkanoid.pin
+++ b/myArkanoid.pin
@@ -160,8 +160,8 @@ GND* : B19 : : :
GND* : B20 : : : : 4 :
GND : B21 : gnd : : : :
VCCIO5 : B22 : power : : 3.3V : 5 :
-led3[3] : C1 : output : 3.3-V LVTTL : : 2 : Y
-led3[2] : C2 : output : 3.3-V LVTTL : : 2 : Y
+hex2[3] : C1 : output : 3.3-V LVTTL : : 2 : Y
+hex2[2] : C2 : output : 3.3-V LVTTL : : 2 : Y
~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : input : 3.3-V LVTTL : : 2 : N
~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : input : 3.3-V LVTTL : : 2 : N
GND : C5 : gnd : : : :
@@ -182,12 +182,12 @@ GND* : C19 : : :
GND* : C20 : : : : 5 :
GND* : C21 : : : : 5 :
GND* : C22 : : : : 5 :
-led2[6] : D1 : output : 3.3-V LVTTL : : 2 : Y
-led2[5] : D2 : output : 3.3-V LVTTL : : 2 : Y
-led3[6] : D3 : output : 3.3-V LVTTL : : 2 : Y
-led4[6] : D4 : output : 3.3-V LVTTL : : 2 : Y
-led4[1] : D5 : output : 3.3-V LVTTL : : 2 : Y
-led4[2] : D6 : output : 3.3-V LVTTL : : 2 : Y
+hex1[6] : D1 : output : 3.3-V LVTTL : : 2 : Y
+hex1[5] : D2 : output : 3.3-V LVTTL : : 2 : Y
+hex2[6] : D3 : output : 3.3-V LVTTL : : 2 : Y
+hex3[6] : D4 : output : 3.3-V LVTTL : : 2 : Y
+hex3[1] : D5 : output : 3.3-V LVTTL : : 2 : Y
+hex3[2] : D6 : output : 3.3-V LVTTL : : 2 : Y
GND* : D7 : : : : 3 :
GND* : D8 : : : : 3 :
red[0] : D9 : output : 3.3-V LVTTL : : 3 : Y
@@ -204,10 +204,10 @@ GND* : D19 : : :
GND* : D20 : : : : 5 :
GND* : D21 : : : : 5 :
GND* : D22 : : : : 5 :
-led2[0] : E1 : output : 3.3-V LVTTL : : 2 : Y
-led1[6] : E2 : output : 3.3-V LVTTL : : 2 : Y
-led3[4] : E3 : output : 3.3-V LVTTL : : 2 : Y
-led3[5] : E4 : output : 3.3-V LVTTL : : 2 : Y
+hex1[0] : E1 : output : 3.3-V LVTTL : : 2 : Y
+hex0[6] : E2 : output : 3.3-V LVTTL : : 2 : Y
+hex2[4] : E3 : output : 3.3-V LVTTL : : 2 : Y
+hex2[5] : E4 : output : 3.3-V LVTTL : : 2 : Y
VCCD_PLL3 : E5 : power : : 1.2V : :
VCCA_PLL3 : E6 : power : : 1.2V : :
GND* : E7 : : : : 3 :
@@ -226,10 +226,10 @@ GND* : E19 : : :
GND* : E20 : : : : 5 :
GND* : E21 : : : : 5 :
GND* : E22 : : : : 5 :
-led1[5] : F1 : output : 3.3-V LVTTL : : 2 : Y
-led1[4] : F2 : output : 3.3-V LVTTL : : 2 : Y
-led4[5] : F3 : output : 3.3-V LVTTL : : 2 : Y
-led4[0] : F4 : output : 3.3-V LVTTL : : 2 : Y
+hex0[5] : F1 : output : 3.3-V LVTTL : : 2 : Y
+hex0[4] : F2 : output : 3.3-V LVTTL : : 2 : Y
+hex3[5] : F3 : output : 3.3-V LVTTL : : 2 : Y
+hex3[0] : F4 : output : 3.3-V LVTTL : : 2 : Y
GND_PLL3 : F5 : gnd : : : :
GND_PLL3 : F6 : gnd : : : :
GNDA_PLL3 : F7 : gnd : : : :
@@ -250,10 +250,10 @@ GND* : F21 : : :
GND* : F22 : : : : 5 :
NC : G1 : : : : :
NC : G2 : : : : :
-led2[4] : G3 : output : 3.3-V LVTTL : : 2 : Y
+hex1[4] : G3 : output : 3.3-V LVTTL : : 2 : Y
GND : G4 : gnd : : : :
-led3[0] : G5 : output : 3.3-V LVTTL : : 2 : Y
-led3[1] : G6 : output : 3.3-V LVTTL : : 2 : Y
+hex2[0] : G5 : output : 3.3-V LVTTL : : 2 : Y
+hex2[1] : G6 : output : 3.3-V LVTTL : : 2 : Y
GND* : G7 : : : : 3 :
GND* : G8 : : : : 3 :
VCCIO3 : G9 : power : : 3.3V : 3 :
@@ -270,12 +270,12 @@ VCCIO5 : G19 : power : : 3.3V
GND* : G20 : : : : 5 :
GND* : G21 : : : : 5 :
GND* : G22 : : : : 5 :
-led1[3] : H1 : output : 3.3-V LVTTL : : 2 : Y
-led1[2] : H2 : output : 3.3-V LVTTL : : 2 : Y
+hex0[3] : H1 : output : 3.3-V LVTTL : : 2 : Y
+hex0[2] : H2 : output : 3.3-V LVTTL : : 2 : Y
GND* : H3 : : : : 2 :
-led2[3] : H4 : output : 3.3-V LVTTL : : 2 : Y
-led2[2] : H5 : output : 3.3-V LVTTL : : 2 : Y
-led2[1] : H6 : output : 3.3-V LVTTL : : 2 : Y
+hex1[3] : H4 : output : 3.3-V LVTTL : : 2 : Y
+hex1[2] : H5 : output : 3.3-V LVTTL : : 2 : Y
+hex1[1] : H6 : output : 3.3-V LVTTL : : 2 : Y
GND* : H7 : : : : 3 :
GND* : H8 : : : : 3 :
GND* : H9 : : : : 3 :
@@ -292,10 +292,10 @@ GND* : H19 : : :
GND : H20 : gnd : : : :
NC : H21 : : : : :
NC : H22 : : : : :
-led1[1] : J1 : output : 3.3-V LVTTL : : 2 : Y
-led1[0] : J2 : output : 3.3-V LVTTL : : 2 : Y
+hex0[1] : J1 : output : 3.3-V LVTTL : : 2 : Y
+hex0[0] : J2 : output : 3.3-V LVTTL : : 2 : Y
NC : J3 : : : : :
-led4[3] : J4 : output : 3.3-V LVTTL : : 2 : Y
+hex3[3] : J4 : output : 3.3-V LVTTL : : 2 : Y
NC : J5 : : : : :
NC : J6 : : : : :
VCCIO2 : J7 : power : : 3.3V : 2 :
@@ -343,7 +343,7 @@ nCONFIG : L4 : : :
TDO : L5 : output : : : 2 :
DCLK : L6 : : : : 2 :
NC : L7 : : : : :
-led4[4] : L8 : output : 3.3-V LVTTL : : 2 : Y
+hex3[4] : L8 : output : 3.3-V LVTTL : : 2 : Y
VCCINT : L9 : power : : 1.2V : :
GND : L10 : gnd : : : :
GND : L11 : gnd : : : :
diff --git a/myArkanoid.pof b/myArkanoid.pof
index 32032de..92eceab 100644
Binary files a/myArkanoid.pof and b/myArkanoid.pof differ
diff --git a/myArkanoid.qsf b/myArkanoid.qsf
index 971f526..7f15961 100644
--- a/myArkanoid.qsf
+++ b/myArkanoid.qsf
@@ -52,35 +52,12 @@ set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE AUTO
-set_location_assignment PIN_J2 -to led1[0]
-set_location_assignment PIN_J1 -to led1[1]
-set_location_assignment PIN_H2 -to led1[2]
-set_location_assignment PIN_H1 -to led1[3]
-set_location_assignment PIN_F2 -to led1[4]
-set_location_assignment PIN_F1 -to led1[5]
-set_location_assignment PIN_E2 -to led1[6]
-set_location_assignment PIN_E1 -to led2[0]
-set_location_assignment PIN_H6 -to led2[1]
-set_location_assignment PIN_H5 -to led2[2]
-set_location_assignment PIN_H4 -to led2[3]
-set_location_assignment PIN_G3 -to led2[4]
-set_location_assignment PIN_D2 -to led2[5]
-set_location_assignment PIN_D1 -to led2[6]
-set_location_assignment PIN_G5 -to led3[0]
-set_location_assignment PIN_G6 -to led3[1]
-set_location_assignment PIN_C2 -to led3[2]
-set_location_assignment PIN_C1 -to led3[3]
-set_location_assignment PIN_E3 -to led3[4]
-set_location_assignment PIN_E4 -to led3[5]
-set_location_assignment PIN_D3 -to led3[6]
-set_location_assignment PIN_F4 -to led4[0]
-set_location_assignment PIN_D5 -to led4[1]
-set_location_assignment PIN_D6 -to led4[2]
-set_location_assignment PIN_J4 -to led4[3]
-set_location_assignment PIN_L8 -to led4[4]
-set_location_assignment PIN_F3 -to led4[5]
-set_location_assignment PIN_D4 -to led4[6]
-set_global_assignment -name MISC_FILE "C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/myArkanoid/myArkanoid.dpf"
+set_location_assignment PIN_T21 -to button1
+set_location_assignment PIN_T22 -to button2
+set_location_assignment PIN_R21 -to button3
+set_location_assignment PIN_R22 -to button4
+set_location_assignment PIN_A11 -to h_sync
+set_location_assignment PIN_B11 -to v_sync
set_location_assignment PIN_D9 -to red[0]
set_location_assignment PIN_C9 -to red[1]
set_location_assignment PIN_A7 -to red[2]
@@ -93,22 +70,34 @@ set_location_assignment PIN_A9 -to blue[0]
set_location_assignment PIN_D11 -to blue[1]
set_location_assignment PIN_A10 -to blue[2]
set_location_assignment PIN_B10 -to blue[3]
-set_location_assignment PIN_T21 -to button1
-set_location_assignment PIN_T22 -to button2
-set_location_assignment PIN_R21 -to button3
-set_location_assignment PIN_R22 -to button4
-set_location_assignment PIN_A11 -to h_sync
-set_location_assignment PIN_B11 -to v_sync
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_global_assignment -name MISC_FILE "C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/myArkanoid.dpf"
-set_global_assignment -name BDF_FILE TotalScheme.bdf
-set_global_assignment -name VERILOG_FILE Arkanoid.v
-set_global_assignment -name VECTOR_WAVEFORM_FILE myArkanoid.vwf
-set_global_assignment -name SIMULATION_MODE TIMING
-set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE myArkanoid.vwf
+set_location_assignment PIN_J2 -to hex0[0]
+set_location_assignment PIN_J1 -to hex0[1]
+set_location_assignment PIN_H2 -to hex0[2]
+set_location_assignment PIN_H1 -to hex0[3]
+set_location_assignment PIN_F2 -to hex0[4]
+set_location_assignment PIN_F1 -to hex0[5]
+set_location_assignment PIN_E2 -to hex0[6]
+set_location_assignment PIN_E1 -to hex1[0]
+set_location_assignment PIN_H6 -to hex1[1]
+set_location_assignment PIN_H5 -to hex1[2]
+set_location_assignment PIN_H4 -to hex1[3]
+set_location_assignment PIN_G3 -to hex1[4]
+set_location_assignment PIN_D2 -to hex1[5]
+set_location_assignment PIN_D1 -to hex1[6]
+set_location_assignment PIN_G5 -to hex2[0]
+set_location_assignment PIN_G6 -to hex2[1]
+set_location_assignment PIN_C2 -to hex2[2]
+set_location_assignment PIN_C1 -to hex2[3]
+set_location_assignment PIN_E3 -to hex2[4]
+set_location_assignment PIN_E4 -to hex2[5]
+set_location_assignment PIN_D3 -to hex2[6]
+set_location_assignment PIN_F4 -to hex3[0]
+set_location_assignment PIN_D5 -to hex3[1]
+set_location_assignment PIN_D6 -to hex3[2]
+set_location_assignment PIN_J4 -to hex3[3]
+set_location_assignment PIN_L8 -to hex3[4]
+set_location_assignment PIN_F3 -to hex3[5]
+set_location_assignment PIN_D4 -to hex3[6]
set_location_assignment PIN_U22 -to led[0]
set_location_assignment PIN_U21 -to led[1]
set_location_assignment PIN_V22 -to led[2]
@@ -117,4 +106,20 @@ set_location_assignment PIN_W22 -to led[4]
set_location_assignment PIN_W21 -to led[5]
set_location_assignment PIN_Y22 -to led[6]
set_location_assignment PIN_Y21 -to led[7]
+set_global_assignment -name MISC_FILE "C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/myArkanoid/myArkanoid.dpf"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name MISC_FILE "C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/myArkanoid.dpf"
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE myArkanoid.vwf
+
+set_global_assignment -name VERILOG_FILE debouncer.v
+set_global_assignment -name BDF_FILE TotalScheme.bdf
+set_global_assignment -name VERILOG_FILE Arkanoid.v
+set_global_assignment -name VERILOG_FILE arkanoid_header.v
+set_global_assignment -name VERILOG_FILE int_to_digital.v
+set_global_assignment -name VERILOG_FILE vga_sync.v
+set_global_assignment -name VERILOG_FILE ClockDivider.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/myArkanoid.qsf.bak b/myArkanoid.qsf.bak
deleted file mode 100644
index 25496f6..0000000
--- a/myArkanoid.qsf.bak
+++ /dev/null
@@ -1,121 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2009 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II
-# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
-# Date created = 14:07:51 October 21, 2009
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# myArkanoid_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus II software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone II"
-set_global_assignment -name DEVICE EP2C20F484C7
-set_global_assignment -name TOP_LEVEL_ENTITY myArkanoidSchematic
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:07:51 OCTOBER 21, 2009"
-set_global_assignment -name LAST_QUARTUS_VERSION 9.1
-set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
-set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name BDF_FILE myArkanoidSchematic.bdf
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_location_assignment PIN_L1 -to clk_50MHz
-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE AREA
-set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
-set_global_assignment -name MUX_RESTRUCTURE ON
-set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION ALWAYS
-set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
-set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
-set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
-set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
-set_global_assignment -name IGNORE_LCELL_BUFFERS ON
-set_global_assignment -name IGNORE_CASCADE_BUFFERS ON
-set_global_assignment -name USE_CONFIGURATION_DEVICE ON
-set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
-set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
-set_location_assignment PIN_J2 -to led1[0]
-set_location_assignment PIN_J1 -to led1[1]
-set_location_assignment PIN_H2 -to led1[2]
-set_location_assignment PIN_H1 -to led1[3]
-set_location_assignment PIN_F2 -to led1[4]
-set_location_assignment PIN_F1 -to led1[5]
-set_location_assignment PIN_E2 -to led1[6]
-set_location_assignment PIN_E1 -to led2[0]
-set_location_assignment PIN_H6 -to led2[1]
-set_location_assignment PIN_H5 -to led2[2]
-set_location_assignment PIN_H4 -to led2[3]
-set_location_assignment PIN_G3 -to led2[4]
-set_location_assignment PIN_D2 -to led2[5]
-set_location_assignment PIN_D1 -to led2[6]
-set_location_assignment PIN_G5 -to led3[0]
-set_location_assignment PIN_G6 -to led3[1]
-set_location_assignment PIN_C2 -to led3[2]
-set_location_assignment PIN_C1 -to led3[3]
-set_location_assignment PIN_E3 -to led3[4]
-set_location_assignment PIN_E4 -to led3[5]
-set_location_assignment PIN_D3 -to led3[6]
-set_location_assignment PIN_F4 -to led4[0]
-set_location_assignment PIN_D5 -to led4[1]
-set_location_assignment PIN_D6 -to led4[2]
-set_location_assignment PIN_J4 -to led4[3]
-set_location_assignment PIN_L8 -to led4[4]
-set_location_assignment PIN_F3 -to led4[5]
-set_location_assignment PIN_D4 -to led4[6]
-set_global_assignment -name VHDL_FILE FrequencyDivider.vhd
-set_global_assignment -name VERILOG_FILE Arkanoid.v
-set_global_assignment -name MISC_FILE "C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/myArkanoid/myArkanoid.dpf"
-set_location_assignment PIN_D9 -to red[0]
-set_location_assignment PIN_C9 -to red[1]
-set_location_assignment PIN_A7 -to red[2]
-set_location_assignment PIN_B7 -to red[3]
-set_location_assignment PIN_B8 -to green[0]
-set_location_assignment PIN_C10 -to green[1]
-set_location_assignment PIN_B9 -to green[2]
-set_location_assignment PIN_A8 -to green[3]
-set_location_assignment PIN_A9 -to blue[0]
-set_location_assignment PIN_D11 -to blue[1]
-set_location_assignment PIN_A10 -to blue[2]
-set_location_assignment PIN_B10 -to blue[3]
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
-set_location_assignment PIN_R22 -to button1
-set_location_assignment PIN_R21 -to button2
-set_location_assignment PIN_T22 -to button3
-set_location_assignment PIN_T21 -to button4
-set_location_assignment PIN_A11 -to h_sync
-set_location_assignment PIN_B11 -to v_sync
\ No newline at end of file
diff --git a/myArkanoid.qws b/myArkanoid.qws
index cf60227..fc216dc 100644
--- a/myArkanoid.qws
+++ b/myArkanoid.qws
@@ -2,15 +2,3 @@
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
-[ProjectWorkspace.Frames.ChildFrames]
-ptn_Child1=Document-0
-[ProjectWorkspace.Frames.ChildFrames.Document-0]
-ptn_Child1=ViewFrame-0
-[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
-DocPathName=Arkanoid.v
-DocumentCLSID={84678d98-dc76-11d0-a0d8-0020affa5bde}
-IsChildFrameDetached=False
-IsActiveChildFrame=True
-ptn_Child1=StateMap
-[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0.StateMap]
-AFC_IN_REPORT=False
diff --git a/myArkanoid.sim.rpt b/myArkanoid.sim.rpt
index 51aafe3..f39f332 100644
--- a/myArkanoid.sim.rpt
+++ b/myArkanoid.sim.rpt
@@ -1,5 +1,5 @@
Simulator report for myArkanoid
-Mon May 21 14:05:52 2012
+Tue May 22 17:24:20 2012
Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version
@@ -38,20 +38,11 @@ applicable agreement for further details.
-+--------------------------------------------+
-; Simulator Summary ;
-+-----------------------------+--------------+
-; Type ; Value ;
-+-----------------------------+--------------+
-; Simulation Start Time ; 0 ps ;
-; Simulation End Time ; 50.0 ms ;
-; Simulation Netlist Size ; 67 nodes ;
-; Simulation Coverage ; 0.00 % ;
-; Total Number of Transitions ; 0 ;
-; Simulation Breakpoints ; 0 ;
-; Family ; Cyclone II ;
-; Device ; EP2C20F484C7 ;
-+-----------------------------+--------------+
++-------------------+
+; Simulator Summary ;
++------+------------+
+; Type ; Value ;
++------+------------+
+-----------------------------------------------------------------------------------------------------------------------------+
@@ -90,19 +81,11 @@ Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.
-+--------------------------------------------------------------------+
-; Coverage Summary ;
-+-----------------------------------------------------+--------------+
-; Type ; Value ;
-+-----------------------------------------------------+--------------+
-; Total coverage as a percentage ; 0.00 % ;
-; Total nodes checked ; 67 ;
-; Total output ports checked ; 62 ;
-; Total output ports with complete 1/0-value coverage ; 0 ;
-; Total output ports with no 1/0-value coverage ; 62 ;
-; Total output ports with no 1-value coverage ; 62 ;
-; Total output ports with no 0-value coverage ; 62 ;
-+-----------------------------------------------------+--------------+
++------------------+
+; Coverage Summary ;
++------+-----------+
+; Type ; Value ;
++------+-----------+
The following table displays output ports that toggle between 1 and 0 during simulation.
@@ -114,145 +97,19 @@ The following table displays output ports that toggle between 1 and 0 during sim
The following table displays output ports that do not toggle to 1 during simulation.
-+------------------------------------------------------------------+
-; Missing 1-Value Coverage ;
-+-----------------------+-----------------------+------------------+
-; Node Name ; Output Port Name ; Output Port Type ;
-+-----------------------+-----------------------+------------------+
-; |TotalScheme|h_sync ; |TotalScheme|h_sync ; padio ;
-; |TotalScheme|v_sync ; |TotalScheme|v_sync ; padio ;
-; |TotalScheme|blue[3] ; |TotalScheme|blue[3] ; padio ;
-; |TotalScheme|blue[2] ; |TotalScheme|blue[2] ; padio ;
-; |TotalScheme|blue[1] ; |TotalScheme|blue[1] ; padio ;
-; |TotalScheme|blue[0] ; |TotalScheme|blue[0] ; padio ;
-; |TotalScheme|green[3] ; |TotalScheme|green[3] ; padio ;
-; |TotalScheme|green[2] ; |TotalScheme|green[2] ; padio ;
-; |TotalScheme|green[1] ; |TotalScheme|green[1] ; padio ;
-; |TotalScheme|green[0] ; |TotalScheme|green[0] ; padio ;
-; |TotalScheme|hort[9] ; |TotalScheme|hort[9] ; padio ;
-; |TotalScheme|hort[8] ; |TotalScheme|hort[8] ; padio ;
-; |TotalScheme|hort[7] ; |TotalScheme|hort[7] ; padio ;
-; |TotalScheme|hort[6] ; |TotalScheme|hort[6] ; padio ;
-; |TotalScheme|hort[5] ; |TotalScheme|hort[5] ; padio ;
-; |TotalScheme|hort[4] ; |TotalScheme|hort[4] ; padio ;
-; |TotalScheme|hort[3] ; |TotalScheme|hort[3] ; padio ;
-; |TotalScheme|hort[2] ; |TotalScheme|hort[2] ; padio ;
-; |TotalScheme|hort[1] ; |TotalScheme|hort[1] ; padio ;
-; |TotalScheme|hort[0] ; |TotalScheme|hort[0] ; padio ;
-; |TotalScheme|led1[6] ; |TotalScheme|led1[6] ; padio ;
-; |TotalScheme|led1[5] ; |TotalScheme|led1[5] ; padio ;
-; |TotalScheme|led1[4] ; |TotalScheme|led1[4] ; padio ;
-; |TotalScheme|led1[3] ; |TotalScheme|led1[3] ; padio ;
-; |TotalScheme|led1[2] ; |TotalScheme|led1[2] ; padio ;
-; |TotalScheme|led1[1] ; |TotalScheme|led1[1] ; padio ;
-; |TotalScheme|led1[0] ; |TotalScheme|led1[0] ; padio ;
-; |TotalScheme|led2[6] ; |TotalScheme|led2[6] ; padio ;
-; |TotalScheme|led2[5] ; |TotalScheme|led2[5] ; padio ;
-; |TotalScheme|led2[4] ; |TotalScheme|led2[4] ; padio ;
-; |TotalScheme|led2[3] ; |TotalScheme|led2[3] ; padio ;
-; |TotalScheme|led2[2] ; |TotalScheme|led2[2] ; padio ;
-; |TotalScheme|led2[1] ; |TotalScheme|led2[1] ; padio ;
-; |TotalScheme|led2[0] ; |TotalScheme|led2[0] ; padio ;
-; |TotalScheme|led3[6] ; |TotalScheme|led3[6] ; padio ;
-; |TotalScheme|led3[5] ; |TotalScheme|led3[5] ; padio ;
-; |TotalScheme|led3[4] ; |TotalScheme|led3[4] ; padio ;
-; |TotalScheme|led3[3] ; |TotalScheme|led3[3] ; padio ;
-; |TotalScheme|led3[2] ; |TotalScheme|led3[2] ; padio ;
-; |TotalScheme|led3[1] ; |TotalScheme|led3[1] ; padio ;
-; |TotalScheme|led3[0] ; |TotalScheme|led3[0] ; padio ;
-; |TotalScheme|led4[6] ; |TotalScheme|led4[6] ; padio ;
-; |TotalScheme|led4[5] ; |TotalScheme|led4[5] ; padio ;
-; |TotalScheme|led4[4] ; |TotalScheme|led4[4] ; padio ;
-; |TotalScheme|led4[3] ; |TotalScheme|led4[3] ; padio ;
-; |TotalScheme|led4[2] ; |TotalScheme|led4[2] ; padio ;
-; |TotalScheme|led4[1] ; |TotalScheme|led4[1] ; padio ;
-; |TotalScheme|led4[0] ; |TotalScheme|led4[0] ; padio ;
-; |TotalScheme|red[3] ; |TotalScheme|red[3] ; padio ;
-; |TotalScheme|red[2] ; |TotalScheme|red[2] ; padio ;
-; |TotalScheme|red[1] ; |TotalScheme|red[1] ; padio ;
-; |TotalScheme|red[0] ; |TotalScheme|red[0] ; padio ;
-; |TotalScheme|vert[9] ; |TotalScheme|vert[9] ; padio ;
-; |TotalScheme|vert[8] ; |TotalScheme|vert[8] ; padio ;
-; |TotalScheme|vert[7] ; |TotalScheme|vert[7] ; padio ;
-; |TotalScheme|vert[6] ; |TotalScheme|vert[6] ; padio ;
-; |TotalScheme|vert[5] ; |TotalScheme|vert[5] ; padio ;
-; |TotalScheme|vert[4] ; |TotalScheme|vert[4] ; padio ;
-; |TotalScheme|vert[3] ; |TotalScheme|vert[3] ; padio ;
-; |TotalScheme|vert[2] ; |TotalScheme|vert[2] ; padio ;
-; |TotalScheme|vert[1] ; |TotalScheme|vert[1] ; padio ;
-; |TotalScheme|vert[0] ; |TotalScheme|vert[0] ; padio ;
-+-----------------------+-----------------------+------------------+
++-------------------------------------------------+
+; Missing 1-Value Coverage ;
++-----------+------------------+------------------+
+; Node Name ; Output Port Name ; Output Port Type ;
++-----------+------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
-+------------------------------------------------------------------+
-; Missing 0-Value Coverage ;
-+-----------------------+-----------------------+------------------+
-; Node Name ; Output Port Name ; Output Port Type ;
-+-----------------------+-----------------------+------------------+
-; |TotalScheme|h_sync ; |TotalScheme|h_sync ; padio ;
-; |TotalScheme|v_sync ; |TotalScheme|v_sync ; padio ;
-; |TotalScheme|blue[3] ; |TotalScheme|blue[3] ; padio ;
-; |TotalScheme|blue[2] ; |TotalScheme|blue[2] ; padio ;
-; |TotalScheme|blue[1] ; |TotalScheme|blue[1] ; padio ;
-; |TotalScheme|blue[0] ; |TotalScheme|blue[0] ; padio ;
-; |TotalScheme|green[3] ; |TotalScheme|green[3] ; padio ;
-; |TotalScheme|green[2] ; |TotalScheme|green[2] ; padio ;
-; |TotalScheme|green[1] ; |TotalScheme|green[1] ; padio ;
-; |TotalScheme|green[0] ; |TotalScheme|green[0] ; padio ;
-; |TotalScheme|hort[9] ; |TotalScheme|hort[9] ; padio ;
-; |TotalScheme|hort[8] ; |TotalScheme|hort[8] ; padio ;
-; |TotalScheme|hort[7] ; |TotalScheme|hort[7] ; padio ;
-; |TotalScheme|hort[6] ; |TotalScheme|hort[6] ; padio ;
-; |TotalScheme|hort[5] ; |TotalScheme|hort[5] ; padio ;
-; |TotalScheme|hort[4] ; |TotalScheme|hort[4] ; padio ;
-; |TotalScheme|hort[3] ; |TotalScheme|hort[3] ; padio ;
-; |TotalScheme|hort[2] ; |TotalScheme|hort[2] ; padio ;
-; |TotalScheme|hort[1] ; |TotalScheme|hort[1] ; padio ;
-; |TotalScheme|hort[0] ; |TotalScheme|hort[0] ; padio ;
-; |TotalScheme|led1[6] ; |TotalScheme|led1[6] ; padio ;
-; |TotalScheme|led1[5] ; |TotalScheme|led1[5] ; padio ;
-; |TotalScheme|led1[4] ; |TotalScheme|led1[4] ; padio ;
-; |TotalScheme|led1[3] ; |TotalScheme|led1[3] ; padio ;
-; |TotalScheme|led1[2] ; |TotalScheme|led1[2] ; padio ;
-; |TotalScheme|led1[1] ; |TotalScheme|led1[1] ; padio ;
-; |TotalScheme|led1[0] ; |TotalScheme|led1[0] ; padio ;
-; |TotalScheme|led2[6] ; |TotalScheme|led2[6] ; padio ;
-; |TotalScheme|led2[5] ; |TotalScheme|led2[5] ; padio ;
-; |TotalScheme|led2[4] ; |TotalScheme|led2[4] ; padio ;
-; |TotalScheme|led2[3] ; |TotalScheme|led2[3] ; padio ;
-; |TotalScheme|led2[2] ; |TotalScheme|led2[2] ; padio ;
-; |TotalScheme|led2[1] ; |TotalScheme|led2[1] ; padio ;
-; |TotalScheme|led2[0] ; |TotalScheme|led2[0] ; padio ;
-; |TotalScheme|led3[6] ; |TotalScheme|led3[6] ; padio ;
-; |TotalScheme|led3[5] ; |TotalScheme|led3[5] ; padio ;
-; |TotalScheme|led3[4] ; |TotalScheme|led3[4] ; padio ;
-; |TotalScheme|led3[3] ; |TotalScheme|led3[3] ; padio ;
-; |TotalScheme|led3[2] ; |TotalScheme|led3[2] ; padio ;
-; |TotalScheme|led3[1] ; |TotalScheme|led3[1] ; padio ;
-; |TotalScheme|led3[0] ; |TotalScheme|led3[0] ; padio ;
-; |TotalScheme|led4[6] ; |TotalScheme|led4[6] ; padio ;
-; |TotalScheme|led4[5] ; |TotalScheme|led4[5] ; padio ;
-; |TotalScheme|led4[4] ; |TotalScheme|led4[4] ; padio ;
-; |TotalScheme|led4[3] ; |TotalScheme|led4[3] ; padio ;
-; |TotalScheme|led4[2] ; |TotalScheme|led4[2] ; padio ;
-; |TotalScheme|led4[1] ; |TotalScheme|led4[1] ; padio ;
-; |TotalScheme|led4[0] ; |TotalScheme|led4[0] ; padio ;
-; |TotalScheme|red[3] ; |TotalScheme|red[3] ; padio ;
-; |TotalScheme|red[2] ; |TotalScheme|red[2] ; padio ;
-; |TotalScheme|red[1] ; |TotalScheme|red[1] ; padio ;
-; |TotalScheme|red[0] ; |TotalScheme|red[0] ; padio ;
-; |TotalScheme|vert[9] ; |TotalScheme|vert[9] ; padio ;
-; |TotalScheme|vert[8] ; |TotalScheme|vert[8] ; padio ;
-; |TotalScheme|vert[7] ; |TotalScheme|vert[7] ; padio ;
-; |TotalScheme|vert[6] ; |TotalScheme|vert[6] ; padio ;
-; |TotalScheme|vert[5] ; |TotalScheme|vert[5] ; padio ;
-; |TotalScheme|vert[4] ; |TotalScheme|vert[4] ; padio ;
-; |TotalScheme|vert[3] ; |TotalScheme|vert[3] ; padio ;
-; |TotalScheme|vert[2] ; |TotalScheme|vert[2] ; padio ;
-; |TotalScheme|vert[1] ; |TotalScheme|vert[1] ; padio ;
-; |TotalScheme|vert[0] ; |TotalScheme|vert[0] ; padio ;
-+-----------------------+-----------------------+------------------+
++-------------------------------------------------+
+; Missing 0-Value Coverage ;
++-----------+------------------+------------------+
+; Node Name ; Output Port Name ; Output Port Type ;
++-----------+------------------+------------------+
+---------------------+
@@ -268,22 +125,14 @@ The following table displays output ports that do not toggle to 0 during simulat
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 9.1 Build 222 10/21/2009 SJ Full Version
- Info: Processing started: Mon May 21 14:02:19 2012
+ Info: Processing started: Tue May 22 17:24:20 2012
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid
-Info: Using vector source file "C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/myArkanoid.vwf"
-Warning: Can't find signal in vector source file for input pin "|TotalScheme|button1"
-Warning: Can't find signal in vector source file for input pin "|TotalScheme|button2"
-Warning: Can't find signal in vector source file for input pin "|TotalScheme|button3"
-Warning: Can't find signal in vector source file for input pin "|TotalScheme|button4"
-Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
- Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
-Info: Simulation partitioned into 1 sub-simulations
-Info: Simulation coverage is 0.00 %
-Info: Number of transitions in simulation is 0
-Info: Quartus II Simulator was successful. 0 errors, 4 warnings
- Info: Peak virtual memory: 136 megabytes
- Info: Processing ended: Mon May 21 14:05:53 2012
- Info: Elapsed time: 00:03:34
- Info: Total CPU time (on all processors): 00:03:34
+Info: Can't find specified vector source file "G:/Verilog/Arkanoid2PDE1/myArkanoid.vwf"
+Error: No valid vector source file specified and default file "G:/Verilog/Arkanoid2PDE1/myArkanoid.cvwf" does not exist
+Error: Quartus II Simulator was unsuccessful. 1 error, 0 warnings
+ Error: Peak virtual memory: 144 megabytes
+ Error: Processing ended: Tue May 22 17:24:20 2012
+ Error: Elapsed time: 00:00:00
+ Error: Total CPU time (on all processors): 00:00:01
diff --git a/myArkanoid.sof b/myArkanoid.sof
index 909d807..e1ad2e7 100644
Binary files a/myArkanoid.sof and b/myArkanoid.sof differ
diff --git a/myArkanoid.tan.rpt b/myArkanoid.tan.rpt
index 1dd120f..b3c4c48 100644
--- a/myArkanoid.tan.rpt
+++ b/myArkanoid.tan.rpt
@@ -1,5 +1,5 @@
Classic Timing Analyzer report for myArkanoid
-Mon May 21 19:54:43 2012
+Mon May 28 14:22:37 2012
Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version
@@ -38,17 +38,17 @@ applicable agreement for further details.
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Timing Analyzer Summary ;
-+------------------------------+-------+---------------+----------------------------------+----------------------------+--------------------------------------+------------+-----------+--------------+
-; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
-+------------------------------+-------+---------------+----------------------------------+----------------------------+--------------------------------------+------------+-----------+--------------+
-; Worst-case tsu ; N/A ; None ; 32.749 ns ; button3 ; Arkanoid:inst|blue_[0] ; -- ; clk_50MHz ; 0 ;
-; Worst-case tco ; N/A ; None ; 15.668 ns ; Arkanoid:inst|v_counter[8] ; v_sync ; clk_50MHz ; -- ; 0 ;
-; Worst-case th ; N/A ; None ; -2.062 ns ; button2 ; Arkanoid:inst|platform1_position[29] ; -- ; clk_50MHz ; 0 ;
-; Clock Setup: 'clk_50MHz' ; N/A ; None ; 9.70 MHz ( period = 103.135 ns ) ; Arkanoid:inst|h_counter[1] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; 0 ;
-; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
-+------------------------------+-------+---------------+----------------------------------+----------------------------+--------------------------------------+------------+-----------+--------------+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Timing Analyzer Summary ;
++------------------------------+-------+---------------+----------------------------------+-------------------------------------+-------------------------------+------------+-----------+--------------+
+; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
++------------------------------+-------+---------------+----------------------------------+-------------------------------------+-------------------------------+------------+-----------+--------------+
+; Worst-case tsu ; N/A ; None ; 3.159 ns ; button4 ; Debouncer:inst5|button_reg[0] ; -- ; clk_50MHz ; 0 ;
+; Worst-case tco ; N/A ; None ; 14.776 ns ; Arkanoid:inst|h_counter[0] ; h_sync ; clk_50MHz ; -- ; 0 ;
+; Worst-case th ; N/A ; None ; -1.772 ns ; button1 ; Debouncer:inst2|button_reg[0] ; -- ; clk_50MHz ; 0 ;
+; Clock Setup: 'clk_50MHz' ; N/A ; None ; 7.55 MHz ( period = 132.461 ns ) ; Arkanoid:inst|platform1_position[3] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; 0 ;
+; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
++------------------------------+-------+---------------+----------------------------------+-------------------------------------+-------------------------------+------------+-----------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -111,393 +111,225 @@ applicable agreement for further details.
+----------------------------+-------------+
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Setup: 'clk_50MHz' ;
-+-----------------------------------------+-----------------------------------------------------+-----------------------------+-------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+
-; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
-+-----------------------------------------+-----------------------------------------------------+-----------------------------+-------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+
-; N/A ; 9.70 MHz ( period = 103.135 ns ) ; Arkanoid:inst|h_counter[1] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.875 ns ;
-; N/A ; 9.71 MHz ( period = 102.993 ns ) ; Arkanoid:inst|h_counter[1] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.733 ns ;
-; N/A ; 9.71 MHz ( period = 102.991 ns ) ; Arkanoid:inst|h_counter[1] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.731 ns ;
-; N/A ; 9.71 MHz ( period = 102.941 ns ) ; Arkanoid:inst|h_counter[1] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.681 ns ;
-; N/A ; 9.73 MHz ( period = 102.825 ns ) ; Arkanoid:inst|h_counter[0] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.582 ns ;
-; N/A ; 9.73 MHz ( period = 102.761 ns ) ; Arkanoid:inst|h_counter[2] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.518 ns ;
-; N/A ; 9.74 MHz ( period = 102.721 ns ) ; Arkanoid:inst|h_counter[3] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.478 ns ;
-; N/A ; 9.74 MHz ( period = 102.683 ns ) ; Arkanoid:inst|h_counter[0] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.440 ns ;
-; N/A ; 9.74 MHz ( period = 102.681 ns ) ; Arkanoid:inst|h_counter[0] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.438 ns ;
-; N/A ; 9.74 MHz ( period = 102.631 ns ) ; Arkanoid:inst|h_counter[0] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.388 ns ;
-; N/A ; 9.74 MHz ( period = 102.619 ns ) ; Arkanoid:inst|h_counter[2] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.376 ns ;
-; N/A ; 9.74 MHz ( period = 102.617 ns ) ; Arkanoid:inst|h_counter[2] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.374 ns ;
-; N/A ; 9.75 MHz ( period = 102.598 ns ) ; Arkanoid:inst|h_counter[4] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.355 ns ;
-; N/A ; 9.75 MHz ( period = 102.579 ns ) ; Arkanoid:inst|h_counter[3] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.336 ns ;
-; N/A ; 9.75 MHz ( period = 102.577 ns ) ; Arkanoid:inst|h_counter[3] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.334 ns ;
-; N/A ; 9.75 MHz ( period = 102.567 ns ) ; Arkanoid:inst|h_counter[2] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.324 ns ;
-; N/A ; 9.75 MHz ( period = 102.558 ns ) ; Arkanoid:inst|h_counter[5] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.315 ns ;
-; N/A ; 9.75 MHz ( period = 102.527 ns ) ; Arkanoid:inst|h_counter[3] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.284 ns ;
-; N/A ; 9.76 MHz ( period = 102.478 ns ) ; Arkanoid:inst|h_counter[6] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.235 ns ;
-; N/A ; 9.76 MHz ( period = 102.456 ns ) ; Arkanoid:inst|h_counter[4] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.213 ns ;
-; N/A ; 9.76 MHz ( period = 102.454 ns ) ; Arkanoid:inst|h_counter[4] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.211 ns ;
-; N/A ; 9.76 MHz ( period = 102.416 ns ) ; Arkanoid:inst|h_counter[5] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.173 ns ;
-; N/A ; 9.76 MHz ( period = 102.414 ns ) ; Arkanoid:inst|h_counter[5] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.171 ns ;
-; N/A ; 9.77 MHz ( period = 102.404 ns ) ; Arkanoid:inst|h_counter[4] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.161 ns ;
-; N/A ; 9.77 MHz ( period = 102.365 ns ) ; Arkanoid:inst|h_counter[7] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.122 ns ;
-; N/A ; 9.77 MHz ( period = 102.364 ns ) ; Arkanoid:inst|h_counter[5] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.121 ns ;
-; N/A ; 9.77 MHz ( period = 102.336 ns ) ; Arkanoid:inst|h_counter[6] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.093 ns ;
-; N/A ; 9.77 MHz ( period = 102.334 ns ) ; Arkanoid:inst|h_counter[6] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.091 ns ;
-; N/A ; 9.78 MHz ( period = 102.296 ns ) ; Arkanoid:inst|h_counter[1] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.036 ns ;
-; N/A ; 9.78 MHz ( period = 102.294 ns ) ; Arkanoid:inst|h_counter[1] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.034 ns ;
-; N/A ; 9.78 MHz ( period = 102.293 ns ) ; Arkanoid:inst|h_counter[1] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.033 ns ;
-; N/A ; 9.78 MHz ( period = 102.290 ns ) ; Arkanoid:inst|h_counter[1] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.030 ns ;
-; N/A ; 9.78 MHz ( period = 102.284 ns ) ; Arkanoid:inst|h_counter[6] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.041 ns ;
-; N/A ; 9.78 MHz ( period = 102.254 ns ) ; Arkanoid:inst|v_counter[1] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.007 ns ;
-; N/A ; 9.78 MHz ( period = 102.223 ns ) ; Arkanoid:inst|h_counter[7] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.980 ns ;
-; N/A ; 9.78 MHz ( period = 102.221 ns ) ; Arkanoid:inst|h_counter[7] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.978 ns ;
-; N/A ; 9.78 MHz ( period = 102.219 ns ) ; Arkanoid:inst|h_counter[8] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.976 ns ;
-; N/A ; 9.79 MHz ( period = 102.182 ns ) ; Arkanoid:inst|v_counter[2] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.935 ns ;
-; N/A ; 9.79 MHz ( period = 102.171 ns ) ; Arkanoid:inst|h_counter[7] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.928 ns ;
-; N/A ; 9.79 MHz ( period = 102.147 ns ) ; Arkanoid:inst|v_counter[3] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.900 ns ;
-; N/A ; 9.79 MHz ( period = 102.102 ns ) ; Arkanoid:inst|v_counter[1] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.855 ns ;
-; N/A ; 9.79 MHz ( period = 102.095 ns ) ; Arkanoid:inst|h_counter[9] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.852 ns ;
-; N/A ; 9.80 MHz ( period = 102.077 ns ) ; Arkanoid:inst|h_counter[8] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.834 ns ;
-; N/A ; 9.80 MHz ( period = 102.075 ns ) ; Arkanoid:inst|h_counter[8] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.832 ns ;
-; N/A ; 9.80 MHz ( period = 102.060 ns ) ; Arkanoid:inst|h_counter[10] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.817 ns ;
-; N/A ; 9.80 MHz ( period = 102.049 ns ) ; Arkanoid:inst|v_counter[1] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.802 ns ;
-; N/A ; 9.80 MHz ( period = 102.030 ns ) ; Arkanoid:inst|v_counter[2] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.783 ns ;
-; N/A ; 9.80 MHz ( period = 102.025 ns ) ; Arkanoid:inst|h_counter[8] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.782 ns ;
-; N/A ; 9.80 MHz ( period = 102.023 ns ) ; Arkanoid:inst|v_counter[4] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.776 ns ;
-; N/A ; 9.80 MHz ( period = 101.995 ns ) ; Arkanoid:inst|v_counter[3] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.748 ns ;
-; N/A ; 9.81 MHz ( period = 101.987 ns ) ; Arkanoid:inst|v_counter[5] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.740 ns ;
-; N/A ; 9.81 MHz ( period = 101.986 ns ) ; Arkanoid:inst|h_counter[0] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.743 ns ;
-; N/A ; 9.81 MHz ( period = 101.984 ns ) ; Arkanoid:inst|h_counter[0] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.741 ns ;
-; N/A ; 9.81 MHz ( period = 101.983 ns ) ; Arkanoid:inst|h_counter[0] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.740 ns ;
-; N/A ; 9.81 MHz ( period = 101.980 ns ) ; Arkanoid:inst|h_counter[0] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.737 ns ;
-; N/A ; 9.81 MHz ( period = 101.977 ns ) ; Arkanoid:inst|v_counter[2] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.730 ns ;
-; N/A ; 9.81 MHz ( period = 101.953 ns ) ; Arkanoid:inst|h_counter[9] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.710 ns ;
-; N/A ; 9.81 MHz ( period = 101.951 ns ) ; Arkanoid:inst|h_counter[9] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.708 ns ;
-; N/A ; 9.81 MHz ( period = 101.942 ns ) ; Arkanoid:inst|v_counter[3] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.695 ns ;
-; N/A ; 9.81 MHz ( period = 101.935 ns ) ; Arkanoid:inst|h_counter[11] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.692 ns ;
-; N/A ; 9.81 MHz ( period = 101.922 ns ) ; Arkanoid:inst|h_counter[2] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.679 ns ;
-; N/A ; 9.81 MHz ( period = 101.920 ns ) ; Arkanoid:inst|h_counter[2] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.677 ns ;
-; N/A ; 9.81 MHz ( period = 101.919 ns ) ; Arkanoid:inst|h_counter[2] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.676 ns ;
-; N/A ; 9.81 MHz ( period = 101.918 ns ) ; Arkanoid:inst|h_counter[10] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.675 ns ;
-; N/A ; 9.81 MHz ( period = 101.916 ns ) ; Arkanoid:inst|h_counter[10] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.673 ns ;
-; N/A ; 9.81 MHz ( period = 101.916 ns ) ; Arkanoid:inst|h_counter[2] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.673 ns ;
-; N/A ; 9.81 MHz ( period = 101.910 ns ) ; Arkanoid:inst|v_counter[6] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.663 ns ;
-; N/A ; 9.81 MHz ( period = 101.901 ns ) ; Arkanoid:inst|h_counter[9] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.658 ns ;
-; N/A ; 9.81 MHz ( period = 101.900 ns ) ; Arkanoid:inst|h_counter[12] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.657 ns ;
-; N/A ; 9.82 MHz ( period = 101.882 ns ) ; Arkanoid:inst|h_counter[3] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.639 ns ;
-; N/A ; 9.82 MHz ( period = 101.880 ns ) ; Arkanoid:inst|h_counter[3] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.637 ns ;
-; N/A ; 9.82 MHz ( period = 101.879 ns ) ; Arkanoid:inst|h_counter[3] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.636 ns ;
-; N/A ; 9.82 MHz ( period = 101.876 ns ) ; Arkanoid:inst|h_counter[3] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.633 ns ;
-; N/A ; 9.82 MHz ( period = 101.871 ns ) ; Arkanoid:inst|v_counter[4] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.624 ns ;
-; N/A ; 9.82 MHz ( period = 101.866 ns ) ; Arkanoid:inst|h_counter[10] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.623 ns ;
-; N/A ; 9.82 MHz ( period = 101.835 ns ) ; Arkanoid:inst|v_counter[5] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.588 ns ;
-; N/A ; 9.82 MHz ( period = 101.818 ns ) ; Arkanoid:inst|v_counter[4] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.571 ns ;
-; N/A ; 9.82 MHz ( period = 101.796 ns ) ; Arkanoid:inst|v_counter[1] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.549 ns ;
-; N/A ; 9.82 MHz ( period = 101.793 ns ) ; Arkanoid:inst|h_counter[11] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.550 ns ;
-; N/A ; 9.82 MHz ( period = 101.791 ns ) ; Arkanoid:inst|h_counter[11] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.548 ns ;
-; N/A ; 9.82 MHz ( period = 101.790 ns ) ; Arkanoid:inst|v_counter[7] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.543 ns ;
-; N/A ; 9.82 MHz ( period = 101.782 ns ) ; Arkanoid:inst|v_counter[5] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.535 ns ;
-; N/A ; 9.83 MHz ( period = 101.780 ns ) ; Arkanoid:inst|h_counter[13] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.537 ns ;
-; N/A ; 9.83 MHz ( period = 101.759 ns ) ; Arkanoid:inst|h_counter[4] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.516 ns ;
-; N/A ; 9.83 MHz ( period = 101.758 ns ) ; Arkanoid:inst|v_counter[6] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.511 ns ;
-; N/A ; 9.83 MHz ( period = 101.758 ns ) ; Arkanoid:inst|h_counter[12] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.515 ns ;
-; N/A ; 9.83 MHz ( period = 101.757 ns ) ; Arkanoid:inst|h_counter[4] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.514 ns ;
-; N/A ; 9.83 MHz ( period = 101.756 ns ) ; Arkanoid:inst|h_counter[12] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.513 ns ;
-; N/A ; 9.83 MHz ( period = 101.756 ns ) ; Arkanoid:inst|h_counter[4] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.513 ns ;
-; N/A ; 9.83 MHz ( period = 101.753 ns ) ; Arkanoid:inst|h_counter[4] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.510 ns ;
-; N/A ; 9.83 MHz ( period = 101.741 ns ) ; Arkanoid:inst|h_counter[11] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.498 ns ;
-; N/A ; 9.83 MHz ( period = 101.724 ns ) ; Arkanoid:inst|v_counter[2] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.477 ns ;
-; N/A ; 9.83 MHz ( period = 101.719 ns ) ; Arkanoid:inst|h_counter[5] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.476 ns ;
-; N/A ; 9.83 MHz ( period = 101.717 ns ) ; Arkanoid:inst|h_counter[5] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.474 ns ;
-; N/A ; 9.83 MHz ( period = 101.716 ns ) ; Arkanoid:inst|h_counter[5] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.473 ns ;
-; N/A ; 9.83 MHz ( period = 101.713 ns ) ; Arkanoid:inst|h_counter[5] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.470 ns ;
-; N/A ; 9.83 MHz ( period = 101.706 ns ) ; Arkanoid:inst|h_counter[12] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.463 ns ;
-; N/A ; 9.83 MHz ( period = 101.705 ns ) ; Arkanoid:inst|v_counter[6] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.458 ns ;
-; N/A ; 9.83 MHz ( period = 101.700 ns ) ; Arkanoid:inst|h_counter[14] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.457 ns ;
-; N/A ; 9.83 MHz ( period = 101.689 ns ) ; Arkanoid:inst|v_counter[3] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.442 ns ;
-; N/A ; 9.84 MHz ( period = 101.648 ns ) ; Arkanoid:inst|v_counter[8] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.401 ns ;
-; N/A ; 9.84 MHz ( period = 101.639 ns ) ; Arkanoid:inst|h_counter[6] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.396 ns ;
-; N/A ; 9.84 MHz ( period = 101.639 ns ) ; Arkanoid:inst|h_counter[15] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.396 ns ;
-; N/A ; 9.84 MHz ( period = 101.638 ns ) ; Arkanoid:inst|v_counter[7] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.391 ns ;
-; N/A ; 9.84 MHz ( period = 101.638 ns ) ; Arkanoid:inst|h_counter[13] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.395 ns ;
-; N/A ; 9.84 MHz ( period = 101.637 ns ) ; Arkanoid:inst|v_counter[1] ; Arkanoid:inst|blue_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.390 ns ;
-; N/A ; 9.84 MHz ( period = 101.637 ns ) ; Arkanoid:inst|h_counter[6] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.394 ns ;
-; N/A ; 9.84 MHz ( period = 101.636 ns ) ; Arkanoid:inst|h_counter[13] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.393 ns ;
-; N/A ; 9.84 MHz ( period = 101.636 ns ) ; Arkanoid:inst|h_counter[6] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.393 ns ;
-; N/A ; 9.84 MHz ( period = 101.633 ns ) ; Arkanoid:inst|h_counter[6] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.390 ns ;
-; N/A ; 9.84 MHz ( period = 101.586 ns ) ; Arkanoid:inst|h_counter[13] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.343 ns ;
-; N/A ; 9.84 MHz ( period = 101.585 ns ) ; Arkanoid:inst|v_counter[7] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.338 ns ;
-; N/A ; 9.85 MHz ( period = 101.565 ns ) ; Arkanoid:inst|v_counter[2] ; Arkanoid:inst|blue_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.318 ns ;
-; N/A ; 9.85 MHz ( period = 101.565 ns ) ; Arkanoid:inst|v_counter[4] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.318 ns ;
-; N/A ; 9.85 MHz ( period = 101.558 ns ) ; Arkanoid:inst|h_counter[14] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.315 ns ;
-; N/A ; 9.85 MHz ( period = 101.556 ns ) ; Arkanoid:inst|h_counter[14] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.313 ns ;
-; N/A ; 9.85 MHz ( period = 101.530 ns ) ; Arkanoid:inst|v_counter[3] ; Arkanoid:inst|blue_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.283 ns ;
-; N/A ; 9.85 MHz ( period = 101.529 ns ) ; Arkanoid:inst|v_counter[5] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.282 ns ;
-; N/A ; 9.85 MHz ( period = 101.526 ns ) ; Arkanoid:inst|h_counter[7] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.283 ns ;
-; N/A ; 9.85 MHz ( period = 101.524 ns ) ; Arkanoid:inst|v_counter[9] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.277 ns ;
-; N/A ; 9.85 MHz ( period = 101.524 ns ) ; Arkanoid:inst|h_counter[7] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.281 ns ;
-; N/A ; 9.85 MHz ( period = 101.523 ns ) ; Arkanoid:inst|h_counter[7] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.280 ns ;
-; N/A ; 9.85 MHz ( period = 101.520 ns ) ; Arkanoid:inst|h_counter[7] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.277 ns ;
-; N/A ; 9.85 MHz ( period = 101.506 ns ) ; Arkanoid:inst|h_counter[14] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.263 ns ;
-; N/A ; 9.85 MHz ( period = 101.497 ns ) ; Arkanoid:inst|h_counter[15] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.254 ns ;
-; N/A ; 9.85 MHz ( period = 101.496 ns ) ; Arkanoid:inst|v_counter[8] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.249 ns ;
-; N/A ; 9.85 MHz ( period = 101.495 ns ) ; Arkanoid:inst|h_counter[15] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.252 ns ;
-; N/A ; 9.85 MHz ( period = 101.489 ns ) ; Arkanoid:inst|v_counter[10] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.242 ns ;
-; N/A ; 9.86 MHz ( period = 101.452 ns ) ; Arkanoid:inst|v_counter[6] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.205 ns ;
-; N/A ; 9.86 MHz ( period = 101.447 ns ) ; Arkanoid:inst|h_counter[16] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.207 ns ;
-; N/A ; 9.86 MHz ( period = 101.445 ns ) ; Arkanoid:inst|h_counter[15] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.202 ns ;
-; N/A ; 9.86 MHz ( period = 101.443 ns ) ; Arkanoid:inst|v_counter[8] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.196 ns ;
-; N/A ; 9.86 MHz ( period = 101.415 ns ) ; Arkanoid:inst|v_counter[1] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.168 ns ;
-; N/A ; 9.86 MHz ( period = 101.406 ns ) ; Arkanoid:inst|v_counter[4] ; Arkanoid:inst|blue_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.159 ns ;
-; N/A ; 9.86 MHz ( period = 101.404 ns ) ; Arkanoid:inst|v_counter[1] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.157 ns ;
-; N/A ; 9.86 MHz ( period = 101.402 ns ) ; Arkanoid:inst|v_counter[1] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.155 ns ;
-; N/A ; 9.86 MHz ( period = 101.380 ns ) ; Arkanoid:inst|h_counter[8] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.137 ns ;
-; N/A ; 9.86 MHz ( period = 101.378 ns ) ; Arkanoid:inst|h_counter[8] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.135 ns ;
-; N/A ; 9.86 MHz ( period = 101.377 ns ) ; Arkanoid:inst|h_counter[8] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.134 ns ;
-; N/A ; 9.86 MHz ( period = 101.374 ns ) ; Arkanoid:inst|h_counter[17] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.134 ns ;
-; N/A ; 9.86 MHz ( period = 101.374 ns ) ; Arkanoid:inst|h_counter[8] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.131 ns ;
-; N/A ; 9.86 MHz ( period = 101.372 ns ) ; Arkanoid:inst|v_counter[9] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.125 ns ;
-; N/A ; 9.86 MHz ( period = 101.370 ns ) ; Arkanoid:inst|v_counter[5] ; Arkanoid:inst|blue_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.123 ns ;
-; N/A ; 9.87 MHz ( period = 101.364 ns ) ; Arkanoid:inst|v_counter[11] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.117 ns ;
-; N/A ; 9.87 MHz ( period = 101.343 ns ) ; Arkanoid:inst|v_counter[2] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.096 ns ;
-; N/A ; 9.87 MHz ( period = 101.337 ns ) ; Arkanoid:inst|v_counter[10] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.090 ns ;
-; N/A ; 9.87 MHz ( period = 101.332 ns ) ; Arkanoid:inst|v_counter[2] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.085 ns ;
-; N/A ; 9.87 MHz ( period = 101.332 ns ) ; Arkanoid:inst|v_counter[7] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.085 ns ;
-; N/A ; 9.87 MHz ( period = 101.330 ns ) ; Arkanoid:inst|v_counter[2] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.083 ns ;
-; N/A ; 9.87 MHz ( period = 101.329 ns ) ; Arkanoid:inst|v_counter[12] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.082 ns ;
-; N/A ; 9.87 MHz ( period = 101.319 ns ) ; Arkanoid:inst|v_counter[9] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.072 ns ;
-; N/A ; 9.87 MHz ( period = 101.308 ns ) ; Arkanoid:inst|v_counter[3] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.061 ns ;
-; N/A ; 9.87 MHz ( period = 101.305 ns ) ; Arkanoid:inst|h_counter[16] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.065 ns ;
-; N/A ; 9.87 MHz ( period = 101.303 ns ) ; Arkanoid:inst|h_counter[16] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.063 ns ;
-; N/A ; 9.87 MHz ( period = 101.297 ns ) ; Arkanoid:inst|v_counter[3] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.050 ns ;
-; N/A ; 9.87 MHz ( period = 101.295 ns ) ; Arkanoid:inst|h_counter[18] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.055 ns ;
-; N/A ; 9.87 MHz ( period = 101.295 ns ) ; Arkanoid:inst|v_counter[3] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.048 ns ;
-; N/A ; 9.87 MHz ( period = 101.293 ns ) ; Arkanoid:inst|v_counter[6] ; Arkanoid:inst|blue_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.046 ns ;
-; N/A ; 9.87 MHz ( period = 101.284 ns ) ; Arkanoid:inst|v_counter[10] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.037 ns ;
-; N/A ; 9.88 MHz ( period = 101.256 ns ) ; Arkanoid:inst|h_counter[9] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.013 ns ;
-; N/A ; 9.88 MHz ( period = 101.256 ns ) ; Arkanoid:inst|h_counter[19] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.016 ns ;
-; N/A ; 9.88 MHz ( period = 101.254 ns ) ; Arkanoid:inst|h_counter[9] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.011 ns ;
-; N/A ; 9.88 MHz ( period = 101.253 ns ) ; Arkanoid:inst|h_counter[9] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.010 ns ;
-; N/A ; 9.88 MHz ( period = 101.253 ns ) ; Arkanoid:inst|h_counter[16] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.013 ns ;
-; N/A ; 9.88 MHz ( period = 101.250 ns ) ; Arkanoid:inst|h_counter[9] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.007 ns ;
-; N/A ; 9.88 MHz ( period = 101.232 ns ) ; Arkanoid:inst|h_counter[17] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.992 ns ;
-; N/A ; 9.88 MHz ( period = 101.230 ns ) ; Arkanoid:inst|h_counter[17] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.990 ns ;
-; N/A ; 9.88 MHz ( period = 101.221 ns ) ; Arkanoid:inst|h_counter[10] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.978 ns ;
-; N/A ; 9.88 MHz ( period = 101.219 ns ) ; Arkanoid:inst|h_counter[10] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.976 ns ;
-; N/A ; 9.88 MHz ( period = 101.218 ns ) ; Arkanoid:inst|h_counter[10] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.975 ns ;
-; N/A ; 9.88 MHz ( period = 101.215 ns ) ; Arkanoid:inst|h_counter[10] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.972 ns ;
-; N/A ; 9.88 MHz ( period = 101.212 ns ) ; Arkanoid:inst|v_counter[11] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.965 ns ;
-; N/A ; 9.88 MHz ( period = 101.209 ns ) ; Arkanoid:inst|v_counter[13] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.962 ns ;
-; N/A ; 9.88 MHz ( period = 101.190 ns ) ; Arkanoid:inst|v_counter[8] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.943 ns ;
-; N/A ; 9.88 MHz ( period = 101.184 ns ) ; Arkanoid:inst|v_counter[4] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.937 ns ;
-; N/A ; 9.88 MHz ( period = 101.180 ns ) ; Arkanoid:inst|h_counter[17] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.940 ns ;
-; N/A ; 9.88 MHz ( period = 101.177 ns ) ; Arkanoid:inst|v_counter[12] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.930 ns ;
-; N/A ; 9.88 MHz ( period = 101.173 ns ) ; Arkanoid:inst|v_counter[7] ; Arkanoid:inst|blue_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.926 ns ;
-; N/A ; 9.88 MHz ( period = 101.173 ns ) ; Arkanoid:inst|v_counter[4] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.926 ns ;
-; N/A ; 9.88 MHz ( period = 101.171 ns ) ; Arkanoid:inst|v_counter[4] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.924 ns ;
-; N/A ; 9.89 MHz ( period = 101.159 ns ) ; Arkanoid:inst|v_counter[11] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.912 ns ;
-; N/A ; 9.89 MHz ( period = 101.153 ns ) ; Arkanoid:inst|h_counter[18] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.913 ns ;
-; N/A ; 9.89 MHz ( period = 101.151 ns ) ; Arkanoid:inst|h_counter[18] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.911 ns ;
-; N/A ; 9.89 MHz ( period = 101.148 ns ) ; Arkanoid:inst|v_counter[5] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.901 ns ;
-; N/A ; 9.89 MHz ( period = 101.137 ns ) ; Arkanoid:inst|v_counter[5] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.890 ns ;
-; N/A ; 9.89 MHz ( period = 101.136 ns ) ; Arkanoid:inst|h_counter[20] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.896 ns ;
-; N/A ; 9.89 MHz ( period = 101.135 ns ) ; Arkanoid:inst|v_counter[5] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.888 ns ;
-; N/A ; 9.89 MHz ( period = 101.129 ns ) ; Arkanoid:inst|v_counter[14] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.882 ns ;
-; N/A ; 9.89 MHz ( period = 101.124 ns ) ; Arkanoid:inst|v_counter[12] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.877 ns ;
-; N/A ; 9.89 MHz ( period = 101.114 ns ) ; Arkanoid:inst|h_counter[19] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.874 ns ;
-; N/A ; 9.89 MHz ( period = 101.112 ns ) ; Arkanoid:inst|h_counter[19] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.872 ns ;
-; N/A ; 9.89 MHz ( period = 101.101 ns ) ; Arkanoid:inst|h_counter[18] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.861 ns ;
-; N/A ; 9.89 MHz ( period = 101.096 ns ) ; Arkanoid:inst|h_counter[11] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.853 ns ;
-; N/A ; 9.89 MHz ( period = 101.096 ns ) ; Arkanoid:inst|h_counter[21] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.856 ns ;
-; N/A ; 9.89 MHz ( period = 101.094 ns ) ; Arkanoid:inst|h_counter[11] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.851 ns ;
-; N/A ; 9.89 MHz ( period = 101.093 ns ) ; Arkanoid:inst|h_counter[11] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.850 ns ;
-; N/A ; 9.89 MHz ( period = 101.093 ns ) ; Arkanoid:inst|v_counter[1] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.846 ns ;
-; N/A ; 9.89 MHz ( period = 101.090 ns ) ; Arkanoid:inst|h_counter[11] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.847 ns ;
-; N/A ; 9.89 MHz ( period = 101.071 ns ) ; Arkanoid:inst|v_counter[6] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.824 ns ;
-; N/A ; 9.89 MHz ( period = 101.068 ns ) ; Arkanoid:inst|v_counter[15] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.821 ns ;
-; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
-+-----------------------------------------+-----------------------------------------------------+-----------------------------+-------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Setup: 'clk_50MHz' ;
++-----------------------------------------+-----------------------------------------------------+--------------------------------------+------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+
+; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
++-----------------------------------------+-----------------------------------------------------+--------------------------------------+------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+
+; N/A ; 7.55 MHz ( period = 132.461 ns ) ; Arkanoid:inst|platform1_position[3] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 132.203 ns ;
+; N/A ; 7.55 MHz ( period = 132.456 ns ) ; Arkanoid:inst|platform1_position[3] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 132.198 ns ;
+; N/A ; 7.55 MHz ( period = 132.389 ns ) ; Arkanoid:inst|platform1_position[10] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 132.131 ns ;
+; N/A ; 7.55 MHz ( period = 132.384 ns ) ; Arkanoid:inst|platform1_position[10] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 132.126 ns ;
+; N/A ; 7.56 MHz ( period = 132.263 ns ) ; Arkanoid:inst|platform1_position[8] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 132.005 ns ;
+; N/A ; 7.56 MHz ( period = 132.258 ns ) ; Arkanoid:inst|platform1_position[8] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 132.000 ns ;
+; N/A ; 7.56 MHz ( period = 132.248 ns ) ; Arkanoid:inst|platform1_position[4] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.990 ns ;
+; N/A ; 7.56 MHz ( period = 132.243 ns ) ; Arkanoid:inst|platform1_position[4] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.985 ns ;
+; N/A ; 7.57 MHz ( period = 132.172 ns ) ; Arkanoid:inst|platform1_position[2] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.914 ns ;
+; N/A ; 7.57 MHz ( period = 132.168 ns ) ; Arkanoid:inst|platform1_position[1] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.910 ns ;
+; N/A ; 7.57 MHz ( period = 132.167 ns ) ; Arkanoid:inst|platform1_position[2] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.909 ns ;
+; N/A ; 7.57 MHz ( period = 132.163 ns ) ; Arkanoid:inst|platform1_position[1] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.905 ns ;
+; N/A ; 7.57 MHz ( period = 132.108 ns ) ; Arkanoid:inst|platform1_position[3] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.850 ns ;
+; N/A ; 7.57 MHz ( period = 132.080 ns ) ; Arkanoid:inst|platform1_position[7] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.822 ns ;
+; N/A ; 7.57 MHz ( period = 132.075 ns ) ; Arkanoid:inst|platform1_position[7] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.817 ns ;
+; N/A ; 7.57 MHz ( period = 132.061 ns ) ; Arkanoid:inst|platform1_position[13] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.803 ns ;
+; N/A ; 7.57 MHz ( period = 132.056 ns ) ; Arkanoid:inst|platform1_position[13] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.798 ns ;
+; N/A ; 7.57 MHz ( period = 132.036 ns ) ; Arkanoid:inst|platform1_position[10] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.778 ns ;
+; N/A ; 7.57 MHz ( period = 132.022 ns ) ; Arkanoid:inst|platform1_position[0] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.764 ns ;
+; N/A ; 7.57 MHz ( period = 132.017 ns ) ; Arkanoid:inst|platform1_position[0] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.759 ns ;
+; N/A ; 7.58 MHz ( period = 131.978 ns ) ; Arkanoid:inst|platform1_position[5] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.720 ns ;
+; N/A ; 7.58 MHz ( period = 131.973 ns ) ; Arkanoid:inst|platform1_position[5] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.715 ns ;
+; N/A ; 7.58 MHz ( period = 131.910 ns ) ; Arkanoid:inst|platform1_position[8] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.652 ns ;
+; N/A ; 7.58 MHz ( period = 131.902 ns ) ; Arkanoid:inst|platform1_position[11] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.643 ns ;
+; N/A ; 7.58 MHz ( period = 131.897 ns ) ; Arkanoid:inst|platform1_position[11] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.638 ns ;
+; N/A ; 7.58 MHz ( period = 131.895 ns ) ; Arkanoid:inst|platform1_position[4] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.637 ns ;
+; N/A ; 7.58 MHz ( period = 131.843 ns ) ; Arkanoid:inst|platform1_position[9] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.585 ns ;
+; N/A ; 7.59 MHz ( period = 131.838 ns ) ; Arkanoid:inst|platform1_position[9] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.580 ns ;
+; N/A ; 7.59 MHz ( period = 131.836 ns ) ; Arkanoid:inst|platform1_position[15] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.578 ns ;
+; N/A ; 7.59 MHz ( period = 131.831 ns ) ; Arkanoid:inst|platform1_position[15] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.573 ns ;
+; N/A ; 7.59 MHz ( period = 131.819 ns ) ; Arkanoid:inst|platform1_position[2] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.561 ns ;
+; N/A ; 7.59 MHz ( period = 131.815 ns ) ; Arkanoid:inst|platform1_position[1] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.557 ns ;
+; N/A ; 7.59 MHz ( period = 131.727 ns ) ; Arkanoid:inst|platform1_position[7] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.469 ns ;
+; N/A ; 7.59 MHz ( period = 131.708 ns ) ; Arkanoid:inst|platform1_position[13] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.450 ns ;
+; N/A ; 7.59 MHz ( period = 131.705 ns ) ; Arkanoid:inst|platform1_position[3] ; Arkanoid:inst|hex1_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.446 ns ;
+; N/A ; 7.59 MHz ( period = 131.705 ns ) ; Arkanoid:inst|platform1_position[3] ; Arkanoid:inst|hex1_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.446 ns ;
+; N/A ; 7.59 MHz ( period = 131.702 ns ) ; Arkanoid:inst|platform1_position[3] ; Arkanoid:inst|hex1_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.443 ns ;
+; N/A ; 7.59 MHz ( period = 131.682 ns ) ; Arkanoid:inst|platform1_position[6] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.424 ns ;
+; N/A ; 7.59 MHz ( period = 131.677 ns ) ; Arkanoid:inst|platform1_position[6] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.419 ns ;
+; N/A ; 7.59 MHz ( period = 131.671 ns ) ; Arkanoid:inst|platform1_position[14] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.412 ns ;
+; N/A ; 7.59 MHz ( period = 131.669 ns ) ; Arkanoid:inst|platform1_position[0] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.411 ns ;
+; N/A ; 7.59 MHz ( period = 131.666 ns ) ; Arkanoid:inst|platform1_position[14] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.407 ns ;
+; N/A ; 7.60 MHz ( period = 131.633 ns ) ; Arkanoid:inst|platform1_position[10] ; Arkanoid:inst|hex1_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.374 ns ;
+; N/A ; 7.60 MHz ( period = 131.633 ns ) ; Arkanoid:inst|platform1_position[10] ; Arkanoid:inst|hex1_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.374 ns ;
+; N/A ; 7.60 MHz ( period = 131.630 ns ) ; Arkanoid:inst|platform1_position[10] ; Arkanoid:inst|hex1_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.371 ns ;
+; N/A ; 7.60 MHz ( period = 131.625 ns ) ; Arkanoid:inst|platform1_position[5] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.367 ns ;
+; N/A ; 7.60 MHz ( period = 131.585 ns ) ; Arkanoid:inst|platform1_position[3] ; Arkanoid:inst|hex0_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.337 ns ;
+; N/A ; 7.60 MHz ( period = 131.549 ns ) ; Arkanoid:inst|platform1_position[11] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.290 ns ;
+; N/A ; 7.60 MHz ( period = 131.531 ns ) ; Arkanoid:inst|platform1_position[12] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.273 ns ;
+; N/A ; 7.60 MHz ( period = 131.526 ns ) ; Arkanoid:inst|platform1_position[12] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.268 ns ;
+; N/A ; 7.60 MHz ( period = 131.525 ns ) ; Arkanoid:inst|platform1_position[27] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.269 ns ;
+; N/A ; 7.60 MHz ( period = 131.520 ns ) ; Arkanoid:inst|platform1_position[27] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.264 ns ;
+; N/A ; 7.60 MHz ( period = 131.514 ns ) ; Debouncer:inst2|debounced ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.254 ns ;
+; N/A ; 7.60 MHz ( period = 131.513 ns ) ; Arkanoid:inst|platform1_position[16] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.257 ns ;
+; N/A ; 7.60 MHz ( period = 131.513 ns ) ; Arkanoid:inst|platform1_position[10] ; Arkanoid:inst|hex0_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.265 ns ;
+; N/A ; 7.60 MHz ( period = 131.511 ns ) ; Arkanoid:inst|game_state ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.253 ns ;
+; N/A ; 7.60 MHz ( period = 131.511 ns ) ; Arkanoid:inst|platform1_position[28] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.255 ns ;
+; N/A ; 7.60 MHz ( period = 131.509 ns ) ; Debouncer:inst2|debounced ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.249 ns ;
+; N/A ; 7.60 MHz ( period = 131.508 ns ) ; Arkanoid:inst|platform1_position[16] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.252 ns ;
+; N/A ; 7.60 MHz ( period = 131.507 ns ) ; Arkanoid:inst|platform1_position[8] ; Arkanoid:inst|hex1_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.248 ns ;
+; N/A ; 7.60 MHz ( period = 131.507 ns ) ; Arkanoid:inst|platform1_position[8] ; Arkanoid:inst|hex1_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.248 ns ;
+; N/A ; 7.60 MHz ( period = 131.506 ns ) ; Arkanoid:inst|game_state ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.248 ns ;
+; N/A ; 7.60 MHz ( period = 131.506 ns ) ; Arkanoid:inst|platform1_position[28] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.250 ns ;
+; N/A ; 7.60 MHz ( period = 131.504 ns ) ; Arkanoid:inst|platform1_position[8] ; Arkanoid:inst|hex1_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.245 ns ;
+; N/A ; 7.61 MHz ( period = 131.492 ns ) ; Arkanoid:inst|platform1_position[4] ; Arkanoid:inst|hex1_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.233 ns ;
+; N/A ; 7.61 MHz ( period = 131.492 ns ) ; Arkanoid:inst|platform1_position[4] ; Arkanoid:inst|hex1_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.233 ns ;
+; N/A ; 7.61 MHz ( period = 131.490 ns ) ; Arkanoid:inst|platform1_position[9] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.232 ns ;
+; N/A ; 7.61 MHz ( period = 131.489 ns ) ; Arkanoid:inst|platform1_position[4] ; Arkanoid:inst|hex1_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.230 ns ;
+; N/A ; 7.61 MHz ( period = 131.483 ns ) ; Arkanoid:inst|platform1_position[15] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.225 ns ;
+; N/A ; 7.61 MHz ( period = 131.431 ns ) ; Arkanoid:inst|platform1_position[30] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.175 ns ;
+; N/A ; 7.61 MHz ( period = 131.426 ns ) ; Arkanoid:inst|platform1_position[30] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.170 ns ;
+; N/A ; 7.61 MHz ( period = 131.416 ns ) ; Arkanoid:inst|platform1_position[2] ; Arkanoid:inst|hex1_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.157 ns ;
+; N/A ; 7.61 MHz ( period = 131.416 ns ) ; Arkanoid:inst|platform1_position[2] ; Arkanoid:inst|hex1_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.157 ns ;
+; N/A ; 7.61 MHz ( period = 131.413 ns ) ; Arkanoid:inst|platform1_position[2] ; Arkanoid:inst|hex1_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.154 ns ;
+; N/A ; 7.61 MHz ( period = 131.412 ns ) ; Arkanoid:inst|platform1_position[1] ; Arkanoid:inst|hex1_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.153 ns ;
+; N/A ; 7.61 MHz ( period = 131.412 ns ) ; Arkanoid:inst|platform1_position[1] ; Arkanoid:inst|hex1_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.153 ns ;
+; N/A ; 7.61 MHz ( period = 131.409 ns ) ; Arkanoid:inst|platform1_position[1] ; Arkanoid:inst|hex1_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.150 ns ;
+; N/A ; 7.61 MHz ( period = 131.387 ns ) ; Arkanoid:inst|platform1_position[8] ; Arkanoid:inst|hex0_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.139 ns ;
+; N/A ; 7.61 MHz ( period = 131.373 ns ) ; Arkanoid:inst|platform1_position[25] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.117 ns ;
+; N/A ; 7.61 MHz ( period = 131.372 ns ) ; Arkanoid:inst|platform1_position[4] ; Arkanoid:inst|hex0_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.124 ns ;
+; N/A ; 7.61 MHz ( period = 131.368 ns ) ; Arkanoid:inst|platform1_position[25] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.112 ns ;
+; N/A ; 7.61 MHz ( period = 131.329 ns ) ; Arkanoid:inst|platform1_position[6] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.071 ns ;
+; N/A ; 7.61 MHz ( period = 131.327 ns ) ; Arkanoid:inst|platform1_position[21] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.071 ns ;
+; N/A ; 7.61 MHz ( period = 131.324 ns ) ; Arkanoid:inst|platform1_position[7] ; Arkanoid:inst|hex1_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.065 ns ;
+; N/A ; 7.61 MHz ( period = 131.324 ns ) ; Arkanoid:inst|platform1_position[7] ; Arkanoid:inst|hex1_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.065 ns ;
+; N/A ; 7.61 MHz ( period = 131.322 ns ) ; Arkanoid:inst|platform1_position[21] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.066 ns ;
+; N/A ; 7.61 MHz ( period = 131.321 ns ) ; Arkanoid:inst|platform1_position[7] ; Arkanoid:inst|hex1_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.062 ns ;
+; N/A ; 7.62 MHz ( period = 131.318 ns ) ; Arkanoid:inst|platform1_position[14] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.059 ns ;
+; N/A ; 7.62 MHz ( period = 131.305 ns ) ; Arkanoid:inst|platform1_position[13] ; Arkanoid:inst|hex1_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.046 ns ;
+; N/A ; 7.62 MHz ( period = 131.305 ns ) ; Arkanoid:inst|platform1_position[13] ; Arkanoid:inst|hex1_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.046 ns ;
+; N/A ; 7.62 MHz ( period = 131.302 ns ) ; Arkanoid:inst|platform1_position[13] ; Arkanoid:inst|hex1_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.043 ns ;
+; N/A ; 7.62 MHz ( period = 131.297 ns ) ; Arkanoid:inst|platform1_position[29] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.040 ns ;
+; N/A ; 7.62 MHz ( period = 131.296 ns ) ; Arkanoid:inst|platform1_position[2] ; Arkanoid:inst|hex0_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.048 ns ;
+; N/A ; 7.62 MHz ( period = 131.292 ns ) ; Arkanoid:inst|platform1_position[29] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.035 ns ;
+; N/A ; 7.62 MHz ( period = 131.292 ns ) ; Arkanoid:inst|platform1_position[1] ; Arkanoid:inst|hex0_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.044 ns ;
+; N/A ; 7.62 MHz ( period = 131.266 ns ) ; Arkanoid:inst|platform1_position[0] ; Arkanoid:inst|hex1_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.007 ns ;
+; N/A ; 7.62 MHz ( period = 131.266 ns ) ; Arkanoid:inst|platform1_position[0] ; Arkanoid:inst|hex1_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.007 ns ;
+; N/A ; 7.62 MHz ( period = 131.266 ns ) ; Debouncer:inst2|debounced ; Arkanoid:inst|hex3_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.033 ns ;
+; N/A ; 7.62 MHz ( period = 131.265 ns ) ; Debouncer:inst2|debounced ; Arkanoid:inst|hex3_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.032 ns ;
+; N/A ; 7.62 MHz ( period = 131.263 ns ) ; Arkanoid:inst|platform1_position[0] ; Arkanoid:inst|hex1_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 131.004 ns ;
+; N/A ; 7.62 MHz ( period = 131.226 ns ) ; Arkanoid:inst|platform1_position[31] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.966 ns ;
+; N/A ; 7.62 MHz ( period = 131.224 ns ) ; Arkanoid:inst|platform1_position[19] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.968 ns ;
+; N/A ; 7.62 MHz ( period = 131.223 ns ) ; Arkanoid:inst|button2_state ; Arkanoid:inst|hex3_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.995 ns ;
+; N/A ; 7.62 MHz ( period = 131.222 ns ) ; Arkanoid:inst|platform1_position[5] ; Arkanoid:inst|hex1_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.963 ns ;
+; N/A ; 7.62 MHz ( period = 131.222 ns ) ; Arkanoid:inst|platform1_position[5] ; Arkanoid:inst|hex1_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.963 ns ;
+; N/A ; 7.62 MHz ( period = 131.222 ns ) ; Arkanoid:inst|button2_state ; Arkanoid:inst|hex3_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.994 ns ;
+; N/A ; 7.62 MHz ( period = 131.221 ns ) ; Arkanoid:inst|platform1_position[31] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.961 ns ;
+; N/A ; 7.62 MHz ( period = 131.219 ns ) ; Arkanoid:inst|platform1_position[19] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.963 ns ;
+; N/A ; 7.62 MHz ( period = 131.219 ns ) ; Arkanoid:inst|platform1_position[5] ; Arkanoid:inst|hex1_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.960 ns ;
+; N/A ; 7.62 MHz ( period = 131.204 ns ) ; Arkanoid:inst|platform1_position[7] ; Arkanoid:inst|hex0_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.956 ns ;
+; N/A ; 7.62 MHz ( period = 131.196 ns ) ; Arkanoid:inst|platform1_position[3] ; Arkanoid:inst|hex1_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.937 ns ;
+; N/A ; 7.62 MHz ( period = 131.185 ns ) ; Arkanoid:inst|platform1_position[13] ; Arkanoid:inst|hex0_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.937 ns ;
+; N/A ; 7.62 MHz ( period = 131.179 ns ) ; Arkanoid:inst|platform1_position[3] ; Arkanoid:inst|hex1_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.920 ns ;
+; N/A ; 7.62 MHz ( period = 131.178 ns ) ; Arkanoid:inst|platform1_position[12] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.920 ns ;
+; N/A ; 7.62 MHz ( period = 131.176 ns ) ; Debouncer:inst3|debounced ; Arkanoid:inst|hex3_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.943 ns ;
+; N/A ; 7.62 MHz ( period = 131.175 ns ) ; Debouncer:inst3|debounced ; Arkanoid:inst|hex3_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.942 ns ;
+; N/A ; 7.62 MHz ( period = 131.172 ns ) ; Arkanoid:inst|platform1_position[27] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.916 ns ;
+; N/A ; 7.62 MHz ( period = 131.161 ns ) ; Debouncer:inst2|debounced ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.901 ns ;
+; N/A ; 7.62 MHz ( period = 131.160 ns ) ; Arkanoid:inst|platform1_position[16] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.904 ns ;
+; N/A ; 7.62 MHz ( period = 131.158 ns ) ; Arkanoid:inst|game_state ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.900 ns ;
+; N/A ; 7.62 MHz ( period = 131.158 ns ) ; Arkanoid:inst|platform1_position[28] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.902 ns ;
+; N/A ; 7.63 MHz ( period = 131.146 ns ) ; Arkanoid:inst|platform1_position[0] ; Arkanoid:inst|hex0_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.898 ns ;
+; N/A ; 7.63 MHz ( period = 131.146 ns ) ; Arkanoid:inst|platform1_position[11] ; Arkanoid:inst|hex1_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.886 ns ;
+; N/A ; 7.63 MHz ( period = 131.146 ns ) ; Arkanoid:inst|platform1_position[11] ; Arkanoid:inst|hex1_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.886 ns ;
+; N/A ; 7.63 MHz ( period = 131.143 ns ) ; Arkanoid:inst|platform1_position[11] ; Arkanoid:inst|hex1_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.883 ns ;
+; N/A ; 7.63 MHz ( period = 131.125 ns ) ; Arkanoid:inst|platform1_position[20] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.869 ns ;
+; N/A ; 7.63 MHz ( period = 131.124 ns ) ; Arkanoid:inst|platform1_position[10] ; Arkanoid:inst|hex1_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.865 ns ;
+; N/A ; 7.63 MHz ( period = 131.120 ns ) ; Arkanoid:inst|platform1_position[20] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.864 ns ;
+; N/A ; 7.63 MHz ( period = 131.113 ns ) ; Arkanoid:inst|platform1_position[3] ; Arkanoid:inst|hex0_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.855 ns ;
+; N/A ; 7.63 MHz ( period = 131.107 ns ) ; Arkanoid:inst|platform1_position[10] ; Arkanoid:inst|hex1_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.848 ns ;
+; N/A ; 7.63 MHz ( period = 131.102 ns ) ; Arkanoid:inst|platform1_position[5] ; Arkanoid:inst|hex0_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.854 ns ;
+; N/A ; 7.63 MHz ( period = 131.087 ns ) ; Arkanoid:inst|platform1_position[9] ; Arkanoid:inst|hex1_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.828 ns ;
+; N/A ; 7.63 MHz ( period = 131.087 ns ) ; Arkanoid:inst|platform1_position[9] ; Arkanoid:inst|hex1_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.828 ns ;
+; N/A ; 7.63 MHz ( period = 131.084 ns ) ; Arkanoid:inst|platform1_position[9] ; Arkanoid:inst|hex1_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.825 ns ;
+; N/A ; 7.63 MHz ( period = 131.080 ns ) ; Arkanoid:inst|platform1_position[15] ; Arkanoid:inst|hex1_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.821 ns ;
+; N/A ; 7.63 MHz ( period = 131.080 ns ) ; Arkanoid:inst|platform1_position[15] ; Arkanoid:inst|hex1_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.821 ns ;
+; N/A ; 7.63 MHz ( period = 131.078 ns ) ; Arkanoid:inst|platform1_position[30] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.822 ns ;
+; N/A ; 7.63 MHz ( period = 131.077 ns ) ; Arkanoid:inst|platform1_position[15] ; Arkanoid:inst|hex1_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.818 ns ;
+; N/A ; 7.63 MHz ( period = 131.041 ns ) ; Arkanoid:inst|platform1_position[10] ; Arkanoid:inst|hex0_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.783 ns ;
+; N/A ; 7.63 MHz ( period = 131.038 ns ) ; Arkanoid:inst|platform1_position[23] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.782 ns ;
+; N/A ; 7.63 MHz ( period = 131.033 ns ) ; Arkanoid:inst|platform1_position[23] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.777 ns ;
+; N/A ; 7.63 MHz ( period = 131.026 ns ) ; Arkanoid:inst|platform1_position[11] ; Arkanoid:inst|hex0_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.777 ns ;
+; N/A ; 7.63 MHz ( period = 131.020 ns ) ; Arkanoid:inst|platform1_position[25] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.764 ns ;
+; N/A ; 7.63 MHz ( period = 131.013 ns ) ; Arkanoid:inst|button1_state ; Arkanoid:inst|hex3_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.780 ns ;
+; N/A ; 7.63 MHz ( period = 131.012 ns ) ; Arkanoid:inst|button1_state ; Arkanoid:inst|hex3_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.779 ns ;
+; N/A ; 7.63 MHz ( period = 131.010 ns ) ; Arkanoid:inst|button1_state ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.750 ns ;
+; N/A ; 7.63 MHz ( period = 131.008 ns ) ; Arkanoid:inst|platform1_position[3] ; Arkanoid:inst|hex1_[4] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.750 ns ;
+; N/A ; 7.63 MHz ( period = 131.005 ns ) ; Arkanoid:inst|button1_state ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.745 ns ;
+; N/A ; 7.63 MHz ( period = 130.998 ns ) ; Arkanoid:inst|platform1_position[8] ; Arkanoid:inst|hex1_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.739 ns ;
+; N/A ; 7.63 MHz ( period = 130.989 ns ) ; Arkanoid:inst|platform1_position[26] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.732 ns ;
+; N/A ; 7.63 MHz ( period = 130.984 ns ) ; Arkanoid:inst|platform1_position[26] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.727 ns ;
+; N/A ; 7.63 MHz ( period = 130.983 ns ) ; Arkanoid:inst|platform1_position[4] ; Arkanoid:inst|hex1_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.724 ns ;
+; N/A ; 7.63 MHz ( period = 130.981 ns ) ; Arkanoid:inst|platform1_position[8] ; Arkanoid:inst|hex1_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.722 ns ;
+; N/A ; 7.64 MHz ( period = 130.974 ns ) ; Arkanoid:inst|platform1_position[21] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.718 ns ;
+; N/A ; 7.64 MHz ( period = 130.967 ns ) ; Arkanoid:inst|platform1_position[9] ; Arkanoid:inst|hex0_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.719 ns ;
+; N/A ; 7.64 MHz ( period = 130.966 ns ) ; Arkanoid:inst|platform1_position[4] ; Arkanoid:inst|hex1_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.707 ns ;
+; N/A ; 7.64 MHz ( period = 130.960 ns ) ; Arkanoid:inst|platform1_position[15] ; Arkanoid:inst|hex0_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.712 ns ;
+; N/A ; 7.64 MHz ( period = 130.945 ns ) ; Arkanoid:inst|platform1_position[17] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.689 ns ;
+; N/A ; 7.64 MHz ( period = 130.944 ns ) ; Arkanoid:inst|platform1_position[24] ; Arkanoid:inst|hex0_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.688 ns ;
+; N/A ; 7.64 MHz ( period = 130.944 ns ) ; Arkanoid:inst|platform1_position[29] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.687 ns ;
+; N/A ; 7.64 MHz ( period = 130.940 ns ) ; Arkanoid:inst|platform1_position[17] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.684 ns ;
+; N/A ; 7.64 MHz ( period = 130.939 ns ) ; Arkanoid:inst|platform1_position[24] ; Arkanoid:inst|hex0_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.683 ns ;
+; N/A ; 7.64 MHz ( period = 130.936 ns ) ; Arkanoid:inst|platform1_position[10] ; Arkanoid:inst|hex1_[4] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.678 ns ;
+; N/A ; 7.64 MHz ( period = 130.926 ns ) ; Arkanoid:inst|platform1_position[6] ; Arkanoid:inst|hex1_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.667 ns ;
+; N/A ; 7.64 MHz ( period = 130.926 ns ) ; Arkanoid:inst|platform1_position[6] ; Arkanoid:inst|hex1_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.667 ns ;
+; N/A ; 7.64 MHz ( period = 130.923 ns ) ; Arkanoid:inst|platform1_position[6] ; Arkanoid:inst|hex1_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.664 ns ;
+; N/A ; 7.64 MHz ( period = 130.915 ns ) ; Arkanoid:inst|platform1_position[8] ; Arkanoid:inst|hex0_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.657 ns ;
+; N/A ; 7.64 MHz ( period = 130.915 ns ) ; Arkanoid:inst|platform1_position[14] ; Arkanoid:inst|hex1_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.655 ns ;
+; N/A ; 7.64 MHz ( period = 130.915 ns ) ; Arkanoid:inst|platform1_position[14] ; Arkanoid:inst|hex1_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.655 ns ;
+; N/A ; 7.64 MHz ( period = 130.912 ns ) ; Arkanoid:inst|platform1_position[14] ; Arkanoid:inst|hex1_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.652 ns ;
+; N/A ; 7.64 MHz ( period = 130.907 ns ) ; Arkanoid:inst|platform1_position[2] ; Arkanoid:inst|hex1_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.648 ns ;
+; N/A ; 7.64 MHz ( period = 130.903 ns ) ; Arkanoid:inst|platform1_position[1] ; Arkanoid:inst|hex1_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.644 ns ;
+; N/A ; 7.64 MHz ( period = 130.900 ns ) ; Arkanoid:inst|platform1_position[4] ; Arkanoid:inst|hex0_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.642 ns ;
+; N/A ; 7.64 MHz ( period = 130.890 ns ) ; Arkanoid:inst|platform1_position[2] ; Arkanoid:inst|hex1_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.631 ns ;
+; N/A ; 7.64 MHz ( period = 130.886 ns ) ; Arkanoid:inst|platform1_position[1] ; Arkanoid:inst|hex1_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.627 ns ;
+; N/A ; 7.64 MHz ( period = 130.873 ns ) ; Arkanoid:inst|platform1_position[31] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.613 ns ;
+; N/A ; 7.64 MHz ( period = 130.871 ns ) ; Arkanoid:inst|platform1_position[19] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.615 ns ;
+; N/A ; 7.64 MHz ( period = 130.833 ns ) ; Arkanoid:inst|platform1_position[3] ; Arkanoid:inst|hex1_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.574 ns ;
+; N/A ; 7.64 MHz ( period = 130.824 ns ) ; Arkanoid:inst|platform1_position[2] ; Arkanoid:inst|hex0_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.566 ns ;
+; N/A ; 7.64 MHz ( period = 130.820 ns ) ; Arkanoid:inst|platform1_position[1] ; Arkanoid:inst|hex0_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.562 ns ;
+; N/A ; 7.64 MHz ( period = 130.815 ns ) ; Arkanoid:inst|platform1_position[7] ; Arkanoid:inst|hex1_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.556 ns ;
+; N/A ; 7.64 MHz ( period = 130.810 ns ) ; Arkanoid:inst|platform1_position[8] ; Arkanoid:inst|hex1_[4] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.552 ns ;
+; N/A ; 7.64 MHz ( period = 130.806 ns ) ; Arkanoid:inst|platform1_position[6] ; Arkanoid:inst|hex0_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.558 ns ;
+; N/A ; 7.65 MHz ( period = 130.798 ns ) ; Arkanoid:inst|platform1_position[7] ; Arkanoid:inst|hex1_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.539 ns ;
+; N/A ; 7.65 MHz ( period = 130.796 ns ) ; Arkanoid:inst|platform1_position[13] ; Arkanoid:inst|hex1_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.537 ns ;
+; N/A ; 7.65 MHz ( period = 130.795 ns ) ; Arkanoid:inst|platform1_position[14] ; Arkanoid:inst|hex0_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.546 ns ;
+; N/A ; 7.65 MHz ( period = 130.795 ns ) ; Arkanoid:inst|platform1_position[4] ; Arkanoid:inst|hex1_[4] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.537 ns ;
+; N/A ; 7.65 MHz ( period = 130.779 ns ) ; Arkanoid:inst|platform1_position[13] ; Arkanoid:inst|hex1_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.520 ns ;
+; N/A ; 7.65 MHz ( period = 130.775 ns ) ; Arkanoid:inst|platform1_position[12] ; Arkanoid:inst|hex1_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.516 ns ;
+; N/A ; 7.65 MHz ( period = 130.775 ns ) ; Arkanoid:inst|platform1_position[12] ; Arkanoid:inst|hex1_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.516 ns ;
+; N/A ; 7.65 MHz ( period = 130.772 ns ) ; Arkanoid:inst|platform1_position[20] ; Arkanoid:inst|hex0_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.516 ns ;
+; N/A ; 7.65 MHz ( period = 130.772 ns ) ; Arkanoid:inst|platform1_position[12] ; Arkanoid:inst|hex1_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.513 ns ;
+; N/A ; 7.65 MHz ( period = 130.769 ns ) ; Arkanoid:inst|platform1_position[27] ; Arkanoid:inst|hex1_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.512 ns ;
+; N/A ; 7.65 MHz ( period = 130.769 ns ) ; Arkanoid:inst|platform1_position[27] ; Arkanoid:inst|hex1_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.512 ns ;
+; N/A ; 7.65 MHz ( period = 130.766 ns ) ; Arkanoid:inst|platform1_position[27] ; Arkanoid:inst|hex1_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.509 ns ;
+; N/A ; 7.65 MHz ( period = 130.761 ns ) ; Arkanoid:inst|platform1_position[10] ; Arkanoid:inst|hex1_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.502 ns ;
+; N/A ; 7.65 MHz ( period = 130.758 ns ) ; Debouncer:inst2|debounced ; Arkanoid:inst|hex1_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.497 ns ;
+; N/A ; 7.65 MHz ( period = 130.758 ns ) ; Debouncer:inst2|debounced ; Arkanoid:inst|hex1_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.497 ns ;
+; N/A ; 7.65 MHz ( period = 130.757 ns ) ; Arkanoid:inst|platform1_position[16] ; Arkanoid:inst|hex1_[6] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.500 ns ;
+; N/A ; 7.65 MHz ( period = 130.757 ns ) ; Arkanoid:inst|platform1_position[16] ; Arkanoid:inst|hex1_[5] ; clk_50MHz ; clk_50MHz ; None ; None ; 130.500 ns ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
++-----------------------------------------+-----------------------------------------------------+--------------------------------------+------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+
-+------------------------------------------------------------------------------------------------+
-; tsu ;
-+-------+--------------+------------+---------+--------------------------------------+-----------+
-; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
-+-------+--------------+------------+---------+--------------------------------------+-----------+
-; N/A ; None ; 32.749 ns ; button3 ; Arkanoid:inst|blue_[0] ; clk_50MHz ;
-; N/A ; None ; 32.607 ns ; button3 ; Arkanoid:inst|red_[1] ; clk_50MHz ;
-; N/A ; None ; 32.604 ns ; button3 ; Arkanoid:inst|green_[3] ; clk_50MHz ;
-; N/A ; None ; 32.586 ns ; button3 ; Arkanoid:inst|red_[3] ; clk_50MHz ;
-; N/A ; None ; 31.939 ns ; button3 ; Arkanoid:inst|red_[2] ; clk_50MHz ;
-; N/A ; None ; 31.910 ns ; button3 ; Arkanoid:inst|blue_[3] ; clk_50MHz ;
-; N/A ; None ; 31.906 ns ; button3 ; Arkanoid:inst|green_[2] ; clk_50MHz ;
-; N/A ; None ; 31.904 ns ; button3 ; Arkanoid:inst|red_[0] ; clk_50MHz ;
-; N/A ; None ; 31.598 ns ; button1 ; Arkanoid:inst|blue_[0] ; clk_50MHz ;
-; N/A ; None ; 31.456 ns ; button1 ; Arkanoid:inst|red_[1] ; clk_50MHz ;
-; N/A ; None ; 31.454 ns ; button1 ; Arkanoid:inst|green_[3] ; clk_50MHz ;
-; N/A ; None ; 31.404 ns ; button1 ; Arkanoid:inst|red_[3] ; clk_50MHz ;
-; N/A ; None ; 30.759 ns ; button1 ; Arkanoid:inst|blue_[3] ; clk_50MHz ;
-; N/A ; None ; 30.757 ns ; button1 ; Arkanoid:inst|red_[2] ; clk_50MHz ;
-; N/A ; None ; 30.756 ns ; button1 ; Arkanoid:inst|green_[2] ; clk_50MHz ;
-; N/A ; None ; 30.753 ns ; button1 ; Arkanoid:inst|red_[0] ; clk_50MHz ;
-; N/A ; None ; 20.225 ns ; button4 ; Arkanoid:inst|blue_[0] ; clk_50MHz ;
-; N/A ; None ; 20.083 ns ; button4 ; Arkanoid:inst|red_[1] ; clk_50MHz ;
-; N/A ; None ; 20.080 ns ; button4 ; Arkanoid:inst|green_[3] ; clk_50MHz ;
-; N/A ; None ; 20.062 ns ; button4 ; Arkanoid:inst|red_[3] ; clk_50MHz ;
-; N/A ; None ; 19.573 ns ; button2 ; Arkanoid:inst|blue_[0] ; clk_50MHz ;
-; N/A ; None ; 19.431 ns ; button2 ; Arkanoid:inst|red_[1] ; clk_50MHz ;
-; N/A ; None ; 19.429 ns ; button2 ; Arkanoid:inst|green_[3] ; clk_50MHz ;
-; N/A ; None ; 19.415 ns ; button4 ; Arkanoid:inst|red_[2] ; clk_50MHz ;
-; N/A ; None ; 19.386 ns ; button4 ; Arkanoid:inst|blue_[3] ; clk_50MHz ;
-; N/A ; None ; 19.382 ns ; button4 ; Arkanoid:inst|green_[2] ; clk_50MHz ;
-; N/A ; None ; 19.380 ns ; button4 ; Arkanoid:inst|red_[0] ; clk_50MHz ;
-; N/A ; None ; 19.379 ns ; button2 ; Arkanoid:inst|red_[3] ; clk_50MHz ;
-; N/A ; None ; 18.801 ns ; button3 ; Arkanoid:inst|platform2_position[31] ; clk_50MHz ;
-; N/A ; None ; 18.734 ns ; button2 ; Arkanoid:inst|blue_[3] ; clk_50MHz ;
-; N/A ; None ; 18.732 ns ; button2 ; Arkanoid:inst|red_[2] ; clk_50MHz ;
-; N/A ; None ; 18.731 ns ; button2 ; Arkanoid:inst|green_[2] ; clk_50MHz ;
-; N/A ; None ; 18.728 ns ; button2 ; Arkanoid:inst|red_[0] ; clk_50MHz ;
-; N/A ; None ; 18.157 ns ; button3 ; Arkanoid:inst|platform2_position[29] ; clk_50MHz ;
-; N/A ; None ; 18.002 ns ; button3 ; Arkanoid:inst|platform2_position[30] ; clk_50MHz ;
-; N/A ; None ; 17.989 ns ; button3 ; Arkanoid:inst|platform2_position[26] ; clk_50MHz ;
-; N/A ; None ; 17.655 ns ; button3 ; Arkanoid:inst|platform2_position[27] ; clk_50MHz ;
-; N/A ; None ; 17.436 ns ; button3 ; Arkanoid:inst|platform2_position[28] ; clk_50MHz ;
-; N/A ; None ; 17.284 ns ; button3 ; Arkanoid:inst|platform2_position[25] ; clk_50MHz ;
-; N/A ; None ; 17.269 ns ; button3 ; Arkanoid:inst|platform2_position[19] ; clk_50MHz ;
-; N/A ; None ; 17.135 ns ; button3 ; Arkanoid:inst|platform2_position[24] ; clk_50MHz ;
-; N/A ; None ; 17.109 ns ; button3 ; Arkanoid:inst|platform2_position[17] ; clk_50MHz ;
-; N/A ; None ; 17.001 ns ; button3 ; Arkanoid:inst|platform2_position[14] ; clk_50MHz ;
-; N/A ; None ; 16.961 ns ; button3 ; Arkanoid:inst|platform2_position[20] ; clk_50MHz ;
-; N/A ; None ; 16.884 ns ; button1 ; Arkanoid:inst|platform1_position[25] ; clk_50MHz ;
-; N/A ; None ; 16.862 ns ; button3 ; Arkanoid:inst|platform2_position[3] ; clk_50MHz ;
-; N/A ; None ; 16.851 ns ; button3 ; Arkanoid:inst|platform2_position[22] ; clk_50MHz ;
-; N/A ; None ; 16.816 ns ; button1 ; Arkanoid:inst|platform1_position[30] ; clk_50MHz ;
-; N/A ; None ; 16.816 ns ; button3 ; Arkanoid:inst|platform2_position[18] ; clk_50MHz ;
-; N/A ; None ; 16.770 ns ; button3 ; Arkanoid:inst|platform2_position[23] ; clk_50MHz ;
-; N/A ; None ; 16.703 ns ; button3 ; Arkanoid:inst|platform2_position[16] ; clk_50MHz ;
-; N/A ; None ; 16.671 ns ; button1 ; Arkanoid:inst|platform1_position[29] ; clk_50MHz ;
-; N/A ; None ; 16.468 ns ; button1 ; Arkanoid:inst|platform1_position[27] ; clk_50MHz ;
-; N/A ; None ; 16.439 ns ; button3 ; Arkanoid:inst|platform2_position[21] ; clk_50MHz ;
-; N/A ; None ; 16.357 ns ; button3 ; Arkanoid:inst|platform2_position[12] ; clk_50MHz ;
-; N/A ; None ; 16.299 ns ; button1 ; Arkanoid:inst|platform1_position[28] ; clk_50MHz ;
-; N/A ; None ; 16.240 ns ; button3 ; Arkanoid:inst|platform2_position[11] ; clk_50MHz ;
-; N/A ; None ; 16.228 ns ; button3 ; Arkanoid:inst|platform2_position[8] ; clk_50MHz ;
-; N/A ; None ; 16.217 ns ; button3 ; Arkanoid:inst|platform2_position[13] ; clk_50MHz ;
-; N/A ; None ; 16.213 ns ; button1 ; Arkanoid:inst|platform1_position[31] ; clk_50MHz ;
-; N/A ; None ; 16.158 ns ; button3 ; Arkanoid:inst|platform2_position[15] ; clk_50MHz ;
-; N/A ; None ; 16.144 ns ; button3 ; Arkanoid:inst|platform2_position[9] ; clk_50MHz ;
-; N/A ; None ; 16.134 ns ; button3 ; Arkanoid:inst|platform2_position[10] ; clk_50MHz ;
-; N/A ; None ; 16.006 ns ; button1 ; Arkanoid:inst|platform1_position[26] ; clk_50MHz ;
-; N/A ; None ; 15.993 ns ; button1 ; Arkanoid:inst|platform1_position[22] ; clk_50MHz ;
-; N/A ; None ; 15.964 ns ; button1 ; Arkanoid:inst|platform1_position[3] ; clk_50MHz ;
-; N/A ; None ; 15.862 ns ; button3 ; Arkanoid:inst|platform2_position[7] ; clk_50MHz ;
-; N/A ; None ; 15.860 ns ; button1 ; Arkanoid:inst|platform1_position[21] ; clk_50MHz ;
-; N/A ; None ; 15.852 ns ; button1 ; Arkanoid:inst|platform1_position[24] ; clk_50MHz ;
-; N/A ; None ; 15.771 ns ; button1 ; Arkanoid:inst|platform1_position[20] ; clk_50MHz ;
-; N/A ; None ; 15.740 ns ; button3 ; Arkanoid:inst|platform2_position[6] ; clk_50MHz ;
-; N/A ; None ; 15.701 ns ; button1 ; Arkanoid:inst|platform1_position[23] ; clk_50MHz ;
-; N/A ; None ; 15.567 ns ; button1 ; Arkanoid:inst|platform1_position[17] ; clk_50MHz ;
-; N/A ; None ; 15.411 ns ; button1 ; Arkanoid:inst|platform1_position[19] ; clk_50MHz ;
-; N/A ; None ; 15.348 ns ; button1 ; Arkanoid:inst|platform1_position[15] ; clk_50MHz ;
-; N/A ; None ; 15.341 ns ; button3 ; Arkanoid:inst|platform2_position[2] ; clk_50MHz ;
-; N/A ; None ; 15.268 ns ; button3 ; Arkanoid:inst|platform2_position[5] ; clk_50MHz ;
-; N/A ; None ; 15.264 ns ; button3 ; Arkanoid:inst|platform2_position[4] ; clk_50MHz ;
-; N/A ; None ; 15.131 ns ; button1 ; Arkanoid:inst|platform1_position[18] ; clk_50MHz ;
-; N/A ; None ; 15.085 ns ; button1 ; Arkanoid:inst|platform1_position[12] ; clk_50MHz ;
-; N/A ; None ; 14.969 ns ; button1 ; Arkanoid:inst|platform1_position[16] ; clk_50MHz ;
-; N/A ; None ; 14.963 ns ; button1 ; Arkanoid:inst|platform1_position[11] ; clk_50MHz ;
-; N/A ; None ; 14.880 ns ; button1 ; Arkanoid:inst|platform1_position[10] ; clk_50MHz ;
-; N/A ; None ; 14.848 ns ; button1 ; Arkanoid:inst|platform1_position[14] ; clk_50MHz ;
-; N/A ; None ; 14.827 ns ; button1 ; Arkanoid:inst|platform1_position[9] ; clk_50MHz ;
-; N/A ; None ; 14.770 ns ; button1 ; Arkanoid:inst|platform1_position[13] ; clk_50MHz ;
-; N/A ; None ; 14.754 ns ; button1 ; Arkanoid:inst|platform1_position[8] ; clk_50MHz ;
-; N/A ; None ; 14.637 ns ; button3 ; Arkanoid:inst|platform2_position[1] ; clk_50MHz ;
-; N/A ; None ; 14.560 ns ; button1 ; Arkanoid:inst|platform1_position[6] ; clk_50MHz ;
-; N/A ; None ; 14.552 ns ; button1 ; Arkanoid:inst|platform1_position[7] ; clk_50MHz ;
-; N/A ; None ; 14.492 ns ; button3 ; Arkanoid:inst|platform2_position[0] ; clk_50MHz ;
-; N/A ; None ; 14.437 ns ; button1 ; Arkanoid:inst|platform1_position[5] ; clk_50MHz ;
-; N/A ; None ; 14.350 ns ; button1 ; Arkanoid:inst|platform1_position[4] ; clk_50MHz ;
-; N/A ; None ; 14.138 ns ; button1 ; Arkanoid:inst|platform1_position[2] ; clk_50MHz ;
-; N/A ; None ; 14.006 ns ; button1 ; Arkanoid:inst|platform1_position[1] ; clk_50MHz ;
-; N/A ; None ; 13.300 ns ; button1 ; Arkanoid:inst|platform1_position[0] ; clk_50MHz ;
-; N/A ; None ; 5.014 ns ; button2 ; Arkanoid:inst|platform1_position[3] ; clk_50MHz ;
-; N/A ; None ; 4.949 ns ; button4 ; Arkanoid:inst|led_[1] ; clk_50MHz ;
-; N/A ; None ; 4.949 ns ; button4 ; Arkanoid:inst|led_[0] ; clk_50MHz ;
-; N/A ; None ; 4.904 ns ; button4 ; Arkanoid:inst|platform2_position[3] ; clk_50MHz ;
-; N/A ; None ; 4.602 ns ; button4 ; Arkanoid:inst|button4_state ; clk_50MHz ;
-; N/A ; None ; 3.879 ns ; button2 ; Arkanoid:inst|button2_state ; clk_50MHz ;
-; N/A ; None ; 3.879 ns ; button2 ; Arkanoid:inst|led_[5] ; clk_50MHz ;
-; N/A ; None ; 3.879 ns ; button2 ; Arkanoid:inst|led_[4] ; clk_50MHz ;
-; N/A ; None ; 3.628 ns ; button4 ; Arkanoid:inst|platform2_position[31] ; clk_50MHz ;
-; N/A ; None ; 3.627 ns ; button4 ; Arkanoid:inst|platform2_position[12] ; clk_50MHz ;
-; N/A ; None ; 3.625 ns ; button4 ; Arkanoid:inst|platform2_position[11] ; clk_50MHz ;
-; N/A ; None ; 3.599 ns ; button3 ; Arkanoid:inst|button3_state ; clk_50MHz ;
-; N/A ; None ; 3.599 ns ; button3 ; Arkanoid:inst|led_[3] ; clk_50MHz ;
-; N/A ; None ; 3.599 ns ; button3 ; Arkanoid:inst|led_[2] ; clk_50MHz ;
-; N/A ; None ; 3.574 ns ; button4 ; Arkanoid:inst|platform2_position[10] ; clk_50MHz ;
-; N/A ; None ; 3.574 ns ; button4 ; Arkanoid:inst|platform2_position[7] ; clk_50MHz ;
-; N/A ; None ; 3.574 ns ; button4 ; Arkanoid:inst|platform2_position[6] ; clk_50MHz ;
-; N/A ; None ; 3.571 ns ; button4 ; Arkanoid:inst|platform2_position[8] ; clk_50MHz ;
-; N/A ; None ; 3.569 ns ; button4 ; Arkanoid:inst|platform2_position[5] ; clk_50MHz ;
-; N/A ; None ; 3.518 ns ; button1 ; Arkanoid:inst|button1_state ; clk_50MHz ;
-; N/A ; None ; 3.518 ns ; button1 ; Arkanoid:inst|led_[7] ; clk_50MHz ;
-; N/A ; None ; 3.518 ns ; button1 ; Arkanoid:inst|led_[6] ; clk_50MHz ;
-; N/A ; None ; 3.501 ns ; button4 ; Arkanoid:inst|platform2_position[29] ; clk_50MHz ;
-; N/A ; None ; 3.305 ns ; button4 ; Arkanoid:inst|platform2_position[20] ; clk_50MHz ;
-; N/A ; None ; 3.304 ns ; button4 ; Arkanoid:inst|platform2_position[16] ; clk_50MHz ;
-; N/A ; None ; 3.303 ns ; button4 ; Arkanoid:inst|platform2_position[19] ; clk_50MHz ;
-; N/A ; None ; 3.302 ns ; button4 ; Arkanoid:inst|platform2_position[17] ; clk_50MHz ;
-; N/A ; None ; 3.301 ns ; button4 ; Arkanoid:inst|platform2_position[15] ; clk_50MHz ;
-; N/A ; None ; 3.286 ns ; button4 ; Arkanoid:inst|platform2_position[4] ; clk_50MHz ;
-; N/A ; None ; 3.284 ns ; button4 ; Arkanoid:inst|platform2_position[2] ; clk_50MHz ;
-; N/A ; None ; 3.282 ns ; button4 ; Arkanoid:inst|platform2_position[0] ; clk_50MHz ;
-; N/A ; None ; 3.282 ns ; button4 ; Arkanoid:inst|platform2_position[1] ; clk_50MHz ;
-; N/A ; None ; 3.219 ns ; button4 ; Arkanoid:inst|platform2_position[18] ; clk_50MHz ;
-; N/A ; None ; 3.218 ns ; button4 ; Arkanoid:inst|platform2_position[30] ; clk_50MHz ;
-; N/A ; None ; 3.168 ns ; button4 ; Arkanoid:inst|platform2_position[21] ; clk_50MHz ;
-; N/A ; None ; 3.165 ns ; button4 ; Arkanoid:inst|platform2_position[27] ; clk_50MHz ;
-; N/A ; None ; 2.951 ns ; button2 ; Arkanoid:inst|platform1_position[1] ; clk_50MHz ;
-; N/A ; None ; 2.946 ns ; button2 ; Arkanoid:inst|platform1_position[0] ; clk_50MHz ;
-; N/A ; None ; 2.828 ns ; button4 ; Arkanoid:inst|platform2_position[14] ; clk_50MHz ;
-; N/A ; None ; 2.828 ns ; button4 ; Arkanoid:inst|platform2_position[13] ; clk_50MHz ;
-; N/A ; None ; 2.821 ns ; button4 ; Arkanoid:inst|platform2_position[22] ; clk_50MHz ;
-; N/A ; None ; 2.820 ns ; button4 ; Arkanoid:inst|platform2_position[9] ; clk_50MHz ;
-; N/A ; None ; 2.819 ns ; button4 ; Arkanoid:inst|platform2_position[26] ; clk_50MHz ;
-; N/A ; None ; 2.818 ns ; button4 ; Arkanoid:inst|platform2_position[28] ; clk_50MHz ;
-; N/A ; None ; 2.818 ns ; button4 ; Arkanoid:inst|platform2_position[23] ; clk_50MHz ;
-; N/A ; None ; 2.814 ns ; button4 ; Arkanoid:inst|platform2_position[24] ; clk_50MHz ;
-; N/A ; None ; 2.813 ns ; button4 ; Arkanoid:inst|platform2_position[25] ; clk_50MHz ;
-; N/A ; None ; 2.755 ns ; button2 ; Arkanoid:inst|platform1_position[13] ; clk_50MHz ;
-; N/A ; None ; 2.755 ns ; button2 ; Arkanoid:inst|platform1_position[14] ; clk_50MHz ;
-; N/A ; None ; 2.751 ns ; button2 ; Arkanoid:inst|platform1_position[15] ; clk_50MHz ;
-; N/A ; None ; 2.706 ns ; button2 ; Arkanoid:inst|platform1_position[21] ; clk_50MHz ;
-; N/A ; None ; 2.706 ns ; button2 ; Arkanoid:inst|platform1_position[30] ; clk_50MHz ;
-; N/A ; None ; 2.705 ns ; button2 ; Arkanoid:inst|platform1_position[25] ; clk_50MHz ;
-; N/A ; None ; 2.704 ns ; button2 ; Arkanoid:inst|platform1_position[28] ; clk_50MHz ;
-; N/A ; None ; 2.702 ns ; button2 ; Arkanoid:inst|platform1_position[23] ; clk_50MHz ;
-; N/A ; None ; 2.702 ns ; button2 ; Arkanoid:inst|platform1_position[2] ; clk_50MHz ;
-; N/A ; None ; 2.696 ns ; button2 ; Arkanoid:inst|platform1_position[24] ; clk_50MHz ;
-; N/A ; None ; 2.693 ns ; button2 ; Arkanoid:inst|platform1_position[26] ; clk_50MHz ;
-; N/A ; None ; 2.577 ns ; button2 ; Arkanoid:inst|platform1_position[16] ; clk_50MHz ;
-; N/A ; None ; 2.575 ns ; button2 ; Arkanoid:inst|platform1_position[19] ; clk_50MHz ;
-; N/A ; None ; 2.573 ns ; button2 ; Arkanoid:inst|platform1_position[18] ; clk_50MHz ;
-; N/A ; None ; 2.573 ns ; button2 ; Arkanoid:inst|platform1_position[17] ; clk_50MHz ;
-; N/A ; None ; 2.572 ns ; button2 ; Arkanoid:inst|platform1_position[31] ; clk_50MHz ;
-; N/A ; None ; 2.572 ns ; button2 ; Arkanoid:inst|platform1_position[20] ; clk_50MHz ;
-; N/A ; None ; 2.327 ns ; button2 ; Arkanoid:inst|platform1_position[4] ; clk_50MHz ;
-; N/A ; None ; 2.326 ns ; button2 ; Arkanoid:inst|platform1_position[11] ; clk_50MHz ;
-; N/A ; None ; 2.325 ns ; button2 ; Arkanoid:inst|platform1_position[6] ; clk_50MHz ;
-; N/A ; None ; 2.324 ns ; button2 ; Arkanoid:inst|platform1_position[7] ; clk_50MHz ;
-; N/A ; None ; 2.322 ns ; button2 ; Arkanoid:inst|platform1_position[10] ; clk_50MHz ;
-; N/A ; None ; 2.321 ns ; button2 ; Arkanoid:inst|platform1_position[12] ; clk_50MHz ;
-; N/A ; None ; 2.320 ns ; button2 ; Arkanoid:inst|platform1_position[5] ; clk_50MHz ;
-; N/A ; None ; 2.318 ns ; button2 ; Arkanoid:inst|platform1_position[22] ; clk_50MHz ;
-; N/A ; None ; 2.315 ns ; button2 ; Arkanoid:inst|platform1_position[9] ; clk_50MHz ;
-; N/A ; None ; 2.313 ns ; button2 ; Arkanoid:inst|platform1_position[8] ; clk_50MHz ;
-; N/A ; None ; 2.312 ns ; button2 ; Arkanoid:inst|platform1_position[27] ; clk_50MHz ;
-; N/A ; None ; 2.310 ns ; button2 ; Arkanoid:inst|platform1_position[29] ; clk_50MHz ;
-+-------+--------------+------------+---------+--------------------------------------+-----------+
++-----------------------------------------------------------------------------------------+
+; tsu ;
++-------+--------------+------------+---------+-------------------------------+-----------+
+; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
++-------+--------------+------------+---------+-------------------------------+-----------+
+; N/A ; None ; 3.159 ns ; button4 ; Debouncer:inst5|button_reg[0] ; clk_50MHz ;
+; N/A ; None ; 2.235 ns ; button2 ; Debouncer:inst3|button_reg[0] ; clk_50MHz ;
+; N/A ; None ; 2.175 ns ; button3 ; Debouncer:inst4|button_reg[0] ; clk_50MHz ;
+; N/A ; None ; 2.020 ns ; button1 ; Debouncer:inst2|button_reg[0] ; clk_50MHz ;
++-------+--------------+------------+---------+-------------------------------+-----------+
+-----------------------------------------------------------------------------------------+
@@ -505,268 +337,130 @@ applicable agreement for further details.
+-------+--------------+------------+-----------------------------+----------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-----------------------------+----------+------------+
-; N/A ; None ; 15.668 ns ; Arkanoid:inst|v_counter[8] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 15.637 ns ; Arkanoid:inst|v_counter[7] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 15.288 ns ; Arkanoid:inst|h_counter[19] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 15.195 ns ; Arkanoid:inst|h_counter[1] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 15.161 ns ; Arkanoid:inst|v_counter[6] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 14.948 ns ; Arkanoid:inst|v_counter[13] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 14.923 ns ; Arkanoid:inst|v_counter[19] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 14.911 ns ; Arkanoid:inst|v_counter[17] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 14.895 ns ; Arkanoid:inst|v_counter[22] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 14.890 ns ; Arkanoid:inst|v_counter[20] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 14.889 ns ; Arkanoid:inst|v_counter[16] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 14.827 ns ; Arkanoid:inst|v_counter[24] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 14.814 ns ; Arkanoid:inst|v_counter[23] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 14.768 ns ; Arkanoid:inst|v_counter[18] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 14.632 ns ; Arkanoid:inst|v_counter[21] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 14.601 ns ; Arkanoid:inst|h_counter[2] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 14.552 ns ; Arkanoid:inst|v_counter[25] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 14.552 ns ; Arkanoid:inst|h_counter[29] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 14.516 ns ; Arkanoid:inst|v_counter[12] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 14.507 ns ; Arkanoid:inst|v_counter[10] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 14.455 ns ; Arkanoid:inst|h_counter[15] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 14.366 ns ; Arkanoid:inst|v_counter[11] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 14.283 ns ; Arkanoid:inst|h_counter[3] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 14.237 ns ; Arkanoid:inst|h_counter[11] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 14.195 ns ; Arkanoid:inst|h_counter[5] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 14.186 ns ; Arkanoid:inst|v_counter[14] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 14.157 ns ; Arkanoid:inst|h_counter[9] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 14.155 ns ; Arkanoid:inst|h_counter[8] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 14.091 ns ; Arkanoid:inst|v_counter[15] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 14.091 ns ; Arkanoid:inst|h_counter[0] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 13.961 ns ; Arkanoid:inst|v_counter[5] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 13.896 ns ; Arkanoid:inst|h_counter[13] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 13.889 ns ; Arkanoid:inst|h_counter[14] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 13.853 ns ; Arkanoid:inst|v_counter[1] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 13.822 ns ; Arkanoid:inst|h_counter[24] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 13.750 ns ; Arkanoid:inst|h_counter[18] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 13.749 ns ; Arkanoid:inst|h_counter[10] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 13.718 ns ; Arkanoid:inst|h_counter[12] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 13.692 ns ; Arkanoid:inst|h_counter[17] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 13.676 ns ; Arkanoid:inst|h_counter[16] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 13.632 ns ; Arkanoid:inst|v_counter[4] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 13.585 ns ; Arkanoid:inst|h_counter[21] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 13.573 ns ; Arkanoid:inst|h_counter[4] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 13.550 ns ; Arkanoid:inst|h_counter[23] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 13.466 ns ; Arkanoid:inst|v_counter[2] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 13.458 ns ; Arkanoid:inst|h_counter[20] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 13.405 ns ; Arkanoid:inst|v_counter[3] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 13.390 ns ; Arkanoid:inst|h_counter[22] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 13.244 ns ; Arkanoid:inst|h_counter[25] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 13.170 ns ; Arkanoid:inst|h_counter[6] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 13.011 ns ; Arkanoid:inst|v_counter[28] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 13.001 ns ; Arkanoid:inst|v_counter[27] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 12.849 ns ; Arkanoid:inst|v_counter[29] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 12.753 ns ; Arkanoid:inst|v_counter[30] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 12.720 ns ; Arkanoid:inst|v_counter[26] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 12.633 ns ; Arkanoid:inst|h_counter[28] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 12.628 ns ; Arkanoid:inst|h_counter[27] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 12.484 ns ; Arkanoid:inst|v_counter[31] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 12.352 ns ; Arkanoid:inst|h_counter[26] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 12.262 ns ; Arkanoid:inst|h_counter[30] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 12.173 ns ; Arkanoid:inst|h_counter[31] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 12.144 ns ; Arkanoid:inst|h_counter[7] ; h_sync ; clk_50MHz ;
-; N/A ; None ; 11.917 ns ; Arkanoid:inst|v_counter[9] ; v_sync ; clk_50MHz ;
-; N/A ; None ; 10.989 ns ; Arkanoid:inst|led_[5] ; led[5] ; clk_50MHz ;
-; N/A ; None ; 10.915 ns ; Arkanoid:inst|led_[3] ; led[3] ; clk_50MHz ;
-; N/A ; None ; 10.702 ns ; Arkanoid:inst|led_[1] ; led[1] ; clk_50MHz ;
-; N/A ; None ; 10.550 ns ; Arkanoid:inst|red_[0] ; red[0] ; clk_50MHz ;
-; N/A ; None ; 10.523 ns ; Arkanoid:inst|red_[3] ; red[3] ; clk_50MHz ;
-; N/A ; None ; 10.519 ns ; Arkanoid:inst|red_[2] ; red[2] ; clk_50MHz ;
-; N/A ; None ; 10.386 ns ; Arkanoid:inst|led_[4] ; led[4] ; clk_50MHz ;
-; N/A ; None ; 10.275 ns ; Arkanoid:inst|green_[3] ; green[3] ; clk_50MHz ;
-; N/A ; None ; 10.248 ns ; Arkanoid:inst|blue_[0] ; blue[0] ; clk_50MHz ;
-; N/A ; None ; 10.236 ns ; Arkanoid:inst|green_[2] ; green[2] ; clk_50MHz ;
-; N/A ; None ; 10.139 ns ; Arkanoid:inst|led_[6] ; led[6] ; clk_50MHz ;
-; N/A ; None ; 10.073 ns ; Arkanoid:inst|led_[2] ; led[2] ; clk_50MHz ;
-; N/A ; None ; 9.936 ns ; Arkanoid:inst|red_[1] ; red[1] ; clk_50MHz ;
-; N/A ; None ; 9.867 ns ; Arkanoid:inst|blue_[3] ; blue[3] ; clk_50MHz ;
-; N/A ; None ; 9.866 ns ; Arkanoid:inst|blue_[1] ; blue[1] ; clk_50MHz ;
-; N/A ; None ; 9.794 ns ; Arkanoid:inst|led_[7] ; led[7] ; clk_50MHz ;
-; N/A ; None ; 9.722 ns ; Arkanoid:inst|led_[0] ; led[0] ; clk_50MHz ;
-; N/A ; None ; 9.635 ns ; Arkanoid:inst|blue_[2] ; blue[2] ; clk_50MHz ;
+; N/A ; None ; 14.776 ns ; Arkanoid:inst|h_counter[0] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 14.744 ns ; Arkanoid:inst|h_counter[2] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 14.661 ns ; Arkanoid:inst|h_counter[4] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 14.642 ns ; Arkanoid:inst|h_counter[18] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 14.601 ns ; Arkanoid:inst|h_counter[16] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 14.574 ns ; Arkanoid:inst|h_counter[3] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 14.503 ns ; Arkanoid:inst|h_counter[22] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 14.461 ns ; Arkanoid:inst|h_counter[11] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 14.435 ns ; Arkanoid:inst|h_counter[13] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 14.429 ns ; Arkanoid:inst|h_counter[1] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 14.425 ns ; Arkanoid:inst|h_counter[17] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 14.386 ns ; Arkanoid:inst|h_counter[24] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 14.378 ns ; Arkanoid:inst|h_counter[25] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 14.330 ns ; Arkanoid:inst|h_counter[20] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 14.325 ns ; Arkanoid:inst|h_counter[15] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 14.311 ns ; Arkanoid:inst|h_counter[12] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 14.291 ns ; Arkanoid:inst|h_counter[14] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 14.241 ns ; Arkanoid:inst|h_counter[6] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 14.149 ns ; Arkanoid:inst|h_counter[8] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 14.066 ns ; Arkanoid:inst|h_counter[27] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 13.977 ns ; Arkanoid:inst|h_counter[23] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 13.945 ns ; Arkanoid:inst|h_counter[19] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 13.901 ns ; Arkanoid:inst|h_counter[5] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 13.890 ns ; Arkanoid:inst|h_counter[10] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 13.854 ns ; Arkanoid:inst|h_counter[29] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 13.808 ns ; Arkanoid:inst|h_counter[26] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 13.804 ns ; Arkanoid:inst|h_counter[21] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 13.757 ns ; Arkanoid:inst|h_counter[28] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 13.589 ns ; Arkanoid:inst|h_counter[9] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 13.461 ns ; Arkanoid:inst|v_counter[10] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 13.352 ns ; Arkanoid:inst|h_counter[30] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 13.194 ns ; Arkanoid:inst|v_counter[12] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 13.173 ns ; Arkanoid:inst|h_counter[31] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 13.145 ns ; Arkanoid:inst|v_counter[6] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 13.084 ns ; Arkanoid:inst|v_counter[8] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 13.058 ns ; Arkanoid:inst|v_counter[13] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 12.944 ns ; Arkanoid:inst|v_counter[4] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 12.918 ns ; Arkanoid:inst|v_counter[11] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 12.908 ns ; Arkanoid:inst|v_counter[7] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 12.779 ns ; Arkanoid:inst|h_counter[7] ; h_sync ; clk_50MHz ;
+; N/A ; None ; 12.460 ns ; Arkanoid:inst|v_counter[14] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 12.383 ns ; Arkanoid:inst|v_counter[15] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 12.255 ns ; Arkanoid:inst|v_counter[23] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 12.241 ns ; Arkanoid:inst|v_counter[1] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 12.235 ns ; Arkanoid:inst|v_counter[24] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 12.127 ns ; Arkanoid:inst|v_counter[5] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 12.100 ns ; Arkanoid:inst|v_counter[22] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 12.026 ns ; Arkanoid:inst|v_counter[3] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 11.930 ns ; Arkanoid:inst|v_counter[25] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 11.920 ns ; Arkanoid:inst|v_counter[16] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 11.911 ns ; Arkanoid:inst|v_counter[21] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 11.878 ns ; Arkanoid:inst|v_counter[20] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 11.834 ns ; Arkanoid:inst|v_counter[26] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 11.776 ns ; Arkanoid:inst|v_counter[17] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 11.762 ns ; Arkanoid:inst|v_counter[18] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 11.621 ns ; Arkanoid:inst|v_counter[19] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 11.576 ns ; Arkanoid:inst|v_counter[28] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 11.436 ns ; Arkanoid:inst|v_counter[27] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 11.336 ns ; Arkanoid:inst|v_counter[2] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 11.299 ns ; Arkanoid:inst|v_counter[29] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 10.988 ns ; Arkanoid:inst|led_[7] ; led[7] ; clk_50MHz ;
+; N/A ; None ; 10.984 ns ; Arkanoid:inst|v_counter[31] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 10.946 ns ; Arkanoid:inst|v_counter[30] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 10.671 ns ; Arkanoid:inst|v_counter[9] ; v_sync ; clk_50MHz ;
+; N/A ; None ; 10.666 ns ; Arkanoid:inst|hex3_[2] ; hex3[2] ; clk_50MHz ;
+; N/A ; None ; 10.458 ns ; Arkanoid:inst|hex3_[6] ; hex3[6] ; clk_50MHz ;
+; N/A ; None ; 10.397 ns ; Arkanoid:inst|led_[6] ; led[6] ; clk_50MHz ;
+; N/A ; None ; 10.390 ns ; Arkanoid:inst|led_[4] ; led[4] ; clk_50MHz ;
+; N/A ; None ; 10.381 ns ; Arkanoid:inst|hex2_[6] ; hex2[6] ; clk_50MHz ;
+; N/A ; None ; 10.366 ns ; Arkanoid:inst|hex3_[1] ; hex3[1] ; clk_50MHz ;
+; N/A ; None ; 10.335 ns ; Arkanoid:inst|hex2_[2] ; hex2[2] ; clk_50MHz ;
+; N/A ; None ; 10.214 ns ; Arkanoid:inst|hex2_[4] ; hex2[4] ; clk_50MHz ;
+; N/A ; None ; 10.202 ns ; Arkanoid:inst|hex2_[3] ; hex2[3] ; clk_50MHz ;
+; N/A ; None ; 10.183 ns ; Arkanoid:inst|hex2_[5] ; hex2[5] ; clk_50MHz ;
+; N/A ; None ; 10.154 ns ; Arkanoid:inst|hex3_[0] ; hex3[0] ; clk_50MHz ;
+; N/A ; None ; 10.103 ns ; Arkanoid:inst|hex2_[0] ; hex2[0] ; clk_50MHz ;
+; N/A ; None ; 10.096 ns ; Arkanoid:inst|red_[1] ; red[1] ; clk_50MHz ;
+; N/A ; None ; 10.023 ns ; Arkanoid:inst|led_[3] ; led[3] ; clk_50MHz ;
+; N/A ; None ; 9.974 ns ; Arkanoid:inst|hex3_[4] ; hex3[4] ; clk_50MHz ;
+; N/A ; None ; 9.965 ns ; Arkanoid:inst|hex2_[1] ; hex2[1] ; clk_50MHz ;
+; N/A ; None ; 9.938 ns ; Arkanoid:inst|green_[3] ; green[3] ; clk_50MHz ;
+; N/A ; None ; 9.915 ns ; Arkanoid:inst|red_[2] ; red[2] ; clk_50MHz ;
+; N/A ; None ; 9.886 ns ; Arkanoid:inst|hex3_[5] ; hex3[5] ; clk_50MHz ;
+; N/A ; None ; 9.881 ns ; Arkanoid:inst|red_[0] ; red[0] ; clk_50MHz ;
+; N/A ; None ; 9.870 ns ; Arkanoid:inst|led_[5] ; led[5] ; clk_50MHz ;
+; N/A ; None ; 9.845 ns ; Arkanoid:inst|red_[3] ; red[3] ; clk_50MHz ;
+; N/A ; None ; 9.845 ns ; Arkanoid:inst|green_[0] ; green[0] ; clk_50MHz ;
+; N/A ; None ; 9.630 ns ; Arkanoid:inst|hex3_[3] ; hex3[3] ; clk_50MHz ;
+; N/A ; None ; 9.617 ns ; Arkanoid:inst|blue_[1] ; blue[1] ; clk_50MHz ;
+; N/A ; None ; 9.614 ns ; Arkanoid:inst|blue_[0] ; blue[0] ; clk_50MHz ;
+; N/A ; None ; 9.603 ns ; Arkanoid:inst|green_[2] ; green[2] ; clk_50MHz ;
+; N/A ; None ; 9.600 ns ; Arkanoid:inst|green_[1] ; green[1] ; clk_50MHz ;
+; N/A ; None ; 9.466 ns ; Arkanoid:inst|led_[2] ; led[2] ; clk_50MHz ;
+; N/A ; None ; 9.406 ns ; Arkanoid:inst|hex0_[0] ; hex0[0] ; clk_50MHz ;
+; N/A ; None ; 9.327 ns ; Arkanoid:inst|hex0_[3] ; hex0[3] ; clk_50MHz ;
+; N/A ; None ; 9.305 ns ; Arkanoid:inst|blue_[3] ; blue[3] ; clk_50MHz ;
+; N/A ; None ; 9.278 ns ; Arkanoid:inst|blue_[2] ; blue[2] ; clk_50MHz ;
+; N/A ; None ; 9.201 ns ; Arkanoid:inst|hex1_[5] ; hex1[5] ; clk_50MHz ;
+; N/A ; None ; 9.190 ns ; Arkanoid:inst|led_[1] ; led[1] ; clk_50MHz ;
+; N/A ; None ; 9.188 ns ; Arkanoid:inst|hex0_[2] ; hex0[2] ; clk_50MHz ;
+; N/A ; None ; 9.184 ns ; Arkanoid:inst|hex1_[6] ; hex1[6] ; clk_50MHz ;
+; N/A ; None ; 9.179 ns ; Arkanoid:inst|hex1_[4] ; hex1[4] ; clk_50MHz ;
+; N/A ; None ; 9.179 ns ; Arkanoid:inst|hex0_[1] ; hex0[1] ; clk_50MHz ;
+; N/A ; None ; 9.149 ns ; Arkanoid:inst|hex1_[3] ; hex1[3] ; clk_50MHz ;
+; N/A ; None ; 9.144 ns ; Arkanoid:inst|hex1_[1] ; hex1[1] ; clk_50MHz ;
+; N/A ; None ; 9.144 ns ; Arkanoid:inst|hex1_[2] ; hex1[2] ; clk_50MHz ;
+; N/A ; None ; 9.138 ns ; Arkanoid:inst|led_[0] ; led[0] ; clk_50MHz ;
+; N/A ; None ; 9.066 ns ; Arkanoid:inst|hex0_[4] ; hex0[4] ; clk_50MHz ;
+; N/A ; None ; 9.064 ns ; Arkanoid:inst|hex0_[6] ; hex0[6] ; clk_50MHz ;
+; N/A ; None ; 9.059 ns ; Arkanoid:inst|hex0_[5] ; hex0[5] ; clk_50MHz ;
+; N/A ; None ; 8.867 ns ; Arkanoid:inst|hex1_[0] ; hex1[0] ; clk_50MHz ;
+-------+--------------+------------+-----------------------------+----------+------------+
-+-------------------------------------------------------------------------------------------------------+
-; th ;
-+---------------+-------------+------------+---------+--------------------------------------+-----------+
-; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
-+---------------+-------------+------------+---------+--------------------------------------+-----------+
-; N/A ; None ; -2.062 ns ; button2 ; Arkanoid:inst|platform1_position[29] ; clk_50MHz ;
-; N/A ; None ; -2.064 ns ; button2 ; Arkanoid:inst|platform1_position[27] ; clk_50MHz ;
-; N/A ; None ; -2.065 ns ; button2 ; Arkanoid:inst|platform1_position[8] ; clk_50MHz ;
-; N/A ; None ; -2.067 ns ; button2 ; Arkanoid:inst|platform1_position[9] ; clk_50MHz ;
-; N/A ; None ; -2.070 ns ; button2 ; Arkanoid:inst|platform1_position[22] ; clk_50MHz ;
-; N/A ; None ; -2.072 ns ; button2 ; Arkanoid:inst|platform1_position[5] ; clk_50MHz ;
-; N/A ; None ; -2.073 ns ; button2 ; Arkanoid:inst|platform1_position[12] ; clk_50MHz ;
-; N/A ; None ; -2.074 ns ; button2 ; Arkanoid:inst|platform1_position[10] ; clk_50MHz ;
-; N/A ; None ; -2.076 ns ; button2 ; Arkanoid:inst|platform1_position[7] ; clk_50MHz ;
-; N/A ; None ; -2.077 ns ; button2 ; Arkanoid:inst|platform1_position[6] ; clk_50MHz ;
-; N/A ; None ; -2.078 ns ; button2 ; Arkanoid:inst|platform1_position[11] ; clk_50MHz ;
-; N/A ; None ; -2.079 ns ; button2 ; Arkanoid:inst|platform1_position[4] ; clk_50MHz ;
-; N/A ; None ; -2.146 ns ; button1 ; Arkanoid:inst|led_[7] ; clk_50MHz ;
-; N/A ; None ; -2.151 ns ; button1 ; Arkanoid:inst|button1_state ; clk_50MHz ;
-; N/A ; None ; -2.151 ns ; button1 ; Arkanoid:inst|led_[6] ; clk_50MHz ;
-; N/A ; None ; -2.324 ns ; button2 ; Arkanoid:inst|platform1_position[31] ; clk_50MHz ;
-; N/A ; None ; -2.324 ns ; button2 ; Arkanoid:inst|platform1_position[20] ; clk_50MHz ;
-; N/A ; None ; -2.325 ns ; button2 ; Arkanoid:inst|platform1_position[18] ; clk_50MHz ;
-; N/A ; None ; -2.325 ns ; button2 ; Arkanoid:inst|platform1_position[17] ; clk_50MHz ;
-; N/A ; None ; -2.327 ns ; button2 ; Arkanoid:inst|platform1_position[19] ; clk_50MHz ;
-; N/A ; None ; -2.329 ns ; button2 ; Arkanoid:inst|platform1_position[16] ; clk_50MHz ;
-; N/A ; None ; -2.421 ns ; button3 ; Arkanoid:inst|led_[2] ; clk_50MHz ;
-; N/A ; None ; -2.423 ns ; button3 ; Arkanoid:inst|led_[3] ; clk_50MHz ;
-; N/A ; None ; -2.445 ns ; button2 ; Arkanoid:inst|platform1_position[26] ; clk_50MHz ;
-; N/A ; None ; -2.448 ns ; button2 ; Arkanoid:inst|platform1_position[24] ; clk_50MHz ;
-; N/A ; None ; -2.454 ns ; button2 ; Arkanoid:inst|platform1_position[23] ; clk_50MHz ;
-; N/A ; None ; -2.454 ns ; button2 ; Arkanoid:inst|platform1_position[2] ; clk_50MHz ;
-; N/A ; None ; -2.456 ns ; button2 ; Arkanoid:inst|platform1_position[28] ; clk_50MHz ;
-; N/A ; None ; -2.457 ns ; button2 ; Arkanoid:inst|platform1_position[25] ; clk_50MHz ;
-; N/A ; None ; -2.458 ns ; button2 ; Arkanoid:inst|platform1_position[21] ; clk_50MHz ;
-; N/A ; None ; -2.458 ns ; button2 ; Arkanoid:inst|platform1_position[30] ; clk_50MHz ;
-; N/A ; None ; -2.496 ns ; button2 ; Arkanoid:inst|button2_state ; clk_50MHz ;
-; N/A ; None ; -2.497 ns ; button2 ; Arkanoid:inst|led_[5] ; clk_50MHz ;
-; N/A ; None ; -2.497 ns ; button2 ; Arkanoid:inst|led_[4] ; clk_50MHz ;
-; N/A ; None ; -2.503 ns ; button2 ; Arkanoid:inst|platform1_position[15] ; clk_50MHz ;
-; N/A ; None ; -2.507 ns ; button2 ; Arkanoid:inst|platform1_position[13] ; clk_50MHz ;
-; N/A ; None ; -2.507 ns ; button2 ; Arkanoid:inst|platform1_position[14] ; clk_50MHz ;
-; N/A ; None ; -2.565 ns ; button4 ; Arkanoid:inst|platform2_position[25] ; clk_50MHz ;
-; N/A ; None ; -2.566 ns ; button4 ; Arkanoid:inst|platform2_position[24] ; clk_50MHz ;
-; N/A ; None ; -2.570 ns ; button4 ; Arkanoid:inst|platform2_position[28] ; clk_50MHz ;
-; N/A ; None ; -2.570 ns ; button4 ; Arkanoid:inst|platform2_position[23] ; clk_50MHz ;
-; N/A ; None ; -2.571 ns ; button4 ; Arkanoid:inst|platform2_position[26] ; clk_50MHz ;
-; N/A ; None ; -2.572 ns ; button4 ; Arkanoid:inst|platform2_position[9] ; clk_50MHz ;
-; N/A ; None ; -2.573 ns ; button4 ; Arkanoid:inst|platform2_position[22] ; clk_50MHz ;
-; N/A ; None ; -2.580 ns ; button4 ; Arkanoid:inst|platform2_position[14] ; clk_50MHz ;
-; N/A ; None ; -2.580 ns ; button4 ; Arkanoid:inst|platform2_position[13] ; clk_50MHz ;
-; N/A ; None ; -2.698 ns ; button2 ; Arkanoid:inst|platform1_position[0] ; clk_50MHz ;
-; N/A ; None ; -2.703 ns ; button2 ; Arkanoid:inst|platform1_position[1] ; clk_50MHz ;
-; N/A ; None ; -2.822 ns ; button3 ; Arkanoid:inst|button3_state ; clk_50MHz ;
-; N/A ; None ; -2.917 ns ; button4 ; Arkanoid:inst|platform2_position[27] ; clk_50MHz ;
-; N/A ; None ; -2.920 ns ; button4 ; Arkanoid:inst|platform2_position[21] ; clk_50MHz ;
-; N/A ; None ; -2.970 ns ; button4 ; Arkanoid:inst|platform2_position[30] ; clk_50MHz ;
-; N/A ; None ; -2.971 ns ; button4 ; Arkanoid:inst|platform2_position[18] ; clk_50MHz ;
-; N/A ; None ; -3.028 ns ; button4 ; Arkanoid:inst|button4_state ; clk_50MHz ;
-; N/A ; None ; -3.034 ns ; button4 ; Arkanoid:inst|platform2_position[0] ; clk_50MHz ;
-; N/A ; None ; -3.034 ns ; button4 ; Arkanoid:inst|platform2_position[1] ; clk_50MHz ;
-; N/A ; None ; -3.036 ns ; button4 ; Arkanoid:inst|platform2_position[2] ; clk_50MHz ;
-; N/A ; None ; -3.038 ns ; button4 ; Arkanoid:inst|platform2_position[4] ; clk_50MHz ;
-; N/A ; None ; -3.053 ns ; button4 ; Arkanoid:inst|platform2_position[15] ; clk_50MHz ;
-; N/A ; None ; -3.054 ns ; button4 ; Arkanoid:inst|platform2_position[17] ; clk_50MHz ;
-; N/A ; None ; -3.055 ns ; button4 ; Arkanoid:inst|platform2_position[19] ; clk_50MHz ;
-; N/A ; None ; -3.056 ns ; button4 ; Arkanoid:inst|platform2_position[16] ; clk_50MHz ;
-; N/A ; None ; -3.057 ns ; button4 ; Arkanoid:inst|platform2_position[20] ; clk_50MHz ;
-; N/A ; None ; -3.253 ns ; button4 ; Arkanoid:inst|platform2_position[29] ; clk_50MHz ;
-; N/A ; None ; -3.315 ns ; button4 ; Arkanoid:inst|led_[1] ; clk_50MHz ;
-; N/A ; None ; -3.315 ns ; button4 ; Arkanoid:inst|led_[0] ; clk_50MHz ;
-; N/A ; None ; -3.321 ns ; button4 ; Arkanoid:inst|platform2_position[5] ; clk_50MHz ;
-; N/A ; None ; -3.323 ns ; button4 ; Arkanoid:inst|platform2_position[8] ; clk_50MHz ;
-; N/A ; None ; -3.326 ns ; button4 ; Arkanoid:inst|platform2_position[10] ; clk_50MHz ;
-; N/A ; None ; -3.326 ns ; button4 ; Arkanoid:inst|platform2_position[7] ; clk_50MHz ;
-; N/A ; None ; -3.326 ns ; button4 ; Arkanoid:inst|platform2_position[6] ; clk_50MHz ;
-; N/A ; None ; -3.377 ns ; button4 ; Arkanoid:inst|platform2_position[11] ; clk_50MHz ;
-; N/A ; None ; -3.379 ns ; button4 ; Arkanoid:inst|platform2_position[12] ; clk_50MHz ;
-; N/A ; None ; -3.380 ns ; button4 ; Arkanoid:inst|platform2_position[31] ; clk_50MHz ;
-; N/A ; None ; -4.656 ns ; button1 ; Arkanoid:inst|platform1_position[22] ; clk_50MHz ;
-; N/A ; None ; -4.656 ns ; button4 ; Arkanoid:inst|platform2_position[3] ; clk_50MHz ;
-; N/A ; None ; -4.766 ns ; button2 ; Arkanoid:inst|platform1_position[3] ; clk_50MHz ;
-; N/A ; None ; -4.819 ns ; button1 ; Arkanoid:inst|platform1_position[21] ; clk_50MHz ;
-; N/A ; None ; -4.969 ns ; button1 ; Arkanoid:inst|platform1_position[8] ; clk_50MHz ;
-; N/A ; None ; -4.970 ns ; button1 ; Arkanoid:inst|platform1_position[7] ; clk_50MHz ;
-; N/A ; None ; -5.015 ns ; button1 ; Arkanoid:inst|platform1_position[6] ; clk_50MHz ;
-; N/A ; None ; -5.023 ns ; button1 ; Arkanoid:inst|platform1_position[4] ; clk_50MHz ;
-; N/A ; None ; -5.024 ns ; button1 ; Arkanoid:inst|platform1_position[5] ; clk_50MHz ;
-; N/A ; None ; -5.125 ns ; button1 ; Arkanoid:inst|platform1_position[15] ; clk_50MHz ;
-; N/A ; None ; -5.142 ns ; button1 ; Arkanoid:inst|platform1_position[31] ; clk_50MHz ;
-; N/A ; None ; -5.165 ns ; button1 ; Arkanoid:inst|platform1_position[18] ; clk_50MHz ;
-; N/A ; None ; -5.168 ns ; button1 ; Arkanoid:inst|platform1_position[12] ; clk_50MHz ;
-; N/A ; None ; -5.172 ns ; button1 ; Arkanoid:inst|platform1_position[20] ; clk_50MHz ;
-; N/A ; None ; -5.173 ns ; button1 ; Arkanoid:inst|platform1_position[23] ; clk_50MHz ;
-; N/A ; None ; -5.201 ns ; button1 ; Arkanoid:inst|platform1_position[24] ; clk_50MHz ;
-; N/A ; None ; -5.220 ns ; button1 ; Arkanoid:inst|platform1_position[19] ; clk_50MHz ;
-; N/A ; None ; -5.226 ns ; button1 ; Arkanoid:inst|platform1_position[9] ; clk_50MHz ;
-; N/A ; None ; -5.470 ns ; button1 ; Arkanoid:inst|platform1_position[14] ; clk_50MHz ;
-; N/A ; None ; -5.472 ns ; button1 ; Arkanoid:inst|platform1_position[11] ; clk_50MHz ;
-; N/A ; None ; -5.475 ns ; button1 ; Arkanoid:inst|platform1_position[10] ; clk_50MHz ;
-; N/A ; None ; -5.484 ns ; button1 ; Arkanoid:inst|platform1_position[13] ; clk_50MHz ;
-; N/A ; None ; -5.499 ns ; button1 ; Arkanoid:inst|platform1_position[0] ; clk_50MHz ;
-; N/A ; None ; -5.531 ns ; button1 ; Arkanoid:inst|platform1_position[1] ; clk_50MHz ;
-; N/A ; None ; -5.532 ns ; button3 ; Arkanoid:inst|platform2_position[16] ; clk_50MHz ;
-; N/A ; None ; -5.551 ns ; button3 ; Arkanoid:inst|platform2_position[7] ; clk_50MHz ;
-; N/A ; None ; -5.555 ns ; button1 ; Arkanoid:inst|platform1_position[25] ; clk_50MHz ;
-; N/A ; None ; -5.561 ns ; button3 ; Arkanoid:inst|platform2_position[27] ; clk_50MHz ;
-; N/A ; None ; -5.572 ns ; button3 ; Arkanoid:inst|platform2_position[29] ; clk_50MHz ;
-; N/A ; None ; -5.574 ns ; button1 ; Arkanoid:inst|platform1_position[26] ; clk_50MHz ;
-; N/A ; None ; -5.597 ns ; button3 ; Arkanoid:inst|platform2_position[17] ; clk_50MHz ;
-; N/A ; None ; -5.604 ns ; button3 ; Arkanoid:inst|platform2_position[6] ; clk_50MHz ;
-; N/A ; None ; -5.606 ns ; button3 ; Arkanoid:inst|platform2_position[19] ; clk_50MHz ;
-; N/A ; None ; -5.612 ns ; button3 ; Arkanoid:inst|platform2_position[24] ; clk_50MHz ;
-; N/A ; None ; -5.620 ns ; button3 ; Arkanoid:inst|platform2_position[31] ; clk_50MHz ;
-; N/A ; None ; -5.627 ns ; button3 ; Arkanoid:inst|platform2_position[10] ; clk_50MHz ;
-; N/A ; None ; -5.656 ns ; button3 ; Arkanoid:inst|platform2_position[26] ; clk_50MHz ;
-; N/A ; None ; -5.722 ns ; button1 ; Arkanoid:inst|platform1_position[27] ; clk_50MHz ;
-; N/A ; None ; -5.727 ns ; button1 ; Arkanoid:inst|platform1_position[28] ; clk_50MHz ;
-; N/A ; None ; -5.730 ns ; button1 ; Arkanoid:inst|platform1_position[16] ; clk_50MHz ;
-; N/A ; None ; -5.815 ns ; button1 ; Arkanoid:inst|platform1_position[2] ; clk_50MHz ;
-; N/A ; None ; -5.845 ns ; button1 ; Arkanoid:inst|platform1_position[17] ; clk_50MHz ;
-; N/A ; None ; -5.879 ns ; button1 ; Arkanoid:inst|platform1_position[29] ; clk_50MHz ;
-; N/A ; None ; -5.881 ns ; button1 ; Arkanoid:inst|platform1_position[30] ; clk_50MHz ;
-; N/A ; None ; -5.888 ns ; button3 ; Arkanoid:inst|platform2_position[25] ; clk_50MHz ;
-; N/A ; None ; -5.923 ns ; button3 ; Arkanoid:inst|platform2_position[5] ; clk_50MHz ;
-; N/A ; None ; -5.952 ns ; button3 ; Arkanoid:inst|platform2_position[28] ; clk_50MHz ;
-; N/A ; None ; -5.953 ns ; button3 ; Arkanoid:inst|platform2_position[23] ; clk_50MHz ;
-; N/A ; None ; -5.960 ns ; button3 ; Arkanoid:inst|platform2_position[0] ; clk_50MHz ;
-; N/A ; None ; -5.960 ns ; button3 ; Arkanoid:inst|platform2_position[20] ; clk_50MHz ;
-; N/A ; None ; -5.978 ns ; button3 ; Arkanoid:inst|platform2_position[15] ; clk_50MHz ;
-; N/A ; None ; -5.989 ns ; button3 ; Arkanoid:inst|platform2_position[1] ; clk_50MHz ;
-; N/A ; None ; -6.008 ns ; button3 ; Arkanoid:inst|platform2_position[8] ; clk_50MHz ;
-; N/A ; None ; -6.050 ns ; button3 ; Arkanoid:inst|platform2_position[21] ; clk_50MHz ;
-; N/A ; None ; -6.056 ns ; button3 ; Arkanoid:inst|platform2_position[30] ; clk_50MHz ;
-; N/A ; None ; -6.116 ns ; button3 ; Arkanoid:inst|platform2_position[9] ; clk_50MHz ;
-; N/A ; None ; -6.127 ns ; button3 ; Arkanoid:inst|platform2_position[14] ; clk_50MHz ;
-; N/A ; None ; -6.159 ns ; button3 ; Arkanoid:inst|platform2_position[4] ; clk_50MHz ;
-; N/A ; None ; -6.243 ns ; button3 ; Arkanoid:inst|platform2_position[2] ; clk_50MHz ;
-; N/A ; None ; -6.271 ns ; button3 ; Arkanoid:inst|platform2_position[18] ; clk_50MHz ;
-; N/A ; None ; -6.354 ns ; button3 ; Arkanoid:inst|platform2_position[11] ; clk_50MHz ;
-; N/A ; None ; -6.357 ns ; button3 ; Arkanoid:inst|platform2_position[12] ; clk_50MHz ;
-; N/A ; None ; -6.584 ns ; button3 ; Arkanoid:inst|platform2_position[22] ; clk_50MHz ;
-; N/A ; None ; -6.911 ns ; button3 ; Arkanoid:inst|platform2_position[13] ; clk_50MHz ;
-; N/A ; None ; -6.992 ns ; button3 ; Arkanoid:inst|platform2_position[3] ; clk_50MHz ;
-; N/A ; None ; -7.289 ns ; button2 ; Arkanoid:inst|red_[0] ; clk_50MHz ;
-; N/A ; None ; -7.292 ns ; button2 ; Arkanoid:inst|green_[2] ; clk_50MHz ;
-; N/A ; None ; -7.293 ns ; button2 ; Arkanoid:inst|red_[2] ; clk_50MHz ;
-; N/A ; None ; -7.295 ns ; button2 ; Arkanoid:inst|blue_[3] ; clk_50MHz ;
-; N/A ; None ; -7.550 ns ; button1 ; Arkanoid:inst|platform1_position[3] ; clk_50MHz ;
-; N/A ; None ; -7.940 ns ; button2 ; Arkanoid:inst|red_[3] ; clk_50MHz ;
-; N/A ; None ; -7.990 ns ; button2 ; Arkanoid:inst|green_[3] ; clk_50MHz ;
-; N/A ; None ; -7.992 ns ; button2 ; Arkanoid:inst|red_[1] ; clk_50MHz ;
-; N/A ; None ; -8.134 ns ; button2 ; Arkanoid:inst|blue_[0] ; clk_50MHz ;
-; N/A ; None ; -8.359 ns ; button4 ; Arkanoid:inst|red_[0] ; clk_50MHz ;
-; N/A ; None ; -8.361 ns ; button4 ; Arkanoid:inst|green_[2] ; clk_50MHz ;
-; N/A ; None ; -8.365 ns ; button4 ; Arkanoid:inst|blue_[3] ; clk_50MHz ;
-; N/A ; None ; -8.394 ns ; button4 ; Arkanoid:inst|red_[2] ; clk_50MHz ;
-; N/A ; None ; -9.041 ns ; button4 ; Arkanoid:inst|red_[3] ; clk_50MHz ;
-; N/A ; None ; -9.059 ns ; button4 ; Arkanoid:inst|green_[3] ; clk_50MHz ;
-; N/A ; None ; -9.062 ns ; button4 ; Arkanoid:inst|red_[1] ; clk_50MHz ;
-; N/A ; None ; -9.204 ns ; button4 ; Arkanoid:inst|blue_[0] ; clk_50MHz ;
-; N/A ; None ; -10.107 ns ; button1 ; Arkanoid:inst|red_[0] ; clk_50MHz ;
-; N/A ; None ; -10.110 ns ; button1 ; Arkanoid:inst|green_[2] ; clk_50MHz ;
-; N/A ; None ; -10.111 ns ; button1 ; Arkanoid:inst|red_[2] ; clk_50MHz ;
-; N/A ; None ; -10.113 ns ; button1 ; Arkanoid:inst|blue_[3] ; clk_50MHz ;
-; N/A ; None ; -10.599 ns ; button3 ; Arkanoid:inst|red_[0] ; clk_50MHz ;
-; N/A ; None ; -10.601 ns ; button3 ; Arkanoid:inst|green_[2] ; clk_50MHz ;
-; N/A ; None ; -10.605 ns ; button3 ; Arkanoid:inst|blue_[3] ; clk_50MHz ;
-; N/A ; None ; -10.634 ns ; button3 ; Arkanoid:inst|red_[2] ; clk_50MHz ;
-; N/A ; None ; -10.758 ns ; button1 ; Arkanoid:inst|red_[3] ; clk_50MHz ;
-; N/A ; None ; -10.808 ns ; button1 ; Arkanoid:inst|green_[3] ; clk_50MHz ;
-; N/A ; None ; -10.810 ns ; button1 ; Arkanoid:inst|red_[1] ; clk_50MHz ;
-; N/A ; None ; -10.952 ns ; button1 ; Arkanoid:inst|blue_[0] ; clk_50MHz ;
-; N/A ; None ; -11.281 ns ; button3 ; Arkanoid:inst|red_[3] ; clk_50MHz ;
-; N/A ; None ; -11.299 ns ; button3 ; Arkanoid:inst|green_[3] ; clk_50MHz ;
-; N/A ; None ; -11.302 ns ; button3 ; Arkanoid:inst|red_[1] ; clk_50MHz ;
-; N/A ; None ; -11.444 ns ; button3 ; Arkanoid:inst|blue_[0] ; clk_50MHz ;
-+---------------+-------------+------------+---------+--------------------------------------+-----------+
++-----------------------------------------------------------------------------------------------+
+; th ;
++---------------+-------------+-----------+---------+-------------------------------+-----------+
+; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
++---------------+-------------+-----------+---------+-------------------------------+-----------+
+; N/A ; None ; -1.772 ns ; button1 ; Debouncer:inst2|button_reg[0] ; clk_50MHz ;
+; N/A ; None ; -1.927 ns ; button3 ; Debouncer:inst4|button_reg[0] ; clk_50MHz ;
+; N/A ; None ; -1.987 ns ; button2 ; Debouncer:inst3|button_reg[0] ; clk_50MHz ;
+; N/A ; None ; -2.911 ns ; button4 ; Debouncer:inst5|button_reg[0] ; clk_50MHz ;
++---------------+-------------+-----------+---------+-------------------------------+-----------+
+--------------------------+
@@ -775,395 +469,367 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 9.1 Build 222 10/21/2009 SJ Full Version
- Info: Processing started: Mon May 21 19:54:40 2012
+ Info: Processing started: Mon May 28 14:22:32 2012
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid --timing_analysis_only
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk_50MHz" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
- Info: Detected ripple clock "Arkanoid:inst|clk25MHz_" as buffer
-Info: Clock "clk_50MHz" has Internal fmax of 9.7 MHz between source register "Arkanoid:inst|h_counter[1]" and destination register "Arkanoid:inst|blue_[0]" (period= 103.135 ns)
- Info: + Longest register to register delay is 102.875 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y11_N3; Fanout = 6; REG Node = 'Arkanoid:inst|h_counter[1]'
- Info: 2: + IC(0.631 ns) + CELL(0.517 ns) = 1.148 ns; Loc. = LCCOMB_X15_Y11_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~1'
- Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.228 ns; Loc. = LCCOMB_X15_Y11_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~3'
- Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.308 ns; Loc. = LCCOMB_X15_Y11_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~5'
- Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.388 ns; Loc. = LCCOMB_X15_Y11_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~7'
- Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 1.468 ns; Loc. = LCCOMB_X15_Y11_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~9'
- Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 1.548 ns; Loc. = LCCOMB_X15_Y11_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~11'
- Info: 8: + IC(0.000 ns) + CELL(0.174 ns) = 1.722 ns; Loc. = LCCOMB_X15_Y11_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~13'
- Info: 9: + IC(0.000 ns) + CELL(0.080 ns) = 1.802 ns; Loc. = LCCOMB_X15_Y11_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~15'
- Info: 10: + IC(0.000 ns) + CELL(0.080 ns) = 1.882 ns; Loc. = LCCOMB_X15_Y11_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~17'
- Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 1.962 ns; Loc. = LCCOMB_X15_Y11_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~19'
- Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 2.042 ns; Loc. = LCCOMB_X15_Y11_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~21'
- Info: 13: + IC(0.000 ns) + CELL(0.080 ns) = 2.122 ns; Loc. = LCCOMB_X15_Y11_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~23'
- Info: 14: + IC(0.000 ns) + CELL(0.080 ns) = 2.202 ns; Loc. = LCCOMB_X15_Y11_N26; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~25'
- Info: 15: + IC(0.000 ns) + CELL(0.080 ns) = 2.282 ns; Loc. = LCCOMB_X15_Y11_N28; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~27'
- Info: 16: + IC(0.000 ns) + CELL(0.161 ns) = 2.443 ns; Loc. = LCCOMB_X15_Y11_N30; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~29'
- Info: 17: + IC(0.000 ns) + CELL(0.080 ns) = 2.523 ns; Loc. = LCCOMB_X15_Y10_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~31'
- Info: 18: + IC(0.000 ns) + CELL(0.080 ns) = 2.603 ns; Loc. = LCCOMB_X15_Y10_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~33'
- Info: 19: + IC(0.000 ns) + CELL(0.080 ns) = 2.683 ns; Loc. = LCCOMB_X15_Y10_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~35'
- Info: 20: + IC(0.000 ns) + CELL(0.080 ns) = 2.763 ns; Loc. = LCCOMB_X15_Y10_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~37'
- Info: 21: + IC(0.000 ns) + CELL(0.080 ns) = 2.843 ns; Loc. = LCCOMB_X15_Y10_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~39'
- Info: 22: + IC(0.000 ns) + CELL(0.080 ns) = 2.923 ns; Loc. = LCCOMB_X15_Y10_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~41'
- Info: 23: + IC(0.000 ns) + CELL(0.080 ns) = 3.003 ns; Loc. = LCCOMB_X15_Y10_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~43'
- Info: 24: + IC(0.000 ns) + CELL(0.174 ns) = 3.177 ns; Loc. = LCCOMB_X15_Y10_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~45'
- Info: 25: + IC(0.000 ns) + CELL(0.080 ns) = 3.257 ns; Loc. = LCCOMB_X15_Y10_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~47'
- Info: 26: + IC(0.000 ns) + CELL(0.080 ns) = 3.337 ns; Loc. = LCCOMB_X15_Y10_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~49'
- Info: 27: + IC(0.000 ns) + CELL(0.080 ns) = 3.417 ns; Loc. = LCCOMB_X15_Y10_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~51'
- Info: 28: + IC(0.000 ns) + CELL(0.080 ns) = 3.497 ns; Loc. = LCCOMB_X15_Y10_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~53'
- Info: 29: + IC(0.000 ns) + CELL(0.080 ns) = 3.577 ns; Loc. = LCCOMB_X15_Y10_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~55'
- Info: 30: + IC(0.000 ns) + CELL(0.080 ns) = 3.657 ns; Loc. = LCCOMB_X15_Y10_N26; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~57'
- Info: 31: + IC(0.000 ns) + CELL(0.080 ns) = 3.737 ns; Loc. = LCCOMB_X15_Y10_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|Add8~59'
- Info: 32: + IC(0.000 ns) + CELL(0.458 ns) = 4.195 ns; Loc. = LCCOMB_X15_Y10_N30; Fanout = 65; COMB Node = 'Arkanoid:inst|Add8~60'
- Info: 33: + IC(1.268 ns) + CELL(0.495 ns) = 5.958 ns; Loc. = LCCOMB_X16_Y11_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7'
- Info: 34: + IC(0.000 ns) + CELL(0.080 ns) = 6.038 ns; Loc. = LCCOMB_X16_Y11_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9'
- Info: 35: + IC(0.000 ns) + CELL(0.080 ns) = 6.118 ns; Loc. = LCCOMB_X16_Y11_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11'
- Info: 36: + IC(0.000 ns) + CELL(0.080 ns) = 6.198 ns; Loc. = LCCOMB_X16_Y11_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13'
- Info: 37: + IC(0.000 ns) + CELL(0.174 ns) = 6.372 ns; Loc. = LCCOMB_X16_Y11_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15'
- Info: 38: + IC(0.000 ns) + CELL(0.080 ns) = 6.452 ns; Loc. = LCCOMB_X16_Y11_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17'
- Info: 39: + IC(0.000 ns) + CELL(0.080 ns) = 6.532 ns; Loc. = LCCOMB_X16_Y11_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19'
- Info: 40: + IC(0.000 ns) + CELL(0.080 ns) = 6.612 ns; Loc. = LCCOMB_X16_Y11_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21'
- Info: 41: + IC(0.000 ns) + CELL(0.080 ns) = 6.692 ns; Loc. = LCCOMB_X16_Y11_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23'
- Info: 42: + IC(0.000 ns) + CELL(0.080 ns) = 6.772 ns; Loc. = LCCOMB_X16_Y11_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25'
- Info: 43: + IC(0.000 ns) + CELL(0.080 ns) = 6.852 ns; Loc. = LCCOMB_X16_Y11_N26; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27'
- Info: 44: + IC(0.000 ns) + CELL(0.080 ns) = 6.932 ns; Loc. = LCCOMB_X16_Y11_N28; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29'
- Info: 45: + IC(0.000 ns) + CELL(0.161 ns) = 7.093 ns; Loc. = LCCOMB_X16_Y11_N30; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31'
- Info: 46: + IC(0.000 ns) + CELL(0.080 ns) = 7.173 ns; Loc. = LCCOMB_X16_Y10_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33'
- Info: 47: + IC(0.000 ns) + CELL(0.080 ns) = 7.253 ns; Loc. = LCCOMB_X16_Y10_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35'
- Info: 48: + IC(0.000 ns) + CELL(0.080 ns) = 7.333 ns; Loc. = LCCOMB_X16_Y10_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37'
- Info: 49: + IC(0.000 ns) + CELL(0.080 ns) = 7.413 ns; Loc. = LCCOMB_X16_Y10_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39'
- Info: 50: + IC(0.000 ns) + CELL(0.080 ns) = 7.493 ns; Loc. = LCCOMB_X16_Y10_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41'
- Info: 51: + IC(0.000 ns) + CELL(0.080 ns) = 7.573 ns; Loc. = LCCOMB_X16_Y10_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43'
- Info: 52: + IC(0.000 ns) + CELL(0.080 ns) = 7.653 ns; Loc. = LCCOMB_X16_Y10_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45'
- Info: 53: + IC(0.000 ns) + CELL(0.174 ns) = 7.827 ns; Loc. = LCCOMB_X16_Y10_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47'
- Info: 54: + IC(0.000 ns) + CELL(0.080 ns) = 7.907 ns; Loc. = LCCOMB_X16_Y10_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49'
- Info: 55: + IC(0.000 ns) + CELL(0.080 ns) = 7.987 ns; Loc. = LCCOMB_X16_Y10_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51'
- Info: 56: + IC(0.000 ns) + CELL(0.080 ns) = 8.067 ns; Loc. = LCCOMB_X16_Y10_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53'
- Info: 57: + IC(0.000 ns) + CELL(0.080 ns) = 8.147 ns; Loc. = LCCOMB_X16_Y10_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55'
- Info: 58: + IC(0.000 ns) + CELL(0.080 ns) = 8.227 ns; Loc. = LCCOMB_X16_Y10_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~57'
- Info: 59: + IC(0.000 ns) + CELL(0.458 ns) = 8.685 ns; Loc. = LCCOMB_X16_Y10_N26; Fanout = 4; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~58'
- Info: 60: + IC(1.260 ns) + CELL(0.495 ns) = 10.440 ns; Loc. = LCCOMB_X16_Y15_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_4_result_int[2]~1'
- Info: 61: + IC(0.000 ns) + CELL(0.080 ns) = 10.520 ns; Loc. = LCCOMB_X16_Y15_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_4_result_int[3]~3'
- Info: 62: + IC(0.000 ns) + CELL(0.080 ns) = 10.600 ns; Loc. = LCCOMB_X16_Y15_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_4_result_int[4]~5'
- Info: 63: + IC(0.000 ns) + CELL(0.458 ns) = 11.058 ns; Loc. = LCCOMB_X16_Y15_N28; Fanout = 11; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_4_result_int[5]~6'
- Info: 64: + IC(0.859 ns) + CELL(0.177 ns) = 12.094 ns; Loc. = LCCOMB_X18_Y15_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[29]~435'
- Info: 65: + IC(0.836 ns) + CELL(0.517 ns) = 13.447 ns; Loc. = LCCOMB_X16_Y15_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_5_result_int[2]~1'
- Info: 66: + IC(0.000 ns) + CELL(0.080 ns) = 13.527 ns; Loc. = LCCOMB_X16_Y15_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_5_result_int[3]~3'
- Info: 67: + IC(0.000 ns) + CELL(0.174 ns) = 13.701 ns; Loc. = LCCOMB_X16_Y15_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_5_result_int[4]~5'
- Info: 68: + IC(0.000 ns) + CELL(0.080 ns) = 13.781 ns; Loc. = LCCOMB_X16_Y15_N16; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_5_result_int[5]~7'
- Info: 69: + IC(0.000 ns) + CELL(0.458 ns) = 14.239 ns; Loc. = LCCOMB_X16_Y15_N18; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_5_result_int[6]~8'
- Info: 70: + IC(0.930 ns) + CELL(0.177 ns) = 15.346 ns; Loc. = LCCOMB_X18_Y15_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[36]~442'
- Info: 71: + IC(0.516 ns) + CELL(0.495 ns) = 16.357 ns; Loc. = LCCOMB_X19_Y15_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[2]~1'
- Info: 72: + IC(0.000 ns) + CELL(0.080 ns) = 16.437 ns; Loc. = LCCOMB_X19_Y15_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[3]~3'
- Info: 73: + IC(0.000 ns) + CELL(0.080 ns) = 16.517 ns; Loc. = LCCOMB_X19_Y15_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[4]~5'
- Info: 74: + IC(0.000 ns) + CELL(0.080 ns) = 16.597 ns; Loc. = LCCOMB_X19_Y15_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[5]~7'
- Info: 75: + IC(0.000 ns) + CELL(0.080 ns) = 16.677 ns; Loc. = LCCOMB_X19_Y15_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[6]~9'
- Info: 76: + IC(0.000 ns) + CELL(0.458 ns) = 17.135 ns; Loc. = LCCOMB_X19_Y15_N28; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[7]~10'
- Info: 77: + IC(0.920 ns) + CELL(0.178 ns) = 18.233 ns; Loc. = LCCOMB_X20_Y18_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[43]~447'
- Info: 78: + IC(0.914 ns) + CELL(0.517 ns) = 19.664 ns; Loc. = LCCOMB_X19_Y15_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[2]~1'
- Info: 79: + IC(0.000 ns) + CELL(0.080 ns) = 19.744 ns; Loc. = LCCOMB_X19_Y15_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[3]~3'
- Info: 80: + IC(0.000 ns) + CELL(0.080 ns) = 19.824 ns; Loc. = LCCOMB_X19_Y15_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[4]~5'
- Info: 81: + IC(0.000 ns) + CELL(0.080 ns) = 19.904 ns; Loc. = LCCOMB_X19_Y15_N8; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[5]~7'
- Info: 82: + IC(0.000 ns) + CELL(0.080 ns) = 19.984 ns; Loc. = LCCOMB_X19_Y15_N10; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[6]~9'
- Info: 83: + IC(0.000 ns) + CELL(0.458 ns) = 20.442 ns; Loc. = LCCOMB_X19_Y15_N12; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[7]~10'
- Info: 84: + IC(0.994 ns) + CELL(0.178 ns) = 21.614 ns; Loc. = LCCOMB_X20_Y18_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[50]~453'
- Info: 85: + IC(0.551 ns) + CELL(0.517 ns) = 22.682 ns; Loc. = LCCOMB_X19_Y18_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[2]~1'
- Info: 86: + IC(0.000 ns) + CELL(0.080 ns) = 22.762 ns; Loc. = LCCOMB_X19_Y18_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[3]~3'
- Info: 87: + IC(0.000 ns) + CELL(0.080 ns) = 22.842 ns; Loc. = LCCOMB_X19_Y18_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[4]~5'
- Info: 88: + IC(0.000 ns) + CELL(0.080 ns) = 22.922 ns; Loc. = LCCOMB_X19_Y18_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[5]~7'
- Info: 89: + IC(0.000 ns) + CELL(0.080 ns) = 23.002 ns; Loc. = LCCOMB_X19_Y18_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[6]~9'
- Info: 90: + IC(0.000 ns) + CELL(0.458 ns) = 23.460 ns; Loc. = LCCOMB_X19_Y18_N30; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[7]~10'
- Info: 91: + IC(0.943 ns) + CELL(0.322 ns) = 24.725 ns; Loc. = LCCOMB_X19_Y22_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[57]~460'
- Info: 92: + IC(0.909 ns) + CELL(0.517 ns) = 26.151 ns; Loc. = LCCOMB_X19_Y18_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[2]~1'
- Info: 93: + IC(0.000 ns) + CELL(0.080 ns) = 26.231 ns; Loc. = LCCOMB_X19_Y18_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[3]~3'
- Info: 94: + IC(0.000 ns) + CELL(0.080 ns) = 26.311 ns; Loc. = LCCOMB_X19_Y18_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[4]~5'
- Info: 95: + IC(0.000 ns) + CELL(0.080 ns) = 26.391 ns; Loc. = LCCOMB_X19_Y18_N6; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[5]~7'
- Info: 96: + IC(0.000 ns) + CELL(0.080 ns) = 26.471 ns; Loc. = LCCOMB_X19_Y18_N8; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[6]~9'
- Info: 97: + IC(0.000 ns) + CELL(0.458 ns) = 26.929 ns; Loc. = LCCOMB_X19_Y18_N10; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[7]~10'
- Info: 98: + IC(0.922 ns) + CELL(0.322 ns) = 28.173 ns; Loc. = LCCOMB_X19_Y22_N12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[68]~461'
- Info: 99: + IC(0.793 ns) + CELL(0.495 ns) = 29.461 ns; Loc. = LCCOMB_X20_Y22_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_10_result_int[6]~9'
- Info: 100: + IC(0.000 ns) + CELL(0.458 ns) = 29.919 ns; Loc. = LCCOMB_X20_Y22_N30; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_10_result_int[7]~10'
- Info: 101: + IC(1.241 ns) + CELL(0.177 ns) = 31.337 ns; Loc. = LCCOMB_X20_Y21_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[71]~472'
- Info: 102: + IC(0.872 ns) + CELL(0.517 ns) = 32.726 ns; Loc. = LCCOMB_X20_Y22_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_11_result_int[2]~1'
- Info: 103: + IC(0.000 ns) + CELL(0.080 ns) = 32.806 ns; Loc. = LCCOMB_X20_Y22_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_11_result_int[3]~3'
- Info: 104: + IC(0.000 ns) + CELL(0.458 ns) = 33.264 ns; Loc. = LCCOMB_X20_Y22_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_11_result_int[4]~4'
- Info: 105: + IC(1.206 ns) + CELL(0.178 ns) = 34.648 ns; Loc. = LCCOMB_X20_Y21_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[81]~474'
- Info: 106: + IC(0.839 ns) + CELL(0.517 ns) = 36.004 ns; Loc. = LCCOMB_X19_Y21_N20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_12_result_int[5]~7'
- Info: 107: + IC(0.000 ns) + CELL(0.080 ns) = 36.084 ns; Loc. = LCCOMB_X19_Y21_N22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_12_result_int[6]~9'
- Info: 108: + IC(0.000 ns) + CELL(0.458 ns) = 36.542 ns; Loc. = LCCOMB_X19_Y21_N24; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_12_result_int[7]~10'
- Info: 109: + IC(0.602 ns) + CELL(0.178 ns) = 37.322 ns; Loc. = LCCOMB_X20_Y21_N30; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[89]~605'
- Info: 110: + IC(0.814 ns) + CELL(0.517 ns) = 38.653 ns; Loc. = LCCOMB_X19_Y21_N8; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_13_result_int[6]~9'
- Info: 111: + IC(0.000 ns) + CELL(0.458 ns) = 39.111 ns; Loc. = LCCOMB_X19_Y21_N10; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_13_result_int[7]~10'
- Info: 112: + IC(0.634 ns) + CELL(0.322 ns) = 40.067 ns; Loc. = LCCOMB_X18_Y21_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[92]~490'
- Info: 113: + IC(0.884 ns) + CELL(0.517 ns) = 41.468 ns; Loc. = LCCOMB_X19_Y20_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[2]~1'
- Info: 114: + IC(0.000 ns) + CELL(0.080 ns) = 41.548 ns; Loc. = LCCOMB_X19_Y20_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[3]~3'
- Info: 115: + IC(0.000 ns) + CELL(0.080 ns) = 41.628 ns; Loc. = LCCOMB_X19_Y20_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[4]~5'
- Info: 116: + IC(0.000 ns) + CELL(0.174 ns) = 41.802 ns; Loc. = LCCOMB_X19_Y20_N14; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[5]~7'
- Info: 117: + IC(0.000 ns) + CELL(0.080 ns) = 41.882 ns; Loc. = LCCOMB_X19_Y20_N16; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[6]~9'
- Info: 118: + IC(0.000 ns) + CELL(0.458 ns) = 42.340 ns; Loc. = LCCOMB_X19_Y20_N18; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[7]~10'
- Info: 119: + IC(0.917 ns) + CELL(0.322 ns) = 43.579 ns; Loc. = LCCOMB_X18_Y21_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[99]~495'
- Info: 120: + IC(0.856 ns) + CELL(0.495 ns) = 44.930 ns; Loc. = LCCOMB_X18_Y20_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[2]~1'
- Info: 121: + IC(0.000 ns) + CELL(0.080 ns) = 45.010 ns; Loc. = LCCOMB_X18_Y20_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[3]~3'
- Info: 122: + IC(0.000 ns) + CELL(0.080 ns) = 45.090 ns; Loc. = LCCOMB_X18_Y20_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[4]~5'
- Info: 123: + IC(0.000 ns) + CELL(0.080 ns) = 45.170 ns; Loc. = LCCOMB_X18_Y20_N6; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[5]~7'
- Info: 124: + IC(0.000 ns) + CELL(0.080 ns) = 45.250 ns; Loc. = LCCOMB_X18_Y20_N8; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[6]~9'
- Info: 125: + IC(0.000 ns) + CELL(0.458 ns) = 45.708 ns; Loc. = LCCOMB_X18_Y20_N10; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[7]~10'
- Info: 126: + IC(0.897 ns) + CELL(0.177 ns) = 46.782 ns; Loc. = LCCOMB_X19_Y19_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[106]~502'
- Info: 127: + IC(0.835 ns) + CELL(0.517 ns) = 48.134 ns; Loc. = LCCOMB_X19_Y20_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[2]~1'
- Info: 128: + IC(0.000 ns) + CELL(0.080 ns) = 48.214 ns; Loc. = LCCOMB_X19_Y20_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[3]~3'
- Info: 129: + IC(0.000 ns) + CELL(0.080 ns) = 48.294 ns; Loc. = LCCOMB_X19_Y20_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[4]~5'
- Info: 130: + IC(0.000 ns) + CELL(0.080 ns) = 48.374 ns; Loc. = LCCOMB_X19_Y20_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[5]~7'
- Info: 131: + IC(0.000 ns) + CELL(0.080 ns) = 48.454 ns; Loc. = LCCOMB_X19_Y20_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[6]~9'
- Info: 132: + IC(0.000 ns) + CELL(0.458 ns) = 48.912 ns; Loc. = LCCOMB_X19_Y20_N30; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[7]~10'
- Info: 133: + IC(0.961 ns) + CELL(0.177 ns) = 50.050 ns; Loc. = LCCOMB_X18_Y19_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[113]~508'
- Info: 134: + IC(0.579 ns) + CELL(0.517 ns) = 51.146 ns; Loc. = LCCOMB_X18_Y19_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[2]~1'
- Info: 135: + IC(0.000 ns) + CELL(0.080 ns) = 51.226 ns; Loc. = LCCOMB_X18_Y19_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[3]~3'
- Info: 136: + IC(0.000 ns) + CELL(0.080 ns) = 51.306 ns; Loc. = LCCOMB_X18_Y19_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[4]~5'
- Info: 137: + IC(0.000 ns) + CELL(0.080 ns) = 51.386 ns; Loc. = LCCOMB_X18_Y19_N12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[5]~7'
- Info: 138: + IC(0.000 ns) + CELL(0.174 ns) = 51.560 ns; Loc. = LCCOMB_X18_Y19_N14; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[6]~9'
- Info: 139: + IC(0.000 ns) + CELL(0.458 ns) = 52.018 ns; Loc. = LCCOMB_X18_Y19_N16; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[7]~10'
- Info: 140: + IC(0.340 ns) + CELL(0.319 ns) = 52.677 ns; Loc. = LCCOMB_X18_Y19_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[120]~513'
- Info: 141: + IC(0.549 ns) + CELL(0.517 ns) = 53.743 ns; Loc. = LCCOMB_X19_Y19_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_18_result_int[2]~1'
- Info: 142: + IC(0.000 ns) + CELL(0.080 ns) = 53.823 ns; Loc. = LCCOMB_X19_Y19_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_18_result_int[3]~3'
- Info: 143: + IC(0.000 ns) + CELL(0.080 ns) = 53.903 ns; Loc. = LCCOMB_X19_Y19_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_18_result_int[4]~5'
- Info: 144: + IC(0.000 ns) + CELL(0.458 ns) = 54.361 ns; Loc. = LCCOMB_X19_Y19_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_18_result_int[5]~6'
- Info: 145: + IC(0.552 ns) + CELL(0.521 ns) = 55.434 ns; Loc. = LCCOMB_X20_Y19_N0; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[131]~515'
- Info: 146: + IC(0.552 ns) + CELL(0.517 ns) = 56.503 ns; Loc. = LCCOMB_X20_Y19_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_19_result_int[6]~9'
- Info: 147: + IC(0.000 ns) + CELL(0.458 ns) = 56.961 ns; Loc. = LCCOMB_X20_Y19_N26; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_19_result_int[7]~10'
- Info: 148: + IC(0.650 ns) + CELL(0.177 ns) = 57.788 ns; Loc. = LCCOMB_X21_Y19_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[134]~526'
- Info: 149: + IC(0.544 ns) + CELL(0.517 ns) = 58.849 ns; Loc. = LCCOMB_X22_Y19_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[2]~1'
- Info: 150: + IC(0.000 ns) + CELL(0.080 ns) = 58.929 ns; Loc. = LCCOMB_X22_Y19_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[3]~3'
- Info: 151: + IC(0.000 ns) + CELL(0.080 ns) = 59.009 ns; Loc. = LCCOMB_X22_Y19_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[4]~5'
- Info: 152: + IC(0.000 ns) + CELL(0.080 ns) = 59.089 ns; Loc. = LCCOMB_X22_Y19_N6; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[5]~7'
- Info: 153: + IC(0.000 ns) + CELL(0.080 ns) = 59.169 ns; Loc. = LCCOMB_X22_Y19_N8; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[6]~9'
- Info: 154: + IC(0.000 ns) + CELL(0.458 ns) = 59.627 ns; Loc. = LCCOMB_X22_Y19_N10; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[7]~10'
- Info: 155: + IC(0.863 ns) + CELL(0.178 ns) = 60.668 ns; Loc. = LCCOMB_X22_Y22_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[141]~531'
- Info: 156: + IC(0.901 ns) + CELL(0.517 ns) = 62.086 ns; Loc. = LCCOMB_X22_Y19_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[2]~1'
- Info: 157: + IC(0.000 ns) + CELL(0.080 ns) = 62.166 ns; Loc. = LCCOMB_X22_Y19_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[3]~3'
- Info: 158: + IC(0.000 ns) + CELL(0.080 ns) = 62.246 ns; Loc. = LCCOMB_X22_Y19_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[4]~5'
- Info: 159: + IC(0.000 ns) + CELL(0.080 ns) = 62.326 ns; Loc. = LCCOMB_X22_Y19_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[5]~7'
- Info: 160: + IC(0.000 ns) + CELL(0.080 ns) = 62.406 ns; Loc. = LCCOMB_X22_Y19_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[6]~9'
- Info: 161: + IC(0.000 ns) + CELL(0.458 ns) = 62.864 ns; Loc. = LCCOMB_X22_Y19_N28; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[7]~10'
- Info: 162: + IC(0.946 ns) + CELL(0.178 ns) = 63.988 ns; Loc. = LCCOMB_X22_Y22_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[148]~537'
- Info: 163: + IC(0.805 ns) + CELL(0.495 ns) = 65.288 ns; Loc. = LCCOMB_X23_Y22_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_22_result_int[2]~1'
- Info: 164: + IC(0.000 ns) + CELL(0.080 ns) = 65.368 ns; Loc. = LCCOMB_X23_Y22_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_22_result_int[3]~3'
- Info: 165: + IC(0.000 ns) + CELL(0.080 ns) = 65.448 ns; Loc. = LCCOMB_X23_Y22_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_22_result_int[4]~5'
- Info: 166: + IC(0.000 ns) + CELL(0.080 ns) = 65.528 ns; Loc. = LCCOMB_X23_Y22_N10; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_22_result_int[5]~7'
- Info: 167: + IC(0.000 ns) + CELL(0.080 ns) = 65.608 ns; Loc. = LCCOMB_X23_Y22_N12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_22_result_int[6]~9'
- Info: 168: + IC(0.000 ns) + CELL(0.458 ns) = 66.066 ns; Loc. = LCCOMB_X23_Y22_N14; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_22_result_int[7]~10'
- Info: 169: + IC(0.562 ns) + CELL(0.322 ns) = 66.950 ns; Loc. = LCCOMB_X22_Y22_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[156]~663'
- Info: 170: + IC(0.545 ns) + CELL(0.517 ns) = 68.012 ns; Loc. = LCCOMB_X23_Y22_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[3]~3'
- Info: 171: + IC(0.000 ns) + CELL(0.080 ns) = 68.092 ns; Loc. = LCCOMB_X23_Y22_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[4]~5'
- Info: 172: + IC(0.000 ns) + CELL(0.080 ns) = 68.172 ns; Loc. = LCCOMB_X23_Y22_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[5]~7'
- Info: 173: + IC(0.000 ns) + CELL(0.080 ns) = 68.252 ns; Loc. = LCCOMB_X23_Y22_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[6]~9'
- Info: 174: + IC(0.000 ns) + CELL(0.458 ns) = 68.710 ns; Loc. = LCCOMB_X23_Y22_N30; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[7]~10'
- Info: 175: + IC(0.550 ns) + CELL(0.322 ns) = 69.582 ns; Loc. = LCCOMB_X24_Y22_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[162]~550'
- Info: 176: + IC(0.550 ns) + CELL(0.517 ns) = 70.649 ns; Loc. = LCCOMB_X25_Y22_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_24_result_int[2]~1'
- Info: 177: + IC(0.000 ns) + CELL(0.080 ns) = 70.729 ns; Loc. = LCCOMB_X25_Y22_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_24_result_int[3]~3'
- Info: 178: + IC(0.000 ns) + CELL(0.080 ns) = 70.809 ns; Loc. = LCCOMB_X25_Y22_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_24_result_int[4]~5'
- Info: 179: + IC(0.000 ns) + CELL(0.080 ns) = 70.889 ns; Loc. = LCCOMB_X25_Y22_N10; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_24_result_int[5]~7'
- Info: 180: + IC(0.000 ns) + CELL(0.080 ns) = 70.969 ns; Loc. = LCCOMB_X25_Y22_N12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_24_result_int[6]~9'
- Info: 181: + IC(0.000 ns) + CELL(0.458 ns) = 71.427 ns; Loc. = LCCOMB_X25_Y22_N14; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_24_result_int[7]~10'
- Info: 182: + IC(1.167 ns) + CELL(0.177 ns) = 72.771 ns; Loc. = LCCOMB_X30_Y22_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[169]~556'
- Info: 183: + IC(1.111 ns) + CELL(0.517 ns) = 74.399 ns; Loc. = LCCOMB_X25_Y22_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[2]~1'
- Info: 184: + IC(0.000 ns) + CELL(0.080 ns) = 74.479 ns; Loc. = LCCOMB_X25_Y22_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[3]~3'
- Info: 185: + IC(0.000 ns) + CELL(0.080 ns) = 74.559 ns; Loc. = LCCOMB_X25_Y22_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[4]~5'
- Info: 186: + IC(0.000 ns) + CELL(0.080 ns) = 74.639 ns; Loc. = LCCOMB_X25_Y22_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[5]~7'
- Info: 187: + IC(0.000 ns) + CELL(0.080 ns) = 74.719 ns; Loc. = LCCOMB_X25_Y22_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[6]~9'
- Info: 188: + IC(0.000 ns) + CELL(0.458 ns) = 75.177 ns; Loc. = LCCOMB_X25_Y22_N30; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[7]~10'
- Info: 189: + IC(1.167 ns) + CELL(0.177 ns) = 76.521 ns; Loc. = LCCOMB_X30_Y22_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[176]~562'
- Info: 190: + IC(0.542 ns) + CELL(0.517 ns) = 77.580 ns; Loc. = LCCOMB_X31_Y22_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_26_result_int[2]~1'
- Info: 191: + IC(0.000 ns) + CELL(0.080 ns) = 77.660 ns; Loc. = LCCOMB_X31_Y22_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_26_result_int[3]~3'
- Info: 192: + IC(0.000 ns) + CELL(0.080 ns) = 77.740 ns; Loc. = LCCOMB_X31_Y22_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_26_result_int[4]~5'
- Info: 193: + IC(0.000 ns) + CELL(0.080 ns) = 77.820 ns; Loc. = LCCOMB_X31_Y22_N22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_26_result_int[5]~7'
- Info: 194: + IC(0.000 ns) + CELL(0.080 ns) = 77.900 ns; Loc. = LCCOMB_X31_Y22_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_26_result_int[6]~9'
- Info: 195: + IC(0.000 ns) + CELL(0.458 ns) = 78.358 ns; Loc. = LCCOMB_X31_Y22_N26; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_26_result_int[7]~10'
- Info: 196: + IC(1.188 ns) + CELL(0.178 ns) = 79.724 ns; Loc. = LCCOMB_X34_Y20_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[183]~567'
- Info: 197: + IC(1.156 ns) + CELL(0.517 ns) = 81.397 ns; Loc. = LCCOMB_X31_Y22_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[2]~1'
- Info: 198: + IC(0.000 ns) + CELL(0.080 ns) = 81.477 ns; Loc. = LCCOMB_X31_Y22_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[3]~3'
- Info: 199: + IC(0.000 ns) + CELL(0.080 ns) = 81.557 ns; Loc. = LCCOMB_X31_Y22_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[4]~5'
- Info: 200: + IC(0.000 ns) + CELL(0.080 ns) = 81.637 ns; Loc. = LCCOMB_X31_Y22_N10; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[5]~7'
- Info: 201: + IC(0.000 ns) + CELL(0.080 ns) = 81.717 ns; Loc. = LCCOMB_X31_Y22_N12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[6]~9'
- Info: 202: + IC(0.000 ns) + CELL(0.458 ns) = 82.175 ns; Loc. = LCCOMB_X31_Y22_N14; Fanout = 15; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[7]~10'
- Info: 203: + IC(0.522 ns) + CELL(0.322 ns) = 83.019 ns; Loc. = LCCOMB_X30_Y22_N6; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[192]~692'
- Info: 204: + IC(1.442 ns) + CELL(0.517 ns) = 84.978 ns; Loc. = LCCOMB_X35_Y20_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_28_result_int[4]~5'
- Info: 205: + IC(0.000 ns) + CELL(0.080 ns) = 85.058 ns; Loc. = LCCOMB_X35_Y20_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_28_result_int[5]~7'
- Info: 206: + IC(0.000 ns) + CELL(0.080 ns) = 85.138 ns; Loc. = LCCOMB_X35_Y20_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_28_result_int[6]~9'
- Info: 207: + IC(0.000 ns) + CELL(0.458 ns) = 85.596 ns; Loc. = LCCOMB_X35_Y20_N30; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_28_result_int[7]~10'
- Info: 208: + IC(0.554 ns) + CELL(0.177 ns) = 86.327 ns; Loc. = LCCOMB_X34_Y20_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[197]~580'
- Info: 209: + IC(0.543 ns) + CELL(0.517 ns) = 87.387 ns; Loc. = LCCOMB_X35_Y20_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[2]~1'
- Info: 210: + IC(0.000 ns) + CELL(0.080 ns) = 87.467 ns; Loc. = LCCOMB_X35_Y20_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[3]~3'
- Info: 211: + IC(0.000 ns) + CELL(0.080 ns) = 87.547 ns; Loc. = LCCOMB_X35_Y20_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[4]~5'
- Info: 212: + IC(0.000 ns) + CELL(0.080 ns) = 87.627 ns; Loc. = LCCOMB_X35_Y20_N12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[5]~7'
- Info: 213: + IC(0.000 ns) + CELL(0.174 ns) = 87.801 ns; Loc. = LCCOMB_X35_Y20_N14; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[6]~9'
- Info: 214: + IC(0.000 ns) + CELL(0.458 ns) = 88.259 ns; Loc. = LCCOMB_X35_Y20_N16; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[7]~10'
- Info: 215: + IC(0.912 ns) + CELL(0.178 ns) = 89.349 ns; Loc. = LCCOMB_X36_Y18_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[205]~670'
- Info: 216: + IC(0.537 ns) + CELL(0.517 ns) = 90.403 ns; Loc. = LCCOMB_X35_Y18_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_30_result_int[3]~3'
- Info: 217: + IC(0.000 ns) + CELL(0.080 ns) = 90.483 ns; Loc. = LCCOMB_X35_Y18_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_30_result_int[4]~5'
- Info: 218: + IC(0.000 ns) + CELL(0.080 ns) = 90.563 ns; Loc. = LCCOMB_X35_Y18_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_30_result_int[5]~7'
- Info: 219: + IC(0.000 ns) + CELL(0.080 ns) = 90.643 ns; Loc. = LCCOMB_X35_Y18_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_30_result_int[6]~9'
- Info: 220: + IC(0.000 ns) + CELL(0.458 ns) = 91.101 ns; Loc. = LCCOMB_X35_Y18_N28; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_30_result_int[7]~10'
- Info: 221: + IC(0.898 ns) + CELL(0.178 ns) = 92.177 ns; Loc. = LCCOMB_X35_Y16_N12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[211]~591'
- Info: 222: + IC(0.314 ns) + CELL(0.517 ns) = 93.008 ns; Loc. = LCCOMB_X35_Y16_N18; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[2]~1'
- Info: 223: + IC(0.000 ns) + CELL(0.080 ns) = 93.088 ns; Loc. = LCCOMB_X35_Y16_N20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[3]~3'
- Info: 224: + IC(0.000 ns) + CELL(0.080 ns) = 93.168 ns; Loc. = LCCOMB_X35_Y16_N22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[4]~5'
- Info: 225: + IC(0.000 ns) + CELL(0.080 ns) = 93.248 ns; Loc. = LCCOMB_X35_Y16_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[5]~7'
- Info: 226: + IC(0.000 ns) + CELL(0.080 ns) = 93.328 ns; Loc. = LCCOMB_X35_Y16_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[6]~9'
- Info: 227: + IC(0.000 ns) + CELL(0.458 ns) = 93.786 ns; Loc. = LCCOMB_X35_Y16_N28; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[7]~10'
- Info: 228: + IC(0.825 ns) + CELL(0.521 ns) = 95.132 ns; Loc. = LCCOMB_X31_Y16_N14; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|op_1~0'
- Info: 229: + IC(0.817 ns) + CELL(0.178 ns) = 96.127 ns; Loc. = LCCOMB_X35_Y16_N0; Fanout = 19; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|quotient[0]~4'
- Info: 230: + IC(0.322 ns) + CELL(0.178 ns) = 96.627 ns; Loc. = LCCOMB_X35_Y16_N4; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~15'
- Info: 231: + IC(0.300 ns) + CELL(0.322 ns) = 97.249 ns; Loc. = LCCOMB_X35_Y16_N6; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~16'
- Info: 232: + IC(1.103 ns) + CELL(0.178 ns) = 98.530 ns; Loc. = LCCOMB_X30_Y16_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~17'
- Info: 233: + IC(0.296 ns) + CELL(0.178 ns) = 99.004 ns; Loc. = LCCOMB_X30_Y16_N0; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~18'
- Info: 234: + IC(0.298 ns) + CELL(0.178 ns) = 99.480 ns; Loc. = LCCOMB_X30_Y16_N18; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~19'
- Info: 235: + IC(0.289 ns) + CELL(0.178 ns) = 99.947 ns; Loc. = LCCOMB_X30_Y16_N22; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~22'
- Info: 236: + IC(1.156 ns) + CELL(0.178 ns) = 101.281 ns; Loc. = LCCOMB_X27_Y18_N16; Fanout = 4; COMB Node = 'Arkanoid:inst|Mux3~3'
- Info: 237: + IC(0.337 ns) + CELL(0.322 ns) = 101.940 ns; Loc. = LCCOMB_X27_Y18_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|blue_~1'
- Info: 238: + IC(0.522 ns) + CELL(0.413 ns) = 102.875 ns; Loc. = LCFF_X26_Y18_N11; Fanout = 1; REG Node = 'Arkanoid:inst|blue_[0]'
- Info: Total cell delay = 50.265 ns ( 48.86 % )
- Info: Total interconnect delay = 52.610 ns ( 51.14 % )
- Info: - Smallest clock skew is -0.021 ns
- Info: + Shortest clock path from clock "clk_50MHz" to destination register is 4.594 ns
+ Info: Detected ripple clock "ClockDivider:inst1|clk25MHz_" as buffer
+Info: Clock "clk_50MHz" has Internal fmax of 7.55 MHz between source register "Arkanoid:inst|platform1_position[3]" and destination register "Arkanoid:inst|hex0_[6]" (period= 132.461 ns)
+ Info: + Longest register to register delay is 132.203 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y12_N7; Fanout = 4; REG Node = 'Arkanoid:inst|platform1_position[3]'
+ Info: 2: + IC(1.188 ns) + CELL(0.178 ns) = 1.366 ns; Loc. = LCCOMB_X34_Y12_N6; Fanout = 1; COMB Node = 'Arkanoid:inst|platform1_position~64'
+ Info: 3: + IC(0.313 ns) + CELL(0.512 ns) = 2.191 ns; Loc. = LCCOMB_X34_Y12_N14; Fanout = 1; COMB Node = 'Arkanoid:inst|platform1_position~68'
+ Info: 4: + IC(0.830 ns) + CELL(0.521 ns) = 3.542 ns; Loc. = LCCOMB_X34_Y11_N0; Fanout = 32; COMB Node = 'Arkanoid:inst|platform1_position~74'
+ Info: 5: + IC(1.490 ns) + CELL(0.322 ns) = 5.354 ns; Loc. = LCCOMB_X34_Y9_N28; Fanout = 5; COMB Node = 'Arkanoid:inst|Add2~80'
+ Info: 6: + IC(0.926 ns) + CELL(0.455 ns) = 6.735 ns; Loc. = LCCOMB_X34_Y13_N4; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan1~6'
+ Info: 7: + IC(0.298 ns) + CELL(0.491 ns) = 7.524 ns; Loc. = LCCOMB_X34_Y13_N8; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan1~9'
+ Info: 8: + IC(0.303 ns) + CELL(0.322 ns) = 8.149 ns; Loc. = LCCOMB_X34_Y13_N26; Fanout = 2; COMB Node = 'Arkanoid:inst|LessThan1~10'
+ Info: 9: + IC(0.901 ns) + CELL(0.517 ns) = 9.567 ns; Loc. = LCCOMB_X35_Y12_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|Add3~1'
+ Info: 10: + IC(0.000 ns) + CELL(0.080 ns) = 9.647 ns; Loc. = LCCOMB_X35_Y12_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|Add3~3'
+ Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 9.727 ns; Loc. = LCCOMB_X35_Y12_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|Add3~5'
+ Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 9.807 ns; Loc. = LCCOMB_X35_Y12_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|Add3~7'
+ Info: 13: + IC(0.000 ns) + CELL(0.080 ns) = 9.887 ns; Loc. = LCCOMB_X35_Y12_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|Add3~9'
+ Info: 14: + IC(0.000 ns) + CELL(0.080 ns) = 9.967 ns; Loc. = LCCOMB_X35_Y12_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add3~11'
+ Info: 15: + IC(0.000 ns) + CELL(0.080 ns) = 10.047 ns; Loc. = LCCOMB_X35_Y12_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|Add3~13'
+ Info: 16: + IC(0.000 ns) + CELL(0.174 ns) = 10.221 ns; Loc. = LCCOMB_X35_Y12_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|Add3~15'
+ Info: 17: + IC(0.000 ns) + CELL(0.080 ns) = 10.301 ns; Loc. = LCCOMB_X35_Y12_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add3~17'
+ Info: 18: + IC(0.000 ns) + CELL(0.080 ns) = 10.381 ns; Loc. = LCCOMB_X35_Y12_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|Add3~19'
+ Info: 19: + IC(0.000 ns) + CELL(0.080 ns) = 10.461 ns; Loc. = LCCOMB_X35_Y12_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|Add3~21'
+ Info: 20: + IC(0.000 ns) + CELL(0.080 ns) = 10.541 ns; Loc. = LCCOMB_X35_Y12_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|Add3~23'
+ Info: 21: + IC(0.000 ns) + CELL(0.080 ns) = 10.621 ns; Loc. = LCCOMB_X35_Y12_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|Add3~25'
+ Info: 22: + IC(0.000 ns) + CELL(0.080 ns) = 10.701 ns; Loc. = LCCOMB_X35_Y12_N26; Fanout = 2; COMB Node = 'Arkanoid:inst|Add3~27'
+ Info: 23: + IC(0.000 ns) + CELL(0.458 ns) = 11.159 ns; Loc. = LCCOMB_X35_Y12_N28; Fanout = 2; COMB Node = 'Arkanoid:inst|Add3~28'
+ Info: 24: + IC(1.165 ns) + CELL(0.178 ns) = 12.502 ns; Loc. = LCCOMB_X34_Y9_N12; Fanout = 3; COMB Node = 'Arkanoid:inst|platform1_position~127'
+ Info: 25: + IC(1.159 ns) + CELL(0.517 ns) = 14.178 ns; Loc. = LCCOMB_X35_Y8_N28; Fanout = 2; COMB Node = 'Arkanoid:inst|Add13~29'
+ Info: 26: + IC(0.000 ns) + CELL(0.161 ns) = 14.339 ns; Loc. = LCCOMB_X35_Y8_N30; Fanout = 2; COMB Node = 'Arkanoid:inst|Add13~31'
+ Info: 27: + IC(0.000 ns) + CELL(0.080 ns) = 14.419 ns; Loc. = LCCOMB_X35_Y7_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|Add13~33'
+ Info: 28: + IC(0.000 ns) + CELL(0.080 ns) = 14.499 ns; Loc. = LCCOMB_X35_Y7_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|Add13~35'
+ Info: 29: + IC(0.000 ns) + CELL(0.080 ns) = 14.579 ns; Loc. = LCCOMB_X35_Y7_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|Add13~37'
+ Info: 30: + IC(0.000 ns) + CELL(0.080 ns) = 14.659 ns; Loc. = LCCOMB_X35_Y7_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|Add13~39'
+ Info: 31: + IC(0.000 ns) + CELL(0.080 ns) = 14.739 ns; Loc. = LCCOMB_X35_Y7_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|Add13~41'
+ Info: 32: + IC(0.000 ns) + CELL(0.080 ns) = 14.819 ns; Loc. = LCCOMB_X35_Y7_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add13~43'
+ Info: 33: + IC(0.000 ns) + CELL(0.080 ns) = 14.899 ns; Loc. = LCCOMB_X35_Y7_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|Add13~45'
+ Info: 34: + IC(0.000 ns) + CELL(0.174 ns) = 15.073 ns; Loc. = LCCOMB_X35_Y7_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|Add13~47'
+ Info: 35: + IC(0.000 ns) + CELL(0.080 ns) = 15.153 ns; Loc. = LCCOMB_X35_Y7_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add13~49'
+ Info: 36: + IC(0.000 ns) + CELL(0.080 ns) = 15.233 ns; Loc. = LCCOMB_X35_Y7_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|Add13~51'
+ Info: 37: + IC(0.000 ns) + CELL(0.458 ns) = 15.691 ns; Loc. = LCCOMB_X35_Y7_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|Add13~52'
+ Info: 38: + IC(0.820 ns) + CELL(0.517 ns) = 17.028 ns; Loc. = LCCOMB_X34_Y7_N20; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan143~53'
+ Info: 39: + IC(0.000 ns) + CELL(0.080 ns) = 17.108 ns; Loc. = LCCOMB_X34_Y7_N22; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan143~55'
+ Info: 40: + IC(0.000 ns) + CELL(0.080 ns) = 17.188 ns; Loc. = LCCOMB_X34_Y7_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan143~57'
+ Info: 41: + IC(0.000 ns) + CELL(0.080 ns) = 17.268 ns; Loc. = LCCOMB_X34_Y7_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan143~59'
+ Info: 42: + IC(0.000 ns) + CELL(0.080 ns) = 17.348 ns; Loc. = LCCOMB_X34_Y7_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan143~61'
+ Info: 43: + IC(0.000 ns) + CELL(0.458 ns) = 17.806 ns; Loc. = LCCOMB_X34_Y7_N30; Fanout = 3; COMB Node = 'Arkanoid:inst|LessThan143~62'
+ Info: 44: + IC(1.097 ns) + CELL(0.178 ns) = 19.081 ns; Loc. = LCCOMB_X29_Y7_N0; Fanout = 3; COMB Node = 'Arkanoid:inst|always2~6'
+ Info: 45: + IC(2.158 ns) + CELL(0.495 ns) = 21.734 ns; Loc. = LCCOMB_X34_Y19_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~1'
+ Info: 46: + IC(0.000 ns) + CELL(0.080 ns) = 21.814 ns; Loc. = LCCOMB_X34_Y19_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~3'
+ Info: 47: + IC(0.000 ns) + CELL(0.080 ns) = 21.894 ns; Loc. = LCCOMB_X34_Y19_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~5'
+ Info: 48: + IC(0.000 ns) + CELL(0.080 ns) = 21.974 ns; Loc. = LCCOMB_X34_Y19_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~7'
+ Info: 49: + IC(0.000 ns) + CELL(0.080 ns) = 22.054 ns; Loc. = LCCOMB_X34_Y19_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~9'
+ Info: 50: + IC(0.000 ns) + CELL(0.080 ns) = 22.134 ns; Loc. = LCCOMB_X34_Y19_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~11'
+ Info: 51: + IC(0.000 ns) + CELL(0.080 ns) = 22.214 ns; Loc. = LCCOMB_X34_Y19_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~13'
+ Info: 52: + IC(0.000 ns) + CELL(0.174 ns) = 22.388 ns; Loc. = LCCOMB_X34_Y19_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~15'
+ Info: 53: + IC(0.000 ns) + CELL(0.080 ns) = 22.468 ns; Loc. = LCCOMB_X34_Y19_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~17'
+ Info: 54: + IC(0.000 ns) + CELL(0.080 ns) = 22.548 ns; Loc. = LCCOMB_X34_Y19_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~19'
+ Info: 55: + IC(0.000 ns) + CELL(0.080 ns) = 22.628 ns; Loc. = LCCOMB_X34_Y19_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~21'
+ Info: 56: + IC(0.000 ns) + CELL(0.080 ns) = 22.708 ns; Loc. = LCCOMB_X34_Y19_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~23'
+ Info: 57: + IC(0.000 ns) + CELL(0.080 ns) = 22.788 ns; Loc. = LCCOMB_X34_Y19_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~25'
+ Info: 58: + IC(0.000 ns) + CELL(0.080 ns) = 22.868 ns; Loc. = LCCOMB_X34_Y19_N26; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~27'
+ Info: 59: + IC(0.000 ns) + CELL(0.080 ns) = 22.948 ns; Loc. = LCCOMB_X34_Y19_N28; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~29'
+ Info: 60: + IC(0.000 ns) + CELL(0.161 ns) = 23.109 ns; Loc. = LCCOMB_X34_Y19_N30; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~31'
+ Info: 61: + IC(0.000 ns) + CELL(0.080 ns) = 23.189 ns; Loc. = LCCOMB_X34_Y18_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~33'
+ Info: 62: + IC(0.000 ns) + CELL(0.080 ns) = 23.269 ns; Loc. = LCCOMB_X34_Y18_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~35'
+ Info: 63: + IC(0.000 ns) + CELL(0.080 ns) = 23.349 ns; Loc. = LCCOMB_X34_Y18_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~37'
+ Info: 64: + IC(0.000 ns) + CELL(0.080 ns) = 23.429 ns; Loc. = LCCOMB_X34_Y18_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~39'
+ Info: 65: + IC(0.000 ns) + CELL(0.080 ns) = 23.509 ns; Loc. = LCCOMB_X34_Y18_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~41'
+ Info: 66: + IC(0.000 ns) + CELL(0.080 ns) = 23.589 ns; Loc. = LCCOMB_X34_Y18_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~43'
+ Info: 67: + IC(0.000 ns) + CELL(0.080 ns) = 23.669 ns; Loc. = LCCOMB_X34_Y18_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~45'
+ Info: 68: + IC(0.000 ns) + CELL(0.174 ns) = 23.843 ns; Loc. = LCCOMB_X34_Y18_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~47'
+ Info: 69: + IC(0.000 ns) + CELL(0.080 ns) = 23.923 ns; Loc. = LCCOMB_X34_Y18_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~49'
+ Info: 70: + IC(0.000 ns) + CELL(0.080 ns) = 24.003 ns; Loc. = LCCOMB_X34_Y18_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~51'
+ Info: 71: + IC(0.000 ns) + CELL(0.080 ns) = 24.083 ns; Loc. = LCCOMB_X34_Y18_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~53'
+ Info: 72: + IC(0.000 ns) + CELL(0.080 ns) = 24.163 ns; Loc. = LCCOMB_X34_Y18_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~55'
+ Info: 73: + IC(0.000 ns) + CELL(0.080 ns) = 24.243 ns; Loc. = LCCOMB_X34_Y18_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~57'
+ Info: 74: + IC(0.000 ns) + CELL(0.080 ns) = 24.323 ns; Loc. = LCCOMB_X34_Y18_N26; Fanout = 2; COMB Node = 'Arkanoid:inst|Add14~59'
+ Info: 75: + IC(0.000 ns) + CELL(0.080 ns) = 24.403 ns; Loc. = LCCOMB_X34_Y18_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|Add14~61'
+ Info: 76: + IC(0.000 ns) + CELL(0.458 ns) = 24.861 ns; Loc. = LCCOMB_X34_Y18_N30; Fanout = 3; COMB Node = 'Arkanoid:inst|Add14~63'
+ Info: 77: + IC(0.950 ns) + CELL(0.178 ns) = 25.989 ns; Loc. = LCCOMB_X35_Y22_N0; Fanout = 151; COMB Node = 'Arkanoid:inst|Add14~65'
+ Info: 78: + IC(1.012 ns) + CELL(0.517 ns) = 27.518 ns; Loc. = LCCOMB_X35_Y20_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~4'
+ Info: 79: + IC(0.000 ns) + CELL(0.080 ns) = 27.598 ns; Loc. = LCCOMB_X35_Y20_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~6'
+ Info: 80: + IC(0.000 ns) + CELL(0.080 ns) = 27.678 ns; Loc. = LCCOMB_X35_Y20_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~8'
+ Info: 81: + IC(0.000 ns) + CELL(0.080 ns) = 27.758 ns; Loc. = LCCOMB_X35_Y20_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~10'
+ Info: 82: + IC(0.000 ns) + CELL(0.080 ns) = 27.838 ns; Loc. = LCCOMB_X35_Y20_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~12'
+ Info: 83: + IC(0.000 ns) + CELL(0.174 ns) = 28.012 ns; Loc. = LCCOMB_X35_Y20_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~14'
+ Info: 84: + IC(0.000 ns) + CELL(0.080 ns) = 28.092 ns; Loc. = LCCOMB_X35_Y20_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~16'
+ Info: 85: + IC(0.000 ns) + CELL(0.080 ns) = 28.172 ns; Loc. = LCCOMB_X35_Y20_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~18'
+ Info: 86: + IC(0.000 ns) + CELL(0.080 ns) = 28.252 ns; Loc. = LCCOMB_X35_Y20_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~20'
+ Info: 87: + IC(0.000 ns) + CELL(0.080 ns) = 28.332 ns; Loc. = LCCOMB_X35_Y20_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~22'
+ Info: 88: + IC(0.000 ns) + CELL(0.080 ns) = 28.412 ns; Loc. = LCCOMB_X35_Y20_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~24'
+ Info: 89: + IC(0.000 ns) + CELL(0.080 ns) = 28.492 ns; Loc. = LCCOMB_X35_Y20_N26; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~26'
+ Info: 90: + IC(0.000 ns) + CELL(0.080 ns) = 28.572 ns; Loc. = LCCOMB_X35_Y20_N28; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~28'
+ Info: 91: + IC(0.000 ns) + CELL(0.161 ns) = 28.733 ns; Loc. = LCCOMB_X35_Y20_N30; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~30'
+ Info: 92: + IC(0.000 ns) + CELL(0.080 ns) = 28.813 ns; Loc. = LCCOMB_X35_Y19_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~32'
+ Info: 93: + IC(0.000 ns) + CELL(0.080 ns) = 28.893 ns; Loc. = LCCOMB_X35_Y19_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~34'
+ Info: 94: + IC(0.000 ns) + CELL(0.080 ns) = 28.973 ns; Loc. = LCCOMB_X35_Y19_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~36'
+ Info: 95: + IC(0.000 ns) + CELL(0.080 ns) = 29.053 ns; Loc. = LCCOMB_X35_Y19_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~38'
+ Info: 96: + IC(0.000 ns) + CELL(0.080 ns) = 29.133 ns; Loc. = LCCOMB_X35_Y19_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~40'
+ Info: 97: + IC(0.000 ns) + CELL(0.080 ns) = 29.213 ns; Loc. = LCCOMB_X35_Y19_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~42'
+ Info: 98: + IC(0.000 ns) + CELL(0.080 ns) = 29.293 ns; Loc. = LCCOMB_X35_Y19_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~44'
+ Info: 99: + IC(0.000 ns) + CELL(0.174 ns) = 29.467 ns; Loc. = LCCOMB_X35_Y19_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~46'
+ Info: 100: + IC(0.000 ns) + CELL(0.080 ns) = 29.547 ns; Loc. = LCCOMB_X35_Y19_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~48'
+ Info: 101: + IC(0.000 ns) + CELL(0.080 ns) = 29.627 ns; Loc. = LCCOMB_X35_Y19_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~50'
+ Info: 102: + IC(0.000 ns) + CELL(0.080 ns) = 29.707 ns; Loc. = LCCOMB_X35_Y19_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~52'
+ Info: 103: + IC(0.000 ns) + CELL(0.080 ns) = 29.787 ns; Loc. = LCCOMB_X35_Y19_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~54'
+ Info: 104: + IC(0.000 ns) + CELL(0.080 ns) = 29.867 ns; Loc. = LCCOMB_X35_Y19_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~56'
+ Info: 105: + IC(0.000 ns) + CELL(0.458 ns) = 30.325 ns; Loc. = LCCOMB_X35_Y19_N26; Fanout = 4; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~57'
+ Info: 106: + IC(1.186 ns) + CELL(0.517 ns) = 32.028 ns; Loc. = LCCOMB_X38_Y21_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[1]~1'
+ Info: 107: + IC(0.000 ns) + CELL(0.080 ns) = 32.108 ns; Loc. = LCCOMB_X38_Y21_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[2]~3'
+ Info: 108: + IC(0.000 ns) + CELL(0.080 ns) = 32.188 ns; Loc. = LCCOMB_X38_Y21_N22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[3]~5'
+ Info: 109: + IC(0.000 ns) + CELL(0.458 ns) = 32.646 ns; Loc. = LCCOMB_X38_Y21_N24; Fanout = 11; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_3_result_int[4]~6'
+ Info: 110: + IC(0.373 ns) + CELL(0.319 ns) = 33.338 ns; Loc. = LCCOMB_X38_Y21_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[18]~358'
+ Info: 111: + IC(0.559 ns) + CELL(0.517 ns) = 34.414 ns; Loc. = LCCOMB_X39_Y21_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[1]~1'
+ Info: 112: + IC(0.000 ns) + CELL(0.080 ns) = 34.494 ns; Loc. = LCCOMB_X39_Y21_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[2]~3'
+ Info: 113: + IC(0.000 ns) + CELL(0.080 ns) = 34.574 ns; Loc. = LCCOMB_X39_Y21_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[3]~5'
+ Info: 114: + IC(0.000 ns) + CELL(0.080 ns) = 34.654 ns; Loc. = LCCOMB_X39_Y21_N6; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[4]~7'
+ Info: 115: + IC(0.000 ns) + CELL(0.458 ns) = 35.112 ns; Loc. = LCCOMB_X39_Y21_N8; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_4_result_int[5]~8'
+ Info: 116: + IC(1.235 ns) + CELL(0.178 ns) = 36.525 ns; Loc. = LCCOMB_X42_Y19_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[24]~365'
+ Info: 117: + IC(1.187 ns) + CELL(0.517 ns) = 38.229 ns; Loc. = LCCOMB_X39_Y21_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[1]~1'
+ Info: 118: + IC(0.000 ns) + CELL(0.080 ns) = 38.309 ns; Loc. = LCCOMB_X39_Y21_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[2]~3'
+ Info: 119: + IC(0.000 ns) + CELL(0.080 ns) = 38.389 ns; Loc. = LCCOMB_X39_Y21_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[3]~5'
+ Info: 120: + IC(0.000 ns) + CELL(0.080 ns) = 38.469 ns; Loc. = LCCOMB_X39_Y21_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[4]~7'
+ Info: 121: + IC(0.000 ns) + CELL(0.080 ns) = 38.549 ns; Loc. = LCCOMB_X39_Y21_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[5]~9'
+ Info: 122: + IC(0.000 ns) + CELL(0.458 ns) = 39.007 ns; Loc. = LCCOMB_X39_Y21_N28; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_5_result_int[6]~10'
+ Info: 123: + IC(1.249 ns) + CELL(0.322 ns) = 40.578 ns; Loc. = LCCOMB_X42_Y19_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[32]~369'
+ Info: 124: + IC(0.544 ns) + CELL(0.517 ns) = 41.639 ns; Loc. = LCCOMB_X43_Y19_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[3]~5'
+ Info: 125: + IC(0.000 ns) + CELL(0.080 ns) = 41.719 ns; Loc. = LCCOMB_X43_Y19_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[4]~7'
+ Info: 126: + IC(0.000 ns) + CELL(0.080 ns) = 41.799 ns; Loc. = LCCOMB_X43_Y19_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[5]~9'
+ Info: 127: + IC(0.000 ns) + CELL(0.458 ns) = 42.257 ns; Loc. = LCCOMB_X43_Y19_N30; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_6_result_int[6]~10'
+ Info: 128: + IC(0.502 ns) + CELL(0.322 ns) = 43.081 ns; Loc. = LCCOMB_X44_Y19_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[36]~380'
+ Info: 129: + IC(0.535 ns) + CELL(0.517 ns) = 44.133 ns; Loc. = LCCOMB_X43_Y19_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[1]~1'
+ Info: 130: + IC(0.000 ns) + CELL(0.080 ns) = 44.213 ns; Loc. = LCCOMB_X43_Y19_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[2]~3'
+ Info: 131: + IC(0.000 ns) + CELL(0.080 ns) = 44.293 ns; Loc. = LCCOMB_X43_Y19_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[3]~5'
+ Info: 132: + IC(0.000 ns) + CELL(0.080 ns) = 44.373 ns; Loc. = LCCOMB_X43_Y19_N6; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[4]~7'
+ Info: 133: + IC(0.000 ns) + CELL(0.080 ns) = 44.453 ns; Loc. = LCCOMB_X43_Y19_N8; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[5]~9'
+ Info: 134: + IC(0.000 ns) + CELL(0.458 ns) = 44.911 ns; Loc. = LCCOMB_X43_Y19_N10; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_7_result_int[6]~10'
+ Info: 135: + IC(0.562 ns) + CELL(0.322 ns) = 45.795 ns; Loc. = LCCOMB_X42_Y19_N22; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[44]~615'
+ Info: 136: + IC(1.148 ns) + CELL(0.495 ns) = 47.438 ns; Loc. = LCCOMB_X44_Y17_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[3]~5'
+ Info: 137: + IC(0.000 ns) + CELL(0.080 ns) = 47.518 ns; Loc. = LCCOMB_X44_Y17_N6; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[4]~7'
+ Info: 138: + IC(0.000 ns) + CELL(0.080 ns) = 47.598 ns; Loc. = LCCOMB_X44_Y17_N8; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[5]~9'
+ Info: 139: + IC(0.000 ns) + CELL(0.458 ns) = 48.056 ns; Loc. = LCCOMB_X44_Y17_N10; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_8_result_int[6]~10'
+ Info: 140: + IC(0.886 ns) + CELL(0.178 ns) = 49.120 ns; Loc. = LCCOMB_X44_Y19_N28; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[50]~616'
+ Info: 141: + IC(1.168 ns) + CELL(0.517 ns) = 50.805 ns; Loc. = LCCOMB_X44_Y17_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[3]~5'
+ Info: 142: + IC(0.000 ns) + CELL(0.080 ns) = 50.885 ns; Loc. = LCCOMB_X44_Y17_N20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[4]~7'
+ Info: 143: + IC(0.000 ns) + CELL(0.080 ns) = 50.965 ns; Loc. = LCCOMB_X44_Y17_N22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[5]~9'
+ Info: 144: + IC(0.000 ns) + CELL(0.458 ns) = 51.423 ns; Loc. = LCCOMB_X44_Y17_N24; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_9_result_int[6]~10'
+ Info: 145: + IC(0.889 ns) + CELL(0.322 ns) = 52.634 ns; Loc. = LCCOMB_X44_Y19_N22; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[56]~617'
+ Info: 146: + IC(1.198 ns) + CELL(0.517 ns) = 54.349 ns; Loc. = LCCOMB_X42_Y17_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[3]~5'
+ Info: 147: + IC(0.000 ns) + CELL(0.080 ns) = 54.429 ns; Loc. = LCCOMB_X42_Y17_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[4]~7'
+ Info: 148: + IC(0.000 ns) + CELL(0.080 ns) = 54.509 ns; Loc. = LCCOMB_X42_Y17_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[5]~9'
+ Info: 149: + IC(0.000 ns) + CELL(0.458 ns) = 54.967 ns; Loc. = LCCOMB_X42_Y17_N28; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_10_result_int[6]~10'
+ Info: 150: + IC(0.871 ns) + CELL(0.178 ns) = 56.016 ns; Loc. = LCCOMB_X40_Y17_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[60]~407'
+ Info: 151: + IC(0.854 ns) + CELL(0.517 ns) = 57.387 ns; Loc. = LCCOMB_X42_Y17_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[1]~1'
+ Info: 152: + IC(0.000 ns) + CELL(0.080 ns) = 57.467 ns; Loc. = LCCOMB_X42_Y17_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[2]~3'
+ Info: 153: + IC(0.000 ns) + CELL(0.080 ns) = 57.547 ns; Loc. = LCCOMB_X42_Y17_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[3]~5'
+ Info: 154: + IC(0.000 ns) + CELL(0.080 ns) = 57.627 ns; Loc. = LCCOMB_X42_Y17_N8; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[4]~7'
+ Info: 155: + IC(0.000 ns) + CELL(0.080 ns) = 57.707 ns; Loc. = LCCOMB_X42_Y17_N10; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[5]~9'
+ Info: 156: + IC(0.000 ns) + CELL(0.458 ns) = 58.165 ns; Loc. = LCCOMB_X42_Y17_N12; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_11_result_int[6]~10'
+ Info: 157: + IC(0.893 ns) + CELL(0.177 ns) = 59.235 ns; Loc. = LCCOMB_X40_Y17_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[66]~415'
+ Info: 158: + IC(0.552 ns) + CELL(0.517 ns) = 60.304 ns; Loc. = LCCOMB_X39_Y17_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[1]~1'
+ Info: 159: + IC(0.000 ns) + CELL(0.080 ns) = 60.384 ns; Loc. = LCCOMB_X39_Y17_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[2]~3'
+ Info: 160: + IC(0.000 ns) + CELL(0.080 ns) = 60.464 ns; Loc. = LCCOMB_X39_Y17_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[3]~5'
+ Info: 161: + IC(0.000 ns) + CELL(0.080 ns) = 60.544 ns; Loc. = LCCOMB_X39_Y17_N12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[4]~7'
+ Info: 162: + IC(0.000 ns) + CELL(0.174 ns) = 60.718 ns; Loc. = LCCOMB_X39_Y17_N14; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[5]~9'
+ Info: 163: + IC(0.000 ns) + CELL(0.458 ns) = 61.176 ns; Loc. = LCCOMB_X39_Y17_N16; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_12_result_int[6]~10'
+ Info: 164: + IC(0.895 ns) + CELL(0.177 ns) = 62.248 ns; Loc. = LCCOMB_X40_Y19_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[72]~422'
+ Info: 165: + IC(0.866 ns) + CELL(0.495 ns) = 63.609 ns; Loc. = LCCOMB_X39_Y17_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[1]~1'
+ Info: 166: + IC(0.000 ns) + CELL(0.080 ns) = 63.689 ns; Loc. = LCCOMB_X39_Y17_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[2]~3'
+ Info: 167: + IC(0.000 ns) + CELL(0.080 ns) = 63.769 ns; Loc. = LCCOMB_X39_Y17_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[3]~5'
+ Info: 168: + IC(0.000 ns) + CELL(0.458 ns) = 64.227 ns; Loc. = LCCOMB_X39_Y17_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_13_result_int[4]~6'
+ Info: 169: + IC(0.537 ns) + CELL(0.521 ns) = 65.285 ns; Loc. = LCCOMB_X40_Y17_N22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[82]~423'
+ Info: 170: + IC(0.812 ns) + CELL(0.517 ns) = 66.614 ns; Loc. = LCCOMB_X38_Y17_N10; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[5]~9'
+ Info: 171: + IC(0.000 ns) + CELL(0.458 ns) = 67.072 ns; Loc. = LCCOMB_X38_Y17_N12; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_14_result_int[6]~10'
+ Info: 172: + IC(0.941 ns) + CELL(0.178 ns) = 68.191 ns; Loc. = LCCOMB_X38_Y16_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[84]~435'
+ Info: 173: + IC(0.333 ns) + CELL(0.517 ns) = 69.041 ns; Loc. = LCCOMB_X38_Y16_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[1]~1'
+ Info: 174: + IC(0.000 ns) + CELL(0.080 ns) = 69.121 ns; Loc. = LCCOMB_X38_Y16_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[2]~3'
+ Info: 175: + IC(0.000 ns) + CELL(0.080 ns) = 69.201 ns; Loc. = LCCOMB_X38_Y16_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[3]~5'
+ Info: 176: + IC(0.000 ns) + CELL(0.080 ns) = 69.281 ns; Loc. = LCCOMB_X38_Y16_N12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[4]~7'
+ Info: 177: + IC(0.000 ns) + CELL(0.174 ns) = 69.455 ns; Loc. = LCCOMB_X38_Y16_N14; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[5]~9'
+ Info: 178: + IC(0.000 ns) + CELL(0.458 ns) = 69.913 ns; Loc. = LCCOMB_X38_Y16_N16; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_15_result_int[6]~10'
+ Info: 179: + IC(0.628 ns) + CELL(0.322 ns) = 70.863 ns; Loc. = LCCOMB_X37_Y16_N22; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[92]~623'
+ Info: 180: + IC(0.552 ns) + CELL(0.517 ns) = 71.932 ns; Loc. = LCCOMB_X37_Y16_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[3]~5'
+ Info: 181: + IC(0.000 ns) + CELL(0.080 ns) = 72.012 ns; Loc. = LCCOMB_X37_Y16_N6; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[4]~7'
+ Info: 182: + IC(0.000 ns) + CELL(0.080 ns) = 72.092 ns; Loc. = LCCOMB_X37_Y16_N8; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[5]~9'
+ Info: 183: + IC(0.000 ns) + CELL(0.458 ns) = 72.550 ns; Loc. = LCCOMB_X37_Y16_N10; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_16_result_int[6]~10'
+ Info: 184: + IC(0.613 ns) + CELL(0.319 ns) = 73.482 ns; Loc. = LCCOMB_X36_Y16_N26; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[97]~447'
+ Info: 185: + IC(0.540 ns) + CELL(0.517 ns) = 74.539 ns; Loc. = LCCOMB_X36_Y16_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[2]~3'
+ Info: 186: + IC(0.000 ns) + CELL(0.080 ns) = 74.619 ns; Loc. = LCCOMB_X36_Y16_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[3]~5'
+ Info: 187: + IC(0.000 ns) + CELL(0.080 ns) = 74.699 ns; Loc. = LCCOMB_X36_Y16_N12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[4]~7'
+ Info: 188: + IC(0.000 ns) + CELL(0.174 ns) = 74.873 ns; Loc. = LCCOMB_X36_Y16_N14; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[5]~9'
+ Info: 189: + IC(0.000 ns) + CELL(0.458 ns) = 75.331 ns; Loc. = LCCOMB_X36_Y16_N16; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_17_result_int[6]~10'
+ Info: 190: + IC(0.611 ns) + CELL(0.322 ns) = 76.264 ns; Loc. = LCCOMB_X35_Y16_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[102]~457'
+ Info: 191: + IC(0.324 ns) + CELL(0.517 ns) = 77.105 ns; Loc. = LCCOMB_X35_Y16_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[1]~1'
+ Info: 192: + IC(0.000 ns) + CELL(0.080 ns) = 77.185 ns; Loc. = LCCOMB_X35_Y16_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[2]~3'
+ Info: 193: + IC(0.000 ns) + CELL(0.080 ns) = 77.265 ns; Loc. = LCCOMB_X35_Y16_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[3]~5'
+ Info: 194: + IC(0.000 ns) + CELL(0.080 ns) = 77.345 ns; Loc. = LCCOMB_X35_Y16_N22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[4]~7'
+ Info: 195: + IC(0.000 ns) + CELL(0.080 ns) = 77.425 ns; Loc. = LCCOMB_X35_Y16_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[5]~9'
+ Info: 196: + IC(0.000 ns) + CELL(0.458 ns) = 77.883 ns; Loc. = LCCOMB_X35_Y16_N26; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_18_result_int[6]~10'
+ Info: 197: + IC(1.134 ns) + CELL(0.322 ns) = 79.339 ns; Loc. = LCCOMB_X27_Y16_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[108]~464'
+ Info: 198: + IC(0.809 ns) + CELL(0.517 ns) = 80.665 ns; Loc. = LCCOMB_X26_Y16_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[1]~1'
+ Info: 199: + IC(0.000 ns) + CELL(0.174 ns) = 80.839 ns; Loc. = LCCOMB_X26_Y16_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[2]~3'
+ Info: 200: + IC(0.000 ns) + CELL(0.080 ns) = 80.919 ns; Loc. = LCCOMB_X26_Y16_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[3]~5'
+ Info: 201: + IC(0.000 ns) + CELL(0.080 ns) = 80.999 ns; Loc. = LCCOMB_X26_Y16_N18; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[4]~7'
+ Info: 202: + IC(0.000 ns) + CELL(0.080 ns) = 81.079 ns; Loc. = LCCOMB_X26_Y16_N20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[5]~9'
+ Info: 203: + IC(0.000 ns) + CELL(0.458 ns) = 81.537 ns; Loc. = LCCOMB_X26_Y16_N22; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_19_result_int[6]~10'
+ Info: 204: + IC(1.409 ns) + CELL(0.178 ns) = 83.124 ns; Loc. = LCCOMB_X35_Y16_N30; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[116]~627'
+ Info: 205: + IC(1.417 ns) + CELL(0.517 ns) = 85.058 ns; Loc. = LCCOMB_X26_Y16_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[3]~5'
+ Info: 206: + IC(0.000 ns) + CELL(0.080 ns) = 85.138 ns; Loc. = LCCOMB_X26_Y16_N6; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[4]~7'
+ Info: 207: + IC(0.000 ns) + CELL(0.080 ns) = 85.218 ns; Loc. = LCCOMB_X26_Y16_N8; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[5]~9'
+ Info: 208: + IC(0.000 ns) + CELL(0.458 ns) = 85.676 ns; Loc. = LCCOMB_X26_Y16_N10; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_20_result_int[6]~10'
+ Info: 209: + IC(0.578 ns) + CELL(0.177 ns) = 86.431 ns; Loc. = LCCOMB_X27_Y16_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[122]~474'
+ Info: 210: + IC(1.476 ns) + CELL(0.517 ns) = 88.424 ns; Loc. = LCCOMB_X21_Y12_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[3]~5'
+ Info: 211: + IC(0.000 ns) + CELL(0.080 ns) = 88.504 ns; Loc. = LCCOMB_X21_Y12_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[4]~7'
+ Info: 212: + IC(0.000 ns) + CELL(0.080 ns) = 88.584 ns; Loc. = LCCOMB_X21_Y12_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[5]~9'
+ Info: 213: + IC(0.000 ns) + CELL(0.458 ns) = 89.042 ns; Loc. = LCCOMB_X21_Y12_N30; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_21_result_int[6]~10'
+ Info: 214: + IC(0.569 ns) + CELL(0.319 ns) = 89.930 ns; Loc. = LCCOMB_X22_Y12_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[126]~484'
+ Info: 215: + IC(0.820 ns) + CELL(0.517 ns) = 91.267 ns; Loc. = LCCOMB_X21_Y12_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[1]~1'
+ Info: 216: + IC(0.000 ns) + CELL(0.080 ns) = 91.347 ns; Loc. = LCCOMB_X21_Y12_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[2]~3'
+ Info: 217: + IC(0.000 ns) + CELL(0.080 ns) = 91.427 ns; Loc. = LCCOMB_X21_Y12_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[3]~5'
+ Info: 218: + IC(0.000 ns) + CELL(0.080 ns) = 91.507 ns; Loc. = LCCOMB_X21_Y12_N12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[4]~7'
+ Info: 219: + IC(0.000 ns) + CELL(0.174 ns) = 91.681 ns; Loc. = LCCOMB_X21_Y12_N14; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[5]~9'
+ Info: 220: + IC(0.000 ns) + CELL(0.458 ns) = 92.139 ns; Loc. = LCCOMB_X21_Y12_N16; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_22_result_int[6]~10'
+ Info: 221: + IC(0.900 ns) + CELL(0.322 ns) = 93.361 ns; Loc. = LCCOMB_X20_Y11_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[132]~492'
+ Info: 222: + IC(0.548 ns) + CELL(0.517 ns) = 94.426 ns; Loc. = LCCOMB_X21_Y11_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[1]~1'
+ Info: 223: + IC(0.000 ns) + CELL(0.080 ns) = 94.506 ns; Loc. = LCCOMB_X21_Y11_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[2]~3'
+ Info: 224: + IC(0.000 ns) + CELL(0.080 ns) = 94.586 ns; Loc. = LCCOMB_X21_Y11_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[3]~5'
+ Info: 225: + IC(0.000 ns) + CELL(0.080 ns) = 94.666 ns; Loc. = LCCOMB_X21_Y11_N12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[4]~7'
+ Info: 226: + IC(0.000 ns) + CELL(0.174 ns) = 94.840 ns; Loc. = LCCOMB_X21_Y11_N14; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[5]~9'
+ Info: 227: + IC(0.000 ns) + CELL(0.458 ns) = 95.298 ns; Loc. = LCCOMB_X21_Y11_N16; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_23_result_int[6]~10'
+ Info: 228: + IC(0.622 ns) + CELL(0.322 ns) = 96.242 ns; Loc. = LCCOMB_X20_Y11_N28; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[138]~498'
+ Info: 229: + IC(0.526 ns) + CELL(0.495 ns) = 97.263 ns; Loc. = LCCOMB_X21_Y11_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[1]~1'
+ Info: 230: + IC(0.000 ns) + CELL(0.080 ns) = 97.343 ns; Loc. = LCCOMB_X21_Y11_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[2]~3'
+ Info: 231: + IC(0.000 ns) + CELL(0.080 ns) = 97.423 ns; Loc. = LCCOMB_X21_Y11_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[3]~5'
+ Info: 232: + IC(0.000 ns) + CELL(0.080 ns) = 97.503 ns; Loc. = LCCOMB_X21_Y11_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[4]~7'
+ Info: 233: + IC(0.000 ns) + CELL(0.080 ns) = 97.583 ns; Loc. = LCCOMB_X21_Y11_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[5]~9'
+ Info: 234: + IC(0.000 ns) + CELL(0.458 ns) = 98.041 ns; Loc. = LCCOMB_X21_Y11_N30; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_24_result_int[6]~10'
+ Info: 235: + IC(0.833 ns) + CELL(0.177 ns) = 99.051 ns; Loc. = LCCOMB_X20_Y11_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[146]~502'
+ Info: 236: + IC(1.622 ns) + CELL(0.517 ns) = 101.190 ns; Loc. = LCCOMB_X20_Y20_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[3]~5'
+ Info: 237: + IC(0.000 ns) + CELL(0.080 ns) = 101.270 ns; Loc. = LCCOMB_X20_Y20_N8; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[4]~7'
+ Info: 238: + IC(0.000 ns) + CELL(0.080 ns) = 101.350 ns; Loc. = LCCOMB_X20_Y20_N10; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[5]~9'
+ Info: 239: + IC(0.000 ns) + CELL(0.458 ns) = 101.808 ns; Loc. = LCCOMB_X20_Y20_N12; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_25_result_int[6]~10'
+ Info: 240: + IC(0.616 ns) + CELL(0.178 ns) = 102.602 ns; Loc. = LCCOMB_X21_Y20_N12; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[152]~633'
+ Info: 241: + IC(0.838 ns) + CELL(0.517 ns) = 103.957 ns; Loc. = LCCOMB_X20_Y20_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[3]~5'
+ Info: 242: + IC(0.000 ns) + CELL(0.080 ns) = 104.037 ns; Loc. = LCCOMB_X20_Y20_N22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[4]~7'
+ Info: 243: + IC(0.000 ns) + CELL(0.080 ns) = 104.117 ns; Loc. = LCCOMB_X20_Y20_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[5]~9'
+ Info: 244: + IC(0.000 ns) + CELL(0.458 ns) = 104.575 ns; Loc. = LCCOMB_X20_Y20_N26; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_26_result_int[6]~10'
+ Info: 245: + IC(2.068 ns) + CELL(0.177 ns) = 106.820 ns; Loc. = LCCOMB_X36_Y21_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[156]~520'
+ Info: 246: + IC(0.552 ns) + CELL(0.517 ns) = 107.889 ns; Loc. = LCCOMB_X37_Y21_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[1]~1'
+ Info: 247: + IC(0.000 ns) + CELL(0.080 ns) = 107.969 ns; Loc. = LCCOMB_X37_Y21_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[2]~3'
+ Info: 248: + IC(0.000 ns) + CELL(0.080 ns) = 108.049 ns; Loc. = LCCOMB_X37_Y21_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[3]~5'
+ Info: 249: + IC(0.000 ns) + CELL(0.080 ns) = 108.129 ns; Loc. = LCCOMB_X37_Y21_N22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[4]~7'
+ Info: 250: + IC(0.000 ns) + CELL(0.080 ns) = 108.209 ns; Loc. = LCCOMB_X37_Y21_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[5]~9'
+ Info: 251: + IC(0.000 ns) + CELL(0.458 ns) = 108.667 ns; Loc. = LCCOMB_X37_Y21_N26; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_27_result_int[6]~10'
+ Info: 252: + IC(0.616 ns) + CELL(0.319 ns) = 109.602 ns; Loc. = LCCOMB_X36_Y21_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[162]~526'
+ Info: 253: + IC(0.546 ns) + CELL(0.517 ns) = 110.665 ns; Loc. = LCCOMB_X37_Y21_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[1]~1'
+ Info: 254: + IC(0.000 ns) + CELL(0.080 ns) = 110.745 ns; Loc. = LCCOMB_X37_Y21_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[2]~3'
+ Info: 255: + IC(0.000 ns) + CELL(0.080 ns) = 110.825 ns; Loc. = LCCOMB_X37_Y21_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[3]~5'
+ Info: 256: + IC(0.000 ns) + CELL(0.080 ns) = 110.905 ns; Loc. = LCCOMB_X37_Y21_N6; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[4]~7'
+ Info: 257: + IC(0.000 ns) + CELL(0.080 ns) = 110.985 ns; Loc. = LCCOMB_X37_Y21_N8; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[5]~9'
+ Info: 258: + IC(0.000 ns) + CELL(0.458 ns) = 111.443 ns; Loc. = LCCOMB_X37_Y21_N10; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_28_result_int[6]~10'
+ Info: 259: + IC(1.180 ns) + CELL(0.322 ns) = 112.945 ns; Loc. = LCCOMB_X39_Y20_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[169]~532'
+ Info: 260: + IC(0.557 ns) + CELL(0.517 ns) = 114.019 ns; Loc. = LCCOMB_X38_Y20_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[2]~3'
+ Info: 261: + IC(0.000 ns) + CELL(0.080 ns) = 114.099 ns; Loc. = LCCOMB_X38_Y20_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[3]~5'
+ Info: 262: + IC(0.000 ns) + CELL(0.080 ns) = 114.179 ns; Loc. = LCCOMB_X38_Y20_N8; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[4]~7'
+ Info: 263: + IC(0.000 ns) + CELL(0.080 ns) = 114.259 ns; Loc. = LCCOMB_X38_Y20_N10; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[5]~9'
+ Info: 264: + IC(0.000 ns) + CELL(0.458 ns) = 114.717 ns; Loc. = LCCOMB_X38_Y20_N12; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_29_result_int[6]~10'
+ Info: 265: + IC(0.622 ns) + CELL(0.178 ns) = 115.517 ns; Loc. = LCCOMB_X39_Y20_N14; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[176]~637'
+ Info: 266: + IC(0.862 ns) + CELL(0.517 ns) = 116.896 ns; Loc. = LCCOMB_X38_Y20_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[3]~5'
+ Info: 267: + IC(0.000 ns) + CELL(0.080 ns) = 116.976 ns; Loc. = LCCOMB_X38_Y20_N20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[4]~7'
+ Info: 268: + IC(0.000 ns) + CELL(0.080 ns) = 117.056 ns; Loc. = LCCOMB_X38_Y20_N22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[5]~9'
+ Info: 269: + IC(0.000 ns) + CELL(0.458 ns) = 117.514 ns; Loc. = LCCOMB_X38_Y20_N24; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_30_result_int[6]~10'
+ Info: 270: + IC(0.914 ns) + CELL(0.322 ns) = 118.750 ns; Loc. = LCCOMB_X37_Y22_N26; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[180]~548'
+ Info: 271: + IC(0.895 ns) + CELL(0.517 ns) = 120.162 ns; Loc. = LCCOMB_X37_Y20_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[1]~1'
+ Info: 272: + IC(0.000 ns) + CELL(0.080 ns) = 120.242 ns; Loc. = LCCOMB_X37_Y20_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[2]~3'
+ Info: 273: + IC(0.000 ns) + CELL(0.080 ns) = 120.322 ns; Loc. = LCCOMB_X37_Y20_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[3]~5'
+ Info: 274: + IC(0.000 ns) + CELL(0.080 ns) = 120.402 ns; Loc. = LCCOMB_X37_Y20_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[4]~7'
+ Info: 275: + IC(0.000 ns) + CELL(0.080 ns) = 120.482 ns; Loc. = LCCOMB_X37_Y20_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[5]~9'
+ Info: 276: + IC(0.000 ns) + CELL(0.458 ns) = 120.940 ns; Loc. = LCCOMB_X37_Y20_N30; Fanout = 10; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|add_sub_31_result_int[6]~10'
+ Info: 277: + IC(1.981 ns) + CELL(0.178 ns) = 123.099 ns; Loc. = LCCOMB_X13_Y19_N18; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|alt_u_div_k2f:divider|StageOut[187]~550'
+ Info: 278: + IC(1.802 ns) + CELL(0.521 ns) = 125.422 ns; Loc. = LCCOMB_X36_Y20_N16; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|op_2~2'
+ Info: 279: + IC(2.114 ns) + CELL(0.178 ns) = 127.714 ns; Loc. = LCCOMB_X13_Y19_N22; Fanout = 8; COMB Node = 'Arkanoid:inst|lpm_divide:Mod1|lpm_divide_ako:auto_generated|abs_divider_kbg:divider|remainder[1]~1'
+ Info: 280: + IC(1.137 ns) + CELL(0.322 ns) = 129.173 ns; Loc. = LCCOMB_X9_Y20_N22; Fanout = 3; COMB Node = 'Arkanoid:inst|Equal36~0'
+ Info: 281: + IC(0.299 ns) + CELL(0.178 ns) = 129.650 ns; Loc. = LCCOMB_X9_Y20_N16; Fanout = 4; COMB Node = 'Arkanoid:inst|low~4'
+ Info: 282: + IC(0.798 ns) + CELL(0.322 ns) = 130.770 ns; Loc. = LCCOMB_X13_Y19_N26; Fanout = 3; COMB Node = 'Arkanoid:inst|low~5'
+ Info: 283: + IC(1.159 ns) + CELL(0.178 ns) = 132.107 ns; Loc. = LCCOMB_X9_Y20_N8; Fanout = 1; COMB Node = 'Arkanoid:inst|low~29'
+ Info: 284: + IC(0.000 ns) + CELL(0.096 ns) = 132.203 ns; Loc. = LCFF_X9_Y20_N9; Fanout = 1; REG Node = 'Arkanoid:inst|hex0_[6]'
+ Info: Total cell delay = 60.731 ns ( 45.94 % )
+ Info: Total interconnect delay = 71.472 ns ( 54.06 % )
+ Info: - Smallest clock skew is -0.019 ns
+ Info: + Shortest clock path from clock "clk_50MHz" to destination register is 4.591 ns
Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz'
- Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'Arkanoid:inst|clk25MHz_'
- Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G2; Fanout = 150; COMB Node = 'Arkanoid:inst|clk25MHz_~clkctrl'
- Info: 4: + IC(0.980 ns) + CELL(0.602 ns) = 4.594 ns; Loc. = LCFF_X26_Y18_N11; Fanout = 1; REG Node = 'Arkanoid:inst|blue_[0]'
- Info: Total cell delay = 2.507 ns ( 54.57 % )
- Info: Total interconnect delay = 2.087 ns ( 45.43 % )
- Info: - Longest clock path from clock "clk_50MHz" to source register is 4.615 ns
+ Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'ClockDivider:inst1|clk25MHz_'
+ Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G0; Fanout = 1085; COMB Node = 'ClockDivider:inst1|clk25MHz_~clkctrl'
+ Info: 4: + IC(0.977 ns) + CELL(0.602 ns) = 4.591 ns; Loc. = LCFF_X9_Y20_N9; Fanout = 1; REG Node = 'Arkanoid:inst|hex0_[6]'
+ Info: Total cell delay = 2.507 ns ( 54.61 % )
+ Info: Total interconnect delay = 2.084 ns ( 45.39 % )
+ Info: - Longest clock path from clock "clk_50MHz" to source register is 4.610 ns
Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz'
- Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'Arkanoid:inst|clk25MHz_'
- Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G2; Fanout = 150; COMB Node = 'Arkanoid:inst|clk25MHz_~clkctrl'
- Info: 4: + IC(1.001 ns) + CELL(0.602 ns) = 4.615 ns; Loc. = LCFF_X14_Y11_N3; Fanout = 6; REG Node = 'Arkanoid:inst|h_counter[1]'
- Info: Total cell delay = 2.507 ns ( 54.32 % )
- Info: Total interconnect delay = 2.108 ns ( 45.68 % )
+ Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'ClockDivider:inst1|clk25MHz_'
+ Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G0; Fanout = 1085; COMB Node = 'ClockDivider:inst1|clk25MHz_~clkctrl'
+ Info: 4: + IC(0.996 ns) + CELL(0.602 ns) = 4.610 ns; Loc. = LCFF_X33_Y12_N7; Fanout = 4; REG Node = 'Arkanoid:inst|platform1_position[3]'
+ Info: Total cell delay = 2.507 ns ( 54.38 % )
+ Info: Total interconnect delay = 2.103 ns ( 45.62 % )
Info: + Micro clock to output delay of source is 0.277 ns
Info: + Micro setup delay of destination is -0.038 ns
-Info: tsu for register "Arkanoid:inst|blue_[0]" (data pin = "button3", clock pin = "clk_50MHz") is 32.749 ns
- Info: + Longest pin to register delay is 37.381 ns
- Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_R21; Fanout = 5; PIN Node = 'button3'
- Info: 2: + IC(6.425 ns) + CELL(0.521 ns) = 7.810 ns; Loc. = LCCOMB_X34_Y21_N26; Fanout = 63; COMB Node = 'Arkanoid:inst|platform2_position~0'
- Info: 3: + IC(0.990 ns) + CELL(0.495 ns) = 9.295 ns; Loc. = LCCOMB_X34_Y19_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~1'
- Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 9.375 ns; Loc. = LCCOMB_X34_Y19_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~3'
- Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 9.455 ns; Loc. = LCCOMB_X34_Y19_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~5'
- Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 9.535 ns; Loc. = LCCOMB_X34_Y19_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~7'
- Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 9.615 ns; Loc. = LCCOMB_X34_Y19_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~9'
- Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 9.695 ns; Loc. = LCCOMB_X34_Y19_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~11'
- Info: 9: + IC(0.000 ns) + CELL(0.080 ns) = 9.775 ns; Loc. = LCCOMB_X34_Y19_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~13'
- Info: 10: + IC(0.000 ns) + CELL(0.174 ns) = 9.949 ns; Loc. = LCCOMB_X34_Y19_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~15'
- Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 10.029 ns; Loc. = LCCOMB_X34_Y19_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~17'
- Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 10.109 ns; Loc. = LCCOMB_X34_Y19_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~19'
- Info: 13: + IC(0.000 ns) + CELL(0.080 ns) = 10.189 ns; Loc. = LCCOMB_X34_Y19_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~21'
- Info: 14: + IC(0.000 ns) + CELL(0.080 ns) = 10.269 ns; Loc. = LCCOMB_X34_Y19_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~23'
- Info: 15: + IC(0.000 ns) + CELL(0.080 ns) = 10.349 ns; Loc. = LCCOMB_X34_Y19_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~25'
- Info: 16: + IC(0.000 ns) + CELL(0.080 ns) = 10.429 ns; Loc. = LCCOMB_X34_Y19_N26; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~27'
- Info: 17: + IC(0.000 ns) + CELL(0.080 ns) = 10.509 ns; Loc. = LCCOMB_X34_Y19_N28; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~29'
- Info: 18: + IC(0.000 ns) + CELL(0.161 ns) = 10.670 ns; Loc. = LCCOMB_X34_Y19_N30; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~31'
- Info: 19: + IC(0.000 ns) + CELL(0.080 ns) = 10.750 ns; Loc. = LCCOMB_X34_Y18_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~33'
- Info: 20: + IC(0.000 ns) + CELL(0.080 ns) = 10.830 ns; Loc. = LCCOMB_X34_Y18_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~35'
- Info: 21: + IC(0.000 ns) + CELL(0.080 ns) = 10.910 ns; Loc. = LCCOMB_X34_Y18_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~37'
- Info: 22: + IC(0.000 ns) + CELL(0.080 ns) = 10.990 ns; Loc. = LCCOMB_X34_Y18_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~39'
- Info: 23: + IC(0.000 ns) + CELL(0.080 ns) = 11.070 ns; Loc. = LCCOMB_X34_Y18_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~41'
- Info: 24: + IC(0.000 ns) + CELL(0.080 ns) = 11.150 ns; Loc. = LCCOMB_X34_Y18_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~43'
- Info: 25: + IC(0.000 ns) + CELL(0.080 ns) = 11.230 ns; Loc. = LCCOMB_X34_Y18_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~45'
- Info: 26: + IC(0.000 ns) + CELL(0.174 ns) = 11.404 ns; Loc. = LCCOMB_X34_Y18_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~47'
- Info: 27: + IC(0.000 ns) + CELL(0.080 ns) = 11.484 ns; Loc. = LCCOMB_X34_Y18_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~49'
- Info: 28: + IC(0.000 ns) + CELL(0.080 ns) = 11.564 ns; Loc. = LCCOMB_X34_Y18_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~51'
- Info: 29: + IC(0.000 ns) + CELL(0.080 ns) = 11.644 ns; Loc. = LCCOMB_X34_Y18_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~53'
- Info: 30: + IC(0.000 ns) + CELL(0.080 ns) = 11.724 ns; Loc. = LCCOMB_X34_Y18_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~55'
- Info: 31: + IC(0.000 ns) + CELL(0.458 ns) = 12.182 ns; Loc. = LCCOMB_X34_Y18_N24; Fanout = 4; COMB Node = 'Arkanoid:inst|Add4~56'
- Info: 32: + IC(0.917 ns) + CELL(0.455 ns) = 13.554 ns; Loc. = LCCOMB_X34_Y17_N16; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan3~8'
- Info: 33: + IC(1.760 ns) + CELL(0.178 ns) = 15.492 ns; Loc. = LCCOMB_X35_Y19_N18; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan3~9'
- Info: 34: + IC(0.293 ns) + CELL(0.521 ns) = 16.306 ns; Loc. = LCCOMB_X35_Y19_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|LessThan3~10'
- Info: 35: + IC(0.884 ns) + CELL(0.495 ns) = 17.685 ns; Loc. = LCCOMB_X34_Y15_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~9'
- Info: 36: + IC(0.000 ns) + CELL(0.080 ns) = 17.765 ns; Loc. = LCCOMB_X34_Y15_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~11'
- Info: 37: + IC(0.000 ns) + CELL(0.080 ns) = 17.845 ns; Loc. = LCCOMB_X34_Y15_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~13'
- Info: 38: + IC(0.000 ns) + CELL(0.080 ns) = 17.925 ns; Loc. = LCCOMB_X34_Y15_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~15'
- Info: 39: + IC(0.000 ns) + CELL(0.080 ns) = 18.005 ns; Loc. = LCCOMB_X34_Y15_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~17'
- Info: 40: + IC(0.000 ns) + CELL(0.080 ns) = 18.085 ns; Loc. = LCCOMB_X34_Y15_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~19'
- Info: 41: + IC(0.000 ns) + CELL(0.080 ns) = 18.165 ns; Loc. = LCCOMB_X34_Y15_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~24'
- Info: 42: + IC(0.000 ns) + CELL(0.174 ns) = 18.339 ns; Loc. = LCCOMB_X34_Y15_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~27'
- Info: 43: + IC(0.000 ns) + CELL(0.080 ns) = 18.419 ns; Loc. = LCCOMB_X34_Y15_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~30'
- Info: 44: + IC(0.000 ns) + CELL(0.080 ns) = 18.499 ns; Loc. = LCCOMB_X34_Y15_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~33'
- Info: 45: + IC(0.000 ns) + CELL(0.080 ns) = 18.579 ns; Loc. = LCCOMB_X34_Y15_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~36'
- Info: 46: + IC(0.000 ns) + CELL(0.080 ns) = 18.659 ns; Loc. = LCCOMB_X34_Y15_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~39'
- Info: 47: + IC(0.000 ns) + CELL(0.080 ns) = 18.739 ns; Loc. = LCCOMB_X34_Y15_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~42'
- Info: 48: + IC(0.000 ns) + CELL(0.080 ns) = 18.819 ns; Loc. = LCCOMB_X34_Y15_N26; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~45'
- Info: 49: + IC(0.000 ns) + CELL(0.458 ns) = 19.277 ns; Loc. = LCCOMB_X34_Y15_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|Add5~47'
- Info: 50: + IC(1.717 ns) + CELL(0.545 ns) = 21.539 ns; Loc. = LCCOMB_X34_Y21_N0; Fanout = 4; COMB Node = 'Arkanoid:inst|Add5~49'
- Info: 51: + IC(1.176 ns) + CELL(0.517 ns) = 23.232 ns; Loc. = LCCOMB_X29_Y20_N26; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~23'
- Info: 52: + IC(0.000 ns) + CELL(0.080 ns) = 23.312 ns; Loc. = LCCOMB_X29_Y20_N28; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~25'
- Info: 53: + IC(0.000 ns) + CELL(0.161 ns) = 23.473 ns; Loc. = LCCOMB_X29_Y20_N30; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~27'
- Info: 54: + IC(0.000 ns) + CELL(0.080 ns) = 23.553 ns; Loc. = LCCOMB_X29_Y19_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~29'
- Info: 55: + IC(0.000 ns) + CELL(0.080 ns) = 23.633 ns; Loc. = LCCOMB_X29_Y19_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~31'
- Info: 56: + IC(0.000 ns) + CELL(0.080 ns) = 23.713 ns; Loc. = LCCOMB_X29_Y19_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~33'
- Info: 57: + IC(0.000 ns) + CELL(0.080 ns) = 23.793 ns; Loc. = LCCOMB_X29_Y19_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~35'
- Info: 58: + IC(0.000 ns) + CELL(0.080 ns) = 23.873 ns; Loc. = LCCOMB_X29_Y19_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~37'
- Info: 59: + IC(0.000 ns) + CELL(0.080 ns) = 23.953 ns; Loc. = LCCOMB_X29_Y19_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~39'
- Info: 60: + IC(0.000 ns) + CELL(0.080 ns) = 24.033 ns; Loc. = LCCOMB_X29_Y19_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~41'
- Info: 61: + IC(0.000 ns) + CELL(0.174 ns) = 24.207 ns; Loc. = LCCOMB_X29_Y19_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~43'
- Info: 62: + IC(0.000 ns) + CELL(0.080 ns) = 24.287 ns; Loc. = LCCOMB_X29_Y19_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~45'
- Info: 63: + IC(0.000 ns) + CELL(0.458 ns) = 24.745 ns; Loc. = LCCOMB_X29_Y19_N18; Fanout = 1; COMB Node = 'Arkanoid:inst|Add6~46'
- Info: 64: + IC(1.551 ns) + CELL(0.455 ns) = 26.751 ns; Loc. = LCCOMB_X30_Y19_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|LessThan29~6'
- Info: 65: + IC(0.300 ns) + CELL(0.322 ns) = 27.373 ns; Loc. = LCCOMB_X30_Y19_N22; Fanout = 15; COMB Node = 'Arkanoid:inst|LessThan29~8'
- Info: 66: + IC(1.593 ns) + CELL(0.178 ns) = 29.144 ns; Loc. = LCCOMB_X32_Y15_N16; Fanout = 16; COMB Node = 'Arkanoid:inst|LessThan29~10'
- Info: 67: + IC(0.994 ns) + CELL(0.545 ns) = 30.683 ns; Loc. = LCCOMB_X32_Y17_N22; Fanout = 1; COMB Node = 'Arkanoid:inst|always3~38'
- Info: 68: + IC(0.297 ns) + CELL(0.521 ns) = 31.501 ns; Loc. = LCCOMB_X32_Y17_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|always3~39'
- Info: 69: + IC(0.787 ns) + CELL(0.485 ns) = 32.773 ns; Loc. = LCCOMB_X32_Y17_N14; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux2~15'
- Info: 70: + IC(0.889 ns) + CELL(0.322 ns) = 33.984 ns; Loc. = LCCOMB_X31_Y18_N2; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux2~16'
- Info: 71: + IC(0.297 ns) + CELL(0.178 ns) = 34.459 ns; Loc. = LCCOMB_X31_Y18_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux2~19'
- Info: 72: + IC(0.798 ns) + CELL(0.322 ns) = 35.579 ns; Loc. = LCCOMB_X27_Y18_N20; Fanout = 4; COMB Node = 'Arkanoid:inst|Mux3~1'
- Info: 73: + IC(0.354 ns) + CELL(0.513 ns) = 36.446 ns; Loc. = LCCOMB_X27_Y18_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|blue_~1'
- Info: 74: + IC(0.522 ns) + CELL(0.413 ns) = 37.381 ns; Loc. = LCFF_X26_Y18_N11; Fanout = 1; REG Node = 'Arkanoid:inst|blue_[0]'
- Info: Total cell delay = 14.837 ns ( 39.69 % )
- Info: Total interconnect delay = 22.544 ns ( 60.31 % )
+Info: tsu for register "Debouncer:inst5|button_reg[0]" (data pin = "button4", clock pin = "clk_50MHz") is 3.159 ns
+ Info: + Longest pin to register delay is 7.814 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_R22; Fanout = 1; PIN Node = 'button4'
+ Info: 2: + IC(6.537 ns) + CELL(0.413 ns) = 7.814 ns; Loc. = LCFF_X12_Y12_N29; Fanout = 2; REG Node = 'Debouncer:inst5|button_reg[0]'
+ Info: Total cell delay = 1.277 ns ( 16.34 % )
+ Info: Total interconnect delay = 6.537 ns ( 83.66 % )
Info: + Micro setup delay of destination is -0.038 ns
- Info: - Shortest clock path from clock "clk_50MHz" to destination register is 4.594 ns
+ Info: - Shortest clock path from clock "clk_50MHz" to destination register is 4.617 ns
Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz'
- Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'Arkanoid:inst|clk25MHz_'
- Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G2; Fanout = 150; COMB Node = 'Arkanoid:inst|clk25MHz_~clkctrl'
- Info: 4: + IC(0.980 ns) + CELL(0.602 ns) = 4.594 ns; Loc. = LCFF_X26_Y18_N11; Fanout = 1; REG Node = 'Arkanoid:inst|blue_[0]'
- Info: Total cell delay = 2.507 ns ( 54.57 % )
- Info: Total interconnect delay = 2.087 ns ( 45.43 % )
-Info: tco from clock "clk_50MHz" to destination pin "v_sync" through register "Arkanoid:inst|v_counter[8]" is 15.668 ns
- Info: + Longest clock path from clock "clk_50MHz" to source register is 4.602 ns
+ Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'ClockDivider:inst1|clk25MHz_'
+ Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G0; Fanout = 1085; COMB Node = 'ClockDivider:inst1|clk25MHz_~clkctrl'
+ Info: 4: + IC(1.003 ns) + CELL(0.602 ns) = 4.617 ns; Loc. = LCFF_X12_Y12_N29; Fanout = 2; REG Node = 'Debouncer:inst5|button_reg[0]'
+ Info: Total cell delay = 2.507 ns ( 54.30 % )
+ Info: Total interconnect delay = 2.110 ns ( 45.70 % )
+Info: tco from clock "clk_50MHz" to destination pin "h_sync" through register "Arkanoid:inst|h_counter[0]" is 14.776 ns
+ Info: + Longest clock path from clock "clk_50MHz" to source register is 4.595 ns
Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz'
- Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'Arkanoid:inst|clk25MHz_'
- Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G2; Fanout = 150; COMB Node = 'Arkanoid:inst|clk25MHz_~clkctrl'
- Info: 4: + IC(0.988 ns) + CELL(0.602 ns) = 4.602 ns; Loc. = LCFF_X15_Y13_N17; Fanout = 5; REG Node = 'Arkanoid:inst|v_counter[8]'
- Info: Total cell delay = 2.507 ns ( 54.48 % )
- Info: Total interconnect delay = 2.095 ns ( 45.52 % )
+ Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'ClockDivider:inst1|clk25MHz_'
+ Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G0; Fanout = 1085; COMB Node = 'ClockDivider:inst1|clk25MHz_~clkctrl'
+ Info: 4: + IC(0.981 ns) + CELL(0.602 ns) = 4.595 ns; Loc. = LCFF_X26_Y5_N1; Fanout = 7; REG Node = 'Arkanoid:inst|h_counter[0]'
+ Info: Total cell delay = 2.507 ns ( 54.56 % )
+ Info: Total interconnect delay = 2.088 ns ( 45.44 % )
Info: + Micro clock to output delay of source is 0.277 ns
- Info: + Longest register to pin delay is 10.789 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y13_N17; Fanout = 5; REG Node = 'Arkanoid:inst|v_counter[8]'
- Info: 2: + IC(0.606 ns) + CELL(0.451 ns) = 1.057 ns; Loc. = LCCOMB_X15_Y13_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|LessThan132~0'
- Info: 3: + IC(1.837 ns) + CELL(0.322 ns) = 3.216 ns; Loc. = LCCOMB_X15_Y14_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|Equal1~7'
- Info: 4: + IC(0.311 ns) + CELL(0.178 ns) = 3.705 ns; Loc. = LCCOMB_X15_Y14_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|Equal2~0'
- Info: 5: + IC(1.225 ns) + CELL(0.507 ns) = 5.437 ns; Loc. = LCCOMB_X18_Y11_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|Equal2~1'
- Info: 6: + IC(2.376 ns) + CELL(2.976 ns) = 10.789 ns; Loc. = PIN_B11; Fanout = 0; PIN Node = 'v_sync'
- Info: Total cell delay = 4.434 ns ( 41.10 % )
- Info: Total interconnect delay = 6.355 ns ( 58.90 % )
-Info: th for register "Arkanoid:inst|platform1_position[29]" (data pin = "button2", clock pin = "clk_50MHz") is -2.062 ns
- Info: + Longest clock path from clock "clk_50MHz" to destination register is 4.609 ns
+ Info: + Longest register to pin delay is 9.904 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y5_N1; Fanout = 7; REG Node = 'Arkanoid:inst|h_counter[0]'
+ Info: 2: + IC(0.640 ns) + CELL(0.512 ns) = 1.152 ns; Loc. = LCCOMB_X27_Y5_N2; Fanout = 3; COMB Node = 'Arkanoid:inst|Equal0~0'
+ Info: 3: + IC(1.181 ns) + CELL(0.545 ns) = 2.878 ns; Loc. = LCCOMB_X25_Y6_N22; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan156~0'
+ Info: 4: + IC(0.301 ns) + CELL(0.521 ns) = 3.700 ns; Loc. = LCCOMB_X25_Y6_N4; Fanout = 1; COMB Node = 'Arkanoid:inst|h_sync~1'
+ Info: 5: + IC(3.198 ns) + CELL(3.006 ns) = 9.904 ns; Loc. = PIN_A11; Fanout = 0; PIN Node = 'h_sync'
+ Info: Total cell delay = 4.584 ns ( 46.28 % )
+ Info: Total interconnect delay = 5.320 ns ( 53.72 % )
+Info: th for register "Debouncer:inst2|button_reg[0]" (data pin = "button1", clock pin = "clk_50MHz") is -1.772 ns
+ Info: + Longest clock path from clock "clk_50MHz" to destination register is 4.606 ns
Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz'
- Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'Arkanoid:inst|clk25MHz_'
- Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G2; Fanout = 150; COMB Node = 'Arkanoid:inst|clk25MHz_~clkctrl'
- Info: 4: + IC(0.995 ns) + CELL(0.602 ns) = 4.609 ns; Loc. = LCFF_X31_Y12_N9; Fanout = 3; REG Node = 'Arkanoid:inst|platform1_position[29]'
- Info: Total cell delay = 2.507 ns ( 54.39 % )
- Info: Total interconnect delay = 2.102 ns ( 45.61 % )
+ Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'ClockDivider:inst1|clk25MHz_'
+ Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G0; Fanout = 1085; COMB Node = 'ClockDivider:inst1|clk25MHz_~clkctrl'
+ Info: 4: + IC(0.992 ns) + CELL(0.602 ns) = 4.606 ns; Loc. = LCFF_X45_Y9_N9; Fanout = 2; REG Node = 'Debouncer:inst2|button_reg[0]'
+ Info: Total cell delay = 2.507 ns ( 54.43 % )
+ Info: Total interconnect delay = 2.099 ns ( 45.57 % )
Info: + Micro hold delay of destination is 0.286 ns
- Info: - Shortest pin to register delay is 6.957 ns
- Info: 1: + IC(0.000 ns) + CELL(0.874 ns) = 0.874 ns; Loc. = PIN_T22; Fanout = 36; PIN Node = 'button2'
- Info: 2: + IC(5.809 ns) + CELL(0.178 ns) = 6.861 ns; Loc. = LCCOMB_X31_Y12_N8; Fanout = 4; COMB Node = 'Arkanoid:inst|Add3~71'
- Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 6.957 ns; Loc. = LCFF_X31_Y12_N9; Fanout = 3; REG Node = 'Arkanoid:inst|platform1_position[29]'
- Info: Total cell delay = 1.148 ns ( 16.50 % )
- Info: Total interconnect delay = 5.809 ns ( 83.50 % )
+ Info: - Shortest pin to register delay is 6.664 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.874 ns) = 0.874 ns; Loc. = PIN_T21; Fanout = 1; PIN Node = 'button1'
+ Info: 2: + IC(5.377 ns) + CELL(0.413 ns) = 6.664 ns; Loc. = LCFF_X45_Y9_N9; Fanout = 2; REG Node = 'Debouncer:inst2|button_reg[0]'
+ Info: Total cell delay = 1.287 ns ( 19.31 % )
+ Info: Total interconnect delay = 5.377 ns ( 80.69 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
- Info: Peak virtual memory: 166 megabytes
- Info: Processing ended: Mon May 21 19:54:43 2012
- Info: Elapsed time: 00:00:03
- Info: Total CPU time (on all processors): 00:00:06
+ Info: Peak virtual memory: 201 megabytes
+ Info: Processing ended: Mon May 28 14:22:38 2012
+ Info: Elapsed time: 00:00:06
+ Info: Total CPU time (on all processors): 00:00:08
diff --git a/myArkanoid.tan.summary b/myArkanoid.tan.summary
index 8b46cf6..d8005de 100644
--- a/myArkanoid.tan.summary
+++ b/myArkanoid.tan.summary
@@ -5,9 +5,9 @@ Timing Analyzer Summary
Type : Worst-case tsu
Slack : N/A
Required Time : None
-Actual Time : 32.749 ns
-From : button3
-To : Arkanoid:inst|blue_[0]
+Actual Time : 3.159 ns
+From : button4
+To : Debouncer:inst5|button_reg[0]
From Clock : --
To Clock : clk_50MHz
Failed Paths : 0
@@ -15,9 +15,9 @@ Failed Paths : 0
Type : Worst-case tco
Slack : N/A
Required Time : None
-Actual Time : 15.668 ns
-From : Arkanoid:inst|v_counter[8]
-To : v_sync
+Actual Time : 14.776 ns
+From : Arkanoid:inst|h_counter[0]
+To : h_sync
From Clock : clk_50MHz
To Clock : --
Failed Paths : 0
@@ -25,9 +25,9 @@ Failed Paths : 0
Type : Worst-case th
Slack : N/A
Required Time : None
-Actual Time : -2.062 ns
-From : button2
-To : Arkanoid:inst|platform1_position[29]
+Actual Time : -1.772 ns
+From : button1
+To : Debouncer:inst2|button_reg[0]
From Clock : --
To Clock : clk_50MHz
Failed Paths : 0
@@ -35,9 +35,9 @@ Failed Paths : 0
Type : Clock Setup: 'clk_50MHz'
Slack : N/A
Required Time : None
-Actual Time : 9.70 MHz ( period = 103.135 ns )
-From : Arkanoid:inst|h_counter[1]
-To : Arkanoid:inst|blue_[0]
+Actual Time : 7.55 MHz ( period = 132.461 ns )
+From : Arkanoid:inst|platform1_position[3]
+To : Arkanoid:inst|hex0_[6]
From Clock : clk_50MHz
To Clock : clk_50MHz
Failed Paths : 0
diff --git a/vga_sync.v b/vga_sync.v
new file mode 100644
index 0000000..e164ca3
--- /dev/null
+++ b/vga_sync.v
@@ -0,0 +1,25 @@
+`ifndef _vga_sync_
+`define _vga_sync_
+
+ // VGA synchronization
+
+ localparam VGA_LINES_LIMIT = 799;
+ localparam VGA_FRAMES_LIMIT = 524;
+
+ always @ (posedge clk25MHz)
+ begin
+ if(h_counter == VGA_LINES_LIMIT)
+ h_counter <= 0;
+ else
+ h_counter <= (h_counter + 1);
+ end
+
+ always @ (posedge clk25MHz)
+ begin
+ if (v_counter == VGA_FRAMES_LIMIT)
+ v_counter <= 0;
+ else if (h_counter == VGA_LINES_LIMIT)
+ v_counter <= (v_counter + 1);
+ end
+
+`endif // _vga_sync_
\ No newline at end of file