diff --git a/Arkanoid.bsf b/Arkanoid.bsf new file mode 100644 index 0000000..489ebbf --- /dev/null +++ b/Arkanoid.bsf @@ -0,0 +1,230 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 168 240) + (text "Arkanoid" (rect 5 0 47 12)(font "Arial" )) + (text "inst" (rect 8 208 25 220)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk50MHz" (rect 0 0 47 12)(font "Arial" )) + (text "clk50MHz" (rect 21 27 68 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "button1" (rect 0 0 36 12)(font "Arial" )) + (text "button1" (rect 21 43 57 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 0 64) + (input) + (text "button2" (rect 0 0 36 12)(font "Arial" )) + (text "button2" (rect 21 59 57 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 1)) + ) + (port + (pt 0 80) + (input) + (text "button3" (rect 0 0 36 12)(font "Arial" )) + (text "button3" (rect 21 75 57 87)(font "Arial" )) + (line (pt 0 80)(pt 16 80)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "button4" (rect 0 0 36 12)(font "Arial" )) + (text "button4" (rect 21 91 57 103)(font "Arial" )) + (line (pt 0 96)(pt 16 96)(line_width 1)) + ) + (port + (pt 152 32) + (output) + (text "h_sync" (rect 0 0 36 12)(font "Arial" )) + (text "h_sync" (rect 95 27 131 39)(font "Arial" )) + (line (pt 152 32)(pt 136 32)(line_width 1)) + ) + (port + (pt 152 48) + (output) + (text "v_sync" (rect 0 0 37 12)(font "Arial" )) + (text "v_sync" (rect 94 43 131 55)(font "Arial" )) + (line (pt 152 48)(pt 136 48)(line_width 1)) + ) + (port + (pt 152 64) + (output) + (text "red[3..0]" (rect 0 0 41 12)(font "Arial" )) + (text "red[3..0]" (rect 90 59 131 71)(font "Arial" )) + (line (pt 152 64)(pt 136 64)(line_width 3)) + ) + (port + (pt 152 80) + (output) + (text "green[3..0]" (rect 0 0 53 12)(font "Arial" )) + (text "green[3..0]" (rect 78 75 131 87)(font "Arial" )) + (line (pt 152 80)(pt 136 80)(line_width 3)) + ) + (port + (pt 152 96) + (output) + (text "blue[3..0]" (rect 0 0 46 12)(font "Arial" )) + (text "blue[3..0]" (rect 85 91 131 103)(font "Arial" )) + (line (pt 152 96)(pt 136 96)(line_width 3)) + ) + (port + (pt 152 112) + (output) + (text "num1[6..0]" (rect 0 0 53 12)(font "Arial" )) + (text "num1[6..0]" (rect 78 107 131 119)(font "Arial" )) + (line (pt 152 112)(pt 136 112)(line_width 3)) + ) + (port + (pt 152 128) + (output) + (text "num2[6..0]" (rect 0 0 53 12)(font "Arial" )) + (text "num2[6..0]" (rect 78 123 131 135)(font "Arial" )) + (line (pt 152 128)(pt 136 128)(line_width 3)) + ) + (port + (pt 152 144) + (output) + (text "num3[6..0]" (rect 0 0 53 12)(font "Arial" )) + (text "num3[6..0]" (rect 78 139 131 151)(font "Arial" )) + (line (pt 152 144)(pt 136 144)(line_width 3)) + ) + (port + (pt 152 160) + (output) + (text "num4[6..0]" (rect 0 0 53 12)(font "Arial" )) + (text "num4[6..0]" (rect 78 155 131 167)(font "Arial" )) + (line (pt 152 160)(pt 136 160)(line_width 3)) + ) + (port + (pt 152 176) + (output) + (text "led[7..0]" (rect 0 0 40 12)(font "Arial" )) + (text "led[7..0]" (rect 91 171 131 183)(font "Arial" )) + (line (pt 152 176)(pt 136 176)(line_width 3)) + ) + (parameter + "SCREEN_WIDTH" + "640" + "" + (type "PARAMETER_SIGNED_DEC") ) + (parameter + "SCREEN_HEIGHT" + "480" + "" + (type "PARAMETER_SIGNED_DEC") ) + (parameter + "CELL_SIZE" + "20" + "" + (type "PARAMETER_SIGNED_DEC") ) + (parameter + "BALL_SIZE" + "1" + "" + (type "PARAMETER_SIGNED_DEC") ) + (parameter + "BALL_SPEED" + "2" + "" + (type "PARAMETER_SIGNED_DEC") ) + (parameter + "PLATFORM_WIDTH" + "8" + "" + (type "PARAMETER_SIGNED_DEC") ) + (parameter + "PLATFORM_SPEED" + "1" + "" + (type "PARAMETER_SIGNED_DEC") ) + (parameter + "BK_COLOR_R" + "1111" + "" + (type "PARAMETER_UNSIGNED_BIN") ) + (parameter + "BK_COLOR_G" + "0000" + "" + (type "PARAMETER_UNSIGNED_BIN") ) + (parameter + "BK_COLOR_B" + "0000" + "" + (type "PARAMETER_UNSIGNED_BIN") ) + (parameter + "STABLE_COLOR_R" + "0011" + "" + (type "PARAMETER_UNSIGNED_BIN") ) + (parameter + "STABLE_COLOR_G" + "1100" + "" + (type "PARAMETER_UNSIGNED_BIN") ) + (parameter + "STABLE_COLOR_B" + "0110" + "" + (type "PARAMETER_UNSIGNED_BIN") ) + (parameter + "BALL_COLOR_R" + "0000" + "" + (type "PARAMETER_UNSIGNED_BIN") ) + (parameter + "BALL_COLOR_G" + "0000" + "" + (type "PARAMETER_UNSIGNED_BIN") ) + (parameter + "BALL_COLOR_B" + "1111" + "" + (type "PARAMETER_UNSIGNED_BIN") ) + (parameter + "PLATFORM_COLOR_R" + "1111" + "" + (type "PARAMETER_UNSIGNED_BIN") ) + (parameter + "PLATFORM_COLOR_G" + "0000" + "" + (type "PARAMETER_UNSIGNED_BIN") ) + (parameter + "PLATFORM_COLOR_B" + "0000" + "" + (type "PARAMETER_UNSIGNED_BIN") ) + (drawing + (rectangle (rect 16 16 136 208)(line_width 1)) + ) + (annotation_block (parameter)(rect 168 -64 268 16)) +) diff --git a/Arkanoid.qws b/Arkanoid.qws new file mode 100644 index 0000000..d7887e2 --- /dev/null +++ b/Arkanoid.qws @@ -0,0 +1,14 @@ +[ProjectWorkspace] +ptn_Child1=Frames +[ProjectWorkspace.Frames] +ptn_Child1=ChildFrames +[ProjectWorkspace.Frames.ChildFrames] +ptn_Child1=Document-0 +[ProjectWorkspace.Frames.ChildFrames.Document-0] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0] +DocPathName=TotalScheme.bdf +DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde} +IsChildFrameDetached=False +IsActiveChildFrame=True +ptn_Child1=StateMap diff --git a/Arkanoid.v b/Arkanoid.v new file mode 100644 index 0000000..460c538 --- /dev/null +++ b/Arkanoid.v @@ -0,0 +1,326 @@ +module Arkanoid + +#( + // Parameters + parameter SCREEN_WIDTH = 640, // Horizontal screen resolution (in pixels) + parameter SCREEN_HEIGHT = 480, // Vertical screen resolution (in pixels) + + parameter CELL_SIZE = 20, // 1 cell has size of 20x20 pixels. + + parameter BALL_SIZE = 1, // Game ball is a square of side 1 cell + parameter BALL_SPEED = 2, // Number of cells per second + + parameter PLATFORM_WIDTH = 8, // Game platform width + parameter PLATFORM_SPEED = 1, // Number of cells per second + + parameter [3:0] BK_COLOR_R = 4'b1111, // Red background + parameter [3:0] BK_COLOR_G = 4'b0000, + parameter [3:0] BK_COLOR_B = 4'b0000, + + parameter [3:0] STABLE_COLOR_R = 4'b0011, // ??? color :) + parameter [3:0] STABLE_COLOR_G = 4'b1100, + parameter [3:0] STABLE_COLOR_B = 4'b0110, + + parameter [3:0] BALL_COLOR_R = 4'b0000, // Blue ball + parameter [3:0] BALL_COLOR_G = 4'b0000, + parameter [3:0] BALL_COLOR_B = 4'b1111, + + parameter [3:0] PLATFORM_COLOR_R = 4'b1111, // Red platforms + parameter [3:0] PLATFORM_COLOR_G = 4'b0000, + parameter [3:0] PLATFORM_COLOR_B = 4'b0000 +) + +( + // Input Ports + input clk50MHz, // 50 MHz clock on DE1 + input button1, button2, button3, button4, // 4 buttons on DE1 (left<->right for 2 players) + + // Output Ports + output h_sync, + output v_sync, + output [3:0] red, green, blue, // Current pixel color (4096 colors = 12 bit) + output [6:0] num1, num2, num3, num4, // Digital LED's on DE1 + output [7:0] led +); + + ////////////////////////////////////// + // **** BEGIN OF MODULE HEADER **** // + ////////////////////////////////////// + + // Output registers + reg [3:0] red_, green_, blue_; + reg [6:0] num1_, num2_, num3_, num4_; + reg [7:0] led_; + + localparam FIELD_WIDTH = SCREEN_WIDTH/CELL_SIZE; // Horizontal screen resolution (in cells) + localparam FIELD_HEIGHT = SCREEN_HEIGHT/CELL_SIZE; // Vertical screen resolution (in cells) + + // VGA Module + localparam line = 799; + localparam frame = 524; + + // 25 MHz clock + reg clk25MHz_; + wire clk25MHz; + + // 2D array of cells, stores game field state + reg [1:0] field[0:FIELD_HEIGHT-1][0:FIELD_WIDTH-1]; + + // Possible cell values: (no comments) + localparam [1:0] EMPTY_CELL = 2'b00; + localparam [1:0] STABLE_CELL = 2'b11; + localparam [1:0] BALL_CELL = 2'b01; + localparam [1:0] PLATFORM_CELL = 2'b10; + + // ATTENTION!!! + // All definitions below are in cells only. + // + + // Informaton about game ball + integer ball_position_x; // Current coordinates + integer ball_position_y; + reg ball_state; // Current state (0 - stopped, 1 - moving) + reg [1:0] ball_direction; // Current moving direction + + // Possible ball directions: + localparam [1:0] LEFT_UP = 2'b00; + localparam [1:0] RIGHT_UP = 2'b01; + localparam [1:0] LEFT_DOWN = 2'b10; + localparam [1:0] RIGHT_DOWN = 2'b11; + + // Information about game platforms + integer platform1_position; // Current position (X axis, left border coordinate) + integer platform2_position; + + // VGA variables + integer h_counter; // Horizontal pixel counter + integer v_counter; // Vertical pixel counter + integer h_cell; // Horizontal cell counter + integer v_cell; // Vertical cell counter + reg [1:0] current_cell; // Current cell value + + // Loops variables + integer i, j; + + // Last buttons state + reg button1_state; + reg button2_state; + reg button3_state; + reg button4_state; + + + //////////////////////////////////// + // **** END OF MODULE HEADER **** // + //////////////////////////////////// + + // Initialization of all module variables + initial + begin + + // Place ball to the center of the screen + ball_position_x = FIELD_WIDTH/2; + ball_position_y = FIELD_HEIGHT/2; + ball_state = 0; + + // Place platforms at the center of the borders + platform1_position = (FIELD_WIDTH-PLATFORM_WIDTH)/2; // central position + platform2_position = platform1_position; + + button1_state = 1'b0; + button2_state = 1'b0; + button3_state = 1'b0; + button4_state = 1'b0; + + h_counter = 0; + v_counter = 0; + + for (i = 0; i < FIELD_HEIGHT; i = i + 1) + for (j = 0; j< FIELD_WIDTH; j = j + 1) + field[i][j] = EMPTY_CELL; + + field[ball_position_y][ball_position_x] = BALL_CELL; + + num1_ = 7'b0000000; + num2_ = 7'b0000000; + num3_ = 7'b0000000; + num4_ = 7'b0000000; + + end + + // Frequency divider (50 MHz to 25 MHz, needed for VGA) + always @ (posedge clk50MHz) + begin + clk25MHz_ = ~clk25MHz_; + end + + // VGA sync + always @ (posedge clk25MHz) + begin + if(h_counter == line) + h_counter <= 0; + else + h_counter <= (h_counter + 1); + end + + always @ (posedge clk25MHz) + begin + if (v_counter == frame) + v_counter <= 0; + else if (h_counter == line) + v_counter <= (v_counter + 1); + end + + + + always @ (posedge clk25MHz) + begin + + if (button1 != button1_state) + begin + if (button1 == 1'b1) + begin + led_[7] = 1'b1; + led_[6] = 1'b1; + if (platform1_position > 0) + platform1_position = platform1_position - 1; + end + else + begin + led_[7] = 1'b0; + led_[6] = 1'b0; + end + button1_state = button1; + end + + if (button2 != button2_state) + begin + if (button2 == 1'b1) + begin + led_[5] = 1'b1; + led_[4] = 1'b1; + if (platform1_position < FIELD_WIDTH-PLATFORM_WIDTH-1) + platform1_position = platform1_position + 1; + end + else + begin + led_[5] = 1'b0; + led_[4] = 1'b0; + end + button2_state = button2; + end + + if (button3 != button3_state) + begin + if (button3 == 1'b1) + begin + led_[3] = 1'b1; + led_[2] = 1'b1; + if (platform2_position > 0) + platform2_position = platform2_position - 1; + end + else + begin + led_[3] = 1'b0; + led_[2] = 1'b0; + end + button3_state = button3; + end + + if (button4 != button4_state) + begin + if (button4 == 1'b1) + begin + led_[1] = 1'b1; + led_[0] = 1'b1; + if (platform2_position < FIELD_WIDTH-PLATFORM_WIDTH-1) + platform2_position = platform2_position + 1; + end + else + begin + led_[1] = 1'b0; + led_[0] = 1'b0; + end + button4_state = button4; + end + + + for (i = 0; i < FIELD_WIDTH; i = i + 1) + begin + if ((i >= platform2_position) && (i <= platform2_position+PLATFORM_WIDTH)) + field[0][i] = PLATFORM_CELL; + else + field[0][i] = EMPTY_CELL; + + if ((i >= platform1_position) && (i <= platform1_position+PLATFORM_WIDTH)) + field[FIELD_HEIGHT-1][i] = PLATFORM_CELL; + else + field[FIELD_HEIGHT-1][i] = EMPTY_CELL; + end + + + // VGA output + h_cell = (h_counter-143)/CELL_SIZE; + v_cell = (v_counter-34)/CELL_SIZE; + if ((v_counter > 34) && (v_counter < 514) && (h_counter > 143) && (h_counter < 783)) + begin + + current_cell = field[v_cell][h_cell]; + + case(current_cell) + + EMPTY_CELL: + begin + red_ = BK_COLOR_R; + green_ = BK_COLOR_G; + blue_ = BK_COLOR_B; + end + + STABLE_CELL: + begin + red_ = STABLE_COLOR_R; + green_ = STABLE_COLOR_G; + blue_ = STABLE_COLOR_B; + end + + BALL_CELL: + begin + red_ = BALL_COLOR_R; + green_ = BALL_COLOR_G; + blue_ = BALL_COLOR_B; + end + + PLATFORM_CELL: + begin + red_ = PLATFORM_COLOR_R; + green_ = PLATFORM_COLOR_G; + blue_ = PLATFORM_COLOR_B; + end + + endcase + + end + else + begin + red_ = 4'b0000; + green_ = 4'b0000; + blue_ = 4'b0000; + end + + end + + assign clk25MHz = clk25MHz_; + + assign h_sync = ~((h_counter > 0) && (h_counter < 95)); + assign v_sync = ~((v_counter == 0) || (v_counter == 1)); + + assign red = red_; + assign green = green_; + assign blue = blue_; + + assign led = led_; + assign num1 = num1_; + assign num2 = num2_; + assign num3 = num3_; + assign num4 = num4_; + +endmodule diff --git a/Arkanoid.v.bak b/Arkanoid.v.bak new file mode 100644 index 0000000..0420c2e --- /dev/null +++ b/Arkanoid.v.bak @@ -0,0 +1,328 @@ +module Arkanoid + +#( + // Parameters + parameter SCREEN_WIDTH = 640, // Horizontal screen resolution (in pixels) + parameter SCREEN_HEIGHT = 480, // Vertical screen resolution (in pixels) + + parameter CELL_SIZE = 20, // 1 cell has size of 20x20 pixels. + + parameter BALL_SIZE = 1, // Game ball is a square of side 1 cell + parameter BALL_SPEED = 2, // Number of cells per second + + parameter PLATFORM_WIDTH = 8, // Game platform width + parameter PLATFORM_SPEED = 1, // Number of cells per second + + parameter [3:0] BK_COLOR_R = 4'b1111, // Red background + parameter [3:0] BK_COLOR_G = 4'b0000, + parameter [3:0] BK_COLOR_B = 4'b0000, + + parameter [3:0] STABLE_COLOR_R = 4'b0011, // ??? color :) + parameter [3:0] STABLE_COLOR_G = 4'b1100, + parameter [3:0] STABLE_COLOR_B = 4'b0110, + + parameter [3:0] BALL_COLOR_R = 4'b0000, // Blue ball + parameter [3:0] BALL_COLOR_G = 4'b0000, + parameter [3:0] BALL_COLOR_B = 4'b1111, + + parameter [3:0] PLATFORM_COLOR_R = 4'b1111, // Red platforms + parameter [3:0] PLATFORM_COLOR_G = 4'b0000, + parameter [3:0] PLATFORM_COLOR_B = 4'b0000 +) + +( + // Input Ports + input clk50MHz, // 50 MHz clock on DE1 + input button1, button2, button3, button4, // 4 buttons on DE1 (left<->right for 2 players) + + // Output Ports + output h_sync, + output v_sync, + output [3:0] red, green, blue, // Current pixel color (4096 colors = 12 bit) + output [6:0] num1, num2, num3, num4, // Digital LED's on DE1 + output [7:0] led +); + + ////////////////////////////////////// + // **** BEGIN OF MODULE HEADER **** // + ////////////////////////////////////// + + // Output registers + reg [3:0] red_, green_, blue_; + reg [6:0] num1_, num2_, num3_, num4_; + reg [7:0] led_; + + localparam FIELD_WIDTH = SCREEN_WIDTH/CELL_SIZE; // Horizontal screen resolution (in cells) + localparam FIELD_HEIGHT = SCREEN_HEIGHT/CELL_SIZE; // Vertical screen resolution (in cells) + + // VGA Module + localparam line = 799; + localparam frame = 524; + + // 25 MHz clock + reg clk25MHz_; + wire clk25MHz; + + // 2D array of cells, stores game field state + reg [1:0] field[0:FIELD_HEIGHT-1][0:FIELD_WIDTH-1]; + + // Possible cell values: (no comments) + localparam [1:0] EMPTY_CELL = 2'b00; + localparam [1:0] STABLE_CELL = 2'b11; + localparam [1:0] BALL_CELL = 2'b01; + localparam [1:0] PLATFORM_CELL = 2'b10; + + // ATTENTION!!! + // All definitions below are in cells only. + // + + // Informaton about game ball + integer ball_position_x; // Current coordinates + integer ball_position_y; + reg ball_state; // Current state (0 - stopped, 1 - moving) + reg [1:0] ball_direction; // Current moving direction + + // Possible ball directions: + localparam [1:0] LEFT_UP = 2'b00; + localparam [1:0] RIGHT_UP = 2'b01; + localparam [1:0] LEFT_DOWN = 2'b10; + localparam [1:0] RIGHT_DOWN = 2'b11; + + // Information about game platforms + integer platform1_position; // Current position (X axis, left border coordinate) + integer platform2_position; + + // VGA variables + integer h_counter; // Horizontal pixel counter + integer v_counter; // Vertical pixel counter + integer h_cell; // Horizontal cell counter + integer v_cell; // Vertical cell counter + reg [1:0] current_cell; // Current cell value + + // Loops variables + integer i, j; + + // Last buttons state + reg button1_state; + reg button2_state; + reg button3_state; + reg button4_state; + + + //////////////////////////////////// + // **** END OF MODULE HEADER **** // + //////////////////////////////////// + + // Initialization of all module variables + initial + begin + + // Place ball to the center of the screen + ball_position_x = FIELD_WIDTH/2; + ball_position_y = FIELD_HEIGHT/2; + ball_state = 0; + + // Place platforms at the center of the borders + platform1_position = (FIELD_WIDTH-PLATFORM_WIDTH)/2; // central position + platform2_position = platform1_position; + + button1_state = 1'b0; + button2_state = 1'b0; + button3_state = 1'b0; + button4_state = 1'b0; + + h_counter = 0; + v_counter = 0; + + for (i = 0; i < FIELD_HEIGHT; i = i + 1) + for (j = 0; j< FIELD_WIDTH; j = j + 1) + field[i][j] = EMPTY_CELL; + + field[ball_position_y][ball_position_x] = BALL_CELL; + + // Print platforms + + num1_ = 7'b0000000; + num2_ = 7'b0000000; + num3_ = 7'b0000000; + num4_ = 7'b0000000; + + end + + // Frequency divider (50 MHz to 25 MHz, needed for VGA) + always @ (posedge clk50MHz) + begin + clk25MHz_ = ~clk25MHz_; + end + + // VGA sync + always @ (posedge clk25MHz) + begin + if(h_counter == line) + h_counter <= 0; + else + h_counter <= (h_counter + 1); + end + + always @ (posedge clk25MHz) + begin + if (v_counter == frame) + v_counter <= 0; + else if (h_counter == line) + v_counter <= (v_counter + 1); + end + + + + always @ (posedge clk25MHz) + begin + + if (button1 != button1_state) + begin + if (button1 == 1'b1) + begin + led_[7] = 1'b1; + led_[6] = 1'b1; + if (platform1_position > 0) + platform1_position = platform1_position - 1; + end + else + begin + led_[7] = 1'b0; + led_[6] = 1'b0; + end + button1_state = button1; + end + + if (button2 != button2_state) + begin + if (button2 == 1'b1) + begin + led_[5] = 1'b1; + led_[4] = 1'b1; + if (platform1_position < FIELD_WIDTH-PLATFORM_WIDTH-1) + platform1_position = platform1_position + 1; + end + else + begin + led_[5] = 1'b0; + led_[4] = 1'b0; + end + button2_state = button2; + end + + if (button3 != button3_state) + begin + if (button3 == 1'b1) + begin + led_[3] = 1'b1; + led_[2] = 1'b1; + if (platform2_position > 0) + platform2_position = platform2_position - 1; + end + else + begin + led_[3] = 1'b0; + led_[2] = 1'b0; + end + button3_state = button3; + end + + if (button4 != button4_state) + begin + if (button4 == 1'b1) + begin + led_[1] = 1'b1; + led_[0] = 1'b1; + if (platform2_position < FIELD_WIDTH-PLATFORM_WIDTH-1) + platform2_position = platform2_position + 1; + end + else + begin + led_[1] = 1'b0; + led_[0] = 1'b0; + end + button4_state = button4; + end + + + for (i = 0; i < FIELD_WIDTH; i = i + 1) + begin + if ((i >= platform2_position) && (i <= platform2_position+PLATFORM_WIDTH)) + field[0][i] = PLATFORM_CELL; + else + field[0][i] = EMPTY_CELL; + + if ((i >= platform1_position) && (i <= platform1_position+PLATFORM_WIDTH)) + field[FIELD_HEIGHT-1][i] = PLATFORM_CELL; + else + field[FIELD_HEIGHT-1][i] = EMPTY_CELL; + end + + + // VGA output + h_cell = (h_counter-143)/CELL_SIZE; + v_cell = (v_counter-34)/CELL_SIZE; + if ((v_counter > 34) && (v_counter < 514) && (h_counter > 143) && (h_counter < 783)) + begin + + current_cell = field[v_cell][h_cell]; + + case(current_cell) + + EMPTY_CELL: + begin + red_ = BK_COLOR_R; + green_ = BK_COLOR_G; + blue_ = BK_COLOR_B; + end + + STABLE_CELL: + begin + red_ = STABLE_COLOR_R; + green_ = STABLE_COLOR_G; + blue_ = STABLE_COLOR_B; + end + + BALL_CELL: + begin + red_ = BALL_COLOR_R; + green_ = BALL_COLOR_G; + blue_ = BALL_COLOR_B; + end + + PLATFORM_CELL: + begin + red_ = PLATFORM_COLOR_R; + green_ = PLATFORM_COLOR_G; + blue_ = PLATFORM_COLOR_B; + end + + endcase + + end + else + begin + red_ = 4'b0000; + green_ = 4'b0000; + blue_ = 4'b0000; + end + + end + + assign clk25MHz = clk25MHz_; + + assign h_sync = ~((h_counter > 0) && (h_counter < 95)); + assign v_sync = ~((v_counter == 0) || (v_counter == 1)); + + assign red = red_; + assign green = green_; + assign blue = blue_; + + assign led = led_; + assign num1 = num1_; + assign num2 = num2_; + assign num3 = num3_; + assign num4 = num4_; + +endmodule diff --git a/TotalScheme.bdf b/TotalScheme.bdf new file mode 100644 index 0000000..9ba07ce --- /dev/null +++ b/TotalScheme.bdf @@ -0,0 +1,638 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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720 304) + (bus) +) +(connector + (pt 720 304) + (pt 720 432) + (bus) +) +(connector + (pt 912 432) + (pt 864 432) + (bus) +) +(connector + (pt 720 432) + (pt 816 432) + (bus) +) diff --git a/myArkanoid.asm.rpt b/myArkanoid.asm.rpt new file mode 100644 index 0000000..f4b3807 --- /dev/null +++ b/myArkanoid.asm.rpt @@ -0,0 +1,130 @@ +Assembler report for myArkanoid +Mon May 21 19:54:38 2012 +Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/myArkanoid.sof + 6. Assembler Device Options: C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/myArkanoid.pof + 7. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Mon May 21 19:54:38 2012 ; +; Revision Name ; myArkanoid ; +; Top-level Entity Name ; TotalScheme ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Generate compressed bitstreams ; On ; On ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; Off ; Off ; +; Use configuration device ; On ; On ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++---------------------------------------------------------------------+ +; Assembler Generated Files ; ++---------------------------------------------------------------------+ +; File Name ; ++---------------------------------------------------------------------+ +; C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/myArkanoid.sof ; +; C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/myArkanoid.pof ; ++---------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/myArkanoid.sof ; ++----------------+------------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+------------------------------------------------------------------------------+ +; Device ; EP2C20F484C7 ; +; JTAG usercode ; 0xFFFFFFFF ; +; Checksum ; 0x002DEAD6 ; ++----------------+------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/myArkanoid.pof ; ++--------------------+--------------------------------------------------------------------------+ +; Option ; Setting ; ++--------------------+--------------------------------------------------------------------------+ +; Device ; EPCS16 ; +; JTAG usercode ; 0x00000000 ; +; Checksum ; 0x1DBBF76B ; +; Compression Ratio ; 2 ; ++--------------------+--------------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II Assembler + Info: Version 9.1 Build 222 10/21/2009 SJ Full Version + Info: Processing started: Mon May 21 19:54:35 2012 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid +Info: Writing out detailed assembly data for power analysis +Info: Assembler is generating device programming files +Info: Quartus II Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 207 megabytes + Info: Processing ended: Mon May 21 19:54:38 2012 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/myArkanoid.cdf b/myArkanoid.cdf new file mode 100644 index 0000000..9a9c1e5 --- /dev/null +++ b/myArkanoid.cdf @@ -0,0 +1,13 @@ +/* Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version */ +JedecChain; + FileRevision(JESD32A); + DefaultMfr(6E); + + P ActionCode(Cfg) + Device PartName(EP2C20F484) Path("C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/") File("myArkanoid.sof") MfrSpec(OpMask(1)); + +ChainEnd; + +AlteraBegin; + ChainType(JTAG); +AlteraEnd; diff --git a/myArkanoid.done b/myArkanoid.done new file mode 100644 index 0000000..7f10ffb --- /dev/null +++ b/myArkanoid.done @@ -0,0 +1 @@ +Mon May 21 19:54:46 2012 diff --git a/myArkanoid.dpf b/myArkanoid.dpf new file mode 100644 index 0000000..abe19d9 --- /dev/null +++ b/myArkanoid.dpf @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/myArkanoid.fit.rpt b/myArkanoid.fit.rpt new file mode 100644 index 0000000..8ef6182 --- /dev/null +++ b/myArkanoid.fit.rpt @@ -0,0 +1,1699 @@ +Fitter report for myArkanoid +Mon May 21 19:54:33 2012 +Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Input Pins + 11. Output Pins + 12. I/O Bank Usage + 13. All Package Pins + 14. Output Pin Default Load For Reported TCO + 15. Fitter Resource Utilization by Entity + 16. Delay Chain Summary + 17. Pad To Core Delay Chain Fanout + 18. Control Signals + 19. Global & Other Fast Signals + 20. Non-Global High Fan-Out Signals + 21. Interconnect Usage Summary + 22. LAB Logic Elements + 23. LAB-wide Signals + 24. LAB Signals Sourced + 25. LAB Signals Sourced Out + 26. LAB Distinct Inputs + 27. Fitter Device Options + 28. Operating Settings and Conditions + 29. Estimated Delay Added for Hold Timing + 30. Fitter Messages + 31. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+------------------------------------------+ +; Fitter Status ; Successful - Mon May 21 19:54:32 2012 ; +; Quartus II Version ; 9.1 Build 222 10/21/2009 SJ Full Version ; +; Revision Name ; myArkanoid ; +; Top-level Entity Name ; TotalScheme ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Total logic elements ; 1,806 / 18,752 ( 10 % ) ; +; Total combinational functions ; 1,793 / 18,752 ( 10 % ) ; +; Dedicated logic registers ; 151 / 18,752 ( < 1 % ) ; +; Total registers ; 151 ; +; Total pins ; 55 / 315 ( 17 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Device ; EP2C20F484C7 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Use TimeQuest Timing Analyzer ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Always Enable Input Buffers ; Off ; Off ; +; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; +; Optimize Multi-Corner Timing ; Off ; Off ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; On ; On ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Global Memory Control Signals ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Merge PLLs ; On ; On ; +; Ignore PLL Mode When Merging PLLs ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Stop After Congestion Map Generation ; Off ; Off ; +; Save Intermediate Fitting Results ; Off ; Off ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Use Best Effort Settings for Compilation ; Off ; Off ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 2 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.17 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; 1 processor ; 100.0% ; +; 2 processors ; 9.1% ; ++----------------------------+-------------+ + + ++-----------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++-------------------------+---------------------+ +; Type ; Value ; ++-------------------------+---------------------+ +; Placement ; ; +; -- Requested ; 0 / 2004 ( 0.00 % ) ; +; -- Achieved ; 0 / 2004 ( 0.00 % ) ; +; ; ; +; Routing (by Connection) ; ; +; -- Requested ; 0 / 0 ( 0.00 % ) ; +; -- Achieved ; 0 / 0 ( 0.00 % ) ; ++-------------------------+---------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ + + ++--------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++----------------+---------+-------------------+-------------------------+-------------------+ +; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; ++----------------+---------+-------------------+-------------------------+-------------------+ +; Top ; 2004 ; 0 ; N/A ; Source File ; ++----------------+---------+-------------------+-------------------------+-------------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/myArkanoid.pin. + + ++-------------------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+---------------------------------+ +; Resource ; Usage ; ++---------------------------------------------+---------------------------------+ +; Total logic elements ; 1,806 / 18,752 ( 10 % ) ; +; -- Combinational with no register ; 1655 ; +; -- Register only ; 13 ; +; -- Combinational with a register ; 138 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 561 ; +; -- 3 input functions ; 452 ; +; -- <=2 input functions ; 780 ; +; -- Register only ; 13 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 1147 ; +; -- arithmetic mode ; 646 ; +; ; ; +; Total registers* ; 151 / 19,649 ( < 1 % ) ; +; -- Dedicated logic registers ; 151 / 18,752 ( < 1 % ) ; +; -- I/O registers ; 0 / 897 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 135 / 1,172 ( 12 % ) ; +; User inserted logic elements ; 0 ; +; Virtual pins ; 0 ; +; I/O pins ; 55 / 315 ( 17 % ) ; +; -- Clock pins ; 1 / 8 ( 13 % ) ; +; Global signals ; 1 ; +; M4Ks ; 0 / 52 ( 0 % ) ; +; Total block memory bits ; 0 / 239,616 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global clocks ; 1 / 16 ( 6 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 2% / 2% / 2% ; +; Peak interconnect usage (total/H/V) ; 10% / 9% / 11% ; +; Maximum fan-out node ; Arkanoid:inst|clk25MHz_~clkctrl ; +; Maximum fan-out ; 150 ; +; Highest non-global fan-out signal ; Arkanoid:inst|Add8~60 ; +; Highest non-global fan-out ; 36 ; +; Total fan-out ; 5404 ; +; Average fan-out ; 2.69 ; ++---------------------------------------------+---------------------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; ++-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; button1 ; T21 ; 6 ; 50 ; 9 ; 1 ; 5 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; button2 ; T22 ; 6 ; 50 ; 9 ; 0 ; 36 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; button3 ; R21 ; 6 ; 50 ; 10 ; 2 ; 5 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; button4 ; R22 ; 6 ; 50 ; 10 ; 1 ; 36 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; clk_50MHz ; L1 ; 2 ; 0 ; 13 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; ++-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ +; blue[0] ; A9 ; 3 ; 15 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; blue[1] ; D11 ; 3 ; 22 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; blue[2] ; A10 ; 3 ; 20 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; blue[3] ; B10 ; 3 ; 20 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; green[0] ; B8 ; 3 ; 13 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; green[1] ; C10 ; 3 ; 18 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; green[2] ; B9 ; 3 ; 15 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; green[3] ; A8 ; 3 ; 13 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; h_sync ; A11 ; 3 ; 22 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led1[0] ; J2 ; 2 ; 0 ; 18 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led1[1] ; J1 ; 2 ; 0 ; 18 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led1[2] ; H2 ; 2 ; 0 ; 19 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led1[3] ; H1 ; 2 ; 0 ; 19 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led1[4] ; F2 ; 2 ; 0 ; 20 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led1[5] ; F1 ; 2 ; 0 ; 20 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led1[6] ; E2 ; 2 ; 0 ; 20 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led2[0] ; E1 ; 2 ; 0 ; 20 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led2[1] ; H6 ; 2 ; 0 ; 21 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led2[2] ; H5 ; 2 ; 0 ; 21 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led2[3] ; H4 ; 2 ; 0 ; 21 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led2[4] ; G3 ; 2 ; 0 ; 21 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led2[5] ; D2 ; 2 ; 0 ; 22 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led2[6] ; D1 ; 2 ; 0 ; 22 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led3[0] ; G5 ; 2 ; 0 ; 22 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led3[1] ; G6 ; 2 ; 0 ; 23 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led3[2] ; C2 ; 2 ; 0 ; 23 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led3[3] ; C1 ; 2 ; 0 ; 23 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led3[4] ; E3 ; 2 ; 0 ; 24 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led3[5] ; E4 ; 2 ; 0 ; 24 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led3[6] ; D3 ; 2 ; 0 ; 25 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led4[0] ; F4 ; 2 ; 0 ; 23 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led4[1] ; D5 ; 2 ; 0 ; 24 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led4[2] ; D6 ; 2 ; 0 ; 24 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led4[3] ; J4 ; 2 ; 0 ; 18 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led4[4] ; L8 ; 2 ; 0 ; 19 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led4[5] ; F3 ; 2 ; 0 ; 22 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led4[6] ; D4 ; 2 ; 0 ; 25 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led[0] ; U22 ; 6 ; 50 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led[1] ; U21 ; 6 ; 50 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led[2] ; V22 ; 6 ; 50 ; 7 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led[3] ; V21 ; 6 ; 50 ; 6 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led[4] ; W22 ; 6 ; 50 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led[5] ; W21 ; 6 ; 50 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led[6] ; Y22 ; 6 ; 50 ; 6 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; led[7] ; Y21 ; 6 ; 50 ; 6 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; red[0] ; D9 ; 3 ; 13 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; red[1] ; C9 ; 3 ; 9 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; red[2] ; A7 ; 3 ; 11 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; red[3] ; B7 ; 3 ; 11 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; +; v_sync ; B11 ; 3 ; 22 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; ++----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 0 / 41 ( 0 % ) ; 3.3V ; -- ; +; 2 ; 31 / 33 ( 94 % ) ; 3.3V ; -- ; +; 3 ; 14 / 43 ( 33 % ) ; 3.3V ; -- ; +; 4 ; 0 / 40 ( 0 % ) ; 3.3V ; -- ; +; 5 ; 0 / 39 ( 0 % ) ; 3.3V ; -- ; +; 6 ; 13 / 36 ( 36 % ) ; 3.3V ; -- ; +; 7 ; 0 / 40 ( 0 % ) ; 3.3V ; -- ; +; 8 ; 0 / 43 ( 0 % ) ; 3.3V ; -- ; ++----------+------------------+---------------+--------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A3 ; 325 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A4 ; 324 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A5 ; 322 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A6 ; 320 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A7 ; 306 ; 3 ; red[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A8 ; 304 ; 3 ; green[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A9 ; 298 ; 3 ; blue[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A10 ; 293 ; 3 ; blue[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A11 ; 287 ; 3 ; h_sync ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A12 ; 283 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A13 ; 281 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A14 ; 279 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A15 ; 273 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A16 ; 271 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A17 ; 265 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A18 ; 251 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A19 ; 249 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A20 ; 247 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A21 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA3 ; 82 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA4 ; 85 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA5 ; 89 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA6 ; 97 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA7 ; 103 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA8 ; 111 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA9 ; 114 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA10 ; 120 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA11 ; 122 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA12 ; 128 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA13 ; 130 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA14 ; 136 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA15 ; 138 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA16 ; 140 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA17 ; 144 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA18 ; 153 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA19 ; 162 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA20 ; 164 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA22 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB3 ; 83 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB4 ; 84 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB5 ; 88 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB6 ; 96 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB7 ; 102 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB8 ; 110 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB9 ; 113 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB10 ; 119 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB11 ; 121 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB12 ; 127 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB13 ; 129 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB14 ; 135 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB15 ; 137 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB16 ; 139 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB17 ; 143 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB18 ; 152 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB19 ; 161 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB20 ; 163 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB21 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B3 ; 326 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B4 ; 323 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B5 ; 321 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B6 ; 319 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B7 ; 305 ; 3 ; red[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B8 ; 303 ; 3 ; green[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B9 ; 297 ; 3 ; green[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B10 ; 292 ; 3 ; blue[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B11 ; 286 ; 3 ; v_sync ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B12 ; 282 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; B13 ; 280 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B14 ; 278 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B15 ; 272 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B16 ; 270 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B17 ; 264 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B18 ; 250 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B19 ; 248 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B20 ; 246 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B22 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C1 ; 8 ; 2 ; led3[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; C2 ; 9 ; 2 ; led3[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; C3 ; 1 ; 2 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; C4 ; 0 ; 2 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C7 ; 315 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C9 ; 310 ; 3 ; red[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C10 ; 296 ; 3 ; green[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C12 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C13 ; 275 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C14 ; 260 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C16 ; 254 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C17 ; 245 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C18 ; 244 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C19 ; 238 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C20 ; 239 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C21 ; 236 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C22 ; 237 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D1 ; 14 ; 2 ; led2[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; D2 ; 15 ; 2 ; led2[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; D3 ; 2 ; 2 ; led3[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; D4 ; 3 ; 2 ; led4[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; D5 ; 4 ; 2 ; led4[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; D6 ; 5 ; 2 ; led4[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; D7 ; 311 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D8 ; 309 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D9 ; 302 ; 3 ; red[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D11 ; 289 ; 3 ; blue[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; D12 ; 284 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D14 ; 267 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D15 ; 259 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D16 ; 255 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D17 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D19 ; 240 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D20 ; 241 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D21 ; 229 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D22 ; 230 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E1 ; 20 ; 2 ; led2[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; E2 ; 21 ; 2 ; led1[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; E3 ; 6 ; 2 ; led3[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; E4 ; 7 ; 2 ; led3[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; E5 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E6 ; ; ; VCCA_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E7 ; 316 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E8 ; 308 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E9 ; 301 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E10 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E11 ; 288 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E12 ; 285 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; E13 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E14 ; 266 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E15 ; 256 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E16 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E17 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E18 ; 243 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E19 ; 242 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E20 ; 234 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E21 ; 227 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E22 ; 228 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F1 ; 22 ; 2 ; led1[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; F2 ; 23 ; 2 ; led1[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; F3 ; 13 ; 2 ; led4[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; F4 ; 10 ; 2 ; led4[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; F5 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F6 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F7 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F8 ; 312 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F9 ; 307 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F10 ; 295 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F11 ; 294 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F12 ; 276 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F13 ; 269 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F14 ; 268 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F15 ; 262 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F16 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F17 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F18 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; F19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F20 ; 235 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F21 ; 223 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F22 ; 224 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; G2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; G3 ; 16 ; 2 ; led2[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G5 ; 12 ; 2 ; led3[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G6 ; 11 ; 2 ; led3[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G7 ; 317 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G8 ; 313 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G11 ; 291 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G12 ; 277 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G14 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G15 ; 261 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G16 ; 252 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G17 ; 231 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G18 ; 232 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G19 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G20 ; 233 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G21 ; 221 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G22 ; 222 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H1 ; 24 ; 2 ; led1[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H2 ; 25 ; 2 ; led1[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H3 ; 27 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H4 ; 17 ; 2 ; led2[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H5 ; 18 ; 2 ; led2[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H6 ; 19 ; 2 ; led2[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H7 ; 318 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H8 ; 314 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H9 ; 300 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H10 ; 299 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H11 ; 290 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H12 ; 274 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H13 ; 263 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H14 ; 257 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H15 ; 253 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H16 ; 219 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H17 ; 226 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H18 ; 225 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H19 ; 214 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; H22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J1 ; 29 ; 2 ; led1[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J2 ; 30 ; 2 ; led1[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J4 ; 28 ; 2 ; led4[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J7 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; J8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J9 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J14 ; 258 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; J15 ; 220 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J16 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; J17 ; 218 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J18 ; 217 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J19 ; 216 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J20 ; 213 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J21 ; 211 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J22 ; 212 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K1 ; 37 ; 2 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; K2 ; 32 ; 2 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; 36 ; 2 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ; +; K5 ; 31 ; 2 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; K6 ; 33 ; 2 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; K7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K20 ; 215 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K21 ; 209 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K22 ; 210 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L1 ; 38 ; 2 ; clk_50MHz ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; L2 ; 39 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; L3 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; L4 ; 40 ; 2 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; L5 ; 34 ; 2 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; L6 ; 35 ; 2 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; +; L7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L8 ; 26 ; 2 ; led4[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L18 ; 208 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L19 ; 207 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L20 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; L21 ; 205 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; L22 ; 206 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M1 ; 41 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M2 ; 42 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M3 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; M4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M5 ; 43 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M6 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M17 ; 198 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; M18 ; 202 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M19 ; 201 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M20 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; M21 ; 203 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M22 ; 204 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; N1 ; 45 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N2 ; 46 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N3 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N4 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; N6 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; N9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N15 ; 194 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N17 ; 197 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; N18 ; 196 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N20 ; 195 ; 6 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; N21 ; 199 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N22 ; 200 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P1 ; 47 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P2 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P3 ; 50 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P5 ; 55 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P6 ; 56 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P8 ; 95 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; P9 ; 94 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; P10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P14 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P15 ; 193 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P16 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P17 ; 186 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P18 ; 187 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P19 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P20 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; R1 ; 57 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R2 ; 58 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; R5 ; 63 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R6 ; 64 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R7 ; 54 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R8 ; 53 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R9 ; 109 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R10 ; 108 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R11 ; 116 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R12 ; 134 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R13 ; 145 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R14 ; 150 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R15 ; 151 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R16 ; 155 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R17 ; 177 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R18 ; 184 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R19 ; 185 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R20 ; 192 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R21 ; 190 ; 6 ; button3 ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; R22 ; 191 ; 6 ; button4 ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; T1 ; 59 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T2 ; 60 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T3 ; 69 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T5 ; 67 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T6 ; 68 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T7 ; 91 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T8 ; 90 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T11 ; 115 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T12 ; 131 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T14 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T15 ; 147 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T16 ; 156 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T17 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; T18 ; 171 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T19 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T21 ; 188 ; 6 ; button1 ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; T22 ; 189 ; 6 ; button2 ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; U1 ; 61 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U2 ; 62 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U3 ; 70 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U4 ; 80 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; U6 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U7 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U8 ; 92 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U9 ; 106 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U10 ; 107 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U11 ; 123 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; U12 ; 124 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; U13 ; 132 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U14 ; 146 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U15 ; 157 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U16 ; ; ; VCCA_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U18 ; 170 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U19 ; 172 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U20 ; 176 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U21 ; 182 ; 6 ; led[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; U22 ; 183 ; 6 ; led[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; V1 ; 65 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V2 ; 66 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V4 ; 81 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V7 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; V8 ; 98 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V9 ; 101 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V10 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V11 ; 118 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V12 ; 126 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; V13 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V14 ; 142 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V15 ; 158 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V16 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; V17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V18 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; V19 ; 166 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V20 ; 173 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V21 ; 180 ; 6 ; led[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; V22 ; 181 ; 6 ; led[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; W1 ; 71 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W2 ; 72 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W3 ; 75 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W4 ; 76 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W5 ; 79 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W6 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W7 ; 99 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W8 ; 100 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W9 ; 105 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W11 ; 117 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W12 ; 125 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W14 ; 141 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W15 ; 149 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W16 ; 160 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W17 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W20 ; 167 ; 6 ; ~LVDS91p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; W21 ; 174 ; 6 ; led[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; W22 ; 175 ; 6 ; led[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; Y1 ; 73 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y2 ; 74 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y3 ; 77 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y4 ; 78 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y5 ; 86 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y6 ; 87 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y7 ; 93 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y9 ; 104 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y10 ; 112 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; Y12 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; Y13 ; 133 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y14 ; 148 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 154 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y17 ; 159 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y18 ; 165 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y19 ; 168 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y20 ; 169 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y21 ; 178 ; 6 ; led[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; Y22 ; 179 ; 6 ; led[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------------------------------------+ +; Output Pin Default Load For Reported TCO ; ++----------------------------------+-------+------------------------------------+ +; I/O Standard ; Load ; Termination Resistance ; ++----------------------------------+-------+------------------------------------+ +; 3.3-V LVTTL ; 0 pF ; Not Available ; +; 3.3-V LVCMOS ; 0 pF ; Not Available ; +; 2.5 V ; 0 pF ; Not Available ; +; 1.8 V ; 0 pF ; Not Available ; +; 1.5 V ; 0 pF ; Not Available ; +; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; +; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ; +; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ; +; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; +; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; +; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; +; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; +; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; +; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; +; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; +; LVDS ; 0 pF ; 100 Ohm (Differential) ; +; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; +; RSDS ; 0 pF ; 100 Ohm (Differential) ; +; Simple RSDS ; 0 pF ; Not Available ; +; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; ++----------------------------------+-------+------------------------------------+ +Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------+--------------+ +; |TotalScheme ; 1806 (0) ; 151 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 55 ; 0 ; 1655 (0) ; 13 (0) ; 138 (0) ; |TotalScheme ; work ; +; |Arkanoid:inst| ; 1806 (779) ; 151 (151) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1655 (628) ; 13 (13) ; 138 (137) ; |TotalScheme|Arkanoid:inst ; ; +; |lpm_divide:Div0| ; 475 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 475 (0) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0 ; ; +; |lpm_divide_8so:auto_generated| ; 475 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 475 (0) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated ; ; +; |abs_divider_lbg:divider| ; 475 (10) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 475 (10) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider ; ; +; |alt_u_div_m2f:divider| ; 433 (433) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 433 (433) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider ; ; +; |lpm_abs_0s9:my_abs_num| ; 32 (32) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (32) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num ; ; +; |lpm_divide:Div1| ; 553 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 552 (0) ; 0 (0) ; 1 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1 ; ; +; |lpm_divide_8so:auto_generated| ; 553 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 552 (0) ; 0 (0) ; 1 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated ; ; +; |abs_divider_lbg:divider| ; 553 (10) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 552 (10) ; 0 (0) ; 1 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider ; ; +; |alt_u_div_m2f:divider| ; 511 (511) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 511 (511) ; 0 (0) ; 0 (0) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider ; ; +; |lpm_abs_0s9:my_abs_num| ; 32 (32) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 (31) ; 0 (0) ; 1 (1) ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num ; ; ++------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++-----------+----------+---------------+---------------+-----------------------+-----+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; ++-----------+----------+---------------+---------------+-----------------------+-----+ +; h_sync ; Output ; -- ; -- ; -- ; -- ; +; v_sync ; Output ; -- ; -- ; -- ; -- ; +; blue[3] ; Output ; -- ; -- ; -- ; -- ; +; blue[2] ; Output ; -- ; -- ; -- ; -- ; +; blue[1] ; Output ; -- ; -- ; -- ; -- ; +; blue[0] ; Output ; -- ; -- ; -- ; -- ; +; green[3] ; Output ; -- ; -- ; -- ; -- ; +; green[2] ; Output ; -- ; -- ; -- ; -- ; +; green[1] ; Output ; -- ; -- ; -- ; -- ; +; green[0] ; Output ; -- ; -- ; -- ; -- ; +; led[7] ; Output ; -- ; -- ; -- ; -- ; +; led[6] ; Output ; -- ; -- ; -- ; -- ; +; led[5] ; Output ; -- ; -- ; -- ; -- ; +; led[4] ; Output ; -- ; -- ; -- ; -- ; +; led[3] ; Output ; -- ; -- ; -- ; -- ; +; led[2] ; Output ; -- ; -- ; -- ; -- ; +; led[1] ; Output ; -- ; -- ; -- ; -- ; +; led[0] ; Output ; -- ; -- ; -- ; -- ; +; led1[6] ; Output ; -- ; -- ; -- ; -- ; +; led1[5] ; Output ; -- ; -- ; -- ; -- ; +; led1[4] ; Output ; -- ; -- ; -- ; -- ; +; led1[3] ; Output ; -- ; -- ; -- ; -- ; +; led1[2] ; Output ; -- ; -- ; -- ; -- ; +; led1[1] ; Output ; -- ; -- ; -- ; -- ; +; led1[0] ; Output ; -- ; -- ; -- ; -- ; +; led2[6] ; Output ; -- ; -- ; -- ; -- ; +; led2[5] ; Output ; -- ; -- ; -- ; -- ; +; led2[4] ; Output ; -- ; -- ; -- ; -- ; +; led2[3] ; Output ; -- ; -- ; -- ; -- ; +; led2[2] ; Output ; -- ; -- ; -- ; -- ; +; led2[1] ; Output ; -- ; -- ; -- ; -- ; +; led2[0] ; Output ; -- ; -- ; -- ; -- ; +; led3[6] ; Output ; -- ; -- ; -- ; -- ; +; led3[5] ; Output ; -- ; -- ; -- ; -- ; +; led3[4] ; Output ; -- ; -- ; -- ; -- ; +; led3[3] ; Output ; -- ; -- ; -- ; -- ; +; led3[2] ; Output ; -- ; -- ; -- ; -- ; +; led3[1] ; Output ; -- ; -- ; -- ; -- ; +; led3[0] ; Output ; -- ; -- ; -- ; -- ; +; led4[6] ; Output ; -- ; -- ; -- ; -- ; +; led4[5] ; Output ; -- ; -- ; -- ; -- ; +; led4[4] ; Output ; -- ; -- ; -- ; -- ; +; led4[3] ; Output ; -- ; -- ; -- ; -- ; +; led4[2] ; Output ; -- ; -- ; -- ; -- ; +; led4[1] ; Output ; -- ; -- ; -- ; -- ; +; led4[0] ; Output ; -- ; -- ; -- ; -- ; +; red[3] ; Output ; -- ; -- ; -- ; -- ; +; red[2] ; Output ; -- ; -- ; -- ; -- ; +; red[1] ; Output ; -- ; -- ; -- ; -- ; +; red[0] ; Output ; -- ; -- ; -- ; -- ; +; button3 ; Input ; (6) 4358 ps ; (6) 4358 ps ; -- ; -- ; +; button4 ; Input ; (6) 4358 ps ; (6) 4358 ps ; -- ; -- ; +; button1 ; Input ; (6) 4358 ps ; (6) 4358 ps ; -- ; -- ; +; button2 ; Input ; (6) 4358 ps ; (6) 4358 ps ; -- ; -- ; +; clk_50MHz ; Input ; (0) 325 ps ; (0) 325 ps ; -- ; -- ; ++-----------+----------+---------------+---------------+-----------------------+-----+ + + ++-------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-------------------------------------------+-------------------+---------+ +; button3 ; ; ; +; - Arkanoid:inst|button3_state ; 0 ; 6 ; +; - Arkanoid:inst|platform2_position~0 ; 0 ; 6 ; +; - Arkanoid:inst|always3~95 ; 0 ; 6 ; +; - Arkanoid:inst|led_[2]~feeder ; 0 ; 6 ; +; - Arkanoid:inst|led_[3]~feeder ; 0 ; 6 ; +; button4 ; ; ; +; - Arkanoid:inst|led_[0] ; 1 ; 6 ; +; - Arkanoid:inst|led_[1] ; 1 ; 6 ; +; - Arkanoid:inst|button4_state ; 1 ; 6 ; +; - Arkanoid:inst|Add5~20 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~21 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~22 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~25 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~28 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~31 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~34 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~37 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~40 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~43 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~46 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~49 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~52 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~55 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~58 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~61 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~64 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~67 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~86 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~87 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~88 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~89 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~90 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~91 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~92 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~93 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~94 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~97 ; 1 ; 6 ; +; - Arkanoid:inst|always3~3 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~100 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~101 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~102 ; 1 ; 6 ; +; - Arkanoid:inst|Add5~103 ; 1 ; 6 ; +; button1 ; ; ; +; - Arkanoid:inst|button1_state ; 1 ; 6 ; +; - Arkanoid:inst|led_[6] ; 1 ; 6 ; +; - Arkanoid:inst|led_[7] ; 1 ; 6 ; +; - Arkanoid:inst|platform1_position~0 ; 1 ; 6 ; +; - Arkanoid:inst|always3~94 ; 1 ; 6 ; +; button2 ; ; ; +; - Arkanoid:inst|led_[4] ; 0 ; 6 ; +; - Arkanoid:inst|led_[5] ; 0 ; 6 ; +; - Arkanoid:inst|button2_state ; 0 ; 6 ; +; - Arkanoid:inst|Add3~70 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~71 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~72 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~73 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~74 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~75 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~76 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~77 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~78 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~79 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~80 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~81 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~82 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~83 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~84 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~85 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~86 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~87 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~88 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~89 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~90 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~91 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~92 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~93 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~94 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~95 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~96 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~97 ; 0 ; 6 ; +; - Arkanoid:inst|always3~51 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~100 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~101 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~102 ; 0 ; 6 ; +; - Arkanoid:inst|Add3~103 ; 0 ; 6 ; +; clk_50MHz ; ; ; ++-------------------------------------------+-------------------+---------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++--------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++--------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; Arkanoid:inst|Equal1~10 ; LCCOMB_X18_Y11_N6 ; 32 ; Sync. clear ; no ; -- ; -- ; -- ; +; Arkanoid:inst|always3~3 ; LCCOMB_X34_Y17_N26 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; Arkanoid:inst|always3~51 ; LCCOMB_X29_Y13_N22 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; Arkanoid:inst|always3~94 ; LCCOMB_X34_Y12_N14 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; Arkanoid:inst|always3~95 ; LCCOMB_X34_Y21_N14 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; Arkanoid:inst|clk25MHz_ ; LCFF_X1_Y13_N29 ; 150 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ; +; clk_50MHz ; PIN_L1 ; 1 ; Clock ; no ; -- ; -- ; -- ; ++--------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++-------------------------+-----------------+---------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++-------------------------+-----------------+---------+----------------------+------------------+---------------------------+ +; Arkanoid:inst|clk25MHz_ ; LCFF_X1_Y13_N29 ; 150 ; Global Clock ; GCLK2 ; -- ; ++-------------------------+-----------------+---------+----------------------+------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Non-Global High Fan-Out Signals ; ++---------------------------------------------------------------------------------------------------------------------------------------+---------+ +; Name ; Fan-Out ; ++---------------------------------------------------------------------------------------------------------------------------------------+---------+ +; button2 ; 36 ; +; button4 ; 36 ; +; Arkanoid:inst|Add9~60 ; 36 ; +; Arkanoid:inst|Add8~60 ; 36 ; +; Arkanoid:inst|Add5~103 ; 34 ; +; Arkanoid:inst|Add3~102 ; 33 ; +; Arkanoid:inst|Add3~101 ; 33 ; +; Arkanoid:inst|button2_state ; 33 ; +; Arkanoid:inst|button4_state ; 33 ; +; Arkanoid:inst|platform1_position~0 ; 32 ; +; Arkanoid:inst|platform2_position~0 ; 32 ; +; Arkanoid:inst|Equal1~10 ; 32 ; +; Arkanoid:inst|Add6~56 ; 32 ; +; Arkanoid:inst|Add7~56 ; 31 ; +; Arkanoid:inst|Add7~0 ; 30 ; +; Arkanoid:inst|Add6~0 ; 29 ; +; Arkanoid:inst|Add3~100 ; 26 ; +; Arkanoid:inst|Add5~102 ; 25 ; +; Arkanoid:inst|Add3~97 ; 23 ; +; Arkanoid:inst|Add5~22 ; 20 ; +; Arkanoid:inst|Add3~96 ; 19 ; +; Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|quotient[0]~4 ; 19 ; +; Arkanoid:inst|Add5~100 ; 18 ; +; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[7]~10 ; 18 ; +; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_28_result_int[7]~10 ; 18 ; +; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[7]~10 ; 18 ; +; Arkanoid:inst|Add5~21 ; 17 ; +; Arkanoid:inst|LessThan31~9 ; 16 ; +; Arkanoid:inst|LessThan29~10 ; 16 ; +; Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|quotient[1]~3 ; 16 ; +; Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|quotient[2]~2 ; 16 ; +; Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|quotient[3]~1 ; 16 ; +; Arkanoid:inst|Add7~2 ; 16 ; +; Arkanoid:inst|Add6~2 ; 16 ; +; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_26_result_int[7]~10 ; 16 ; +; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[7]~10 ; 16 ; +; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_24_result_int[7]~10 ; 16 ; +; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[7]~10 ; 16 ; +; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_22_result_int[7]~10 ; 16 ; +; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[7]~10 ; 16 ; +; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[7]~10 ; 16 ; +; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_19_result_int[7]~10 ; 16 ; +; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_18_result_int[7]~10 ; 16 ; +; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[7]~10 ; 16 ; +; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[7]~10 ; 16 ; +; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[7]~10 ; 16 ; +; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[7]~10 ; 16 ; +; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_13_result_int[7]~10 ; 16 ; +; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_12_result_int[7]~10 ; 16 ; +; Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_11_result_int[7]~10 ; 16 ; ++---------------------------------------------------------------------------------------------------------------------------------------+---------+ + + ++-----------------------------------------------------+ +; Interconnect Usage Summary ; ++----------------------------+------------------------+ +; Interconnect Resource Type ; Usage ; ++----------------------------+------------------------+ +; Block interconnects ; 2,288 / 54,004 ( 4 % ) ; +; C16 interconnects ; 6 / 2,100 ( < 1 % ) ; +; C4 interconnects ; 1,077 / 36,000 ( 3 % ) ; +; Direct links ; 690 / 54,004 ( 1 % ) ; +; Global clocks ; 1 / 16 ( 6 % ) ; +; Local interconnects ; 583 / 18,752 ( 3 % ) ; +; R24 interconnects ; 24 / 1,900 ( 1 % ) ; +; R4 interconnects ; 1,279 / 46,920 ( 3 % ) ; ++----------------------------+------------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+-------------------------------+ +; Number of Logic Elements (Average = 13.38) ; Number of LABs (Total = 135) ; ++---------------------------------------------+-------------------------------+ +; 1 ; 13 ; +; 2 ; 3 ; +; 3 ; 3 ; +; 4 ; 1 ; +; 5 ; 3 ; +; 6 ; 2 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 1 ; +; 10 ; 0 ; +; 11 ; 1 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 1 ; +; 16 ; 107 ; ++---------------------------------------------+-------------------------------+ + + ++--------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+-------------------------------+ +; LAB-wide Signals (Average = 0.19) ; Number of LABs (Total = 135) ; ++------------------------------------+-------------------------------+ +; 1 Clock ; 21 ; +; 1 Clock enable ; 2 ; +; 1 Sync. clear ; 3 ; ++------------------------------------+-------------------------------+ + + ++------------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+-------------------------------+ +; Number of Signals Sourced (Average = 13.96) ; Number of LABs (Total = 135) ; ++----------------------------------------------+-------------------------------+ +; 0 ; 0 ; +; 1 ; 11 ; +; 2 ; 5 ; +; 3 ; 3 ; +; 4 ; 1 ; +; 5 ; 2 ; +; 6 ; 2 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 1 ; +; 10 ; 0 ; +; 11 ; 3 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 18 ; +; 15 ; 20 ; +; 16 ; 53 ; +; 17 ; 2 ; +; 18 ; 0 ; +; 19 ; 1 ; +; 20 ; 0 ; +; 21 ; 2 ; +; 22 ; 1 ; +; 23 ; 1 ; +; 24 ; 3 ; +; 25 ; 2 ; +; 26 ; 0 ; +; 27 ; 0 ; +; 28 ; 0 ; +; 29 ; 0 ; +; 30 ; 1 ; +; 31 ; 1 ; +; 32 ; 2 ; ++----------------------------------------------+-------------------------------+ + + ++----------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++--------------------------------------------------+-------------------------------+ +; Number of Signals Sourced Out (Average = 10.92) ; Number of LABs (Total = 135) ; ++--------------------------------------------------+-------------------------------+ +; 0 ; 0 ; +; 1 ; 16 ; +; 2 ; 5 ; +; 3 ; 4 ; +; 4 ; 6 ; +; 5 ; 3 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 2 ; +; 9 ; 15 ; +; 10 ; 5 ; +; 11 ; 20 ; +; 12 ; 6 ; +; 13 ; 5 ; +; 14 ; 5 ; +; 15 ; 1 ; +; 16 ; 30 ; +; 17 ; 1 ; +; 18 ; 0 ; +; 19 ; 2 ; +; 20 ; 1 ; +; 21 ; 1 ; +; 22 ; 1 ; +; 23 ; 0 ; +; 24 ; 1 ; +; 25 ; 0 ; +; 26 ; 0 ; +; 27 ; 0 ; +; 28 ; 0 ; +; 29 ; 0 ; +; 30 ; 1 ; +; 31 ; 1 ; +; 32 ; 2 ; ++--------------------------------------------------+-------------------------------+ + + ++------------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+-------------------------------+ +; Number of Distinct Inputs (Average = 15.07) ; Number of LABs (Total = 135) ; ++----------------------------------------------+-------------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 4 ; +; 3 ; 6 ; +; 4 ; 7 ; +; 5 ; 3 ; +; 6 ; 1 ; +; 7 ; 2 ; +; 8 ; 1 ; +; 9 ; 0 ; +; 10 ; 1 ; +; 11 ; 3 ; +; 12 ; 3 ; +; 13 ; 10 ; +; 14 ; 14 ; +; 15 ; 4 ; +; 16 ; 11 ; +; 17 ; 20 ; +; 18 ; 4 ; +; 19 ; 7 ; +; 20 ; 15 ; +; 21 ; 3 ; +; 22 ; 2 ; +; 23 ; 2 ; +; 24 ; 3 ; +; 25 ; 1 ; +; 26 ; 0 ; +; 27 ; 2 ; +; 28 ; 2 ; +; 29 ; 0 ; +; 30 ; 3 ; ++----------------------------------------------+-------------------------------+ + + ++-------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+--------------------------+ +; Option ; Setting ; ++----------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; nCEO ; As output driving ground ; +; ASDO,nCSO ; As input tri-stated ; +; Reserve all unused pins ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++----------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing ; ++-----------------+----------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++-----------------+----------------------+-------------------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Info: ******************************************************************* +Info: Running Quartus II Fitter + Info: Version 9.1 Build 222 10/21/2009 SJ Full Version + Info: Processing started: Mon May 21 19:54:21 2012 +Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid +Info: Parallel compilation is enabled and will use 2 of the 2 processors detected +Info: Selected device EP2C20F484C7 for design "myArkanoid" +Info: Low junction temperature is 0 degrees C +Info: High junction temperature is 85 degrees C +Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info: Device EP2C15AF484C7 is compatible + Info: Device EP2C35F484C7 is compatible + Info: Device EP2C50F484C7 is compatible +Info: Fitter converted 3 user pins into dedicated programming pins + Info: Pin ~ASDO~ is reserved at location C4 + Info: Pin ~nCSO~ is reserved at location C3 + Info: Pin ~LVDS91p/nCEO~ is reserved at location W20 +Info: Timing-driven compilation is using the Classic Timing Analyzer +Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time. +Info: Automatically promoted node Arkanoid:inst|clk25MHz_ + Info: Automatically promoted destinations to use location or clock signal Global Clock + Info: Following destination nodes may be non-global or may not use global or regional clocks + Info: Destination node Arkanoid:inst|clk25MHz_~0 +Info: Starting register packing +Info: Finished register packing + Extra Info: No registers were packed into other blocks +Info: Fitter preparation operations ending: elapsed time is 00:00:01 +Info: Fitter placement preparation operations beginning +Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info: Fitter placement operations beginning +Info: Fitter placement was successful +Info: Fitter placement operations ending: elapsed time is 00:00:01 +Info: Estimated most critical path is register to register delay of 110.730 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X14_Y11; Fanout = 6; REG Node = 'Arkanoid:inst|h_counter[1]' + Info: 2: + IC(0.781 ns) + CELL(0.517 ns) = 1.298 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~1' + Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.378 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~3' + Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.458 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~5' + Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.538 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~7' + Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 1.618 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~9' + Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 1.698 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~11' + Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 1.778 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~13' + Info: 9: + IC(0.000 ns) + CELL(0.080 ns) = 1.858 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~15' + Info: 10: + IC(0.000 ns) + CELL(0.080 ns) = 1.938 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~17' + Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 2.018 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~19' + Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 2.098 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~21' + Info: 13: + IC(0.000 ns) + CELL(0.080 ns) = 2.178 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~23' + Info: 14: + IC(0.000 ns) + CELL(0.080 ns) = 2.258 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~25' + Info: 15: + IC(0.000 ns) + CELL(0.080 ns) = 2.338 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~27' + Info: 16: + IC(0.000 ns) + CELL(0.080 ns) = 2.418 ns; Loc. = LAB_X15_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~29' + Info: 17: + IC(0.098 ns) + CELL(0.080 ns) = 2.596 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~31' + Info: 18: + IC(0.000 ns) + CELL(0.080 ns) = 2.676 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~33' + Info: 19: + IC(0.000 ns) + CELL(0.080 ns) = 2.756 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~35' + Info: 20: + IC(0.000 ns) + CELL(0.080 ns) = 2.836 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~37' + Info: 21: + IC(0.000 ns) + CELL(0.080 ns) = 2.916 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~39' + Info: 22: + IC(0.000 ns) + CELL(0.080 ns) = 2.996 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~41' + Info: 23: + IC(0.000 ns) + CELL(0.080 ns) = 3.076 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~43' + Info: 24: + IC(0.000 ns) + CELL(0.080 ns) = 3.156 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~45' + Info: 25: + IC(0.000 ns) + CELL(0.080 ns) = 3.236 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~47' + Info: 26: + IC(0.000 ns) + CELL(0.080 ns) = 3.316 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~49' + Info: 27: + IC(0.000 ns) + CELL(0.080 ns) = 3.396 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~51' + Info: 28: + IC(0.000 ns) + CELL(0.080 ns) = 3.476 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~53' + Info: 29: + IC(0.000 ns) + CELL(0.080 ns) = 3.556 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~55' + Info: 30: + IC(0.000 ns) + CELL(0.080 ns) = 3.636 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~57' + Info: 31: + IC(0.000 ns) + CELL(0.080 ns) = 3.716 ns; Loc. = LAB_X15_Y10; Fanout = 1; COMB Node = 'Arkanoid:inst|Add8~59' + Info: 32: + IC(0.000 ns) + CELL(0.458 ns) = 4.174 ns; Loc. = LAB_X15_Y10; Fanout = 65; COMB Node = 'Arkanoid:inst|Add8~60' + Info: 33: + IC(1.060 ns) + CELL(0.517 ns) = 5.751 ns; Loc. = LAB_X16_Y11; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~1' + Info: 34: + IC(0.000 ns) + CELL(0.080 ns) = 5.831 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~3' + Info: 35: + IC(0.000 ns) + CELL(0.080 ns) = 5.911 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~5' + Info: 36: + IC(0.000 ns) + CELL(0.080 ns) = 5.991 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7' + Info: 37: + IC(0.000 ns) + CELL(0.080 ns) = 6.071 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9' + Info: 38: + IC(0.000 ns) + CELL(0.080 ns) = 6.151 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11' + Info: 39: + IC(0.000 ns) + CELL(0.080 ns) = 6.231 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13' + Info: 40: + IC(0.000 ns) + CELL(0.080 ns) = 6.311 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15' + Info: 41: + IC(0.000 ns) + CELL(0.080 ns) = 6.391 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17' + Info: 42: + IC(0.000 ns) + CELL(0.080 ns) = 6.471 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19' + Info: 43: + IC(0.000 ns) + CELL(0.080 ns) = 6.551 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21' + Info: 44: + IC(0.000 ns) + CELL(0.080 ns) = 6.631 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23' + Info: 45: + IC(0.000 ns) + CELL(0.080 ns) = 6.711 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25' + Info: 46: + IC(0.000 ns) + CELL(0.080 ns) = 6.791 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27' + Info: 47: + IC(0.000 ns) + CELL(0.080 ns) = 6.871 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29' + Info: 48: + IC(0.000 ns) + CELL(0.080 ns) = 6.951 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31' + Info: 49: + IC(0.098 ns) + CELL(0.080 ns) = 7.129 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33' + Info: 50: + IC(0.000 ns) + CELL(0.080 ns) = 7.209 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35' + Info: 51: + IC(0.000 ns) + CELL(0.080 ns) = 7.289 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37' + Info: 52: + IC(0.000 ns) + CELL(0.080 ns) = 7.369 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39' + Info: 53: + IC(0.000 ns) + CELL(0.080 ns) = 7.449 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41' + Info: 54: + IC(0.000 ns) + CELL(0.080 ns) = 7.529 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43' + Info: 55: + IC(0.000 ns) + CELL(0.080 ns) = 7.609 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45' + Info: 56: + IC(0.000 ns) + CELL(0.080 ns) = 7.689 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47' + Info: 57: + IC(0.000 ns) + CELL(0.080 ns) = 7.769 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49' + Info: 58: + IC(0.000 ns) + CELL(0.080 ns) = 7.849 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51' + Info: 59: + IC(0.000 ns) + CELL(0.080 ns) = 7.929 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53' + Info: 60: + IC(0.000 ns) + CELL(0.080 ns) = 8.009 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55' + Info: 61: + IC(0.000 ns) + CELL(0.080 ns) = 8.089 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~57' + Info: 62: + IC(0.000 ns) + CELL(0.458 ns) = 8.547 ns; Loc. = LAB_X16_Y10; Fanout = 4; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~58' + Info: 63: + IC(1.405 ns) + CELL(0.517 ns) = 10.469 ns; Loc. = LAB_X16_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_4_result_int[2]~1' + Info: 64: + IC(0.000 ns) + CELL(0.080 ns) = 10.549 ns; Loc. = LAB_X16_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_4_result_int[3]~3' + Info: 65: + IC(0.000 ns) + CELL(0.080 ns) = 10.629 ns; Loc. = LAB_X16_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_4_result_int[4]~5' + Info: 66: + IC(0.000 ns) + CELL(0.458 ns) = 11.087 ns; Loc. = LAB_X16_Y15; Fanout = 11; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_4_result_int[5]~6' + Info: 67: + IC(1.037 ns) + CELL(0.177 ns) = 12.301 ns; Loc. = LAB_X18_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[29]~435' + Info: 68: + IC(1.037 ns) + CELL(0.495 ns) = 13.833 ns; Loc. = LAB_X16_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_5_result_int[2]~1' + Info: 69: + IC(0.000 ns) + CELL(0.080 ns) = 13.913 ns; Loc. = LAB_X16_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_5_result_int[3]~3' + Info: 70: + IC(0.000 ns) + CELL(0.080 ns) = 13.993 ns; Loc. = LAB_X16_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_5_result_int[4]~5' + Info: 71: + IC(0.000 ns) + CELL(0.080 ns) = 14.073 ns; Loc. = LAB_X16_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_5_result_int[5]~7' + Info: 72: + IC(0.000 ns) + CELL(0.458 ns) = 14.531 ns; Loc. = LAB_X16_Y15; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_5_result_int[6]~8' + Info: 73: + IC(0.693 ns) + CELL(0.521 ns) = 15.745 ns; Loc. = LAB_X18_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[36]~441' + Info: 74: + IC(0.709 ns) + CELL(0.517 ns) = 16.971 ns; Loc. = LAB_X19_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[2]~1' + Info: 75: + IC(0.000 ns) + CELL(0.080 ns) = 17.051 ns; Loc. = LAB_X19_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[3]~3' + Info: 76: + IC(0.000 ns) + CELL(0.080 ns) = 17.131 ns; Loc. = LAB_X19_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[4]~5' + Info: 77: + IC(0.000 ns) + CELL(0.080 ns) = 17.211 ns; Loc. = LAB_X19_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[5]~7' + Info: 78: + IC(0.000 ns) + CELL(0.080 ns) = 17.291 ns; Loc. = LAB_X19_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[6]~9' + Info: 79: + IC(0.000 ns) + CELL(0.458 ns) = 17.749 ns; Loc. = LAB_X19_Y15; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[7]~10' + Info: 80: + IC(0.745 ns) + CELL(0.521 ns) = 19.015 ns; Loc. = LAB_X20_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[43]~447' + Info: 81: + IC(1.066 ns) + CELL(0.517 ns) = 20.598 ns; Loc. = LAB_X19_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[2]~1' + Info: 82: + IC(0.000 ns) + CELL(0.080 ns) = 20.678 ns; Loc. = LAB_X19_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[3]~3' + Info: 83: + IC(0.000 ns) + CELL(0.080 ns) = 20.758 ns; Loc. = LAB_X19_Y15; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[4]~5' + Info: 84: + IC(0.000 ns) + CELL(0.080 ns) = 20.838 ns; Loc. = LAB_X19_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[5]~7' + Info: 85: + IC(0.000 ns) + CELL(0.080 ns) = 20.918 ns; Loc. = LAB_X19_Y15; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[6]~9' + Info: 86: + IC(0.000 ns) + CELL(0.458 ns) = 21.376 ns; Loc. = LAB_X19_Y15; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[7]~10' + Info: 87: + IC(0.745 ns) + CELL(0.521 ns) = 22.642 ns; Loc. = LAB_X20_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[50]~453' + Info: 88: + IC(0.709 ns) + CELL(0.517 ns) = 23.868 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[2]~1' + Info: 89: + IC(0.000 ns) + CELL(0.080 ns) = 23.948 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[3]~3' + Info: 90: + IC(0.000 ns) + CELL(0.080 ns) = 24.028 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[4]~5' + Info: 91: + IC(0.000 ns) + CELL(0.080 ns) = 24.108 ns; Loc. = LAB_X19_Y18; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[5]~7' + Info: 92: + IC(0.000 ns) + CELL(0.080 ns) = 24.188 ns; Loc. = LAB_X19_Y18; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[6]~9' + Info: 93: + IC(0.000 ns) + CELL(0.458 ns) = 24.646 ns; Loc. = LAB_X19_Y18; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[7]~10' + Info: 94: + IC(0.745 ns) + CELL(0.521 ns) = 25.912 ns; Loc. = LAB_X19_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[57]~459' + Info: 95: + IC(1.066 ns) + CELL(0.517 ns) = 27.495 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[2]~1' + Info: 96: + IC(0.000 ns) + CELL(0.080 ns) = 27.575 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[3]~3' + Info: 97: + IC(0.000 ns) + CELL(0.080 ns) = 27.655 ns; Loc. = LAB_X19_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[4]~5' + Info: 98: + IC(0.000 ns) + CELL(0.080 ns) = 27.735 ns; Loc. = LAB_X19_Y18; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[5]~7' + Info: 99: + IC(0.000 ns) + CELL(0.080 ns) = 27.815 ns; Loc. = LAB_X19_Y18; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[6]~9' + Info: 100: + IC(0.000 ns) + CELL(0.458 ns) = 28.273 ns; Loc. = LAB_X19_Y18; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[7]~10' + Info: 101: + IC(0.745 ns) + CELL(0.521 ns) = 29.539 ns; Loc. = LAB_X19_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[64]~465' + Info: 102: + IC(0.709 ns) + CELL(0.517 ns) = 30.765 ns; Loc. = LAB_X20_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_10_result_int[2]~1' + Info: 103: + IC(0.000 ns) + CELL(0.080 ns) = 30.845 ns; Loc. = LAB_X20_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_10_result_int[3]~3' + Info: 104: + IC(0.000 ns) + CELL(0.080 ns) = 30.925 ns; Loc. = LAB_X20_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_10_result_int[4]~5' + Info: 105: + IC(0.000 ns) + CELL(0.080 ns) = 31.005 ns; Loc. = LAB_X20_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_10_result_int[5]~7' + Info: 106: + IC(0.000 ns) + CELL(0.080 ns) = 31.085 ns; Loc. = LAB_X20_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_10_result_int[6]~9' + Info: 107: + IC(0.000 ns) + CELL(0.458 ns) = 31.543 ns; Loc. = LAB_X20_Y22; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_10_result_int[7]~10' + Info: 108: + IC(0.729 ns) + CELL(0.521 ns) = 32.793 ns; Loc. = LAB_X20_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[71]~471' + Info: 109: + IC(1.050 ns) + CELL(0.517 ns) = 34.360 ns; Loc. = LAB_X20_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_11_result_int[2]~1' + Info: 110: + IC(0.000 ns) + CELL(0.080 ns) = 34.440 ns; Loc. = LAB_X20_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_11_result_int[3]~3' + Info: 111: + IC(0.000 ns) + CELL(0.080 ns) = 34.520 ns; Loc. = LAB_X20_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_11_result_int[4]~5' + Info: 112: + IC(0.000 ns) + CELL(0.080 ns) = 34.600 ns; Loc. = LAB_X20_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_11_result_int[5]~7' + Info: 113: + IC(0.000 ns) + CELL(0.080 ns) = 34.680 ns; Loc. = LAB_X20_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_11_result_int[6]~9' + Info: 114: + IC(0.000 ns) + CELL(0.458 ns) = 35.138 ns; Loc. = LAB_X20_Y22; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_11_result_int[7]~10' + Info: 115: + IC(0.729 ns) + CELL(0.521 ns) = 36.388 ns; Loc. = LAB_X20_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[78]~477' + Info: 116: + IC(0.709 ns) + CELL(0.517 ns) = 37.614 ns; Loc. = LAB_X19_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_12_result_int[2]~1' + Info: 117: + IC(0.000 ns) + CELL(0.080 ns) = 37.694 ns; Loc. = LAB_X19_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_12_result_int[3]~3' + Info: 118: + IC(0.000 ns) + CELL(0.080 ns) = 37.774 ns; Loc. = LAB_X19_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_12_result_int[4]~5' + Info: 119: + IC(0.000 ns) + CELL(0.080 ns) = 37.854 ns; Loc. = LAB_X19_Y21; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_12_result_int[5]~7' + Info: 120: + IC(0.000 ns) + CELL(0.080 ns) = 37.934 ns; Loc. = LAB_X19_Y21; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_12_result_int[6]~9' + Info: 121: + IC(0.000 ns) + CELL(0.458 ns) = 38.392 ns; Loc. = LAB_X19_Y21; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_12_result_int[7]~10' + Info: 122: + IC(0.388 ns) + CELL(0.521 ns) = 39.301 ns; Loc. = LAB_X18_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[85]~483' + Info: 123: + IC(0.709 ns) + CELL(0.517 ns) = 40.527 ns; Loc. = LAB_X19_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_13_result_int[2]~1' + Info: 124: + IC(0.000 ns) + CELL(0.080 ns) = 40.607 ns; Loc. = LAB_X19_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_13_result_int[3]~3' + Info: 125: + IC(0.000 ns) + CELL(0.080 ns) = 40.687 ns; Loc. = LAB_X19_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_13_result_int[4]~5' + Info: 126: + IC(0.000 ns) + CELL(0.080 ns) = 40.767 ns; Loc. = LAB_X19_Y21; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_13_result_int[5]~7' + Info: 127: + IC(0.000 ns) + CELL(0.080 ns) = 40.847 ns; Loc. = LAB_X19_Y21; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_13_result_int[6]~9' + Info: 128: + IC(0.000 ns) + CELL(0.458 ns) = 41.305 ns; Loc. = LAB_X19_Y21; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_13_result_int[7]~10' + Info: 129: + IC(0.388 ns) + CELL(0.521 ns) = 42.214 ns; Loc. = LAB_X18_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[92]~489' + Info: 130: + IC(1.050 ns) + CELL(0.517 ns) = 43.781 ns; Loc. = LAB_X19_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[2]~1' + Info: 131: + IC(0.000 ns) + CELL(0.080 ns) = 43.861 ns; Loc. = LAB_X19_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[3]~3' + Info: 132: + IC(0.000 ns) + CELL(0.080 ns) = 43.941 ns; Loc. = LAB_X19_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[4]~5' + Info: 133: + IC(0.000 ns) + CELL(0.080 ns) = 44.021 ns; Loc. = LAB_X19_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[5]~7' + Info: 134: + IC(0.000 ns) + CELL(0.080 ns) = 44.101 ns; Loc. = LAB_X19_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[6]~9' + Info: 135: + IC(0.000 ns) + CELL(0.458 ns) = 44.559 ns; Loc. = LAB_X19_Y20; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[7]~10' + Info: 136: + IC(0.729 ns) + CELL(0.521 ns) = 45.809 ns; Loc. = LAB_X18_Y21; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[99]~495' + Info: 137: + IC(1.050 ns) + CELL(0.517 ns) = 47.376 ns; Loc. = LAB_X18_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[2]~1' + Info: 138: + IC(0.000 ns) + CELL(0.080 ns) = 47.456 ns; Loc. = LAB_X18_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[3]~3' + Info: 139: + IC(0.000 ns) + CELL(0.080 ns) = 47.536 ns; Loc. = LAB_X18_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[4]~5' + Info: 140: + IC(0.000 ns) + CELL(0.080 ns) = 47.616 ns; Loc. = LAB_X18_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[5]~7' + Info: 141: + IC(0.000 ns) + CELL(0.080 ns) = 47.696 ns; Loc. = LAB_X18_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[6]~9' + Info: 142: + IC(0.000 ns) + CELL(0.458 ns) = 48.154 ns; Loc. = LAB_X18_Y20; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[7]~10' + Info: 143: + IC(0.729 ns) + CELL(0.521 ns) = 49.404 ns; Loc. = LAB_X19_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[106]~501' + Info: 144: + IC(1.050 ns) + CELL(0.517 ns) = 50.971 ns; Loc. = LAB_X19_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[2]~1' + Info: 145: + IC(0.000 ns) + CELL(0.080 ns) = 51.051 ns; Loc. = LAB_X19_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[3]~3' + Info: 146: + IC(0.000 ns) + CELL(0.080 ns) = 51.131 ns; Loc. = LAB_X19_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[4]~5' + Info: 147: + IC(0.000 ns) + CELL(0.080 ns) = 51.211 ns; Loc. = LAB_X19_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[5]~7' + Info: 148: + IC(0.000 ns) + CELL(0.080 ns) = 51.291 ns; Loc. = LAB_X19_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[6]~9' + Info: 149: + IC(0.000 ns) + CELL(0.458 ns) = 51.749 ns; Loc. = LAB_X19_Y20; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[7]~10' + Info: 150: + IC(0.929 ns) + CELL(0.322 ns) = 53.000 ns; Loc. = LAB_X19_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[114]~657' + Info: 151: + IC(0.709 ns) + CELL(0.517 ns) = 54.226 ns; Loc. = LAB_X18_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[3]~3' + Info: 152: + IC(0.000 ns) + CELL(0.080 ns) = 54.306 ns; Loc. = LAB_X18_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[4]~5' + Info: 153: + IC(0.000 ns) + CELL(0.080 ns) = 54.386 ns; Loc. = LAB_X18_Y19; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[5]~7' + Info: 154: + IC(0.000 ns) + CELL(0.080 ns) = 54.466 ns; Loc. = LAB_X18_Y19; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[6]~9' + Info: 155: + IC(0.000 ns) + CELL(0.458 ns) = 54.924 ns; Loc. = LAB_X18_Y19; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[7]~10' + Info: 156: + IC(0.154 ns) + CELL(0.521 ns) = 55.599 ns; Loc. = LAB_X18_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[120]~513' + Info: 157: + IC(0.709 ns) + CELL(0.517 ns) = 56.825 ns; Loc. = LAB_X19_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_18_result_int[2]~1' + Info: 158: + IC(0.000 ns) + CELL(0.080 ns) = 56.905 ns; Loc. = LAB_X19_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_18_result_int[3]~3' + Info: 159: + IC(0.000 ns) + CELL(0.080 ns) = 56.985 ns; Loc. = LAB_X19_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_18_result_int[4]~5' + Info: 160: + IC(0.000 ns) + CELL(0.080 ns) = 57.065 ns; Loc. = LAB_X19_Y19; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_18_result_int[5]~7' + Info: 161: + IC(0.000 ns) + CELL(0.080 ns) = 57.145 ns; Loc. = LAB_X19_Y19; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_18_result_int[6]~9' + Info: 162: + IC(0.000 ns) + CELL(0.458 ns) = 57.603 ns; Loc. = LAB_X19_Y19; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_18_result_int[7]~10' + Info: 163: + IC(0.388 ns) + CELL(0.521 ns) = 58.512 ns; Loc. = LAB_X20_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[127]~519' + Info: 164: + IC(0.475 ns) + CELL(0.517 ns) = 59.504 ns; Loc. = LAB_X20_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_19_result_int[2]~1' + Info: 165: + IC(0.000 ns) + CELL(0.080 ns) = 59.584 ns; Loc. = LAB_X20_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_19_result_int[3]~3' + Info: 166: + IC(0.000 ns) + CELL(0.080 ns) = 59.664 ns; Loc. = LAB_X20_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_19_result_int[4]~5' + Info: 167: + IC(0.000 ns) + CELL(0.080 ns) = 59.744 ns; Loc. = LAB_X20_Y19; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_19_result_int[5]~7' + Info: 168: + IC(0.000 ns) + CELL(0.080 ns) = 59.824 ns; Loc. = LAB_X20_Y19; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_19_result_int[6]~9' + Info: 169: + IC(0.000 ns) + CELL(0.458 ns) = 60.282 ns; Loc. = LAB_X20_Y19; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_19_result_int[7]~10' + Info: 170: + IC(0.388 ns) + CELL(0.521 ns) = 61.191 ns; Loc. = LAB_X21_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[134]~525' + Info: 171: + IC(0.709 ns) + CELL(0.517 ns) = 62.417 ns; Loc. = LAB_X22_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[2]~1' + Info: 172: + IC(0.000 ns) + CELL(0.080 ns) = 62.497 ns; Loc. = LAB_X22_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[3]~3' + Info: 173: + IC(0.000 ns) + CELL(0.080 ns) = 62.577 ns; Loc. = LAB_X22_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[4]~5' + Info: 174: + IC(0.000 ns) + CELL(0.080 ns) = 62.657 ns; Loc. = LAB_X22_Y19; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[5]~7' + Info: 175: + IC(0.000 ns) + CELL(0.080 ns) = 62.737 ns; Loc. = LAB_X22_Y19; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[6]~9' + Info: 176: + IC(0.000 ns) + CELL(0.458 ns) = 63.195 ns; Loc. = LAB_X22_Y19; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[7]~10' + Info: 177: + IC(0.745 ns) + CELL(0.521 ns) = 64.461 ns; Loc. = LAB_X22_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[141]~531' + Info: 178: + IC(1.066 ns) + CELL(0.517 ns) = 66.044 ns; Loc. = LAB_X22_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[2]~1' + Info: 179: + IC(0.000 ns) + CELL(0.080 ns) = 66.124 ns; Loc. = LAB_X22_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[3]~3' + Info: 180: + IC(0.000 ns) + CELL(0.080 ns) = 66.204 ns; Loc. = LAB_X22_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[4]~5' + Info: 181: + IC(0.000 ns) + CELL(0.080 ns) = 66.284 ns; Loc. = LAB_X22_Y19; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[5]~7' + Info: 182: + IC(0.000 ns) + CELL(0.080 ns) = 66.364 ns; Loc. = LAB_X22_Y19; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[6]~9' + Info: 183: + IC(0.000 ns) + CELL(0.458 ns) = 66.822 ns; Loc. = LAB_X22_Y19; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[7]~10' + Info: 184: + IC(0.732 ns) + CELL(0.177 ns) = 67.731 ns; Loc. = LAB_X21_Y19; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[150]~535' + Info: 185: + IC(1.397 ns) + CELL(0.495 ns) = 69.623 ns; Loc. = LAB_X23_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_22_result_int[4]~5' + Info: 186: + IC(0.000 ns) + CELL(0.080 ns) = 69.703 ns; Loc. = LAB_X23_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_22_result_int[5]~7' + Info: 187: + IC(0.000 ns) + CELL(0.080 ns) = 69.783 ns; Loc. = LAB_X23_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_22_result_int[6]~9' + Info: 188: + IC(0.000 ns) + CELL(0.458 ns) = 70.241 ns; Loc. = LAB_X23_Y22; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_22_result_int[7]~10' + Info: 189: + IC(0.388 ns) + CELL(0.521 ns) = 71.150 ns; Loc. = LAB_X24_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[155]~543' + Info: 190: + IC(0.709 ns) + CELL(0.517 ns) = 72.376 ns; Loc. = LAB_X23_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[2]~1' + Info: 191: + IC(0.000 ns) + CELL(0.080 ns) = 72.456 ns; Loc. = LAB_X23_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[3]~3' + Info: 192: + IC(0.000 ns) + CELL(0.080 ns) = 72.536 ns; Loc. = LAB_X23_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[4]~5' + Info: 193: + IC(0.000 ns) + CELL(0.080 ns) = 72.616 ns; Loc. = LAB_X23_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[5]~7' + Info: 194: + IC(0.000 ns) + CELL(0.080 ns) = 72.696 ns; Loc. = LAB_X23_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[6]~9' + Info: 195: + IC(0.000 ns) + CELL(0.458 ns) = 73.154 ns; Loc. = LAB_X23_Y22; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[7]~10' + Info: 196: + IC(0.732 ns) + CELL(0.177 ns) = 74.063 ns; Loc. = LAB_X22_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[164]~547' + Info: 197: + IC(1.039 ns) + CELL(0.495 ns) = 75.597 ns; Loc. = LAB_X25_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_24_result_int[4]~5' + Info: 198: + IC(0.000 ns) + CELL(0.080 ns) = 75.677 ns; Loc. = LAB_X25_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_24_result_int[5]~7' + Info: 199: + IC(0.000 ns) + CELL(0.080 ns) = 75.757 ns; Loc. = LAB_X25_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_24_result_int[6]~9' + Info: 200: + IC(0.000 ns) + CELL(0.458 ns) = 76.215 ns; Loc. = LAB_X25_Y22; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_24_result_int[7]~10' + Info: 201: + IC(0.737 ns) + CELL(0.521 ns) = 77.473 ns; Loc. = LAB_X30_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[169]~555' + Info: 202: + IC(1.035 ns) + CELL(0.517 ns) = 79.025 ns; Loc. = LAB_X25_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[2]~1' + Info: 203: + IC(0.000 ns) + CELL(0.080 ns) = 79.105 ns; Loc. = LAB_X25_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[3]~3' + Info: 204: + IC(0.000 ns) + CELL(0.080 ns) = 79.185 ns; Loc. = LAB_X25_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[4]~5' + Info: 205: + IC(0.000 ns) + CELL(0.080 ns) = 79.265 ns; Loc. = LAB_X25_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[5]~7' + Info: 206: + IC(0.000 ns) + CELL(0.080 ns) = 79.345 ns; Loc. = LAB_X25_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[6]~9' + Info: 207: + IC(0.000 ns) + CELL(0.458 ns) = 79.803 ns; Loc. = LAB_X25_Y22; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[7]~10' + Info: 208: + IC(0.755 ns) + CELL(0.177 ns) = 80.735 ns; Loc. = LAB_X24_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[178]~559' + Info: 209: + IC(1.351 ns) + CELL(0.495 ns) = 82.581 ns; Loc. = LAB_X31_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_26_result_int[4]~5' + Info: 210: + IC(0.000 ns) + CELL(0.080 ns) = 82.661 ns; Loc. = LAB_X31_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_26_result_int[5]~7' + Info: 211: + IC(0.000 ns) + CELL(0.080 ns) = 82.741 ns; Loc. = LAB_X31_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_26_result_int[6]~9' + Info: 212: + IC(0.000 ns) + CELL(0.458 ns) = 83.199 ns; Loc. = LAB_X31_Y22; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_26_result_int[7]~10' + Info: 213: + IC(1.049 ns) + CELL(0.521 ns) = 84.769 ns; Loc. = LAB_X34_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[183]~567' + Info: 214: + IC(1.370 ns) + CELL(0.517 ns) = 86.656 ns; Loc. = LAB_X31_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[2]~1' + Info: 215: + IC(0.000 ns) + CELL(0.080 ns) = 86.736 ns; Loc. = LAB_X31_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[3]~3' + Info: 216: + IC(0.000 ns) + CELL(0.080 ns) = 86.816 ns; Loc. = LAB_X31_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[4]~5' + Info: 217: + IC(0.000 ns) + CELL(0.080 ns) = 86.896 ns; Loc. = LAB_X31_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[5]~7' + Info: 218: + IC(0.000 ns) + CELL(0.080 ns) = 86.976 ns; Loc. = LAB_X31_Y22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[6]~9' + Info: 219: + IC(0.000 ns) + CELL(0.458 ns) = 87.434 ns; Loc. = LAB_X31_Y22; Fanout = 15; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[7]~10' + Info: 220: + IC(0.732 ns) + CELL(0.177 ns) = 88.343 ns; Loc. = LAB_X30_Y22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[192]~571' + Info: 221: + IC(1.703 ns) + CELL(0.495 ns) = 90.541 ns; Loc. = LAB_X35_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_28_result_int[4]~5' + Info: 222: + IC(0.000 ns) + CELL(0.080 ns) = 90.621 ns; Loc. = LAB_X35_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_28_result_int[5]~7' + Info: 223: + IC(0.000 ns) + CELL(0.080 ns) = 90.701 ns; Loc. = LAB_X35_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_28_result_int[6]~9' + Info: 224: + IC(0.000 ns) + CELL(0.458 ns) = 91.159 ns; Loc. = LAB_X35_Y20; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_28_result_int[7]~10' + Info: 225: + IC(0.388 ns) + CELL(0.521 ns) = 92.068 ns; Loc. = LAB_X34_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[197]~579' + Info: 226: + IC(0.709 ns) + CELL(0.517 ns) = 93.294 ns; Loc. = LAB_X35_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[2]~1' + Info: 227: + IC(0.000 ns) + CELL(0.080 ns) = 93.374 ns; Loc. = LAB_X35_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[3]~3' + Info: 228: + IC(0.000 ns) + CELL(0.080 ns) = 93.454 ns; Loc. = LAB_X35_Y20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[4]~5' + Info: 229: + IC(0.000 ns) + CELL(0.080 ns) = 93.534 ns; Loc. = LAB_X35_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[5]~7' + Info: 230: + IC(0.000 ns) + CELL(0.080 ns) = 93.614 ns; Loc. = LAB_X35_Y20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[6]~9' + Info: 231: + IC(0.000 ns) + CELL(0.458 ns) = 94.072 ns; Loc. = LAB_X35_Y20; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[7]~10' + Info: 232: + IC(1.084 ns) + CELL(0.177 ns) = 95.333 ns; Loc. = LAB_X36_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[205]~584' + Info: 233: + IC(0.732 ns) + CELL(0.495 ns) = 96.560 ns; Loc. = LAB_X35_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_30_result_int[3]~3' + Info: 234: + IC(0.000 ns) + CELL(0.080 ns) = 96.640 ns; Loc. = LAB_X35_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_30_result_int[4]~5' + Info: 235: + IC(0.000 ns) + CELL(0.080 ns) = 96.720 ns; Loc. = LAB_X35_Y18; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_30_result_int[5]~7' + Info: 236: + IC(0.000 ns) + CELL(0.080 ns) = 96.800 ns; Loc. = LAB_X35_Y18; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_30_result_int[6]~9' + Info: 237: + IC(0.000 ns) + CELL(0.458 ns) = 97.258 ns; Loc. = LAB_X35_Y18; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_30_result_int[7]~10' + Info: 238: + IC(0.740 ns) + CELL(0.521 ns) = 98.519 ns; Loc. = LAB_X35_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[211]~591' + Info: 239: + IC(0.475 ns) + CELL(0.517 ns) = 99.511 ns; Loc. = LAB_X35_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[2]~1' + Info: 240: + IC(0.000 ns) + CELL(0.080 ns) = 99.591 ns; Loc. = LAB_X35_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[3]~3' + Info: 241: + IC(0.000 ns) + CELL(0.080 ns) = 99.671 ns; Loc. = LAB_X35_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[4]~5' + Info: 242: + IC(0.000 ns) + CELL(0.080 ns) = 99.751 ns; Loc. = LAB_X35_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[5]~7' + Info: 243: + IC(0.000 ns) + CELL(0.080 ns) = 99.831 ns; Loc. = LAB_X35_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[6]~9' + Info: 244: + IC(0.000 ns) + CELL(0.458 ns) = 100.289 ns; Loc. = LAB_X35_Y16; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[7]~10' + Info: 245: + IC(1.017 ns) + CELL(0.545 ns) = 101.851 ns; Loc. = LAB_X31_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|op_1~0' + Info: 246: + IC(0.673 ns) + CELL(0.545 ns) = 103.069 ns; Loc. = LAB_X35_Y16; Fanout = 19; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|quotient[0]~4' + Info: 247: + IC(0.498 ns) + CELL(0.178 ns) = 103.745 ns; Loc. = LAB_X35_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~15' + Info: 248: + IC(0.498 ns) + CELL(0.178 ns) = 104.421 ns; Loc. = LAB_X35_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~16' + Info: 249: + IC(1.058 ns) + CELL(0.178 ns) = 105.657 ns; Loc. = LAB_X30_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~17' + Info: 250: + IC(0.354 ns) + CELL(0.322 ns) = 106.333 ns; Loc. = LAB_X30_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~18' + Info: 251: + IC(0.498 ns) + CELL(0.178 ns) = 107.009 ns; Loc. = LAB_X30_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~19' + Info: 252: + IC(0.354 ns) + CELL(0.319 ns) = 107.682 ns; Loc. = LAB_X30_Y16; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~22' + Info: 253: + IC(1.249 ns) + CELL(0.322 ns) = 109.253 ns; Loc. = LAB_X27_Y18; Fanout = 4; COMB Node = 'Arkanoid:inst|Mux3~3' + Info: 254: + IC(0.354 ns) + CELL(0.322 ns) = 109.929 ns; Loc. = LAB_X27_Y18; Fanout = 2; COMB Node = 'Arkanoid:inst|blue_~1' + Info: 255: + IC(0.705 ns) + CELL(0.096 ns) = 110.730 ns; Loc. = LAB_X26_Y18; Fanout = 1; REG Node = 'Arkanoid:inst|blue_[0]' + Info: Total cell delay = 56.585 ns ( 51.10 % ) + Info: Total interconnect delay = 54.145 ns ( 48.90 % ) +Info: Fitter routing operations beginning +Info: Average interconnect usage is 2% of the available device resources + Info: Peak interconnect usage is 9% of the available device resources in the region that extends from location X25_Y14 to location X37_Y27 +Info: Fitter routing operations ending: elapsed time is 00:00:02 +Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info: Optimizations that may affect the design's routability were skipped + Info: Optimizations that may affect the design's timing were skipped +Info: Started post-fitting delay annotation +Warning: Found 50 output pins without output pin load capacitance assignment + Info: Pin "h_sync" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "v_sync" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "blue[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "blue[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "blue[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "blue[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "green[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "green[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "green[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "green[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led1[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led1[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led1[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led1[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led1[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led1[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led1[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led2[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led2[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led2[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led2[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led2[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led2[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led2[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led3[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led3[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led3[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led3[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led3[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led3[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led3[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led4[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led4[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led4[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led4[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led4[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led4[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "led4[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "red[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "red[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "red[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "red[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis +Info: Delay annotation completed successfully +Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. +Info: Generated suppressed messages file C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/myArkanoid.fit.smsg +Info: Quartus II Fitter was successful. 0 errors, 2 warnings + Info: Peak virtual memory: 237 megabytes + Info: Processing ended: Mon May 21 19:54:33 2012 + Info: Elapsed time: 00:00:12 + Info: Total CPU time (on all processors): 00:00:14 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/myArkanoid.fit.smsg. + + diff --git a/myArkanoid.fit.smsg b/myArkanoid.fit.smsg new file mode 100644 index 0000000..14764e7 --- /dev/null +++ b/myArkanoid.fit.smsg @@ -0,0 +1,6 @@ +Extra Info: Performing register packing on registers with non-logic cell location assignments +Extra Info: Completed register packing on registers with non-logic cell location assignments +Extra Info: Started Fast Input/Output/OE register processing +Extra Info: Finished Fast Input/Output/OE register processing +Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/myArkanoid.fit.summary b/myArkanoid.fit.summary new file mode 100644 index 0000000..6819d17 --- /dev/null +++ b/myArkanoid.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Mon May 21 19:54:32 2012 +Quartus II Version : 9.1 Build 222 10/21/2009 SJ Full Version +Revision Name : myArkanoid +Top-level Entity Name : TotalScheme +Family : Cyclone II +Device : EP2C20F484C7 +Timing Models : Final +Total logic elements : 1,806 / 18,752 ( 10 % ) + Total combinational functions : 1,793 / 18,752 ( 10 % ) + Dedicated logic registers : 151 / 18,752 ( < 1 % ) +Total registers : 151 +Total pins : 55 / 315 ( 17 % ) +Total virtual pins : 0 +Total memory bits : 0 / 239,616 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) diff --git a/myArkanoid.flow.rpt b/myArkanoid.flow.rpt new file mode 100644 index 0000000..6a08c48 --- /dev/null +++ b/myArkanoid.flow.rpt @@ -0,0 +1,122 @@ +Flow report for myArkanoid +Mon May 21 19:54:43 2012 +Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+------------------------------------------+ +; Flow Status ; Successful - Mon May 21 19:54:41 2012 ; +; Quartus II Version ; 9.1 Build 222 10/21/2009 SJ Full Version ; +; Revision Name ; myArkanoid ; +; Top-level Entity Name ; TotalScheme ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Met timing requirements ; Yes ; +; Total logic elements ; 1,806 / 18,752 ( 10 % ) ; +; Total combinational functions ; 1,793 / 18,752 ( 10 % ) ; +; Dedicated logic registers ; 151 / 18,752 ( < 1 % ) ; +; Total registers ; 151 ; +; Total pins ; 55 / 315 ( 17 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 05/21/2012 19:54:04 ; +; Main task ; Compilation ; +; Revision Name ; myArkanoid ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++------------------------+-----------------------------------------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++------------------------+-----------------------------------------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 1097476773127.133761564404376 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; MISC_FILE ; C:/Users/ProGOLD/Desktop/Политех/Altera DE1/myArkanoid/myArkanoid.dpf ; -- ; -- ; -- ; +; MISC_FILE ; C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/myArkanoid.dpf ; -- ; -- ; -- ; +; PARTITION_COLOR ; 16764057 ; -- ; TotalScheme ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; TotalScheme ; Top ; +; TOP_LEVEL_ENTITY ; TotalScheme ; myArkanoid ; -- ; -- ; ++------------------------+-----------------------------------------------------------------------+---------------+-------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:15 ; 1.0 ; 204 MB ; 00:00:16 ; +; Fitter ; 00:00:11 ; 1.2 ; 237 MB ; 00:00:13 ; +; Assembler ; 00:00:03 ; 1.0 ; 207 MB ; 00:00:04 ; +; Classic Timing Analyzer ; 00:00:02 ; 1.0 ; 151 MB ; 00:00:02 ; +; Total ; 00:00:31 ; -- ; -- ; 00:00:35 ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++------------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++-------------------------+------------------+---------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++-------------------------+------------------+---------------+------------+----------------+ +; Analysis & Synthesis ; ProGOLD-laptop ; Windows Vista ; 6.1 ; i686 ; +; Fitter ; ProGOLD-laptop ; Windows Vista ; 6.1 ; i686 ; +; Assembler ; ProGOLD-laptop ; Windows Vista ; 6.1 ; i686 ; +; Classic Timing Analyzer ; ProGOLD-laptop ; Windows Vista ; 6.1 ; i686 ; ++-------------------------+------------------+---------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid +quartus_fit --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid +quartus_asm --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid +quartus_tan --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid --timing_analysis_only + + + diff --git a/myArkanoid.map.rpt b/myArkanoid.map.rpt new file mode 100644 index 0000000..7e1d33b --- /dev/null +++ b/myArkanoid.map.rpt @@ -0,0 +1,435 @@ +Analysis & Synthesis report for myArkanoid +Mon May 21 19:54:20 2012 +Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Registers Removed During Synthesis + 9. General Register Statistics + 10. Inverted Register Statistics + 11. Multiplexer Restructuring Statistics (Restructuring Performed) + 12. Parameter Settings for User Entity Instance: Arkanoid:inst + 13. Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Div0 + 14. Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Div1 + 15. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Mon May 21 19:54:20 2012 ; +; Quartus II Version ; 9.1 Build 222 10/21/2009 SJ Full Version ; +; Revision Name ; myArkanoid ; +; Top-level Entity Name ; TotalScheme ; +; Family ; Cyclone II ; +; Total logic elements ; 1,810 ; +; Total combinational functions ; 1,793 ; +; Dedicated logic registers ; 151 ; +; Total registers ; 151 ; +; Total pins ; 55 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP2C20F484C7 ; ; +; Top-level entity name ; TotalScheme ; myArkanoid ; +; Family name ; Cyclone II ; Stratix II ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Parallel Synthesis ; Off ; Off ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; Off ; Off ; +; Show Parameter Settings Tables in Synthesis Report ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 2 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; 1 processor ; 100.0% ; +; 2 processors ; 0.0% ; ++----------------------------+-------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------+ +; TotalScheme.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/TotalScheme.bdf ; +; Arkanoid.v ; yes ; User Verilog HDL File ; C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/Arkanoid.v ; +; lpm_divide.tdf ; yes ; Megafunction ; c:/quartus/quartus/libraries/megafunctions/lpm_divide.tdf ; +; db/lpm_divide_8so.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/db/lpm_divide_8so.tdf ; +; db/abs_divider_lbg.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/db/abs_divider_lbg.tdf ; +; db/alt_u_div_m2f.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/db/alt_u_div_m2f.tdf ; +; db/add_sub_lkc.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/db/add_sub_lkc.tdf ; +; db/add_sub_mkc.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/db/add_sub_mkc.tdf ; +; db/lpm_abs_hq9.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/db/lpm_abs_hq9.tdf ; +; db/lpm_abs_0s9.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/db/lpm_abs_0s9.tdf ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------------------------+ +; Resource ; Usage ; ++---------------------------------------------+-------------------------+ +; Estimated Total logic elements ; 1,810 ; +; ; ; +; Total combinational functions ; 1793 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 561 ; +; -- 3 input functions ; 452 ; +; -- <=2 input functions ; 780 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 1147 ; +; -- arithmetic mode ; 646 ; +; ; ; +; Total registers ; 151 ; +; -- Dedicated logic registers ; 151 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 55 ; +; Maximum fan-out node ; Arkanoid:inst|clk25MHz_ ; +; Maximum fan-out ; 151 ; +; Total fan-out ; 5397 ; +; Average fan-out ; 2.70 ; ++---------------------------------------------+-------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------+--------------+ +; |TotalScheme ; 1793 (0) ; 151 (0) ; 0 ; 0 ; 0 ; 0 ; 55 ; 0 ; |TotalScheme ; work ; +; |Arkanoid:inst| ; 1793 (765) ; 151 (151) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst ; ; +; |lpm_divide:Div0| ; 475 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0 ; ; +; |lpm_divide_8so:auto_generated| ; 475 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated ; ; +; |abs_divider_lbg:divider| ; 475 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider ; ; +; |alt_u_div_m2f:divider| ; 433 (433) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider ; ; +; |lpm_abs_0s9:my_abs_num| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num ; ; +; |lpm_divide:Div1| ; 553 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1 ; ; +; |lpm_divide_8so:auto_generated| ; 553 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated ; ; +; |abs_divider_lbg:divider| ; 553 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider ; ; +; |alt_u_div_m2f:divider| ; 511 (511) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider ; ; +; |lpm_abs_0s9:my_abs_num| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num ; ; ++------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++---------------------------------------+----------------------------------------+ +; Register name ; Reason for Removal ; ++---------------------------------------+----------------------------------------+ +; Arkanoid:inst|green_[0..1] ; Stuck at GND due to stuck port data_in ; +; Total Number of Removed Registers = 2 ; ; ++---------------------------------------+----------------------------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 151 ; +; Number of registers using Synchronous Clear ; 32 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 12 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++--------------------------------------------------+ +; Inverted Register Statistics ; ++----------------------------------------+---------+ +; Inverted Register ; Fan out ; ++----------------------------------------+---------+ +; Arkanoid:inst|platform2_position[3] ; 2 ; +; Arkanoid:inst|platform2_position[2] ; 2 ; +; Arkanoid:inst|platform1_position[2] ; 2 ; +; Arkanoid:inst|platform1_position[3] ; 2 ; +; Total number of inverted registers = 4 ; ; ++----------------------------------------+---------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+ +; 3:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; No ; |TotalScheme|Arkanoid:inst|platform1_position ; +; 3:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; No ; |TotalScheme|Arkanoid:inst|platform2_position ; +; 4:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; No ; |TotalScheme|Arkanoid:inst|platform1_position ; +; 4:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; No ; |TotalScheme|Arkanoid:inst|platform2_position ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+ + + ++------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Arkanoid:inst ; ++------------------+-------+---------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------+-------+---------------------------------+ +; SCREEN_WIDTH ; 640 ; Signed Integer ; +; SCREEN_HEIGHT ; 480 ; Signed Integer ; +; CELL_SIZE ; 20 ; Signed Integer ; +; BALL_SIZE ; 1 ; Signed Integer ; +; BALL_SPEED ; 2 ; Signed Integer ; +; PLATFORM_WIDTH ; 8 ; Signed Integer ; +; PLATFORM_SPEED ; 1 ; Signed Integer ; +; BK_COLOR_R ; 0000 ; Unsigned Binary ; +; BK_COLOR_G ; 0000 ; Unsigned Binary ; +; BK_COLOR_B ; 0000 ; Unsigned Binary ; +; STABLE_COLOR_R ; 0011 ; Unsigned Binary ; +; STABLE_COLOR_G ; 1100 ; Unsigned Binary ; +; STABLE_COLOR_B ; 0110 ; Unsigned Binary ; +; BALL_COLOR_R ; 0000 ; Unsigned Binary ; +; BALL_COLOR_G ; 0000 ; Unsigned Binary ; +; BALL_COLOR_B ; 1111 ; Unsigned Binary ; +; PLATFORM_COLOR_R ; 1111 ; Unsigned Binary ; +; PLATFORM_COLOR_G ; 0000 ; Unsigned Binary ; +; PLATFORM_COLOR_B ; 0000 ; Unsigned Binary ; ++------------------+-------+---------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------+ +; Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Div0 ; ++------------------------+----------------+--------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+----------------+--------------------------------------+ +; LPM_WIDTHN ; 32 ; Untyped ; +; LPM_WIDTHD ; 6 ; Untyped ; +; LPM_NREPRESENTATION ; SIGNED ; Untyped ; +; LPM_DREPRESENTATION ; SIGNED ; Untyped ; +; LPM_PIPELINE ; 0 ; Untyped ; +; LPM_REMAINDERPOSITIVE ; FALSE ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; CBXI_PARAMETER ; lpm_divide_8so ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+----------------+--------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------+ +; Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Div1 ; ++------------------------+----------------+--------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+----------------+--------------------------------------+ +; LPM_WIDTHN ; 32 ; Untyped ; +; LPM_WIDTHD ; 6 ; Untyped ; +; LPM_NREPRESENTATION ; SIGNED ; Untyped ; +; LPM_DREPRESENTATION ; SIGNED ; Untyped ; +; LPM_PIPELINE ; 0 ; Untyped ; +; LPM_REMAINDERPOSITIVE ; FALSE ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; CBXI_PARAMETER ; lpm_divide_8so ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+----------------+--------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Analysis & Synthesis + Info: Version 9.1 Build 222 10/21/2009 SJ Full Version + Info: Processing started: Mon May 21 19:54:04 2012 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid +Info: Parallel compilation is enabled and will use 2 of the 2 processors detected +Info: Found 1 design units, including 1 entities, in source file totalscheme.bdf + Info: Found entity 1: TotalScheme +Info: Found 1 design units, including 1 entities, in source file arkanoid.v + Info: Found entity 1: Arkanoid +Info: Elaborating entity "TotalScheme" for the top level hierarchy +Info: Elaborating entity "Arkanoid" for hierarchy "Arkanoid:inst" +Warning (10036): Verilog HDL or VHDL warning at Arkanoid.v(82): object "ball_state" assigned a value but never read +Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "field" into its bus +Info: Inferred 2 megafunctions from design logic + Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Arkanoid:inst|Div0" + Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Arkanoid:inst|Div1" +Info: Elaborated megafunction instantiation "Arkanoid:inst|lpm_divide:Div0" +Info: Instantiated megafunction "Arkanoid:inst|lpm_divide:Div0" with the following parameter: + Info: Parameter "LPM_WIDTHN" = "32" + Info: Parameter "LPM_WIDTHD" = "6" + Info: Parameter "LPM_NREPRESENTATION" = "SIGNED" + Info: Parameter "LPM_DREPRESENTATION" = "SIGNED" + Info: Parameter "LPM_HINT" = "LPM_REMAINDERPOSITIVE=FALSE" +Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_8so.tdf + Info: Found entity 1: lpm_divide_8so +Info: Found 1 design units, including 1 entities, in source file db/abs_divider_lbg.tdf + Info: Found entity 1: abs_divider_lbg +Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_m2f.tdf + Info: Found entity 1: alt_u_div_m2f +Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf + Info: Found entity 1: add_sub_lkc +Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf + Info: Found entity 1: add_sub_mkc +Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_hq9.tdf + Info: Found entity 1: lpm_abs_hq9 +Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_0s9.tdf + Info: Found entity 1: lpm_abs_0s9 +Warning: Output pins are stuck at VCC or GND + Warning (13410): Pin "green[1]" is stuck at GND + Warning (13410): Pin "green[0]" is stuck at GND + Warning (13410): Pin "led1[6]" is stuck at GND + Warning (13410): Pin "led1[5]" is stuck at GND + Warning (13410): Pin "led1[4]" is stuck at GND + Warning (13410): Pin "led1[3]" is stuck at GND + Warning (13410): Pin "led1[2]" is stuck at GND + Warning (13410): Pin "led1[1]" is stuck at GND + Warning (13410): Pin "led1[0]" is stuck at GND + Warning (13410): Pin "led2[6]" is stuck at GND + Warning (13410): Pin "led2[5]" is stuck at GND + Warning (13410): Pin "led2[4]" is stuck at GND + Warning (13410): Pin "led2[3]" is stuck at GND + Warning (13410): Pin "led2[2]" is stuck at GND + Warning (13410): Pin "led2[1]" is stuck at GND + Warning (13410): Pin "led2[0]" is stuck at GND + Warning (13410): Pin "led3[6]" is stuck at GND + Warning (13410): Pin "led3[5]" is stuck at GND + Warning (13410): Pin "led3[4]" is stuck at GND + Warning (13410): Pin "led3[3]" is stuck at GND + Warning (13410): Pin "led3[2]" is stuck at GND + Warning (13410): Pin "led3[1]" is stuck at GND + Warning (13410): Pin "led3[0]" is stuck at GND + Warning (13410): Pin "led4[6]" is stuck at GND + Warning (13410): Pin "led4[5]" is stuck at GND + Warning (13410): Pin "led4[4]" is stuck at GND + Warning (13410): Pin "led4[3]" is stuck at GND + Warning (13410): Pin "led4[2]" is stuck at GND + Warning (13410): Pin "led4[1]" is stuck at GND + Warning (13410): Pin "led4[0]" is stuck at GND +Info: Implemented 1932 device resources after synthesis - the final resource count might be different + Info: Implemented 5 input pins + Info: Implemented 50 output pins + Info: Implemented 1877 logic cells +Info: Quartus II Analysis & Synthesis was successful. 0 errors, 32 warnings + Info: Peak virtual memory: 204 megabytes + Info: Processing ended: Mon May 21 19:54:20 2012 + Info: Elapsed time: 00:00:16 + Info: Total CPU time (on all processors): 00:00:17 + + diff --git a/myArkanoid.map.smsg b/myArkanoid.map.smsg new file mode 100644 index 0000000..52eddc8 --- /dev/null +++ b/myArkanoid.map.smsg @@ -0,0 +1 @@ +Warning (10268): Verilog HDL information at Arkanoid.v(168): always construct contains both blocking and non-blocking assignments diff --git a/myArkanoid.map.summary b/myArkanoid.map.summary new file mode 100644 index 0000000..aa2c8eb --- /dev/null +++ b/myArkanoid.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Mon May 21 19:54:20 2012 +Quartus II Version : 9.1 Build 222 10/21/2009 SJ Full Version +Revision Name : myArkanoid +Top-level Entity Name : TotalScheme +Family : Cyclone II +Total logic elements : 1,810 + Total combinational functions : 1,793 + Dedicated logic registers : 151 +Total registers : 151 +Total pins : 55 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 diff --git a/myArkanoid.pin b/myArkanoid.pin new file mode 100644 index 0000000..6903afe --- /dev/null +++ b/myArkanoid.pin @@ -0,0 +1,558 @@ + -- Copyright (C) 1991-2009 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 3.3V + -- Bank 5: 3.3V + -- Bank 6: 3.3V + -- Bank 7: 3.3V + -- Bank 8: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17), + -- connect each pin marked GND* either individually through a 10k Ohm resistor + -- to GND or tie all pins together and connect through a single 10k Ohm resistor + -- to GND. + -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version +CHIP "myArkanoid" ASSIGNED TO AN: EP2C20F484C7 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +VCCIO3 : A2 : power : : 3.3V : 3 : +GND* : A3 : : : : 3 : +GND* : A4 : : : : 3 : +GND* : A5 : : : : 3 : +GND* : A6 : : : : 3 : +red[2] : A7 : output : 3.3-V LVTTL : : 3 : Y +green[3] : A8 : output : 3.3-V LVTTL : : 3 : Y +blue[0] : A9 : output : 3.3-V LVTTL : : 3 : Y +blue[2] : A10 : output : 3.3-V LVTTL : : 3 : Y +h_sync : A11 : output : 3.3-V LVTTL : : 3 : Y +GND+ : A12 : : : : 4 : +GND* : A13 : : : : 4 : +GND* : A14 : : : : 4 : +GND* : A15 : : : : 4 : +GND* : A16 : : : : 4 : +GND* : A17 : : : : 4 : +GND* : A18 : : : : 4 : +GND* : A19 : : : : 4 : +GND* : A20 : : : : 4 : +VCCIO4 : A21 : power : : 3.3V : 4 : +GND : A22 : gnd : : : : +VCCIO1 : AA1 : power : : 3.3V : 1 : +GND : AA2 : gnd : : : : +GND* : AA3 : : : : 8 : +GND* : AA4 : : : : 8 : +GND* : AA5 : : : : 8 : +GND* : AA6 : : : : 8 : +GND* : AA7 : : : : 8 : +GND* : AA8 : : : : 8 : +GND* : AA9 : : : : 8 : +GND* : AA10 : : : : 8 : +GND* : AA11 : : : : 8 : +GND* : AA12 : : : : 7 : +GND* : AA13 : : : : 7 : +GND* : AA14 : : : : 7 : +GND* : AA15 : : : : 7 : +GND* : AA16 : : : : 7 : +GND* : AA17 : : : : 7 : +GND* : AA18 : : : : 7 : +GND* : AA19 : : : : 7 : +GND* : AA20 : : : : 7 : +GND : AA21 : gnd : : : : +VCCIO6 : AA22 : power : : 3.3V : 6 : +GND : AB1 : gnd : : : : +VCCIO8 : AB2 : power : : 3.3V : 8 : +GND* : AB3 : : : : 8 : +GND* : AB4 : : : : 8 : +GND* : AB5 : : : : 8 : +GND* : AB6 : : : : 8 : +GND* : AB7 : : : : 8 : +GND* : AB8 : : : : 8 : +GND* : AB9 : : : : 8 : +GND* : AB10 : : : : 8 : +GND* : AB11 : : : : 8 : +GND* : AB12 : : : : 7 : +GND* : AB13 : : : : 7 : +GND* : AB14 : : : : 7 : +GND* : AB15 : : : : 7 : +GND* : AB16 : : : : 7 : +GND* : AB17 : : : : 7 : +GND* : AB18 : : : : 7 : +GND* : AB19 : : : : 7 : +GND* : AB20 : : : : 7 : +VCCIO7 : AB21 : power : : 3.3V : 7 : +GND : AB22 : gnd : : : : +VCCIO2 : B1 : power : : 3.3V : 2 : +GND : B2 : gnd : : : : +GND* : B3 : : : : 3 : +GND* : B4 : : : : 3 : +GND* : B5 : : : : 3 : +GND* : B6 : : : : 3 : +red[3] : B7 : output : 3.3-V LVTTL : : 3 : Y +green[0] : B8 : output : 3.3-V LVTTL : : 3 : Y +green[2] : B9 : output : 3.3-V LVTTL : : 3 : Y +blue[3] : B10 : output : 3.3-V LVTTL : : 3 : Y +v_sync : B11 : output : 3.3-V LVTTL : : 3 : Y +GND+ : B12 : : : : 4 : +GND* : B13 : : : : 4 : +GND* : B14 : : : : 4 : +GND* : B15 : : : : 4 : +GND* : B16 : : : : 4 : +GND* : B17 : : : : 4 : +GND* : B18 : : : : 4 : +GND* : B19 : : : : 4 : +GND* : B20 : : : : 4 : +GND : B21 : gnd : : : : +VCCIO5 : B22 : power : : 3.3V : 5 : +led3[3] : C1 : output : 3.3-V LVTTL : : 2 : Y +led3[2] : C2 : output : 3.3-V LVTTL : : 2 : Y +~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : input : 3.3-V LVTTL : : 2 : N +~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : input : 3.3-V LVTTL : : 2 : N +GND : C5 : gnd : : : : +VCCIO3 : C6 : power : : 3.3V : 3 : +GND* : C7 : : : : 3 : +GND : C8 : gnd : : : : +red[1] : C9 : output : 3.3-V LVTTL : : 3 : Y +green[1] : C10 : output : 3.3-V LVTTL : : 3 : Y +VCCIO3 : C11 : power : : 3.3V : 3 : +VCCIO4 : C12 : power : : 3.3V : 4 : +GND* : C13 : : : : 4 : +GND* : C14 : : : : 4 : +GND : C15 : gnd : : : : +GND* : C16 : : : : 4 : +GND* : C17 : : : : 4 : +GND* : C18 : : : : 4 : +GND* : C19 : : : : 5 : +GND* : C20 : : : : 5 : +GND* : C21 : : : : 5 : +GND* : C22 : : : : 5 : +led2[6] : D1 : output : 3.3-V LVTTL : : 2 : Y +led2[5] : D2 : output : 3.3-V LVTTL : : 2 : Y +led3[6] : D3 : output : 3.3-V LVTTL : : 2 : Y +led4[6] : D4 : output : 3.3-V LVTTL : : 2 : Y +led4[1] : D5 : output : 3.3-V LVTTL : : 2 : Y +led4[2] : D6 : output : 3.3-V LVTTL : : 2 : Y +GND* : D7 : : : : 3 : +GND* : D8 : : : : 3 : +red[0] : D9 : output : 3.3-V LVTTL : : 3 : Y +GND : D10 : gnd : : : : +blue[1] : D11 : output : 3.3-V LVTTL : : 3 : Y +GND+ : D12 : : : : 3 : +GND : D13 : gnd : : : : +GND* : D14 : : : : 4 : +GND* : D15 : : : : 4 : +GND* : D16 : : : : 4 : +VCCIO4 : D17 : power : : 3.3V : 4 : +GND : D18 : gnd : : : : +GND* : D19 : : : : 5 : +GND* : D20 : : : : 5 : +GND* : D21 : : : : 5 : +GND* : D22 : : : : 5 : +led2[0] : E1 : output : 3.3-V LVTTL : : 2 : Y +led1[6] : E2 : output : 3.3-V LVTTL : : 2 : Y +led3[4] : E3 : output : 3.3-V LVTTL : : 2 : Y +led3[5] : E4 : output : 3.3-V LVTTL : : 2 : Y +VCCD_PLL3 : E5 : power : : 1.2V : : +VCCA_PLL3 : E6 : power : : 1.2V : : +GND* : E7 : : : : 3 : +GND* : E8 : : : : 3 : +GND* : E9 : : : : 3 : +VCCIO3 : E10 : power : : 3.3V : 3 : +GND* : E11 : : : : 3 : +GND+ : E12 : : : : 3 : +VCCIO4 : E13 : power : : 3.3V : 4 : +GND* : E14 : : : : 4 : +GND* : E15 : : : : 4 : +GNDA_PLL2 : E16 : gnd : : : : +GND_PLL2 : E17 : gnd : : : : +GND* : E18 : : : : 5 : +GND* : E19 : : : : 5 : +GND* : E20 : : : : 5 : +GND* : E21 : : : : 5 : +GND* : E22 : : : : 5 : +led1[5] : F1 : output : 3.3-V LVTTL : : 2 : Y +led1[4] : F2 : output : 3.3-V LVTTL : : 2 : Y +led4[5] : F3 : output : 3.3-V LVTTL : : 2 : Y +led4[0] : F4 : output : 3.3-V LVTTL : : 2 : Y +GND_PLL3 : F5 : gnd : : : : +GND_PLL3 : F6 : gnd : : : : +GNDA_PLL3 : F7 : gnd : : : : +GND* : F8 : : : : 3 : +GND* : F9 : : : : 3 : +GND* : F10 : : : : 3 : +GND* : F11 : : : : 3 : +GND* : F12 : : : : 4 : +GND* : F13 : : : : 4 : +GND* : F14 : : : : 4 : +GND* : F15 : : : : 4 : +VCCA_PLL2 : F16 : power : : 1.2V : : +VCCD_PLL2 : F17 : power : : 1.2V : : +GND_PLL2 : F18 : gnd : : : : +GND : F19 : gnd : : : : +GND* : F20 : : : : 5 : +GND* : F21 : : : : 5 : +GND* : F22 : : : : 5 : +NC : G1 : : : : : +NC : G2 : : : : : +led2[4] : G3 : output : 3.3-V LVTTL : : 2 : Y +GND : G4 : gnd : : : : +led3[0] : G5 : output : 3.3-V LVTTL : : 2 : Y +led3[1] : G6 : output : 3.3-V LVTTL : : 2 : Y +GND* : G7 : : : : 3 : +GND* : G8 : : : : 3 : +VCCIO3 : G9 : power : : 3.3V : 3 : +GND : G10 : gnd : : : : +GND* : G11 : : : : 3 : +GND* : G12 : : : : 4 : +GND : G13 : gnd : : : : +VCCIO4 : G14 : power : : 3.3V : 4 : +GND* : G15 : : : : 4 : +GND* : G16 : : : : 4 : +GND* : G17 : : : : 5 : +GND* : G18 : : : : 5 : +VCCIO5 : G19 : power : : 3.3V : 5 : +GND* : G20 : : : : 5 : +GND* : G21 : : : : 5 : +GND* : G22 : : : : 5 : +led1[3] : H1 : output : 3.3-V LVTTL : : 2 : Y +led1[2] : H2 : output : 3.3-V LVTTL : : 2 : Y +GND* : H3 : : : : 2 : +led2[3] : H4 : output : 3.3-V LVTTL : : 2 : Y +led2[2] : H5 : output : 3.3-V LVTTL : : 2 : Y +led2[1] : H6 : output : 3.3-V LVTTL : : 2 : Y +GND* : H7 : : : : 3 : +GND* : H8 : : : : 3 : +GND* : H9 : : : : 3 : +GND* : H10 : : : : 3 : +GND* : H11 : : : : 3 : +GND* : H12 : : : : 4 : +GND* : H13 : : : : 4 : +GND* : H14 : : : : 4 : +GND* : H15 : : : : 4 : +GND* : H16 : : : : 5 : +GND* : H17 : : : : 5 : +GND* : H18 : : : : 5 : +GND* : H19 : : : : 5 : +GND : H20 : gnd : : : : +NC : H21 : : : : : +NC : H22 : : : : : +led1[1] : J1 : output : 3.3-V LVTTL : : 2 : Y +led1[0] : J2 : output : 3.3-V LVTTL : : 2 : Y +NC : J3 : : : : : +led4[3] : J4 : output : 3.3-V LVTTL : : 2 : Y +NC : J5 : : : : : +NC : J6 : : : : : +VCCIO2 : J7 : power : : 3.3V : 2 : +NC : J8 : : : : : +NC : J9 : : : : : +VCCINT : J10 : power : : 1.2V : : +VCCINT : J11 : power : : 1.2V : : +VCCINT : J12 : power : : 1.2V : : +VCCINT : J13 : power : : 1.2V : : +GND* : J14 : : : : 4 : +GND* : J15 : : : : 5 : +VCCIO5 : J16 : power : : 3.3V : 5 : +GND* : J17 : : : : 5 : +GND* : J18 : : : : 5 : +GND* : J19 : : : : 5 : +GND* : J20 : : : : 5 : +GND* : J21 : : : : 5 : +GND* : J22 : : : : 5 : +nCE : K1 : : : : 2 : +TCK : K2 : input : : : 2 : +GND : K3 : gnd : : : : +DATA0 : K4 : input : : : 2 : +TDI : K5 : input : : : 2 : +TMS : K6 : input : : : 2 : +GND : K7 : gnd : : : : +NC : K8 : : : : : +VCCINT : K9 : power : : 1.2V : : +GND : K10 : gnd : : : : +GND : K11 : gnd : : : : +GND : K12 : gnd : : : : +GND : K13 : gnd : : : : +VCCINT : K14 : power : : 1.2V : : +NC : K15 : : : : : +GND : K16 : gnd : : : : +NC : K17 : : : : : +NC : K18 : : : : : +GND : K19 : gnd : : : : +GND* : K20 : : : : 5 : +GND* : K21 : : : : 5 : +GND* : K22 : : : : 5 : +clk_50MHz : L1 : input : 3.3-V LVTTL : : 2 : Y +GND+ : L2 : : : : 2 : +VCCIO2 : L3 : power : : 3.3V : 2 : +nCONFIG : L4 : : : : 2 : +TDO : L5 : output : : : 2 : +DCLK : L6 : : : : 2 : +NC : L7 : : : : : +led4[4] : L8 : output : 3.3-V LVTTL : : 2 : Y +VCCINT : L9 : power : : 1.2V : : +GND : L10 : gnd : : : : +GND : L11 : gnd : : : : +GND : L12 : gnd : : : : +GND : L13 : gnd : : : : +VCCINT : L14 : power : : 1.2V : : +NC : L15 : : : : : +NC : L16 : : : : : +NC : L17 : : : : : +GND* : L18 : : : : 5 : +GND* : L19 : : : : 5 : +VCCIO5 : L20 : power : : 3.3V : 5 : +GND+ : L21 : : : : 5 : +GND+ : L22 : : : : 5 : +GND+ : M1 : : : : 1 : +GND+ : M2 : : : : 1 : +VCCIO1 : M3 : power : : 3.3V : 1 : +GND : M4 : gnd : : : : +GND* : M5 : : : : 1 : +GND* : M6 : : : : 1 : +NC : M7 : : : : : +NC : M8 : : : : : +VCCINT : M9 : power : : 1.2V : : +GND : M10 : gnd : : : : +GND : M11 : gnd : : : : +GND : M12 : gnd : : : : +GND : M13 : gnd : : : : +VCCINT : M14 : power : : 1.2V : : +NC : M15 : : : : : +NC : M16 : : : : : +MSEL0 : M17 : : : : 6 : +GND* : M18 : : : : 6 : +GND* : M19 : : : : 6 : +VCCIO6 : M20 : power : : 3.3V : 6 : +GND+ : M21 : : : : 6 : +GND+ : M22 : : : : 6 : +GND* : N1 : : : : 1 : +GND* : N2 : : : : 1 : +GND* : N3 : : : : 1 : +GND* : N4 : : : : 1 : +NC : N5 : : : : : +GND* : N6 : : : : 1 : +GND : N7 : gnd : : : : +NC : N8 : : : : : +VCCINT : N9 : power : : 1.2V : : +GND : N10 : gnd : : : : +GND : N11 : gnd : : : : +GND : N12 : gnd : : : : +GND : N13 : gnd : : : : +VCCINT : N14 : power : : 1.2V : : +GND* : N15 : : : : 6 : +GND : N16 : gnd : : : : +MSEL1 : N17 : : : : 6 : +CONF_DONE : N18 : : : : 6 : +GND : N19 : gnd : : : : +nSTATUS : N20 : : : : 6 : +GND* : N21 : : : : 6 : +GND* : N22 : : : : 6 : +GND* : P1 : : : : 1 : +GND* : P2 : : : : 1 : +GND* : P3 : : : : 1 : +NC : P4 : : : : : +GND* : P5 : : : : 1 : +GND* : P6 : : : : 1 : +VCCIO1 : P7 : power : : 3.3V : 1 : +GND* : P8 : : : : 8 : +GND* : P9 : : : : 8 : +VCCINT : P10 : power : : 1.2V : : +VCCINT : P11 : power : : 1.2V : : +VCCINT : P12 : power : : 1.2V : : +VCCINT : P13 : power : : 1.2V : : +NC : P14 : : : : : +GND* : P15 : : : : 6 : +VCCIO6 : P16 : power : : 3.3V : 6 : +GND* : P17 : : : : 6 : +GND* : P18 : : : : 6 : +NC : P19 : : : : : +NC : P20 : : : : : +NC : P21 : : : : : +NC : P22 : : : : : +GND* : R1 : : : : 1 : +GND* : R2 : : : : 1 : +GND : R3 : gnd : : : : +NC : R4 : : : : : +GND* : R5 : : : : 1 : +GND* : R6 : : : : 1 : +GND* : R7 : : : : 1 : +GND* : R8 : : : : 1 : +GND* : R9 : : : : 8 : +GND* : R10 : : : : 8 : +GND* : R11 : : : : 8 : +GND* : R12 : : : : 7 : +GND* : R13 : : : : 7 : +GND* : R14 : : : : 7 : +GND* : R15 : : : : 7 : +GND* : R16 : : : : 7 : +GND* : R17 : : : : 6 : +GND* : R18 : : : : 6 : +GND* : R19 : : : : 6 : +GND* : R20 : : : : 6 : +button3 : R21 : input : 3.3-V LVTTL : : 6 : Y +button4 : R22 : input : 3.3-V LVTTL : : 6 : Y +GND* : T1 : : : : 1 : +GND* : T2 : : : : 1 : +GND* : T3 : : : : 1 : +VCCIO1 : T4 : power : : 3.3V : 1 : +GND* : T5 : : : : 1 : +GND* : T6 : : : : 1 : +GND* : T7 : : : : 8 : +GND* : T8 : : : : 8 : +VCCIO8 : T9 : power : : 3.3V : 8 : +GND : T10 : gnd : : : : +GND* : T11 : : : : 8 : +GND* : T12 : : : : 7 : +GND : T13 : gnd : : : : +VCCIO7 : T14 : power : : 3.3V : 7 : +GND* : T15 : : : : 7 : +GND* : T16 : : : : 7 : +GND_PLL4 : T17 : gnd : : : : +GND* : T18 : : : : 6 : +VCCIO6 : T19 : power : : 3.3V : 6 : +GND : T20 : gnd : : : : +button1 : T21 : input : 3.3-V LVTTL : : 6 : Y +button2 : T22 : input : 3.3-V LVTTL : : 6 : Y +GND* : U1 : : : : 1 : +GND* : U2 : : : : 1 : +GND* : U3 : : : : 1 : +GND* : U4 : : : : 1 : +GND_PLL1 : U5 : gnd : : : : +VCCD_PLL1 : U6 : power : : 1.2V : : +VCCA_PLL1 : U7 : power : : 1.2V : : +GND* : U8 : : : : 8 : +GND* : U9 : : : : 8 : +GND* : U10 : : : : 8 : +GND+ : U11 : : : : 8 : +GND+ : U12 : : : : 8 : +GND* : U13 : : : : 7 : +GND* : U14 : : : : 7 : +GND* : U15 : : : : 7 : +VCCA_PLL4 : U16 : power : : 1.2V : : +VCCD_PLL4 : U17 : power : : 1.2V : : +GND* : U18 : : : : 6 : +GND* : U19 : : : : 6 : +GND* : U20 : : : : 6 : +led[1] : U21 : output : 3.3-V LVTTL : : 6 : Y +led[0] : U22 : output : 3.3-V LVTTL : : 6 : Y +GND* : V1 : : : : 1 : +GND* : V2 : : : : 1 : +GND : V3 : gnd : : : : +GND* : V4 : : : : 1 : +GND_PLL1 : V5 : gnd : : : : +GND : V6 : gnd : : : : +GNDA_PLL1 : V7 : gnd : : : : +GND* : V8 : : : : 8 : +GND* : V9 : : : : 8 : +VCCIO8 : V10 : power : : 3.3V : 8 : +GND* : V11 : : : : 8 : +GND+ : V12 : : : : 7 : +VCCIO7 : V13 : power : : 3.3V : 7 : +GND* : V14 : : : : 7 : +GND* : V15 : : : : 7 : +GNDA_PLL4 : V16 : gnd : : : : +GND : V17 : gnd : : : : +GND_PLL4 : V18 : gnd : : : : +GND* : V19 : : : : 6 : +GND* : V20 : : : : 6 : +led[3] : V21 : output : 3.3-V LVTTL : : 6 : Y +led[2] : V22 : output : 3.3-V LVTTL : : 6 : Y +GND* : W1 : : : : 1 : +GND* : W2 : : : : 1 : +GND* : W3 : : : : 1 : +GND* : W4 : : : : 1 : +GND* : W5 : : : : 1 : +VCCIO8 : W6 : power : : 3.3V : 8 : +GND* : W7 : : : : 8 : +GND* : W8 : : : : 8 : +GND* : W9 : : : : 8 : +GND : W10 : gnd : : : : +GND* : W11 : : : : 8 : +GND+ : W12 : : : : 7 : +GND : W13 : gnd : : : : +GND* : W14 : : : : 7 : +GND* : W15 : : : : 7 : +GND* : W16 : : : : 7 : +VCCIO7 : W17 : power : : 3.3V : 7 : +NC : W18 : : : : : +GND : W19 : gnd : : : : +~LVDS91p/nCEO~ : W20 : output : 3.3-V LVTTL : : 6 : N +led[5] : W21 : output : 3.3-V LVTTL : : 6 : Y +led[4] : W22 : output : 3.3-V LVTTL : : 6 : Y +GND* : Y1 : : : : 1 : +GND* : Y2 : : : : 1 : +GND* : Y3 : : : : 1 : +GND* : Y4 : : : : 1 : +GND* : Y5 : : : : 8 : +GND* : Y6 : : : : 8 : +GND* : Y7 : : : : 8 : +GND : Y8 : gnd : : : : +GND* : Y9 : : : : 8 : +GND* : Y10 : : : : 8 : +VCCIO8 : Y11 : power : : 3.3V : 8 : +VCCIO7 : Y12 : power : : 3.3V : 7 : +GND* : Y13 : : : : 7 : +GND* : Y14 : : : : 7 : +GND : Y15 : gnd : : : : +GND* : Y16 : : : : 7 : +GND* : Y17 : : : : 7 : +GND* : Y18 : : : : 6 : +GND* : Y19 : : : : 6 : +GND* : Y20 : : : : 6 : +led[7] : Y21 : output : 3.3-V LVTTL : : 6 : Y +led[6] : Y22 : output : 3.3-V LVTTL : : 6 : Y diff --git a/myArkanoid.pof b/myArkanoid.pof new file mode 100644 index 0000000..32032de Binary files /dev/null and b/myArkanoid.pof differ diff --git a/myArkanoid.qpf b/myArkanoid.qpf new file mode 100644 index 0000000..12ffd56 --- /dev/null +++ b/myArkanoid.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +# Date created = 14:07:51 October 21, 2009 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "9.0" +DATE = "14:07:51 October 21, 2009" + +# Revisions + +PROJECT_REVISION = "myArkanoid" diff --git a/myArkanoid.qsf b/myArkanoid.qsf new file mode 100644 index 0000000..971f526 --- /dev/null +++ b/myArkanoid.qsf @@ -0,0 +1,120 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +# Date created = 14:07:51 October 21, 2009 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# myArkanoid_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C20F484C7 +set_global_assignment -name TOP_LEVEL_ENTITY TotalScheme +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:07:51 OCTOBER 21, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION 9.1 +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_location_assignment PIN_L1 -to clk_50MHz +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE AUTO +set_location_assignment PIN_J2 -to led1[0] +set_location_assignment PIN_J1 -to led1[1] +set_location_assignment PIN_H2 -to led1[2] +set_location_assignment PIN_H1 -to led1[3] +set_location_assignment PIN_F2 -to led1[4] +set_location_assignment PIN_F1 -to led1[5] +set_location_assignment PIN_E2 -to led1[6] +set_location_assignment PIN_E1 -to led2[0] +set_location_assignment PIN_H6 -to led2[1] +set_location_assignment PIN_H5 -to led2[2] +set_location_assignment PIN_H4 -to led2[3] +set_location_assignment PIN_G3 -to led2[4] +set_location_assignment PIN_D2 -to led2[5] +set_location_assignment PIN_D1 -to led2[6] +set_location_assignment PIN_G5 -to led3[0] +set_location_assignment PIN_G6 -to led3[1] +set_location_assignment PIN_C2 -to led3[2] +set_location_assignment PIN_C1 -to led3[3] +set_location_assignment PIN_E3 -to led3[4] +set_location_assignment PIN_E4 -to led3[5] +set_location_assignment PIN_D3 -to led3[6] +set_location_assignment PIN_F4 -to led4[0] +set_location_assignment PIN_D5 -to led4[1] +set_location_assignment PIN_D6 -to led4[2] +set_location_assignment PIN_J4 -to led4[3] +set_location_assignment PIN_L8 -to led4[4] +set_location_assignment PIN_F3 -to led4[5] +set_location_assignment PIN_D4 -to led4[6] +set_global_assignment -name MISC_FILE "C:/Users/ProGOLD/Desktop/Политех/Altera DE1/myArkanoid/myArkanoid.dpf" +set_location_assignment PIN_D9 -to red[0] +set_location_assignment PIN_C9 -to red[1] +set_location_assignment PIN_A7 -to red[2] +set_location_assignment PIN_B7 -to red[3] +set_location_assignment PIN_B8 -to green[0] +set_location_assignment PIN_C10 -to green[1] +set_location_assignment PIN_B9 -to green[2] +set_location_assignment PIN_A8 -to green[3] +set_location_assignment PIN_A9 -to blue[0] +set_location_assignment PIN_D11 -to blue[1] +set_location_assignment PIN_A10 -to blue[2] +set_location_assignment PIN_B10 -to blue[3] +set_location_assignment PIN_T21 -to button1 +set_location_assignment PIN_T22 -to button2 +set_location_assignment PIN_R21 -to button3 +set_location_assignment PIN_R22 -to button4 +set_location_assignment PIN_A11 -to h_sync +set_location_assignment PIN_B11 -to v_sync +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name MISC_FILE "C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/myArkanoid.dpf" +set_global_assignment -name BDF_FILE TotalScheme.bdf +set_global_assignment -name VERILOG_FILE Arkanoid.v +set_global_assignment -name VECTOR_WAVEFORM_FILE myArkanoid.vwf +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE myArkanoid.vwf +set_location_assignment PIN_U22 -to led[0] +set_location_assignment PIN_U21 -to led[1] +set_location_assignment PIN_V22 -to led[2] +set_location_assignment PIN_V21 -to led[3] +set_location_assignment PIN_W22 -to led[4] +set_location_assignment PIN_W21 -to led[5] +set_location_assignment PIN_Y22 -to led[6] +set_location_assignment PIN_Y21 -to led[7] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/myArkanoid.qsf.bak b/myArkanoid.qsf.bak new file mode 100644 index 0000000..25496f6 --- /dev/null +++ b/myArkanoid.qsf.bak @@ -0,0 +1,121 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +# Date created = 14:07:51 October 21, 2009 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# myArkanoid_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C20F484C7 +set_global_assignment -name TOP_LEVEL_ENTITY myArkanoidSchematic +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:07:51 OCTOBER 21, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION 9.1 +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name BDF_FILE myArkanoidSchematic.bdf +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_location_assignment PIN_L1 -to clk_50MHz +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE AREA +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON +set_global_assignment -name MUX_RESTRUCTURE ON +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION ALWAYS +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_global_assignment -name IGNORE_LCELL_BUFFERS ON +set_global_assignment -name IGNORE_CASCADE_BUFFERS ON +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4 +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" +set_location_assignment PIN_J2 -to led1[0] +set_location_assignment PIN_J1 -to led1[1] +set_location_assignment PIN_H2 -to led1[2] +set_location_assignment PIN_H1 -to led1[3] +set_location_assignment PIN_F2 -to led1[4] +set_location_assignment PIN_F1 -to led1[5] +set_location_assignment PIN_E2 -to led1[6] +set_location_assignment PIN_E1 -to led2[0] +set_location_assignment PIN_H6 -to led2[1] +set_location_assignment PIN_H5 -to led2[2] +set_location_assignment PIN_H4 -to led2[3] +set_location_assignment PIN_G3 -to led2[4] +set_location_assignment PIN_D2 -to led2[5] +set_location_assignment PIN_D1 -to led2[6] +set_location_assignment PIN_G5 -to led3[0] +set_location_assignment PIN_G6 -to led3[1] +set_location_assignment PIN_C2 -to led3[2] +set_location_assignment PIN_C1 -to led3[3] +set_location_assignment PIN_E3 -to led3[4] +set_location_assignment PIN_E4 -to led3[5] +set_location_assignment PIN_D3 -to led3[6] +set_location_assignment PIN_F4 -to led4[0] +set_location_assignment PIN_D5 -to led4[1] +set_location_assignment PIN_D6 -to led4[2] +set_location_assignment PIN_J4 -to led4[3] +set_location_assignment PIN_L8 -to led4[4] +set_location_assignment PIN_F3 -to led4[5] +set_location_assignment PIN_D4 -to led4[6] +set_global_assignment -name VHDL_FILE FrequencyDivider.vhd +set_global_assignment -name VERILOG_FILE Arkanoid.v +set_global_assignment -name MISC_FILE "C:/Users/ProGOLD/Desktop/Политех/Altera DE1/myArkanoid/myArkanoid.dpf" +set_location_assignment PIN_D9 -to red[0] +set_location_assignment PIN_C9 -to red[1] +set_location_assignment PIN_A7 -to red[2] +set_location_assignment PIN_B7 -to red[3] +set_location_assignment PIN_B8 -to green[0] +set_location_assignment PIN_C10 -to green[1] +set_location_assignment PIN_B9 -to green[2] +set_location_assignment PIN_A8 -to green[3] +set_location_assignment PIN_A9 -to blue[0] +set_location_assignment PIN_D11 -to blue[1] +set_location_assignment PIN_A10 -to blue[2] +set_location_assignment PIN_B10 -to blue[3] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_location_assignment PIN_R22 -to button1 +set_location_assignment PIN_R21 -to button2 +set_location_assignment PIN_T22 -to button3 +set_location_assignment PIN_T21 -to button4 +set_location_assignment PIN_A11 -to h_sync +set_location_assignment PIN_B11 -to v_sync \ No newline at end of file diff --git a/myArkanoid.qws b/myArkanoid.qws new file mode 100644 index 0000000..cf60227 --- /dev/null +++ b/myArkanoid.qws @@ -0,0 +1,16 @@ +[ProjectWorkspace] +ptn_Child1=Frames +[ProjectWorkspace.Frames] +ptn_Child1=ChildFrames +[ProjectWorkspace.Frames.ChildFrames] +ptn_Child1=Document-0 +[ProjectWorkspace.Frames.ChildFrames.Document-0] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0] +DocPathName=Arkanoid.v +DocumentCLSID={84678d98-dc76-11d0-a0d8-0020affa5bde} +IsChildFrameDetached=False +IsActiveChildFrame=True +ptn_Child1=StateMap +[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0.StateMap] +AFC_IN_REPORT=False diff --git a/myArkanoid.sim.rpt b/myArkanoid.sim.rpt new file mode 100644 index 0000000..51aafe3 --- /dev/null +++ b/myArkanoid.sim.rpt @@ -0,0 +1,289 @@ +Simulator report for myArkanoid +Mon May 21 14:05:52 2012 +Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Simulator Summary + 3. Simulator Settings + 4. Simulation Waveforms + 5. Coverage Summary + 6. Complete 1/0-Value Coverage + 7. Missing 1-Value Coverage + 8. Missing 0-Value Coverage + 9. Simulator INI Usage + 10. Simulator Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------+ +; Simulator Summary ; ++-----------------------------+--------------+ +; Type ; Value ; ++-----------------------------+--------------+ +; Simulation Start Time ; 0 ps ; +; Simulation End Time ; 50.0 ms ; +; Simulation Netlist Size ; 67 nodes ; +; Simulation Coverage ; 0.00 % ; +; Total Number of Transitions ; 0 ; +; Simulation Breakpoints ; 0 ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; ++-----------------------------+--------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Simulator Settings ; ++--------------------------------------------------------------------------------------------+----------------+---------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------------------------------+----------------+---------------+ +; Simulation mode ; Timing ; Timing ; +; Start time ; 0 ns ; 0 ns ; +; Simulation results format ; CVWF ; ; +; Vector input source ; myArkanoid.vwf ; ; +; Add pins automatically to simulation output waveforms ; On ; On ; +; Check outputs ; Off ; Off ; +; Report simulation coverage ; On ; On ; +; Display complete 1/0 value coverage report ; On ; On ; +; Display missing 1-value coverage report ; On ; On ; +; Display missing 0-value coverage report ; On ; On ; +; Detect setup and hold time violations ; Off ; Off ; +; Detect glitches ; Off ; Off ; +; Disable timing delays in Timing Simulation ; Off ; Off ; +; Generate Signal Activity File ; Off ; Off ; +; Generate VCD File for PowerPlay Power Analyzer ; Off ; Off ; +; Group bus channels in simulation results ; Off ; Off ; +; Preserve fewer signal transitions to reduce memory requirements ; On ; On ; +; Trigger vector comparison with the specified mode ; INPUT_EDGE ; INPUT_EDGE ; +; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off ; Off ; +; Overwrite Waveform Inputs With Simulation Outputs ; Off ; ; +; Perform Glitch Filtering in Timing Simulation ; Auto ; Auto ; ++--------------------------------------------------------------------------------------------+----------------+---------------+ + + ++----------------------+ +; Simulation Waveforms ; ++----------------------+ +Waveform report data cannot be output to ASCII. +Please use Quartus II to view the waveform report data. + + ++--------------------------------------------------------------------+ +; Coverage Summary ; ++-----------------------------------------------------+--------------+ +; Type ; Value ; ++-----------------------------------------------------+--------------+ +; Total coverage as a percentage ; 0.00 % ; +; Total nodes checked ; 67 ; +; Total output ports checked ; 62 ; +; Total output ports with complete 1/0-value coverage ; 0 ; +; Total output ports with no 1/0-value coverage ; 62 ; +; Total output ports with no 1-value coverage ; 62 ; +; Total output ports with no 0-value coverage ; 62 ; ++-----------------------------------------------------+--------------+ + + +The following table displays output ports that toggle between 1 and 0 during simulation. ++-------------------------------------------------+ +; Complete 1/0-Value Coverage ; ++-----------+------------------+------------------+ +; Node Name ; Output Port Name ; Output Port Type ; ++-----------+------------------+------------------+ + + +The following table displays output ports that do not toggle to 1 during simulation. ++------------------------------------------------------------------+ +; Missing 1-Value Coverage ; ++-----------------------+-----------------------+------------------+ +; Node Name ; Output Port Name ; Output Port Type ; ++-----------------------+-----------------------+------------------+ +; |TotalScheme|h_sync ; |TotalScheme|h_sync ; padio ; +; |TotalScheme|v_sync ; |TotalScheme|v_sync ; padio ; +; |TotalScheme|blue[3] ; |TotalScheme|blue[3] ; padio ; +; |TotalScheme|blue[2] ; |TotalScheme|blue[2] ; padio ; +; |TotalScheme|blue[1] ; |TotalScheme|blue[1] ; padio ; +; |TotalScheme|blue[0] ; |TotalScheme|blue[0] ; padio ; +; |TotalScheme|green[3] ; |TotalScheme|green[3] ; padio ; +; |TotalScheme|green[2] ; |TotalScheme|green[2] ; padio ; +; |TotalScheme|green[1] ; |TotalScheme|green[1] ; padio ; +; |TotalScheme|green[0] ; |TotalScheme|green[0] ; padio ; +; |TotalScheme|hort[9] ; |TotalScheme|hort[9] ; padio ; +; |TotalScheme|hort[8] ; |TotalScheme|hort[8] ; padio ; +; |TotalScheme|hort[7] ; |TotalScheme|hort[7] ; padio ; +; |TotalScheme|hort[6] ; |TotalScheme|hort[6] ; padio ; +; |TotalScheme|hort[5] ; |TotalScheme|hort[5] ; padio ; +; |TotalScheme|hort[4] ; |TotalScheme|hort[4] ; padio ; +; |TotalScheme|hort[3] ; |TotalScheme|hort[3] ; padio ; +; |TotalScheme|hort[2] ; |TotalScheme|hort[2] ; padio ; +; |TotalScheme|hort[1] ; |TotalScheme|hort[1] ; padio ; +; |TotalScheme|hort[0] ; |TotalScheme|hort[0] ; padio ; +; |TotalScheme|led1[6] ; |TotalScheme|led1[6] ; padio ; +; |TotalScheme|led1[5] ; |TotalScheme|led1[5] ; padio ; +; |TotalScheme|led1[4] ; |TotalScheme|led1[4] ; padio ; +; |TotalScheme|led1[3] ; |TotalScheme|led1[3] ; padio ; +; |TotalScheme|led1[2] ; |TotalScheme|led1[2] ; padio ; +; |TotalScheme|led1[1] ; |TotalScheme|led1[1] ; padio ; +; |TotalScheme|led1[0] ; |TotalScheme|led1[0] ; padio ; +; |TotalScheme|led2[6] ; |TotalScheme|led2[6] ; padio ; +; |TotalScheme|led2[5] ; |TotalScheme|led2[5] ; padio ; +; |TotalScheme|led2[4] ; |TotalScheme|led2[4] ; padio ; +; |TotalScheme|led2[3] ; |TotalScheme|led2[3] ; padio ; +; |TotalScheme|led2[2] ; |TotalScheme|led2[2] ; padio ; +; |TotalScheme|led2[1] ; |TotalScheme|led2[1] ; padio ; +; |TotalScheme|led2[0] ; |TotalScheme|led2[0] ; padio ; +; |TotalScheme|led3[6] ; |TotalScheme|led3[6] ; padio ; +; |TotalScheme|led3[5] ; |TotalScheme|led3[5] ; padio ; +; |TotalScheme|led3[4] ; |TotalScheme|led3[4] ; padio ; +; |TotalScheme|led3[3] ; |TotalScheme|led3[3] ; padio ; +; |TotalScheme|led3[2] ; |TotalScheme|led3[2] ; padio ; +; |TotalScheme|led3[1] ; |TotalScheme|led3[1] ; padio ; +; |TotalScheme|led3[0] ; |TotalScheme|led3[0] ; padio ; +; |TotalScheme|led4[6] ; |TotalScheme|led4[6] ; padio ; +; |TotalScheme|led4[5] ; |TotalScheme|led4[5] ; padio ; +; |TotalScheme|led4[4] ; |TotalScheme|led4[4] ; padio ; +; |TotalScheme|led4[3] ; |TotalScheme|led4[3] ; padio ; +; |TotalScheme|led4[2] ; |TotalScheme|led4[2] ; padio ; +; |TotalScheme|led4[1] ; |TotalScheme|led4[1] ; padio ; +; |TotalScheme|led4[0] ; |TotalScheme|led4[0] ; padio ; +; |TotalScheme|red[3] ; |TotalScheme|red[3] ; padio ; +; |TotalScheme|red[2] ; |TotalScheme|red[2] ; padio ; +; |TotalScheme|red[1] ; |TotalScheme|red[1] ; padio ; +; |TotalScheme|red[0] ; |TotalScheme|red[0] ; padio ; +; |TotalScheme|vert[9] ; |TotalScheme|vert[9] ; padio ; +; |TotalScheme|vert[8] ; |TotalScheme|vert[8] ; padio ; +; |TotalScheme|vert[7] ; |TotalScheme|vert[7] ; padio ; +; |TotalScheme|vert[6] ; |TotalScheme|vert[6] ; padio ; +; |TotalScheme|vert[5] ; |TotalScheme|vert[5] ; padio ; +; |TotalScheme|vert[4] ; |TotalScheme|vert[4] ; padio ; +; |TotalScheme|vert[3] ; |TotalScheme|vert[3] ; padio ; +; |TotalScheme|vert[2] ; |TotalScheme|vert[2] ; padio ; +; |TotalScheme|vert[1] ; |TotalScheme|vert[1] ; padio ; +; |TotalScheme|vert[0] ; |TotalScheme|vert[0] ; padio ; ++-----------------------+-----------------------+------------------+ + + +The following table displays output ports that do not toggle to 0 during simulation. ++------------------------------------------------------------------+ +; Missing 0-Value Coverage ; ++-----------------------+-----------------------+------------------+ +; Node Name ; Output Port Name ; Output Port Type ; ++-----------------------+-----------------------+------------------+ +; |TotalScheme|h_sync ; |TotalScheme|h_sync ; padio ; +; |TotalScheme|v_sync ; |TotalScheme|v_sync ; padio ; +; |TotalScheme|blue[3] ; |TotalScheme|blue[3] ; padio ; +; |TotalScheme|blue[2] ; |TotalScheme|blue[2] ; padio ; +; |TotalScheme|blue[1] ; |TotalScheme|blue[1] ; padio ; +; |TotalScheme|blue[0] ; |TotalScheme|blue[0] ; padio ; +; |TotalScheme|green[3] ; |TotalScheme|green[3] ; padio ; +; |TotalScheme|green[2] ; |TotalScheme|green[2] ; padio ; +; |TotalScheme|green[1] ; |TotalScheme|green[1] ; padio ; +; |TotalScheme|green[0] ; |TotalScheme|green[0] ; padio ; +; |TotalScheme|hort[9] ; |TotalScheme|hort[9] ; padio ; +; |TotalScheme|hort[8] ; |TotalScheme|hort[8] ; padio ; +; |TotalScheme|hort[7] ; |TotalScheme|hort[7] ; padio ; +; |TotalScheme|hort[6] ; |TotalScheme|hort[6] ; padio ; +; |TotalScheme|hort[5] ; |TotalScheme|hort[5] ; padio ; +; |TotalScheme|hort[4] ; |TotalScheme|hort[4] ; padio ; +; |TotalScheme|hort[3] ; |TotalScheme|hort[3] ; padio ; +; |TotalScheme|hort[2] ; |TotalScheme|hort[2] ; padio ; +; |TotalScheme|hort[1] ; |TotalScheme|hort[1] ; padio ; +; |TotalScheme|hort[0] ; |TotalScheme|hort[0] ; padio ; +; |TotalScheme|led1[6] ; |TotalScheme|led1[6] ; padio ; +; |TotalScheme|led1[5] ; |TotalScheme|led1[5] ; padio ; +; |TotalScheme|led1[4] ; |TotalScheme|led1[4] ; padio ; +; |TotalScheme|led1[3] ; |TotalScheme|led1[3] ; padio ; +; |TotalScheme|led1[2] ; |TotalScheme|led1[2] ; padio ; +; |TotalScheme|led1[1] ; |TotalScheme|led1[1] ; padio ; +; |TotalScheme|led1[0] ; |TotalScheme|led1[0] ; padio ; +; |TotalScheme|led2[6] ; |TotalScheme|led2[6] ; padio ; +; |TotalScheme|led2[5] ; |TotalScheme|led2[5] ; padio ; +; |TotalScheme|led2[4] ; |TotalScheme|led2[4] ; padio ; +; |TotalScheme|led2[3] ; |TotalScheme|led2[3] ; padio ; +; |TotalScheme|led2[2] ; |TotalScheme|led2[2] ; padio ; +; |TotalScheme|led2[1] ; |TotalScheme|led2[1] ; padio ; +; |TotalScheme|led2[0] ; |TotalScheme|led2[0] ; padio ; +; |TotalScheme|led3[6] ; |TotalScheme|led3[6] ; padio ; +; |TotalScheme|led3[5] ; |TotalScheme|led3[5] ; padio ; +; |TotalScheme|led3[4] ; |TotalScheme|led3[4] ; padio ; +; |TotalScheme|led3[3] ; |TotalScheme|led3[3] ; padio ; +; |TotalScheme|led3[2] ; |TotalScheme|led3[2] ; padio ; +; |TotalScheme|led3[1] ; |TotalScheme|led3[1] ; padio ; +; |TotalScheme|led3[0] ; |TotalScheme|led3[0] ; padio ; +; |TotalScheme|led4[6] ; |TotalScheme|led4[6] ; padio ; +; |TotalScheme|led4[5] ; |TotalScheme|led4[5] ; padio ; +; |TotalScheme|led4[4] ; |TotalScheme|led4[4] ; padio ; +; |TotalScheme|led4[3] ; |TotalScheme|led4[3] ; padio ; +; |TotalScheme|led4[2] ; |TotalScheme|led4[2] ; padio ; +; |TotalScheme|led4[1] ; |TotalScheme|led4[1] ; padio ; +; |TotalScheme|led4[0] ; |TotalScheme|led4[0] ; padio ; +; |TotalScheme|red[3] ; |TotalScheme|red[3] ; padio ; +; |TotalScheme|red[2] ; |TotalScheme|red[2] ; padio ; +; |TotalScheme|red[1] ; |TotalScheme|red[1] ; padio ; +; |TotalScheme|red[0] ; |TotalScheme|red[0] ; padio ; +; |TotalScheme|vert[9] ; |TotalScheme|vert[9] ; padio ; +; |TotalScheme|vert[8] ; |TotalScheme|vert[8] ; padio ; +; |TotalScheme|vert[7] ; |TotalScheme|vert[7] ; padio ; +; |TotalScheme|vert[6] ; |TotalScheme|vert[6] ; padio ; +; |TotalScheme|vert[5] ; |TotalScheme|vert[5] ; padio ; +; |TotalScheme|vert[4] ; |TotalScheme|vert[4] ; padio ; +; |TotalScheme|vert[3] ; |TotalScheme|vert[3] ; padio ; +; |TotalScheme|vert[2] ; |TotalScheme|vert[2] ; padio ; +; |TotalScheme|vert[1] ; |TotalScheme|vert[1] ; padio ; +; |TotalScheme|vert[0] ; |TotalScheme|vert[0] ; padio ; ++-----------------------+-----------------------+------------------+ + + ++---------------------+ +; Simulator INI Usage ; ++--------+------------+ +; Option ; Usage ; ++--------+------------+ + + ++--------------------+ +; Simulator Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II Simulator + Info: Version 9.1 Build 222 10/21/2009 SJ Full Version + Info: Processing started: Mon May 21 14:02:19 2012 +Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid +Info: Using vector source file "C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/myArkanoid.vwf" +Warning: Can't find signal in vector source file for input pin "|TotalScheme|button1" +Warning: Can't find signal in vector source file for input pin "|TotalScheme|button2" +Warning: Can't find signal in vector source file for input pin "|TotalScheme|button3" +Warning: Can't find signal in vector source file for input pin "|TotalScheme|button4" +Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled + Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements. +Info: Simulation partitioned into 1 sub-simulations +Info: Simulation coverage is 0.00 % +Info: Number of transitions in simulation is 0 +Info: Quartus II Simulator was successful. 0 errors, 4 warnings + Info: Peak virtual memory: 136 megabytes + Info: Processing ended: Mon May 21 14:05:53 2012 + Info: Elapsed time: 00:03:34 + Info: Total CPU time (on all processors): 00:03:34 + + diff --git a/myArkanoid.sof b/myArkanoid.sof new file mode 100644 index 0000000..909d807 Binary files /dev/null and b/myArkanoid.sof differ diff --git a/myArkanoid.tan.rpt b/myArkanoid.tan.rpt new file mode 100644 index 0000000..1dd120f --- /dev/null +++ b/myArkanoid.tan.rpt @@ -0,0 +1,1169 @@ +Classic Timing Analyzer report for myArkanoid +Mon May 21 19:54:43 2012 +Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Timing Analyzer Settings + 4. Clock Settings Summary + 5. Parallel Compilation + 6. Clock Setup: 'clk_50MHz' + 7. tsu + 8. tco + 9. th + 10. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++------------------------------+-------+---------------+----------------------------------+----------------------------+--------------------------------------+------------+-----------+--------------+ +; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; ++------------------------------+-------+---------------+----------------------------------+----------------------------+--------------------------------------+------------+-----------+--------------+ +; Worst-case tsu ; N/A ; None ; 32.749 ns ; button3 ; Arkanoid:inst|blue_[0] ; -- ; clk_50MHz ; 0 ; +; Worst-case tco ; N/A ; None ; 15.668 ns ; Arkanoid:inst|v_counter[8] ; v_sync ; clk_50MHz ; -- ; 0 ; +; Worst-case th ; N/A ; None ; -2.062 ns ; button2 ; Arkanoid:inst|platform1_position[29] ; -- ; clk_50MHz ; 0 ; +; Clock Setup: 'clk_50MHz' ; N/A ; None ; 9.70 MHz ( period = 103.135 ns ) ; Arkanoid:inst|h_counter[1] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; 0 ; +; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; ++------------------------------+-------+---------------+----------------------------------+----------------------------+--------------------------------------+------------+-----------+--------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Settings ; ++------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+ +; Option ; Setting ; From ; To ; Entity Name ; ++------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+ +; Device Name ; EP2C20F484C7 ; ; ; ; +; Timing Models ; Final ; ; ; ; +; Default hold multicycle ; Same as Multicycle ; ; ; ; +; Cut paths between unrelated clock domains ; On ; ; ; ; +; Cut off read during write signal paths ; On ; ; ; ; +; Cut off feedback from I/O pins ; On ; ; ; ; +; Report Combined Fast/Slow Timing ; Off ; ; ; ; +; Ignore Clock Settings ; Off ; ; ; ; +; Analyze latches as synchronous elements ; On ; ; ; ; +; Enable Recovery/Removal analysis ; Off ; ; ; ; +; Enable Clock Latency ; Off ; ; ; ; +; Use TimeQuest Timing Analyzer ; Off ; ; ; ; +; Minimum Core Junction Temperature ; 0 ; ; ; ; +; Maximum Core Junction Temperature ; 85 ; ; ; ; +; Number of source nodes to report per destination node ; 10 ; ; ; ; +; Number of destination nodes to report ; 10 ; ; ; ; +; Number of paths to report ; 200 ; ; ; ; +; Report Minimum Timing Checks ; Off ; ; ; ; +; Use Fast Timing Models ; Off ; ; ; ; +; Report IO Paths Separately ; Off ; ; ; ; +; Perform Multicorner Analysis ; On ; ; ; ; +; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; +; Reports worst-case timing paths for each clock domain and analysis ; On ; ; ; ; +; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100 ; ; ; ; +; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ; +; Output I/O Timing Endpoint ; Near End ; ; ; ; ++------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Settings Summary ; ++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ +; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ; ++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ +; clk_50MHz ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; ++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 2 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; 1 processor ; 100.0% ; +; 2 processors ; 0.0% ; ++----------------------------+-------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'clk_50MHz' ; ++-----------------------------------------+-----------------------------------------------------+-----------------------------+-------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-----------------------------------------+-----------------------------------------------------+-----------------------------+-------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+ +; N/A ; 9.70 MHz ( period = 103.135 ns ) ; Arkanoid:inst|h_counter[1] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.875 ns ; +; N/A ; 9.71 MHz ( period = 102.993 ns ) ; Arkanoid:inst|h_counter[1] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.733 ns ; +; N/A ; 9.71 MHz ( period = 102.991 ns ) ; Arkanoid:inst|h_counter[1] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.731 ns ; +; N/A ; 9.71 MHz ( period = 102.941 ns ) ; Arkanoid:inst|h_counter[1] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.681 ns ; +; N/A ; 9.73 MHz ( period = 102.825 ns ) ; Arkanoid:inst|h_counter[0] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.582 ns ; +; N/A ; 9.73 MHz ( period = 102.761 ns ) ; Arkanoid:inst|h_counter[2] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.518 ns ; +; N/A ; 9.74 MHz ( period = 102.721 ns ) ; Arkanoid:inst|h_counter[3] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.478 ns ; +; N/A ; 9.74 MHz ( period = 102.683 ns ) ; Arkanoid:inst|h_counter[0] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.440 ns ; +; N/A ; 9.74 MHz ( period = 102.681 ns ) ; Arkanoid:inst|h_counter[0] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.438 ns ; +; N/A ; 9.74 MHz ( period = 102.631 ns ) ; Arkanoid:inst|h_counter[0] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.388 ns ; +; N/A ; 9.74 MHz ( period = 102.619 ns ) ; Arkanoid:inst|h_counter[2] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.376 ns ; +; N/A ; 9.74 MHz ( period = 102.617 ns ) ; Arkanoid:inst|h_counter[2] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.374 ns ; +; N/A ; 9.75 MHz ( period = 102.598 ns ) ; Arkanoid:inst|h_counter[4] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.355 ns ; +; N/A ; 9.75 MHz ( period = 102.579 ns ) ; Arkanoid:inst|h_counter[3] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.336 ns ; +; N/A ; 9.75 MHz ( period = 102.577 ns ) ; Arkanoid:inst|h_counter[3] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.334 ns ; +; N/A ; 9.75 MHz ( period = 102.567 ns ) ; Arkanoid:inst|h_counter[2] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.324 ns ; +; N/A ; 9.75 MHz ( period = 102.558 ns ) ; Arkanoid:inst|h_counter[5] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.315 ns ; +; N/A ; 9.75 MHz ( period = 102.527 ns ) ; Arkanoid:inst|h_counter[3] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.284 ns ; +; N/A ; 9.76 MHz ( period = 102.478 ns ) ; Arkanoid:inst|h_counter[6] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.235 ns ; +; N/A ; 9.76 MHz ( period = 102.456 ns ) ; Arkanoid:inst|h_counter[4] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.213 ns ; +; N/A ; 9.76 MHz ( period = 102.454 ns ) ; Arkanoid:inst|h_counter[4] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.211 ns ; +; N/A ; 9.76 MHz ( period = 102.416 ns ) ; Arkanoid:inst|h_counter[5] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.173 ns ; +; N/A ; 9.76 MHz ( period = 102.414 ns ) ; Arkanoid:inst|h_counter[5] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.171 ns ; +; N/A ; 9.77 MHz ( period = 102.404 ns ) ; Arkanoid:inst|h_counter[4] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.161 ns ; +; N/A ; 9.77 MHz ( period = 102.365 ns ) ; Arkanoid:inst|h_counter[7] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.122 ns ; +; N/A ; 9.77 MHz ( period = 102.364 ns ) ; Arkanoid:inst|h_counter[5] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.121 ns ; +; N/A ; 9.77 MHz ( period = 102.336 ns ) ; Arkanoid:inst|h_counter[6] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.093 ns ; +; N/A ; 9.77 MHz ( period = 102.334 ns ) ; Arkanoid:inst|h_counter[6] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.091 ns ; +; N/A ; 9.78 MHz ( period = 102.296 ns ) ; Arkanoid:inst|h_counter[1] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.036 ns ; +; N/A ; 9.78 MHz ( period = 102.294 ns ) ; Arkanoid:inst|h_counter[1] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.034 ns ; +; N/A ; 9.78 MHz ( period = 102.293 ns ) ; Arkanoid:inst|h_counter[1] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.033 ns ; +; N/A ; 9.78 MHz ( period = 102.290 ns ) ; Arkanoid:inst|h_counter[1] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.030 ns ; +; N/A ; 9.78 MHz ( period = 102.284 ns ) ; Arkanoid:inst|h_counter[6] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.041 ns ; +; N/A ; 9.78 MHz ( period = 102.254 ns ) ; Arkanoid:inst|v_counter[1] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 102.007 ns ; +; N/A ; 9.78 MHz ( period = 102.223 ns ) ; Arkanoid:inst|h_counter[7] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.980 ns ; +; N/A ; 9.78 MHz ( period = 102.221 ns ) ; Arkanoid:inst|h_counter[7] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.978 ns ; +; N/A ; 9.78 MHz ( period = 102.219 ns ) ; Arkanoid:inst|h_counter[8] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.976 ns ; +; N/A ; 9.79 MHz ( period = 102.182 ns ) ; Arkanoid:inst|v_counter[2] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.935 ns ; +; N/A ; 9.79 MHz ( period = 102.171 ns ) ; Arkanoid:inst|h_counter[7] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.928 ns ; +; N/A ; 9.79 MHz ( period = 102.147 ns ) ; Arkanoid:inst|v_counter[3] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.900 ns ; +; N/A ; 9.79 MHz ( period = 102.102 ns ) ; Arkanoid:inst|v_counter[1] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.855 ns ; +; N/A ; 9.79 MHz ( period = 102.095 ns ) ; Arkanoid:inst|h_counter[9] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.852 ns ; +; N/A ; 9.80 MHz ( period = 102.077 ns ) ; Arkanoid:inst|h_counter[8] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.834 ns ; +; N/A ; 9.80 MHz ( period = 102.075 ns ) ; Arkanoid:inst|h_counter[8] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.832 ns ; +; N/A ; 9.80 MHz ( period = 102.060 ns ) ; Arkanoid:inst|h_counter[10] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.817 ns ; +; N/A ; 9.80 MHz ( period = 102.049 ns ) ; Arkanoid:inst|v_counter[1] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.802 ns ; +; N/A ; 9.80 MHz ( period = 102.030 ns ) ; Arkanoid:inst|v_counter[2] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.783 ns ; +; N/A ; 9.80 MHz ( period = 102.025 ns ) ; Arkanoid:inst|h_counter[8] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.782 ns ; +; N/A ; 9.80 MHz ( period = 102.023 ns ) ; Arkanoid:inst|v_counter[4] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.776 ns ; +; N/A ; 9.80 MHz ( period = 101.995 ns ) ; Arkanoid:inst|v_counter[3] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.748 ns ; +; N/A ; 9.81 MHz ( period = 101.987 ns ) ; Arkanoid:inst|v_counter[5] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.740 ns ; +; N/A ; 9.81 MHz ( period = 101.986 ns ) ; Arkanoid:inst|h_counter[0] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.743 ns ; +; N/A ; 9.81 MHz ( period = 101.984 ns ) ; Arkanoid:inst|h_counter[0] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.741 ns ; +; N/A ; 9.81 MHz ( period = 101.983 ns ) ; Arkanoid:inst|h_counter[0] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.740 ns ; +; N/A ; 9.81 MHz ( period = 101.980 ns ) ; Arkanoid:inst|h_counter[0] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.737 ns ; +; N/A ; 9.81 MHz ( period = 101.977 ns ) ; Arkanoid:inst|v_counter[2] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.730 ns ; +; N/A ; 9.81 MHz ( period = 101.953 ns ) ; Arkanoid:inst|h_counter[9] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.710 ns ; +; N/A ; 9.81 MHz ( period = 101.951 ns ) ; Arkanoid:inst|h_counter[9] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.708 ns ; +; N/A ; 9.81 MHz ( period = 101.942 ns ) ; Arkanoid:inst|v_counter[3] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.695 ns ; +; N/A ; 9.81 MHz ( period = 101.935 ns ) ; Arkanoid:inst|h_counter[11] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.692 ns ; +; N/A ; 9.81 MHz ( period = 101.922 ns ) ; Arkanoid:inst|h_counter[2] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.679 ns ; +; N/A ; 9.81 MHz ( period = 101.920 ns ) ; Arkanoid:inst|h_counter[2] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.677 ns ; +; N/A ; 9.81 MHz ( period = 101.919 ns ) ; Arkanoid:inst|h_counter[2] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.676 ns ; +; N/A ; 9.81 MHz ( period = 101.918 ns ) ; Arkanoid:inst|h_counter[10] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.675 ns ; +; N/A ; 9.81 MHz ( period = 101.916 ns ) ; Arkanoid:inst|h_counter[10] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.673 ns ; +; N/A ; 9.81 MHz ( period = 101.916 ns ) ; Arkanoid:inst|h_counter[2] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.673 ns ; +; N/A ; 9.81 MHz ( period = 101.910 ns ) ; Arkanoid:inst|v_counter[6] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.663 ns ; +; N/A ; 9.81 MHz ( period = 101.901 ns ) ; Arkanoid:inst|h_counter[9] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.658 ns ; +; N/A ; 9.81 MHz ( period = 101.900 ns ) ; Arkanoid:inst|h_counter[12] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.657 ns ; +; N/A ; 9.82 MHz ( period = 101.882 ns ) ; Arkanoid:inst|h_counter[3] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.639 ns ; +; N/A ; 9.82 MHz ( period = 101.880 ns ) ; Arkanoid:inst|h_counter[3] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.637 ns ; +; N/A ; 9.82 MHz ( period = 101.879 ns ) ; Arkanoid:inst|h_counter[3] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.636 ns ; +; N/A ; 9.82 MHz ( period = 101.876 ns ) ; Arkanoid:inst|h_counter[3] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.633 ns ; +; N/A ; 9.82 MHz ( period = 101.871 ns ) ; Arkanoid:inst|v_counter[4] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.624 ns ; +; N/A ; 9.82 MHz ( period = 101.866 ns ) ; Arkanoid:inst|h_counter[10] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.623 ns ; +; N/A ; 9.82 MHz ( period = 101.835 ns ) ; Arkanoid:inst|v_counter[5] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.588 ns ; +; N/A ; 9.82 MHz ( period = 101.818 ns ) ; Arkanoid:inst|v_counter[4] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.571 ns ; +; N/A ; 9.82 MHz ( period = 101.796 ns ) ; Arkanoid:inst|v_counter[1] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.549 ns ; +; N/A ; 9.82 MHz ( period = 101.793 ns ) ; Arkanoid:inst|h_counter[11] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.550 ns ; +; N/A ; 9.82 MHz ( period = 101.791 ns ) ; Arkanoid:inst|h_counter[11] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.548 ns ; +; N/A ; 9.82 MHz ( period = 101.790 ns ) ; Arkanoid:inst|v_counter[7] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.543 ns ; +; N/A ; 9.82 MHz ( period = 101.782 ns ) ; Arkanoid:inst|v_counter[5] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.535 ns ; +; N/A ; 9.83 MHz ( period = 101.780 ns ) ; Arkanoid:inst|h_counter[13] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.537 ns ; +; N/A ; 9.83 MHz ( period = 101.759 ns ) ; Arkanoid:inst|h_counter[4] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.516 ns ; +; N/A ; 9.83 MHz ( period = 101.758 ns ) ; Arkanoid:inst|v_counter[6] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.511 ns ; +; N/A ; 9.83 MHz ( period = 101.758 ns ) ; Arkanoid:inst|h_counter[12] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.515 ns ; +; N/A ; 9.83 MHz ( period = 101.757 ns ) ; Arkanoid:inst|h_counter[4] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.514 ns ; +; N/A ; 9.83 MHz ( period = 101.756 ns ) ; Arkanoid:inst|h_counter[12] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.513 ns ; +; N/A ; 9.83 MHz ( period = 101.756 ns ) ; Arkanoid:inst|h_counter[4] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.513 ns ; +; N/A ; 9.83 MHz ( period = 101.753 ns ) ; Arkanoid:inst|h_counter[4] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.510 ns ; +; N/A ; 9.83 MHz ( period = 101.741 ns ) ; Arkanoid:inst|h_counter[11] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.498 ns ; +; N/A ; 9.83 MHz ( period = 101.724 ns ) ; Arkanoid:inst|v_counter[2] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.477 ns ; +; N/A ; 9.83 MHz ( period = 101.719 ns ) ; Arkanoid:inst|h_counter[5] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.476 ns ; +; N/A ; 9.83 MHz ( period = 101.717 ns ) ; Arkanoid:inst|h_counter[5] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.474 ns ; +; N/A ; 9.83 MHz ( period = 101.716 ns ) ; Arkanoid:inst|h_counter[5] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.473 ns ; +; N/A ; 9.83 MHz ( period = 101.713 ns ) ; Arkanoid:inst|h_counter[5] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.470 ns ; +; N/A ; 9.83 MHz ( period = 101.706 ns ) ; Arkanoid:inst|h_counter[12] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.463 ns ; +; N/A ; 9.83 MHz ( period = 101.705 ns ) ; Arkanoid:inst|v_counter[6] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.458 ns ; +; N/A ; 9.83 MHz ( period = 101.700 ns ) ; Arkanoid:inst|h_counter[14] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.457 ns ; +; N/A ; 9.83 MHz ( period = 101.689 ns ) ; Arkanoid:inst|v_counter[3] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.442 ns ; +; N/A ; 9.84 MHz ( period = 101.648 ns ) ; Arkanoid:inst|v_counter[8] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.401 ns ; +; N/A ; 9.84 MHz ( period = 101.639 ns ) ; Arkanoid:inst|h_counter[6] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.396 ns ; +; N/A ; 9.84 MHz ( period = 101.639 ns ) ; Arkanoid:inst|h_counter[15] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.396 ns ; +; N/A ; 9.84 MHz ( period = 101.638 ns ) ; Arkanoid:inst|v_counter[7] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.391 ns ; +; N/A ; 9.84 MHz ( period = 101.638 ns ) ; Arkanoid:inst|h_counter[13] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.395 ns ; +; N/A ; 9.84 MHz ( period = 101.637 ns ) ; Arkanoid:inst|v_counter[1] ; Arkanoid:inst|blue_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.390 ns ; +; N/A ; 9.84 MHz ( period = 101.637 ns ) ; Arkanoid:inst|h_counter[6] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.394 ns ; +; N/A ; 9.84 MHz ( period = 101.636 ns ) ; Arkanoid:inst|h_counter[13] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.393 ns ; +; N/A ; 9.84 MHz ( period = 101.636 ns ) ; Arkanoid:inst|h_counter[6] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.393 ns ; +; N/A ; 9.84 MHz ( period = 101.633 ns ) ; Arkanoid:inst|h_counter[6] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.390 ns ; +; N/A ; 9.84 MHz ( period = 101.586 ns ) ; Arkanoid:inst|h_counter[13] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.343 ns ; +; N/A ; 9.84 MHz ( period = 101.585 ns ) ; Arkanoid:inst|v_counter[7] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.338 ns ; +; N/A ; 9.85 MHz ( period = 101.565 ns ) ; Arkanoid:inst|v_counter[2] ; Arkanoid:inst|blue_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.318 ns ; +; N/A ; 9.85 MHz ( period = 101.565 ns ) ; Arkanoid:inst|v_counter[4] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.318 ns ; +; N/A ; 9.85 MHz ( period = 101.558 ns ) ; Arkanoid:inst|h_counter[14] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.315 ns ; +; N/A ; 9.85 MHz ( period = 101.556 ns ) ; Arkanoid:inst|h_counter[14] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.313 ns ; +; N/A ; 9.85 MHz ( period = 101.530 ns ) ; Arkanoid:inst|v_counter[3] ; Arkanoid:inst|blue_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.283 ns ; +; N/A ; 9.85 MHz ( period = 101.529 ns ) ; Arkanoid:inst|v_counter[5] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.282 ns ; +; N/A ; 9.85 MHz ( period = 101.526 ns ) ; Arkanoid:inst|h_counter[7] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.283 ns ; +; N/A ; 9.85 MHz ( period = 101.524 ns ) ; Arkanoid:inst|v_counter[9] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.277 ns ; +; N/A ; 9.85 MHz ( period = 101.524 ns ) ; Arkanoid:inst|h_counter[7] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.281 ns ; +; N/A ; 9.85 MHz ( period = 101.523 ns ) ; Arkanoid:inst|h_counter[7] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.280 ns ; +; N/A ; 9.85 MHz ( period = 101.520 ns ) ; Arkanoid:inst|h_counter[7] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.277 ns ; +; N/A ; 9.85 MHz ( period = 101.506 ns ) ; Arkanoid:inst|h_counter[14] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.263 ns ; +; N/A ; 9.85 MHz ( period = 101.497 ns ) ; Arkanoid:inst|h_counter[15] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.254 ns ; +; N/A ; 9.85 MHz ( period = 101.496 ns ) ; Arkanoid:inst|v_counter[8] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.249 ns ; +; N/A ; 9.85 MHz ( period = 101.495 ns ) ; Arkanoid:inst|h_counter[15] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.252 ns ; +; N/A ; 9.85 MHz ( period = 101.489 ns ) ; Arkanoid:inst|v_counter[10] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.242 ns ; +; N/A ; 9.86 MHz ( period = 101.452 ns ) ; Arkanoid:inst|v_counter[6] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.205 ns ; +; N/A ; 9.86 MHz ( period = 101.447 ns ) ; Arkanoid:inst|h_counter[16] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.207 ns ; +; N/A ; 9.86 MHz ( period = 101.445 ns ) ; Arkanoid:inst|h_counter[15] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.202 ns ; +; N/A ; 9.86 MHz ( period = 101.443 ns ) ; Arkanoid:inst|v_counter[8] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.196 ns ; +; N/A ; 9.86 MHz ( period = 101.415 ns ) ; Arkanoid:inst|v_counter[1] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.168 ns ; +; N/A ; 9.86 MHz ( period = 101.406 ns ) ; Arkanoid:inst|v_counter[4] ; Arkanoid:inst|blue_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.159 ns ; +; N/A ; 9.86 MHz ( period = 101.404 ns ) ; Arkanoid:inst|v_counter[1] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.157 ns ; +; N/A ; 9.86 MHz ( period = 101.402 ns ) ; Arkanoid:inst|v_counter[1] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.155 ns ; +; N/A ; 9.86 MHz ( period = 101.380 ns ) ; Arkanoid:inst|h_counter[8] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.137 ns ; +; N/A ; 9.86 MHz ( period = 101.378 ns ) ; Arkanoid:inst|h_counter[8] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.135 ns ; +; N/A ; 9.86 MHz ( period = 101.377 ns ) ; Arkanoid:inst|h_counter[8] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.134 ns ; +; N/A ; 9.86 MHz ( period = 101.374 ns ) ; Arkanoid:inst|h_counter[17] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.134 ns ; +; N/A ; 9.86 MHz ( period = 101.374 ns ) ; Arkanoid:inst|h_counter[8] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.131 ns ; +; N/A ; 9.86 MHz ( period = 101.372 ns ) ; Arkanoid:inst|v_counter[9] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.125 ns ; +; N/A ; 9.86 MHz ( period = 101.370 ns ) ; Arkanoid:inst|v_counter[5] ; Arkanoid:inst|blue_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.123 ns ; +; N/A ; 9.87 MHz ( period = 101.364 ns ) ; Arkanoid:inst|v_counter[11] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.117 ns ; +; N/A ; 9.87 MHz ( period = 101.343 ns ) ; Arkanoid:inst|v_counter[2] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.096 ns ; +; N/A ; 9.87 MHz ( period = 101.337 ns ) ; Arkanoid:inst|v_counter[10] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.090 ns ; +; N/A ; 9.87 MHz ( period = 101.332 ns ) ; Arkanoid:inst|v_counter[2] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.085 ns ; +; N/A ; 9.87 MHz ( period = 101.332 ns ) ; Arkanoid:inst|v_counter[7] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.085 ns ; +; N/A ; 9.87 MHz ( period = 101.330 ns ) ; Arkanoid:inst|v_counter[2] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.083 ns ; +; N/A ; 9.87 MHz ( period = 101.329 ns ) ; Arkanoid:inst|v_counter[12] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.082 ns ; +; N/A ; 9.87 MHz ( period = 101.319 ns ) ; Arkanoid:inst|v_counter[9] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.072 ns ; +; N/A ; 9.87 MHz ( period = 101.308 ns ) ; Arkanoid:inst|v_counter[3] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.061 ns ; +; N/A ; 9.87 MHz ( period = 101.305 ns ) ; Arkanoid:inst|h_counter[16] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.065 ns ; +; N/A ; 9.87 MHz ( period = 101.303 ns ) ; Arkanoid:inst|h_counter[16] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.063 ns ; +; N/A ; 9.87 MHz ( period = 101.297 ns ) ; Arkanoid:inst|v_counter[3] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.050 ns ; +; N/A ; 9.87 MHz ( period = 101.295 ns ) ; Arkanoid:inst|h_counter[18] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.055 ns ; +; N/A ; 9.87 MHz ( period = 101.295 ns ) ; Arkanoid:inst|v_counter[3] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.048 ns ; +; N/A ; 9.87 MHz ( period = 101.293 ns ) ; Arkanoid:inst|v_counter[6] ; Arkanoid:inst|blue_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.046 ns ; +; N/A ; 9.87 MHz ( period = 101.284 ns ) ; Arkanoid:inst|v_counter[10] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.037 ns ; +; N/A ; 9.88 MHz ( period = 101.256 ns ) ; Arkanoid:inst|h_counter[9] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.013 ns ; +; N/A ; 9.88 MHz ( period = 101.256 ns ) ; Arkanoid:inst|h_counter[19] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.016 ns ; +; N/A ; 9.88 MHz ( period = 101.254 ns ) ; Arkanoid:inst|h_counter[9] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.011 ns ; +; N/A ; 9.88 MHz ( period = 101.253 ns ) ; Arkanoid:inst|h_counter[9] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.010 ns ; +; N/A ; 9.88 MHz ( period = 101.253 ns ) ; Arkanoid:inst|h_counter[16] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.013 ns ; +; N/A ; 9.88 MHz ( period = 101.250 ns ) ; Arkanoid:inst|h_counter[9] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 101.007 ns ; +; N/A ; 9.88 MHz ( period = 101.232 ns ) ; Arkanoid:inst|h_counter[17] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.992 ns ; +; N/A ; 9.88 MHz ( period = 101.230 ns ) ; Arkanoid:inst|h_counter[17] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.990 ns ; +; N/A ; 9.88 MHz ( period = 101.221 ns ) ; Arkanoid:inst|h_counter[10] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.978 ns ; +; N/A ; 9.88 MHz ( period = 101.219 ns ) ; Arkanoid:inst|h_counter[10] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.976 ns ; +; N/A ; 9.88 MHz ( period = 101.218 ns ) ; Arkanoid:inst|h_counter[10] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.975 ns ; +; N/A ; 9.88 MHz ( period = 101.215 ns ) ; Arkanoid:inst|h_counter[10] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.972 ns ; +; N/A ; 9.88 MHz ( period = 101.212 ns ) ; Arkanoid:inst|v_counter[11] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.965 ns ; +; N/A ; 9.88 MHz ( period = 101.209 ns ) ; Arkanoid:inst|v_counter[13] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.962 ns ; +; N/A ; 9.88 MHz ( period = 101.190 ns ) ; Arkanoid:inst|v_counter[8] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.943 ns ; +; N/A ; 9.88 MHz ( period = 101.184 ns ) ; Arkanoid:inst|v_counter[4] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.937 ns ; +; N/A ; 9.88 MHz ( period = 101.180 ns ) ; Arkanoid:inst|h_counter[17] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.940 ns ; +; N/A ; 9.88 MHz ( period = 101.177 ns ) ; Arkanoid:inst|v_counter[12] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.930 ns ; +; N/A ; 9.88 MHz ( period = 101.173 ns ) ; Arkanoid:inst|v_counter[7] ; Arkanoid:inst|blue_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.926 ns ; +; N/A ; 9.88 MHz ( period = 101.173 ns ) ; Arkanoid:inst|v_counter[4] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.926 ns ; +; N/A ; 9.88 MHz ( period = 101.171 ns ) ; Arkanoid:inst|v_counter[4] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.924 ns ; +; N/A ; 9.89 MHz ( period = 101.159 ns ) ; Arkanoid:inst|v_counter[11] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.912 ns ; +; N/A ; 9.89 MHz ( period = 101.153 ns ) ; Arkanoid:inst|h_counter[18] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.913 ns ; +; N/A ; 9.89 MHz ( period = 101.151 ns ) ; Arkanoid:inst|h_counter[18] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.911 ns ; +; N/A ; 9.89 MHz ( period = 101.148 ns ) ; Arkanoid:inst|v_counter[5] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.901 ns ; +; N/A ; 9.89 MHz ( period = 101.137 ns ) ; Arkanoid:inst|v_counter[5] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.890 ns ; +; N/A ; 9.89 MHz ( period = 101.136 ns ) ; Arkanoid:inst|h_counter[20] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.896 ns ; +; N/A ; 9.89 MHz ( period = 101.135 ns ) ; Arkanoid:inst|v_counter[5] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.888 ns ; +; N/A ; 9.89 MHz ( period = 101.129 ns ) ; Arkanoid:inst|v_counter[14] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.882 ns ; +; N/A ; 9.89 MHz ( period = 101.124 ns ) ; Arkanoid:inst|v_counter[12] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.877 ns ; +; N/A ; 9.89 MHz ( period = 101.114 ns ) ; Arkanoid:inst|h_counter[19] ; Arkanoid:inst|red_[1] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.874 ns ; +; N/A ; 9.89 MHz ( period = 101.112 ns ) ; Arkanoid:inst|h_counter[19] ; Arkanoid:inst|green_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.872 ns ; +; N/A ; 9.89 MHz ( period = 101.101 ns ) ; Arkanoid:inst|h_counter[18] ; Arkanoid:inst|red_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.861 ns ; +; N/A ; 9.89 MHz ( period = 101.096 ns ) ; Arkanoid:inst|h_counter[11] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.853 ns ; +; N/A ; 9.89 MHz ( period = 101.096 ns ) ; Arkanoid:inst|h_counter[21] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.856 ns ; +; N/A ; 9.89 MHz ( period = 101.094 ns ) ; Arkanoid:inst|h_counter[11] ; Arkanoid:inst|red_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.851 ns ; +; N/A ; 9.89 MHz ( period = 101.093 ns ) ; Arkanoid:inst|h_counter[11] ; Arkanoid:inst|green_[2] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.850 ns ; +; N/A ; 9.89 MHz ( period = 101.093 ns ) ; Arkanoid:inst|v_counter[1] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.846 ns ; +; N/A ; 9.89 MHz ( period = 101.090 ns ) ; Arkanoid:inst|h_counter[11] ; Arkanoid:inst|red_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.847 ns ; +; N/A ; 9.89 MHz ( period = 101.071 ns ) ; Arkanoid:inst|v_counter[6] ; Arkanoid:inst|blue_[3] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.824 ns ; +; N/A ; 9.89 MHz ( period = 101.068 ns ) ; Arkanoid:inst|v_counter[15] ; Arkanoid:inst|blue_[0] ; clk_50MHz ; clk_50MHz ; None ; None ; 100.821 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+-----------------------------+-------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+ + + ++------------------------------------------------------------------------------------------------+ +; tsu ; ++-------+--------------+------------+---------+--------------------------------------+-----------+ +; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ; ++-------+--------------+------------+---------+--------------------------------------+-----------+ +; N/A ; None ; 32.749 ns ; button3 ; Arkanoid:inst|blue_[0] ; clk_50MHz ; +; N/A ; None ; 32.607 ns ; button3 ; Arkanoid:inst|red_[1] ; clk_50MHz ; +; N/A ; None ; 32.604 ns ; button3 ; Arkanoid:inst|green_[3] ; clk_50MHz ; +; N/A ; None ; 32.586 ns ; button3 ; Arkanoid:inst|red_[3] ; clk_50MHz ; +; N/A ; None ; 31.939 ns ; button3 ; Arkanoid:inst|red_[2] ; clk_50MHz ; +; N/A ; None ; 31.910 ns ; button3 ; Arkanoid:inst|blue_[3] ; clk_50MHz ; +; N/A ; None ; 31.906 ns ; button3 ; Arkanoid:inst|green_[2] ; clk_50MHz ; +; N/A ; None ; 31.904 ns ; button3 ; Arkanoid:inst|red_[0] ; clk_50MHz ; +; N/A ; None ; 31.598 ns ; button1 ; Arkanoid:inst|blue_[0] ; clk_50MHz ; +; N/A ; None ; 31.456 ns ; button1 ; Arkanoid:inst|red_[1] ; clk_50MHz ; +; N/A ; None ; 31.454 ns ; button1 ; Arkanoid:inst|green_[3] ; clk_50MHz ; +; N/A ; None ; 31.404 ns ; button1 ; Arkanoid:inst|red_[3] ; clk_50MHz ; +; N/A ; None ; 30.759 ns ; button1 ; Arkanoid:inst|blue_[3] ; clk_50MHz ; +; N/A ; None ; 30.757 ns ; button1 ; Arkanoid:inst|red_[2] ; clk_50MHz ; +; N/A ; None ; 30.756 ns ; button1 ; Arkanoid:inst|green_[2] ; clk_50MHz ; +; N/A ; None ; 30.753 ns ; button1 ; Arkanoid:inst|red_[0] ; clk_50MHz ; +; N/A ; None ; 20.225 ns ; button4 ; Arkanoid:inst|blue_[0] ; clk_50MHz ; +; N/A ; None ; 20.083 ns ; button4 ; Arkanoid:inst|red_[1] ; clk_50MHz ; +; N/A ; None ; 20.080 ns ; button4 ; Arkanoid:inst|green_[3] ; clk_50MHz ; +; N/A ; None ; 20.062 ns ; button4 ; Arkanoid:inst|red_[3] ; clk_50MHz ; +; N/A ; None ; 19.573 ns ; button2 ; Arkanoid:inst|blue_[0] ; clk_50MHz ; +; N/A ; None ; 19.431 ns ; button2 ; Arkanoid:inst|red_[1] ; clk_50MHz ; +; N/A ; None ; 19.429 ns ; button2 ; Arkanoid:inst|green_[3] ; clk_50MHz ; +; N/A ; None ; 19.415 ns ; button4 ; Arkanoid:inst|red_[2] ; clk_50MHz ; +; N/A ; None ; 19.386 ns ; button4 ; Arkanoid:inst|blue_[3] ; clk_50MHz ; +; N/A ; None ; 19.382 ns ; button4 ; Arkanoid:inst|green_[2] ; clk_50MHz ; +; N/A ; None ; 19.380 ns ; button4 ; Arkanoid:inst|red_[0] ; clk_50MHz ; +; N/A ; None ; 19.379 ns ; button2 ; Arkanoid:inst|red_[3] ; clk_50MHz ; +; N/A ; None ; 18.801 ns ; button3 ; Arkanoid:inst|platform2_position[31] ; clk_50MHz ; +; N/A ; None ; 18.734 ns ; button2 ; Arkanoid:inst|blue_[3] ; clk_50MHz ; +; N/A ; None ; 18.732 ns ; button2 ; Arkanoid:inst|red_[2] ; clk_50MHz ; +; N/A ; None ; 18.731 ns ; button2 ; Arkanoid:inst|green_[2] ; clk_50MHz ; +; N/A ; None ; 18.728 ns ; button2 ; Arkanoid:inst|red_[0] ; clk_50MHz ; +; N/A ; None ; 18.157 ns ; button3 ; Arkanoid:inst|platform2_position[29] ; clk_50MHz ; +; N/A ; None ; 18.002 ns ; button3 ; Arkanoid:inst|platform2_position[30] ; clk_50MHz ; +; N/A ; None ; 17.989 ns ; button3 ; Arkanoid:inst|platform2_position[26] ; clk_50MHz ; +; N/A ; None ; 17.655 ns ; button3 ; Arkanoid:inst|platform2_position[27] ; clk_50MHz ; +; N/A ; None ; 17.436 ns ; button3 ; Arkanoid:inst|platform2_position[28] ; clk_50MHz ; +; N/A ; None ; 17.284 ns ; button3 ; Arkanoid:inst|platform2_position[25] ; clk_50MHz ; +; N/A ; None ; 17.269 ns ; button3 ; Arkanoid:inst|platform2_position[19] ; clk_50MHz ; +; N/A ; None ; 17.135 ns ; button3 ; Arkanoid:inst|platform2_position[24] ; clk_50MHz ; +; N/A ; None ; 17.109 ns ; button3 ; Arkanoid:inst|platform2_position[17] ; clk_50MHz ; +; N/A ; None ; 17.001 ns ; button3 ; Arkanoid:inst|platform2_position[14] ; clk_50MHz ; +; N/A ; None ; 16.961 ns ; button3 ; Arkanoid:inst|platform2_position[20] ; clk_50MHz ; +; N/A ; None ; 16.884 ns ; button1 ; Arkanoid:inst|platform1_position[25] ; clk_50MHz ; +; N/A ; None ; 16.862 ns ; button3 ; Arkanoid:inst|platform2_position[3] ; clk_50MHz ; +; N/A ; None ; 16.851 ns ; button3 ; Arkanoid:inst|platform2_position[22] ; clk_50MHz ; +; N/A ; None ; 16.816 ns ; button1 ; Arkanoid:inst|platform1_position[30] ; clk_50MHz ; +; N/A ; None ; 16.816 ns ; button3 ; Arkanoid:inst|platform2_position[18] ; clk_50MHz ; +; N/A ; None ; 16.770 ns ; button3 ; Arkanoid:inst|platform2_position[23] ; clk_50MHz ; +; N/A ; None ; 16.703 ns ; button3 ; Arkanoid:inst|platform2_position[16] ; clk_50MHz ; +; N/A ; None ; 16.671 ns ; button1 ; Arkanoid:inst|platform1_position[29] ; clk_50MHz ; +; N/A ; None ; 16.468 ns ; button1 ; Arkanoid:inst|platform1_position[27] ; clk_50MHz ; +; N/A ; None ; 16.439 ns ; button3 ; Arkanoid:inst|platform2_position[21] ; clk_50MHz ; +; N/A ; None ; 16.357 ns ; button3 ; Arkanoid:inst|platform2_position[12] ; clk_50MHz ; +; N/A ; None ; 16.299 ns ; button1 ; Arkanoid:inst|platform1_position[28] ; clk_50MHz ; +; N/A ; None ; 16.240 ns ; button3 ; Arkanoid:inst|platform2_position[11] ; clk_50MHz ; +; N/A ; None ; 16.228 ns ; button3 ; Arkanoid:inst|platform2_position[8] ; clk_50MHz ; +; N/A ; None ; 16.217 ns ; button3 ; Arkanoid:inst|platform2_position[13] ; clk_50MHz ; +; N/A ; None ; 16.213 ns ; button1 ; Arkanoid:inst|platform1_position[31] ; clk_50MHz ; +; N/A ; None ; 16.158 ns ; button3 ; Arkanoid:inst|platform2_position[15] ; clk_50MHz ; +; N/A ; None ; 16.144 ns ; button3 ; Arkanoid:inst|platform2_position[9] ; clk_50MHz ; +; N/A ; None ; 16.134 ns ; button3 ; Arkanoid:inst|platform2_position[10] ; clk_50MHz ; +; N/A ; None ; 16.006 ns ; button1 ; Arkanoid:inst|platform1_position[26] ; clk_50MHz ; +; N/A ; None ; 15.993 ns ; button1 ; Arkanoid:inst|platform1_position[22] ; clk_50MHz ; +; N/A ; None ; 15.964 ns ; button1 ; Arkanoid:inst|platform1_position[3] ; clk_50MHz ; +; N/A ; None ; 15.862 ns ; button3 ; Arkanoid:inst|platform2_position[7] ; clk_50MHz ; +; N/A ; None ; 15.860 ns ; button1 ; Arkanoid:inst|platform1_position[21] ; clk_50MHz ; +; N/A ; None ; 15.852 ns ; button1 ; Arkanoid:inst|platform1_position[24] ; clk_50MHz ; +; N/A ; None ; 15.771 ns ; button1 ; Arkanoid:inst|platform1_position[20] ; clk_50MHz ; +; N/A ; None ; 15.740 ns ; button3 ; Arkanoid:inst|platform2_position[6] ; clk_50MHz ; +; N/A ; None ; 15.701 ns ; button1 ; Arkanoid:inst|platform1_position[23] ; clk_50MHz ; +; N/A ; None ; 15.567 ns ; button1 ; Arkanoid:inst|platform1_position[17] ; clk_50MHz ; +; N/A ; None ; 15.411 ns ; button1 ; Arkanoid:inst|platform1_position[19] ; clk_50MHz ; +; N/A ; None ; 15.348 ns ; button1 ; Arkanoid:inst|platform1_position[15] ; clk_50MHz ; +; N/A ; None ; 15.341 ns ; button3 ; Arkanoid:inst|platform2_position[2] ; clk_50MHz ; +; N/A ; None ; 15.268 ns ; button3 ; Arkanoid:inst|platform2_position[5] ; clk_50MHz ; +; N/A ; None ; 15.264 ns ; button3 ; Arkanoid:inst|platform2_position[4] ; clk_50MHz ; +; N/A ; None ; 15.131 ns ; button1 ; Arkanoid:inst|platform1_position[18] ; clk_50MHz ; +; N/A ; None ; 15.085 ns ; button1 ; Arkanoid:inst|platform1_position[12] ; clk_50MHz ; +; N/A ; None ; 14.969 ns ; button1 ; Arkanoid:inst|platform1_position[16] ; clk_50MHz ; +; N/A ; None ; 14.963 ns ; button1 ; Arkanoid:inst|platform1_position[11] ; clk_50MHz ; +; N/A ; None ; 14.880 ns ; button1 ; Arkanoid:inst|platform1_position[10] ; clk_50MHz ; +; N/A ; None ; 14.848 ns ; button1 ; Arkanoid:inst|platform1_position[14] ; clk_50MHz ; +; N/A ; None ; 14.827 ns ; button1 ; Arkanoid:inst|platform1_position[9] ; clk_50MHz ; +; N/A ; None ; 14.770 ns ; button1 ; Arkanoid:inst|platform1_position[13] ; clk_50MHz ; +; N/A ; None ; 14.754 ns ; button1 ; Arkanoid:inst|platform1_position[8] ; clk_50MHz ; +; N/A ; None ; 14.637 ns ; button3 ; Arkanoid:inst|platform2_position[1] ; clk_50MHz ; +; N/A ; None ; 14.560 ns ; button1 ; Arkanoid:inst|platform1_position[6] ; clk_50MHz ; +; N/A ; None ; 14.552 ns ; button1 ; Arkanoid:inst|platform1_position[7] ; clk_50MHz ; +; N/A ; None ; 14.492 ns ; button3 ; Arkanoid:inst|platform2_position[0] ; clk_50MHz ; +; N/A ; None ; 14.437 ns ; button1 ; Arkanoid:inst|platform1_position[5] ; clk_50MHz ; +; N/A ; None ; 14.350 ns ; button1 ; Arkanoid:inst|platform1_position[4] ; clk_50MHz ; +; N/A ; None ; 14.138 ns ; button1 ; Arkanoid:inst|platform1_position[2] ; clk_50MHz ; +; N/A ; None ; 14.006 ns ; button1 ; Arkanoid:inst|platform1_position[1] ; clk_50MHz ; +; N/A ; None ; 13.300 ns ; button1 ; Arkanoid:inst|platform1_position[0] ; clk_50MHz ; +; N/A ; None ; 5.014 ns ; button2 ; Arkanoid:inst|platform1_position[3] ; clk_50MHz ; +; N/A ; None ; 4.949 ns ; button4 ; Arkanoid:inst|led_[1] ; clk_50MHz ; +; N/A ; None ; 4.949 ns ; button4 ; Arkanoid:inst|led_[0] ; clk_50MHz ; +; N/A ; None ; 4.904 ns ; button4 ; Arkanoid:inst|platform2_position[3] ; clk_50MHz ; +; N/A ; None ; 4.602 ns ; button4 ; Arkanoid:inst|button4_state ; clk_50MHz ; +; N/A ; None ; 3.879 ns ; button2 ; Arkanoid:inst|button2_state ; clk_50MHz ; +; N/A ; None ; 3.879 ns ; button2 ; Arkanoid:inst|led_[5] ; clk_50MHz ; +; N/A ; None ; 3.879 ns ; button2 ; Arkanoid:inst|led_[4] ; clk_50MHz ; +; N/A ; None ; 3.628 ns ; button4 ; Arkanoid:inst|platform2_position[31] ; clk_50MHz ; +; N/A ; None ; 3.627 ns ; button4 ; Arkanoid:inst|platform2_position[12] ; clk_50MHz ; +; N/A ; None ; 3.625 ns ; button4 ; Arkanoid:inst|platform2_position[11] ; clk_50MHz ; +; N/A ; None ; 3.599 ns ; button3 ; Arkanoid:inst|button3_state ; clk_50MHz ; +; N/A ; None ; 3.599 ns ; button3 ; Arkanoid:inst|led_[3] ; clk_50MHz ; +; N/A ; None ; 3.599 ns ; button3 ; Arkanoid:inst|led_[2] ; clk_50MHz ; +; N/A ; None ; 3.574 ns ; button4 ; Arkanoid:inst|platform2_position[10] ; clk_50MHz ; +; N/A ; None ; 3.574 ns ; button4 ; Arkanoid:inst|platform2_position[7] ; clk_50MHz ; +; N/A ; None ; 3.574 ns ; button4 ; Arkanoid:inst|platform2_position[6] ; clk_50MHz ; +; N/A ; None ; 3.571 ns ; button4 ; Arkanoid:inst|platform2_position[8] ; clk_50MHz ; +; N/A ; None ; 3.569 ns ; button4 ; Arkanoid:inst|platform2_position[5] ; clk_50MHz ; +; N/A ; None ; 3.518 ns ; button1 ; Arkanoid:inst|button1_state ; clk_50MHz ; +; N/A ; None ; 3.518 ns ; button1 ; Arkanoid:inst|led_[7] ; clk_50MHz ; +; N/A ; None ; 3.518 ns ; button1 ; Arkanoid:inst|led_[6] ; clk_50MHz ; +; N/A ; None ; 3.501 ns ; button4 ; Arkanoid:inst|platform2_position[29] ; clk_50MHz ; +; N/A ; None ; 3.305 ns ; button4 ; Arkanoid:inst|platform2_position[20] ; clk_50MHz ; +; N/A ; None ; 3.304 ns ; button4 ; Arkanoid:inst|platform2_position[16] ; clk_50MHz ; +; N/A ; None ; 3.303 ns ; button4 ; Arkanoid:inst|platform2_position[19] ; clk_50MHz ; +; N/A ; None ; 3.302 ns ; button4 ; Arkanoid:inst|platform2_position[17] ; clk_50MHz ; +; N/A ; None ; 3.301 ns ; button4 ; Arkanoid:inst|platform2_position[15] ; clk_50MHz ; +; N/A ; None ; 3.286 ns ; button4 ; Arkanoid:inst|platform2_position[4] ; clk_50MHz ; +; N/A ; None ; 3.284 ns ; button4 ; Arkanoid:inst|platform2_position[2] ; clk_50MHz ; +; N/A ; None ; 3.282 ns ; button4 ; Arkanoid:inst|platform2_position[0] ; clk_50MHz ; +; N/A ; None ; 3.282 ns ; button4 ; Arkanoid:inst|platform2_position[1] ; clk_50MHz ; +; N/A ; None ; 3.219 ns ; button4 ; Arkanoid:inst|platform2_position[18] ; clk_50MHz ; +; N/A ; None ; 3.218 ns ; button4 ; Arkanoid:inst|platform2_position[30] ; clk_50MHz ; +; N/A ; None ; 3.168 ns ; button4 ; Arkanoid:inst|platform2_position[21] ; clk_50MHz ; +; N/A ; None ; 3.165 ns ; button4 ; Arkanoid:inst|platform2_position[27] ; clk_50MHz ; +; N/A ; None ; 2.951 ns ; button2 ; Arkanoid:inst|platform1_position[1] ; clk_50MHz ; +; N/A ; None ; 2.946 ns ; button2 ; Arkanoid:inst|platform1_position[0] ; clk_50MHz ; +; N/A ; None ; 2.828 ns ; button4 ; Arkanoid:inst|platform2_position[14] ; clk_50MHz ; +; N/A ; None ; 2.828 ns ; button4 ; Arkanoid:inst|platform2_position[13] ; clk_50MHz ; +; N/A ; None ; 2.821 ns ; button4 ; Arkanoid:inst|platform2_position[22] ; clk_50MHz ; +; N/A ; None ; 2.820 ns ; button4 ; Arkanoid:inst|platform2_position[9] ; clk_50MHz ; +; N/A ; None ; 2.819 ns ; button4 ; Arkanoid:inst|platform2_position[26] ; clk_50MHz ; +; N/A ; None ; 2.818 ns ; button4 ; Arkanoid:inst|platform2_position[28] ; clk_50MHz ; +; N/A ; None ; 2.818 ns ; button4 ; Arkanoid:inst|platform2_position[23] ; clk_50MHz ; +; N/A ; None ; 2.814 ns ; button4 ; Arkanoid:inst|platform2_position[24] ; clk_50MHz ; +; N/A ; None ; 2.813 ns ; button4 ; Arkanoid:inst|platform2_position[25] ; clk_50MHz ; +; N/A ; None ; 2.755 ns ; button2 ; Arkanoid:inst|platform1_position[13] ; clk_50MHz ; +; N/A ; None ; 2.755 ns ; button2 ; Arkanoid:inst|platform1_position[14] ; clk_50MHz ; +; N/A ; None ; 2.751 ns ; button2 ; Arkanoid:inst|platform1_position[15] ; clk_50MHz ; +; N/A ; None ; 2.706 ns ; button2 ; Arkanoid:inst|platform1_position[21] ; clk_50MHz ; +; N/A ; None ; 2.706 ns ; button2 ; Arkanoid:inst|platform1_position[30] ; clk_50MHz ; +; N/A ; None ; 2.705 ns ; button2 ; Arkanoid:inst|platform1_position[25] ; clk_50MHz ; +; N/A ; None ; 2.704 ns ; button2 ; Arkanoid:inst|platform1_position[28] ; clk_50MHz ; +; N/A ; None ; 2.702 ns ; button2 ; Arkanoid:inst|platform1_position[23] ; clk_50MHz ; +; N/A ; None ; 2.702 ns ; button2 ; Arkanoid:inst|platform1_position[2] ; clk_50MHz ; +; N/A ; None ; 2.696 ns ; button2 ; Arkanoid:inst|platform1_position[24] ; clk_50MHz ; +; N/A ; None ; 2.693 ns ; button2 ; Arkanoid:inst|platform1_position[26] ; clk_50MHz ; +; N/A ; None ; 2.577 ns ; button2 ; Arkanoid:inst|platform1_position[16] ; clk_50MHz ; +; N/A ; None ; 2.575 ns ; button2 ; Arkanoid:inst|platform1_position[19] ; clk_50MHz ; +; N/A ; None ; 2.573 ns ; button2 ; Arkanoid:inst|platform1_position[18] ; clk_50MHz ; +; N/A ; None ; 2.573 ns ; button2 ; Arkanoid:inst|platform1_position[17] ; clk_50MHz ; +; N/A ; None ; 2.572 ns ; button2 ; Arkanoid:inst|platform1_position[31] ; clk_50MHz ; +; N/A ; None ; 2.572 ns ; button2 ; Arkanoid:inst|platform1_position[20] ; clk_50MHz ; +; N/A ; None ; 2.327 ns ; button2 ; Arkanoid:inst|platform1_position[4] ; clk_50MHz ; +; N/A ; None ; 2.326 ns ; button2 ; Arkanoid:inst|platform1_position[11] ; clk_50MHz ; +; N/A ; None ; 2.325 ns ; button2 ; Arkanoid:inst|platform1_position[6] ; clk_50MHz ; +; N/A ; None ; 2.324 ns ; button2 ; Arkanoid:inst|platform1_position[7] ; clk_50MHz ; +; N/A ; None ; 2.322 ns ; button2 ; Arkanoid:inst|platform1_position[10] ; clk_50MHz ; +; N/A ; None ; 2.321 ns ; button2 ; Arkanoid:inst|platform1_position[12] ; clk_50MHz ; +; N/A ; None ; 2.320 ns ; button2 ; Arkanoid:inst|platform1_position[5] ; clk_50MHz ; +; N/A ; None ; 2.318 ns ; button2 ; Arkanoid:inst|platform1_position[22] ; clk_50MHz ; +; N/A ; None ; 2.315 ns ; button2 ; Arkanoid:inst|platform1_position[9] ; clk_50MHz ; +; N/A ; None ; 2.313 ns ; button2 ; Arkanoid:inst|platform1_position[8] ; clk_50MHz ; +; N/A ; None ; 2.312 ns ; button2 ; Arkanoid:inst|platform1_position[27] ; clk_50MHz ; +; N/A ; None ; 2.310 ns ; button2 ; Arkanoid:inst|platform1_position[29] ; clk_50MHz ; ++-------+--------------+------------+---------+--------------------------------------+-----------+ + + ++-----------------------------------------------------------------------------------------+ +; tco ; ++-------+--------------+------------+-----------------------------+----------+------------+ +; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ; ++-------+--------------+------------+-----------------------------+----------+------------+ +; N/A ; None ; 15.668 ns ; Arkanoid:inst|v_counter[8] ; v_sync ; clk_50MHz ; +; N/A ; None ; 15.637 ns ; Arkanoid:inst|v_counter[7] ; v_sync ; clk_50MHz ; +; N/A ; None ; 15.288 ns ; Arkanoid:inst|h_counter[19] ; h_sync ; clk_50MHz ; +; N/A ; None ; 15.195 ns ; Arkanoid:inst|h_counter[1] ; h_sync ; clk_50MHz ; +; N/A ; None ; 15.161 ns ; Arkanoid:inst|v_counter[6] ; v_sync ; clk_50MHz ; +; N/A ; None ; 14.948 ns ; Arkanoid:inst|v_counter[13] ; v_sync ; clk_50MHz ; +; N/A ; None ; 14.923 ns ; Arkanoid:inst|v_counter[19] ; v_sync ; clk_50MHz ; +; N/A ; None ; 14.911 ns ; Arkanoid:inst|v_counter[17] ; v_sync ; clk_50MHz ; +; N/A ; None ; 14.895 ns ; Arkanoid:inst|v_counter[22] ; v_sync ; clk_50MHz ; +; N/A ; None ; 14.890 ns ; Arkanoid:inst|v_counter[20] ; v_sync ; clk_50MHz ; +; N/A ; None ; 14.889 ns ; Arkanoid:inst|v_counter[16] ; v_sync ; clk_50MHz ; +; N/A ; None ; 14.827 ns ; Arkanoid:inst|v_counter[24] ; v_sync ; clk_50MHz ; +; N/A ; None ; 14.814 ns ; Arkanoid:inst|v_counter[23] ; v_sync ; clk_50MHz ; +; N/A ; None ; 14.768 ns ; Arkanoid:inst|v_counter[18] ; v_sync ; clk_50MHz ; +; N/A ; None ; 14.632 ns ; Arkanoid:inst|v_counter[21] ; v_sync ; clk_50MHz ; +; N/A ; None ; 14.601 ns ; Arkanoid:inst|h_counter[2] ; h_sync ; clk_50MHz ; +; N/A ; None ; 14.552 ns ; Arkanoid:inst|v_counter[25] ; v_sync ; clk_50MHz ; +; N/A ; None ; 14.552 ns ; Arkanoid:inst|h_counter[29] ; h_sync ; clk_50MHz ; +; N/A ; None ; 14.516 ns ; Arkanoid:inst|v_counter[12] ; v_sync ; clk_50MHz ; +; N/A ; None ; 14.507 ns ; Arkanoid:inst|v_counter[10] ; v_sync ; clk_50MHz ; +; N/A ; None ; 14.455 ns ; Arkanoid:inst|h_counter[15] ; h_sync ; clk_50MHz ; +; N/A ; None ; 14.366 ns ; Arkanoid:inst|v_counter[11] ; v_sync ; clk_50MHz ; +; N/A ; None ; 14.283 ns ; Arkanoid:inst|h_counter[3] ; h_sync ; clk_50MHz ; +; N/A ; None ; 14.237 ns ; Arkanoid:inst|h_counter[11] ; h_sync ; clk_50MHz ; +; N/A ; None ; 14.195 ns ; Arkanoid:inst|h_counter[5] ; h_sync ; clk_50MHz ; +; N/A ; None ; 14.186 ns ; Arkanoid:inst|v_counter[14] ; v_sync ; clk_50MHz ; +; N/A ; None ; 14.157 ns ; Arkanoid:inst|h_counter[9] ; h_sync ; clk_50MHz ; +; N/A ; None ; 14.155 ns ; Arkanoid:inst|h_counter[8] ; h_sync ; clk_50MHz ; +; N/A ; None ; 14.091 ns ; Arkanoid:inst|v_counter[15] ; v_sync ; clk_50MHz ; +; N/A ; None ; 14.091 ns ; Arkanoid:inst|h_counter[0] ; h_sync ; clk_50MHz ; +; N/A ; None ; 13.961 ns ; Arkanoid:inst|v_counter[5] ; v_sync ; clk_50MHz ; +; N/A ; None ; 13.896 ns ; Arkanoid:inst|h_counter[13] ; h_sync ; clk_50MHz ; +; N/A ; None ; 13.889 ns ; Arkanoid:inst|h_counter[14] ; h_sync ; clk_50MHz ; +; N/A ; None ; 13.853 ns ; Arkanoid:inst|v_counter[1] ; v_sync ; clk_50MHz ; +; N/A ; None ; 13.822 ns ; Arkanoid:inst|h_counter[24] ; h_sync ; clk_50MHz ; +; N/A ; None ; 13.750 ns ; Arkanoid:inst|h_counter[18] ; h_sync ; clk_50MHz ; +; N/A ; None ; 13.749 ns ; Arkanoid:inst|h_counter[10] ; h_sync ; clk_50MHz ; +; N/A ; None ; 13.718 ns ; Arkanoid:inst|h_counter[12] ; h_sync ; clk_50MHz ; +; N/A ; None ; 13.692 ns ; Arkanoid:inst|h_counter[17] ; h_sync ; clk_50MHz ; +; N/A ; None ; 13.676 ns ; Arkanoid:inst|h_counter[16] ; h_sync ; clk_50MHz ; +; N/A ; None ; 13.632 ns ; Arkanoid:inst|v_counter[4] ; v_sync ; clk_50MHz ; +; N/A ; None ; 13.585 ns ; Arkanoid:inst|h_counter[21] ; h_sync ; clk_50MHz ; +; N/A ; None ; 13.573 ns ; Arkanoid:inst|h_counter[4] ; h_sync ; clk_50MHz ; +; N/A ; None ; 13.550 ns ; Arkanoid:inst|h_counter[23] ; h_sync ; clk_50MHz ; +; N/A ; None ; 13.466 ns ; Arkanoid:inst|v_counter[2] ; v_sync ; clk_50MHz ; +; N/A ; None ; 13.458 ns ; Arkanoid:inst|h_counter[20] ; h_sync ; clk_50MHz ; +; N/A ; None ; 13.405 ns ; Arkanoid:inst|v_counter[3] ; v_sync ; clk_50MHz ; +; N/A ; None ; 13.390 ns ; Arkanoid:inst|h_counter[22] ; h_sync ; clk_50MHz ; +; N/A ; None ; 13.244 ns ; Arkanoid:inst|h_counter[25] ; h_sync ; clk_50MHz ; +; N/A ; None ; 13.170 ns ; Arkanoid:inst|h_counter[6] ; h_sync ; clk_50MHz ; +; N/A ; None ; 13.011 ns ; Arkanoid:inst|v_counter[28] ; v_sync ; clk_50MHz ; +; N/A ; None ; 13.001 ns ; Arkanoid:inst|v_counter[27] ; v_sync ; clk_50MHz ; +; N/A ; None ; 12.849 ns ; Arkanoid:inst|v_counter[29] ; v_sync ; clk_50MHz ; +; N/A ; None ; 12.753 ns ; Arkanoid:inst|v_counter[30] ; v_sync ; clk_50MHz ; +; N/A ; None ; 12.720 ns ; Arkanoid:inst|v_counter[26] ; v_sync ; clk_50MHz ; +; N/A ; None ; 12.633 ns ; Arkanoid:inst|h_counter[28] ; h_sync ; clk_50MHz ; +; N/A ; None ; 12.628 ns ; Arkanoid:inst|h_counter[27] ; h_sync ; clk_50MHz ; +; N/A ; None ; 12.484 ns ; Arkanoid:inst|v_counter[31] ; v_sync ; clk_50MHz ; +; N/A ; None ; 12.352 ns ; Arkanoid:inst|h_counter[26] ; h_sync ; clk_50MHz ; +; N/A ; None ; 12.262 ns ; Arkanoid:inst|h_counter[30] ; h_sync ; clk_50MHz ; +; N/A ; None ; 12.173 ns ; Arkanoid:inst|h_counter[31] ; h_sync ; clk_50MHz ; +; N/A ; None ; 12.144 ns ; Arkanoid:inst|h_counter[7] ; h_sync ; clk_50MHz ; +; N/A ; None ; 11.917 ns ; Arkanoid:inst|v_counter[9] ; v_sync ; clk_50MHz ; +; N/A ; None ; 10.989 ns ; Arkanoid:inst|led_[5] ; led[5] ; clk_50MHz ; +; N/A ; None ; 10.915 ns ; Arkanoid:inst|led_[3] ; led[3] ; clk_50MHz ; +; N/A ; None ; 10.702 ns ; Arkanoid:inst|led_[1] ; led[1] ; clk_50MHz ; +; N/A ; None ; 10.550 ns ; Arkanoid:inst|red_[0] ; red[0] ; clk_50MHz ; +; N/A ; None ; 10.523 ns ; Arkanoid:inst|red_[3] ; red[3] ; clk_50MHz ; +; N/A ; None ; 10.519 ns ; Arkanoid:inst|red_[2] ; red[2] ; clk_50MHz ; +; N/A ; None ; 10.386 ns ; Arkanoid:inst|led_[4] ; led[4] ; clk_50MHz ; +; N/A ; None ; 10.275 ns ; Arkanoid:inst|green_[3] ; green[3] ; clk_50MHz ; +; N/A ; None ; 10.248 ns ; Arkanoid:inst|blue_[0] ; blue[0] ; clk_50MHz ; +; N/A ; None ; 10.236 ns ; Arkanoid:inst|green_[2] ; green[2] ; clk_50MHz ; +; N/A ; None ; 10.139 ns ; Arkanoid:inst|led_[6] ; led[6] ; clk_50MHz ; +; N/A ; None ; 10.073 ns ; Arkanoid:inst|led_[2] ; led[2] ; clk_50MHz ; +; N/A ; None ; 9.936 ns ; Arkanoid:inst|red_[1] ; red[1] ; clk_50MHz ; +; N/A ; None ; 9.867 ns ; Arkanoid:inst|blue_[3] ; blue[3] ; clk_50MHz ; +; N/A ; None ; 9.866 ns ; Arkanoid:inst|blue_[1] ; blue[1] ; clk_50MHz ; +; N/A ; None ; 9.794 ns ; Arkanoid:inst|led_[7] ; led[7] ; clk_50MHz ; +; N/A ; None ; 9.722 ns ; Arkanoid:inst|led_[0] ; led[0] ; clk_50MHz ; +; N/A ; None ; 9.635 ns ; Arkanoid:inst|blue_[2] ; blue[2] ; clk_50MHz ; ++-------+--------------+------------+-----------------------------+----------+------------+ + + ++-------------------------------------------------------------------------------------------------------+ +; th ; ++---------------+-------------+------------+---------+--------------------------------------+-----------+ +; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ; ++---------------+-------------+------------+---------+--------------------------------------+-----------+ +; N/A ; None ; -2.062 ns ; button2 ; Arkanoid:inst|platform1_position[29] ; clk_50MHz ; +; N/A ; None ; -2.064 ns ; button2 ; Arkanoid:inst|platform1_position[27] ; clk_50MHz ; +; N/A ; None ; -2.065 ns ; button2 ; Arkanoid:inst|platform1_position[8] ; clk_50MHz ; +; N/A ; None ; -2.067 ns ; button2 ; Arkanoid:inst|platform1_position[9] ; clk_50MHz ; +; N/A ; None ; -2.070 ns ; button2 ; Arkanoid:inst|platform1_position[22] ; clk_50MHz ; +; N/A ; None ; -2.072 ns ; button2 ; Arkanoid:inst|platform1_position[5] ; clk_50MHz ; +; N/A ; None ; -2.073 ns ; button2 ; Arkanoid:inst|platform1_position[12] ; clk_50MHz ; +; N/A ; None ; -2.074 ns ; button2 ; Arkanoid:inst|platform1_position[10] ; clk_50MHz ; +; N/A ; None ; -2.076 ns ; button2 ; Arkanoid:inst|platform1_position[7] ; clk_50MHz ; +; N/A ; None ; -2.077 ns ; button2 ; Arkanoid:inst|platform1_position[6] ; clk_50MHz ; +; N/A ; None ; -2.078 ns ; button2 ; Arkanoid:inst|platform1_position[11] ; clk_50MHz ; +; N/A ; None ; -2.079 ns ; button2 ; Arkanoid:inst|platform1_position[4] ; clk_50MHz ; +; N/A ; None ; -2.146 ns ; button1 ; Arkanoid:inst|led_[7] ; clk_50MHz ; +; N/A ; None ; -2.151 ns ; button1 ; Arkanoid:inst|button1_state ; clk_50MHz ; +; N/A ; None ; -2.151 ns ; button1 ; Arkanoid:inst|led_[6] ; clk_50MHz ; +; N/A ; None ; -2.324 ns ; button2 ; Arkanoid:inst|platform1_position[31] ; clk_50MHz ; +; N/A ; None ; -2.324 ns ; button2 ; Arkanoid:inst|platform1_position[20] ; clk_50MHz ; +; N/A ; None ; -2.325 ns ; button2 ; Arkanoid:inst|platform1_position[18] ; clk_50MHz ; +; N/A ; None ; -2.325 ns ; button2 ; Arkanoid:inst|platform1_position[17] ; clk_50MHz ; +; N/A ; None ; -2.327 ns ; button2 ; Arkanoid:inst|platform1_position[19] ; clk_50MHz ; +; N/A ; None ; -2.329 ns ; button2 ; Arkanoid:inst|platform1_position[16] ; clk_50MHz ; +; N/A ; None ; -2.421 ns ; button3 ; Arkanoid:inst|led_[2] ; clk_50MHz ; +; N/A ; None ; -2.423 ns ; button3 ; Arkanoid:inst|led_[3] ; clk_50MHz ; +; N/A ; None ; -2.445 ns ; button2 ; Arkanoid:inst|platform1_position[26] ; clk_50MHz ; +; N/A ; None ; -2.448 ns ; button2 ; Arkanoid:inst|platform1_position[24] ; clk_50MHz ; +; N/A ; None ; -2.454 ns ; button2 ; Arkanoid:inst|platform1_position[23] ; clk_50MHz ; +; N/A ; None ; -2.454 ns ; button2 ; Arkanoid:inst|platform1_position[2] ; clk_50MHz ; +; N/A ; None ; -2.456 ns ; button2 ; Arkanoid:inst|platform1_position[28] ; clk_50MHz ; +; N/A ; None ; -2.457 ns ; button2 ; Arkanoid:inst|platform1_position[25] ; clk_50MHz ; +; N/A ; None ; -2.458 ns ; button2 ; Arkanoid:inst|platform1_position[21] ; clk_50MHz ; +; N/A ; None ; -2.458 ns ; button2 ; Arkanoid:inst|platform1_position[30] ; clk_50MHz ; +; N/A ; None ; -2.496 ns ; button2 ; Arkanoid:inst|button2_state ; clk_50MHz ; +; N/A ; None ; -2.497 ns ; button2 ; Arkanoid:inst|led_[5] ; clk_50MHz ; +; N/A ; None ; -2.497 ns ; button2 ; Arkanoid:inst|led_[4] ; clk_50MHz ; +; N/A ; None ; -2.503 ns ; button2 ; Arkanoid:inst|platform1_position[15] ; clk_50MHz ; +; N/A ; None ; -2.507 ns ; button2 ; Arkanoid:inst|platform1_position[13] ; clk_50MHz ; +; N/A ; None ; -2.507 ns ; button2 ; Arkanoid:inst|platform1_position[14] ; clk_50MHz ; +; N/A ; None ; -2.565 ns ; button4 ; Arkanoid:inst|platform2_position[25] ; clk_50MHz ; +; N/A ; None ; -2.566 ns ; button4 ; Arkanoid:inst|platform2_position[24] ; clk_50MHz ; +; N/A ; None ; -2.570 ns ; button4 ; Arkanoid:inst|platform2_position[28] ; clk_50MHz ; +; N/A ; None ; -2.570 ns ; button4 ; Arkanoid:inst|platform2_position[23] ; clk_50MHz ; +; N/A ; None ; -2.571 ns ; button4 ; Arkanoid:inst|platform2_position[26] ; clk_50MHz ; +; N/A ; None ; -2.572 ns ; button4 ; Arkanoid:inst|platform2_position[9] ; clk_50MHz ; +; N/A ; None ; -2.573 ns ; button4 ; Arkanoid:inst|platform2_position[22] ; clk_50MHz ; +; N/A ; None ; -2.580 ns ; button4 ; Arkanoid:inst|platform2_position[14] ; clk_50MHz ; +; N/A ; None ; -2.580 ns ; button4 ; Arkanoid:inst|platform2_position[13] ; clk_50MHz ; +; N/A ; None ; -2.698 ns ; button2 ; Arkanoid:inst|platform1_position[0] ; clk_50MHz ; +; N/A ; None ; -2.703 ns ; button2 ; Arkanoid:inst|platform1_position[1] ; clk_50MHz ; +; N/A ; None ; -2.822 ns ; button3 ; Arkanoid:inst|button3_state ; clk_50MHz ; +; N/A ; None ; -2.917 ns ; button4 ; Arkanoid:inst|platform2_position[27] ; clk_50MHz ; +; N/A ; None ; -2.920 ns ; button4 ; Arkanoid:inst|platform2_position[21] ; clk_50MHz ; +; N/A ; None ; -2.970 ns ; button4 ; Arkanoid:inst|platform2_position[30] ; clk_50MHz ; +; N/A ; None ; -2.971 ns ; button4 ; Arkanoid:inst|platform2_position[18] ; clk_50MHz ; +; N/A ; None ; -3.028 ns ; button4 ; Arkanoid:inst|button4_state ; clk_50MHz ; +; N/A ; None ; -3.034 ns ; button4 ; Arkanoid:inst|platform2_position[0] ; clk_50MHz ; +; N/A ; None ; -3.034 ns ; button4 ; Arkanoid:inst|platform2_position[1] ; clk_50MHz ; +; N/A ; None ; -3.036 ns ; button4 ; Arkanoid:inst|platform2_position[2] ; clk_50MHz ; +; N/A ; None ; -3.038 ns ; button4 ; Arkanoid:inst|platform2_position[4] ; clk_50MHz ; +; N/A ; None ; -3.053 ns ; button4 ; Arkanoid:inst|platform2_position[15] ; clk_50MHz ; +; N/A ; None ; -3.054 ns ; button4 ; Arkanoid:inst|platform2_position[17] ; clk_50MHz ; +; N/A ; None ; -3.055 ns ; button4 ; Arkanoid:inst|platform2_position[19] ; clk_50MHz ; +; N/A ; None ; -3.056 ns ; button4 ; Arkanoid:inst|platform2_position[16] ; clk_50MHz ; +; N/A ; None ; -3.057 ns ; button4 ; Arkanoid:inst|platform2_position[20] ; clk_50MHz ; +; N/A ; None ; -3.253 ns ; button4 ; Arkanoid:inst|platform2_position[29] ; clk_50MHz ; +; N/A ; None ; -3.315 ns ; button4 ; Arkanoid:inst|led_[1] ; clk_50MHz ; +; N/A ; None ; -3.315 ns ; button4 ; Arkanoid:inst|led_[0] ; clk_50MHz ; +; N/A ; None ; -3.321 ns ; button4 ; Arkanoid:inst|platform2_position[5] ; clk_50MHz ; +; N/A ; None ; -3.323 ns ; button4 ; Arkanoid:inst|platform2_position[8] ; clk_50MHz ; +; N/A ; None ; -3.326 ns ; button4 ; Arkanoid:inst|platform2_position[10] ; clk_50MHz ; +; N/A ; None ; -3.326 ns ; button4 ; Arkanoid:inst|platform2_position[7] ; clk_50MHz ; +; N/A ; None ; -3.326 ns ; button4 ; Arkanoid:inst|platform2_position[6] ; clk_50MHz ; +; N/A ; None ; -3.377 ns ; button4 ; Arkanoid:inst|platform2_position[11] ; clk_50MHz ; +; N/A ; None ; -3.379 ns ; button4 ; Arkanoid:inst|platform2_position[12] ; clk_50MHz ; +; N/A ; None ; -3.380 ns ; button4 ; Arkanoid:inst|platform2_position[31] ; clk_50MHz ; +; N/A ; None ; -4.656 ns ; button1 ; Arkanoid:inst|platform1_position[22] ; clk_50MHz ; +; N/A ; None ; -4.656 ns ; button4 ; Arkanoid:inst|platform2_position[3] ; clk_50MHz ; +; N/A ; None ; -4.766 ns ; button2 ; Arkanoid:inst|platform1_position[3] ; clk_50MHz ; +; N/A ; None ; -4.819 ns ; button1 ; Arkanoid:inst|platform1_position[21] ; clk_50MHz ; +; N/A ; None ; -4.969 ns ; button1 ; Arkanoid:inst|platform1_position[8] ; clk_50MHz ; +; N/A ; None ; -4.970 ns ; button1 ; Arkanoid:inst|platform1_position[7] ; clk_50MHz ; +; N/A ; None ; -5.015 ns ; button1 ; Arkanoid:inst|platform1_position[6] ; clk_50MHz ; +; N/A ; None ; -5.023 ns ; button1 ; Arkanoid:inst|platform1_position[4] ; clk_50MHz ; +; N/A ; None ; -5.024 ns ; button1 ; Arkanoid:inst|platform1_position[5] ; clk_50MHz ; +; N/A ; None ; -5.125 ns ; button1 ; Arkanoid:inst|platform1_position[15] ; clk_50MHz ; +; N/A ; None ; -5.142 ns ; button1 ; Arkanoid:inst|platform1_position[31] ; clk_50MHz ; +; N/A ; None ; -5.165 ns ; button1 ; Arkanoid:inst|platform1_position[18] ; clk_50MHz ; +; N/A ; None ; -5.168 ns ; button1 ; Arkanoid:inst|platform1_position[12] ; clk_50MHz ; +; N/A ; None ; -5.172 ns ; button1 ; Arkanoid:inst|platform1_position[20] ; clk_50MHz ; +; N/A ; None ; -5.173 ns ; button1 ; Arkanoid:inst|platform1_position[23] ; clk_50MHz ; +; N/A ; None ; -5.201 ns ; button1 ; Arkanoid:inst|platform1_position[24] ; clk_50MHz ; +; N/A ; None ; -5.220 ns ; button1 ; Arkanoid:inst|platform1_position[19] ; clk_50MHz ; +; N/A ; None ; -5.226 ns ; button1 ; Arkanoid:inst|platform1_position[9] ; clk_50MHz ; +; N/A ; None ; -5.470 ns ; button1 ; Arkanoid:inst|platform1_position[14] ; clk_50MHz ; +; N/A ; None ; -5.472 ns ; button1 ; Arkanoid:inst|platform1_position[11] ; clk_50MHz ; +; N/A ; None ; -5.475 ns ; button1 ; Arkanoid:inst|platform1_position[10] ; clk_50MHz ; +; N/A ; None ; -5.484 ns ; button1 ; Arkanoid:inst|platform1_position[13] ; clk_50MHz ; +; N/A ; None ; -5.499 ns ; button1 ; Arkanoid:inst|platform1_position[0] ; clk_50MHz ; +; N/A ; None ; -5.531 ns ; button1 ; Arkanoid:inst|platform1_position[1] ; clk_50MHz ; +; N/A ; None ; -5.532 ns ; button3 ; Arkanoid:inst|platform2_position[16] ; clk_50MHz ; +; N/A ; None ; -5.551 ns ; button3 ; Arkanoid:inst|platform2_position[7] ; clk_50MHz ; +; N/A ; None ; -5.555 ns ; button1 ; Arkanoid:inst|platform1_position[25] ; clk_50MHz ; +; N/A ; None ; -5.561 ns ; button3 ; Arkanoid:inst|platform2_position[27] ; clk_50MHz ; +; N/A ; None ; -5.572 ns ; button3 ; Arkanoid:inst|platform2_position[29] ; clk_50MHz ; +; N/A ; None ; -5.574 ns ; button1 ; Arkanoid:inst|platform1_position[26] ; clk_50MHz ; +; N/A ; None ; -5.597 ns ; button3 ; Arkanoid:inst|platform2_position[17] ; clk_50MHz ; +; N/A ; None ; -5.604 ns ; button3 ; Arkanoid:inst|platform2_position[6] ; clk_50MHz ; +; N/A ; None ; -5.606 ns ; button3 ; Arkanoid:inst|platform2_position[19] ; clk_50MHz ; +; N/A ; None ; -5.612 ns ; button3 ; Arkanoid:inst|platform2_position[24] ; clk_50MHz ; +; N/A ; None ; -5.620 ns ; button3 ; Arkanoid:inst|platform2_position[31] ; clk_50MHz ; +; N/A ; None ; -5.627 ns ; button3 ; Arkanoid:inst|platform2_position[10] ; clk_50MHz ; +; N/A ; None ; -5.656 ns ; button3 ; Arkanoid:inst|platform2_position[26] ; clk_50MHz ; +; N/A ; None ; -5.722 ns ; button1 ; Arkanoid:inst|platform1_position[27] ; clk_50MHz ; +; N/A ; None ; -5.727 ns ; button1 ; Arkanoid:inst|platform1_position[28] ; clk_50MHz ; +; N/A ; None ; -5.730 ns ; button1 ; Arkanoid:inst|platform1_position[16] ; clk_50MHz ; +; N/A ; None ; -5.815 ns ; button1 ; Arkanoid:inst|platform1_position[2] ; clk_50MHz ; +; N/A ; None ; -5.845 ns ; button1 ; Arkanoid:inst|platform1_position[17] ; clk_50MHz ; +; N/A ; None ; -5.879 ns ; button1 ; Arkanoid:inst|platform1_position[29] ; clk_50MHz ; +; N/A ; None ; -5.881 ns ; button1 ; Arkanoid:inst|platform1_position[30] ; clk_50MHz ; +; N/A ; None ; -5.888 ns ; button3 ; Arkanoid:inst|platform2_position[25] ; clk_50MHz ; +; N/A ; None ; -5.923 ns ; button3 ; Arkanoid:inst|platform2_position[5] ; clk_50MHz ; +; N/A ; None ; -5.952 ns ; button3 ; Arkanoid:inst|platform2_position[28] ; clk_50MHz ; +; N/A ; None ; -5.953 ns ; button3 ; Arkanoid:inst|platform2_position[23] ; clk_50MHz ; +; N/A ; None ; -5.960 ns ; button3 ; Arkanoid:inst|platform2_position[0] ; clk_50MHz ; +; N/A ; None ; -5.960 ns ; button3 ; Arkanoid:inst|platform2_position[20] ; clk_50MHz ; +; N/A ; None ; -5.978 ns ; button3 ; Arkanoid:inst|platform2_position[15] ; clk_50MHz ; +; N/A ; None ; -5.989 ns ; button3 ; Arkanoid:inst|platform2_position[1] ; clk_50MHz ; +; N/A ; None ; -6.008 ns ; button3 ; Arkanoid:inst|platform2_position[8] ; clk_50MHz ; +; N/A ; None ; -6.050 ns ; button3 ; Arkanoid:inst|platform2_position[21] ; clk_50MHz ; +; N/A ; None ; -6.056 ns ; button3 ; Arkanoid:inst|platform2_position[30] ; clk_50MHz ; +; N/A ; None ; -6.116 ns ; button3 ; Arkanoid:inst|platform2_position[9] ; clk_50MHz ; +; N/A ; None ; -6.127 ns ; button3 ; Arkanoid:inst|platform2_position[14] ; clk_50MHz ; +; N/A ; None ; -6.159 ns ; button3 ; Arkanoid:inst|platform2_position[4] ; clk_50MHz ; +; N/A ; None ; -6.243 ns ; button3 ; Arkanoid:inst|platform2_position[2] ; clk_50MHz ; +; N/A ; None ; -6.271 ns ; button3 ; Arkanoid:inst|platform2_position[18] ; clk_50MHz ; +; N/A ; None ; -6.354 ns ; button3 ; Arkanoid:inst|platform2_position[11] ; clk_50MHz ; +; N/A ; None ; -6.357 ns ; button3 ; Arkanoid:inst|platform2_position[12] ; clk_50MHz ; +; N/A ; None ; -6.584 ns ; button3 ; Arkanoid:inst|platform2_position[22] ; clk_50MHz ; +; N/A ; None ; -6.911 ns ; button3 ; Arkanoid:inst|platform2_position[13] ; clk_50MHz ; +; N/A ; None ; -6.992 ns ; button3 ; Arkanoid:inst|platform2_position[3] ; clk_50MHz ; +; N/A ; None ; -7.289 ns ; button2 ; Arkanoid:inst|red_[0] ; clk_50MHz ; +; N/A ; None ; -7.292 ns ; button2 ; Arkanoid:inst|green_[2] ; clk_50MHz ; +; N/A ; None ; -7.293 ns ; button2 ; Arkanoid:inst|red_[2] ; clk_50MHz ; +; N/A ; None ; -7.295 ns ; button2 ; Arkanoid:inst|blue_[3] ; clk_50MHz ; +; N/A ; None ; -7.550 ns ; button1 ; Arkanoid:inst|platform1_position[3] ; clk_50MHz ; +; N/A ; None ; -7.940 ns ; button2 ; Arkanoid:inst|red_[3] ; clk_50MHz ; +; N/A ; None ; -7.990 ns ; button2 ; Arkanoid:inst|green_[3] ; clk_50MHz ; +; N/A ; None ; -7.992 ns ; button2 ; Arkanoid:inst|red_[1] ; clk_50MHz ; +; N/A ; None ; -8.134 ns ; button2 ; Arkanoid:inst|blue_[0] ; clk_50MHz ; +; N/A ; None ; -8.359 ns ; button4 ; Arkanoid:inst|red_[0] ; clk_50MHz ; +; N/A ; None ; -8.361 ns ; button4 ; Arkanoid:inst|green_[2] ; clk_50MHz ; +; N/A ; None ; -8.365 ns ; button4 ; Arkanoid:inst|blue_[3] ; clk_50MHz ; +; N/A ; None ; -8.394 ns ; button4 ; Arkanoid:inst|red_[2] ; clk_50MHz ; +; N/A ; None ; -9.041 ns ; button4 ; Arkanoid:inst|red_[3] ; clk_50MHz ; +; N/A ; None ; -9.059 ns ; button4 ; Arkanoid:inst|green_[3] ; clk_50MHz ; +; N/A ; None ; -9.062 ns ; button4 ; Arkanoid:inst|red_[1] ; clk_50MHz ; +; N/A ; None ; -9.204 ns ; button4 ; Arkanoid:inst|blue_[0] ; clk_50MHz ; +; N/A ; None ; -10.107 ns ; button1 ; Arkanoid:inst|red_[0] ; clk_50MHz ; +; N/A ; None ; -10.110 ns ; button1 ; Arkanoid:inst|green_[2] ; clk_50MHz ; +; N/A ; None ; -10.111 ns ; button1 ; Arkanoid:inst|red_[2] ; clk_50MHz ; +; N/A ; None ; -10.113 ns ; button1 ; Arkanoid:inst|blue_[3] ; clk_50MHz ; +; N/A ; None ; -10.599 ns ; button3 ; Arkanoid:inst|red_[0] ; clk_50MHz ; +; N/A ; None ; -10.601 ns ; button3 ; Arkanoid:inst|green_[2] ; clk_50MHz ; +; N/A ; None ; -10.605 ns ; button3 ; Arkanoid:inst|blue_[3] ; clk_50MHz ; +; N/A ; None ; -10.634 ns ; button3 ; Arkanoid:inst|red_[2] ; clk_50MHz ; +; N/A ; None ; -10.758 ns ; button1 ; Arkanoid:inst|red_[3] ; clk_50MHz ; +; N/A ; None ; -10.808 ns ; button1 ; Arkanoid:inst|green_[3] ; clk_50MHz ; +; N/A ; None ; -10.810 ns ; button1 ; Arkanoid:inst|red_[1] ; clk_50MHz ; +; N/A ; None ; -10.952 ns ; button1 ; Arkanoid:inst|blue_[0] ; clk_50MHz ; +; N/A ; None ; -11.281 ns ; button3 ; Arkanoid:inst|red_[3] ; clk_50MHz ; +; N/A ; None ; -11.299 ns ; button3 ; Arkanoid:inst|green_[3] ; clk_50MHz ; +; N/A ; None ; -11.302 ns ; button3 ; Arkanoid:inst|red_[1] ; clk_50MHz ; +; N/A ; None ; -11.444 ns ; button3 ; Arkanoid:inst|blue_[0] ; clk_50MHz ; ++---------------+-------------+------------+---------+--------------------------------------+-----------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Classic Timing Analyzer + Info: Version 9.1 Build 222 10/21/2009 SJ Full Version + Info: Processing started: Mon May 21 19:54:40 2012 +Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid --timing_analysis_only +Info: Parallel compilation is enabled and will use 2 of the 2 processors detected +Warning: Found pins functioning as undefined clocks and/or memory enables + Info: Assuming node "clk_50MHz" is an undefined clock +Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew + Info: Detected ripple clock "Arkanoid:inst|clk25MHz_" as buffer +Info: Clock "clk_50MHz" has Internal fmax of 9.7 MHz between source register "Arkanoid:inst|h_counter[1]" and destination register "Arkanoid:inst|blue_[0]" (period= 103.135 ns) + Info: + Longest register to register delay is 102.875 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y11_N3; Fanout = 6; REG Node = 'Arkanoid:inst|h_counter[1]' + Info: 2: + IC(0.631 ns) + CELL(0.517 ns) = 1.148 ns; Loc. = LCCOMB_X15_Y11_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~1' + Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.228 ns; Loc. = LCCOMB_X15_Y11_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~3' + Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.308 ns; Loc. = LCCOMB_X15_Y11_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~5' + Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.388 ns; Loc. = LCCOMB_X15_Y11_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~7' + Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 1.468 ns; Loc. = LCCOMB_X15_Y11_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~9' + Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 1.548 ns; Loc. = LCCOMB_X15_Y11_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~11' + Info: 8: + IC(0.000 ns) + CELL(0.174 ns) = 1.722 ns; Loc. = LCCOMB_X15_Y11_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~13' + Info: 9: + IC(0.000 ns) + CELL(0.080 ns) = 1.802 ns; Loc. = LCCOMB_X15_Y11_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~15' + Info: 10: + IC(0.000 ns) + CELL(0.080 ns) = 1.882 ns; Loc. = LCCOMB_X15_Y11_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~17' + Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 1.962 ns; Loc. = LCCOMB_X15_Y11_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~19' + Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 2.042 ns; Loc. = LCCOMB_X15_Y11_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~21' + Info: 13: + IC(0.000 ns) + CELL(0.080 ns) = 2.122 ns; Loc. = LCCOMB_X15_Y11_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~23' + Info: 14: + IC(0.000 ns) + CELL(0.080 ns) = 2.202 ns; Loc. = LCCOMB_X15_Y11_N26; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~25' + Info: 15: + IC(0.000 ns) + CELL(0.080 ns) = 2.282 ns; Loc. = LCCOMB_X15_Y11_N28; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~27' + Info: 16: + IC(0.000 ns) + CELL(0.161 ns) = 2.443 ns; Loc. = LCCOMB_X15_Y11_N30; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~29' + Info: 17: + IC(0.000 ns) + CELL(0.080 ns) = 2.523 ns; Loc. = LCCOMB_X15_Y10_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~31' + Info: 18: + IC(0.000 ns) + CELL(0.080 ns) = 2.603 ns; Loc. = LCCOMB_X15_Y10_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~33' + Info: 19: + IC(0.000 ns) + CELL(0.080 ns) = 2.683 ns; Loc. = LCCOMB_X15_Y10_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~35' + Info: 20: + IC(0.000 ns) + CELL(0.080 ns) = 2.763 ns; Loc. = LCCOMB_X15_Y10_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~37' + Info: 21: + IC(0.000 ns) + CELL(0.080 ns) = 2.843 ns; Loc. = LCCOMB_X15_Y10_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~39' + Info: 22: + IC(0.000 ns) + CELL(0.080 ns) = 2.923 ns; Loc. = LCCOMB_X15_Y10_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~41' + Info: 23: + IC(0.000 ns) + CELL(0.080 ns) = 3.003 ns; Loc. = LCCOMB_X15_Y10_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~43' + Info: 24: + IC(0.000 ns) + CELL(0.174 ns) = 3.177 ns; Loc. = LCCOMB_X15_Y10_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~45' + Info: 25: + IC(0.000 ns) + CELL(0.080 ns) = 3.257 ns; Loc. = LCCOMB_X15_Y10_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~47' + Info: 26: + IC(0.000 ns) + CELL(0.080 ns) = 3.337 ns; Loc. = LCCOMB_X15_Y10_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~49' + Info: 27: + IC(0.000 ns) + CELL(0.080 ns) = 3.417 ns; Loc. = LCCOMB_X15_Y10_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~51' + Info: 28: + IC(0.000 ns) + CELL(0.080 ns) = 3.497 ns; Loc. = LCCOMB_X15_Y10_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~53' + Info: 29: + IC(0.000 ns) + CELL(0.080 ns) = 3.577 ns; Loc. = LCCOMB_X15_Y10_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~55' + Info: 30: + IC(0.000 ns) + CELL(0.080 ns) = 3.657 ns; Loc. = LCCOMB_X15_Y10_N26; Fanout = 2; COMB Node = 'Arkanoid:inst|Add8~57' + Info: 31: + IC(0.000 ns) + CELL(0.080 ns) = 3.737 ns; Loc. = LCCOMB_X15_Y10_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|Add8~59' + Info: 32: + IC(0.000 ns) + CELL(0.458 ns) = 4.195 ns; Loc. = LCCOMB_X15_Y10_N30; Fanout = 65; COMB Node = 'Arkanoid:inst|Add8~60' + Info: 33: + IC(1.268 ns) + CELL(0.495 ns) = 5.958 ns; Loc. = LCCOMB_X16_Y11_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~7' + Info: 34: + IC(0.000 ns) + CELL(0.080 ns) = 6.038 ns; Loc. = LCCOMB_X16_Y11_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~9' + Info: 35: + IC(0.000 ns) + CELL(0.080 ns) = 6.118 ns; Loc. = LCCOMB_X16_Y11_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~11' + Info: 36: + IC(0.000 ns) + CELL(0.080 ns) = 6.198 ns; Loc. = LCCOMB_X16_Y11_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~13' + Info: 37: + IC(0.000 ns) + CELL(0.174 ns) = 6.372 ns; Loc. = LCCOMB_X16_Y11_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~15' + Info: 38: + IC(0.000 ns) + CELL(0.080 ns) = 6.452 ns; Loc. = LCCOMB_X16_Y11_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~17' + Info: 39: + IC(0.000 ns) + CELL(0.080 ns) = 6.532 ns; Loc. = LCCOMB_X16_Y11_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~19' + Info: 40: + IC(0.000 ns) + CELL(0.080 ns) = 6.612 ns; Loc. = LCCOMB_X16_Y11_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~21' + Info: 41: + IC(0.000 ns) + CELL(0.080 ns) = 6.692 ns; Loc. = LCCOMB_X16_Y11_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~23' + Info: 42: + IC(0.000 ns) + CELL(0.080 ns) = 6.772 ns; Loc. = LCCOMB_X16_Y11_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~25' + Info: 43: + IC(0.000 ns) + CELL(0.080 ns) = 6.852 ns; Loc. = LCCOMB_X16_Y11_N26; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~27' + Info: 44: + IC(0.000 ns) + CELL(0.080 ns) = 6.932 ns; Loc. = LCCOMB_X16_Y11_N28; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~29' + Info: 45: + IC(0.000 ns) + CELL(0.161 ns) = 7.093 ns; Loc. = LCCOMB_X16_Y11_N30; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~31' + Info: 46: + IC(0.000 ns) + CELL(0.080 ns) = 7.173 ns; Loc. = LCCOMB_X16_Y10_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~33' + Info: 47: + IC(0.000 ns) + CELL(0.080 ns) = 7.253 ns; Loc. = LCCOMB_X16_Y10_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~35' + Info: 48: + IC(0.000 ns) + CELL(0.080 ns) = 7.333 ns; Loc. = LCCOMB_X16_Y10_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~37' + Info: 49: + IC(0.000 ns) + CELL(0.080 ns) = 7.413 ns; Loc. = LCCOMB_X16_Y10_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~39' + Info: 50: + IC(0.000 ns) + CELL(0.080 ns) = 7.493 ns; Loc. = LCCOMB_X16_Y10_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~41' + Info: 51: + IC(0.000 ns) + CELL(0.080 ns) = 7.573 ns; Loc. = LCCOMB_X16_Y10_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~43' + Info: 52: + IC(0.000 ns) + CELL(0.080 ns) = 7.653 ns; Loc. = LCCOMB_X16_Y10_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~45' + Info: 53: + IC(0.000 ns) + CELL(0.174 ns) = 7.827 ns; Loc. = LCCOMB_X16_Y10_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~47' + Info: 54: + IC(0.000 ns) + CELL(0.080 ns) = 7.907 ns; Loc. = LCCOMB_X16_Y10_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~49' + Info: 55: + IC(0.000 ns) + CELL(0.080 ns) = 7.987 ns; Loc. = LCCOMB_X16_Y10_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~51' + Info: 56: + IC(0.000 ns) + CELL(0.080 ns) = 8.067 ns; Loc. = LCCOMB_X16_Y10_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~53' + Info: 57: + IC(0.000 ns) + CELL(0.080 ns) = 8.147 ns; Loc. = LCCOMB_X16_Y10_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~55' + Info: 58: + IC(0.000 ns) + CELL(0.080 ns) = 8.227 ns; Loc. = LCCOMB_X16_Y10_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~57' + Info: 59: + IC(0.000 ns) + CELL(0.458 ns) = 8.685 ns; Loc. = LCCOMB_X16_Y10_N26; Fanout = 4; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num|cs2a[1]~58' + Info: 60: + IC(1.260 ns) + CELL(0.495 ns) = 10.440 ns; Loc. = LCCOMB_X16_Y15_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_4_result_int[2]~1' + Info: 61: + IC(0.000 ns) + CELL(0.080 ns) = 10.520 ns; Loc. = LCCOMB_X16_Y15_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_4_result_int[3]~3' + Info: 62: + IC(0.000 ns) + CELL(0.080 ns) = 10.600 ns; Loc. = LCCOMB_X16_Y15_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_4_result_int[4]~5' + Info: 63: + IC(0.000 ns) + CELL(0.458 ns) = 11.058 ns; Loc. = LCCOMB_X16_Y15_N28; Fanout = 11; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_4_result_int[5]~6' + Info: 64: + IC(0.859 ns) + CELL(0.177 ns) = 12.094 ns; Loc. = LCCOMB_X18_Y15_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[29]~435' + Info: 65: + IC(0.836 ns) + CELL(0.517 ns) = 13.447 ns; Loc. = LCCOMB_X16_Y15_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_5_result_int[2]~1' + Info: 66: + IC(0.000 ns) + CELL(0.080 ns) = 13.527 ns; Loc. = LCCOMB_X16_Y15_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_5_result_int[3]~3' + Info: 67: + IC(0.000 ns) + CELL(0.174 ns) = 13.701 ns; Loc. = LCCOMB_X16_Y15_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_5_result_int[4]~5' + Info: 68: + IC(0.000 ns) + CELL(0.080 ns) = 13.781 ns; Loc. = LCCOMB_X16_Y15_N16; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_5_result_int[5]~7' + Info: 69: + IC(0.000 ns) + CELL(0.458 ns) = 14.239 ns; Loc. = LCCOMB_X16_Y15_N18; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_5_result_int[6]~8' + Info: 70: + IC(0.930 ns) + CELL(0.177 ns) = 15.346 ns; Loc. = LCCOMB_X18_Y15_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[36]~442' + Info: 71: + IC(0.516 ns) + CELL(0.495 ns) = 16.357 ns; Loc. = LCCOMB_X19_Y15_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[2]~1' + Info: 72: + IC(0.000 ns) + CELL(0.080 ns) = 16.437 ns; Loc. = LCCOMB_X19_Y15_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[3]~3' + Info: 73: + IC(0.000 ns) + CELL(0.080 ns) = 16.517 ns; Loc. = LCCOMB_X19_Y15_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[4]~5' + Info: 74: + IC(0.000 ns) + CELL(0.080 ns) = 16.597 ns; Loc. = LCCOMB_X19_Y15_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[5]~7' + Info: 75: + IC(0.000 ns) + CELL(0.080 ns) = 16.677 ns; Loc. = LCCOMB_X19_Y15_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[6]~9' + Info: 76: + IC(0.000 ns) + CELL(0.458 ns) = 17.135 ns; Loc. = LCCOMB_X19_Y15_N28; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_6_result_int[7]~10' + Info: 77: + IC(0.920 ns) + CELL(0.178 ns) = 18.233 ns; Loc. = LCCOMB_X20_Y18_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[43]~447' + Info: 78: + IC(0.914 ns) + CELL(0.517 ns) = 19.664 ns; Loc. = LCCOMB_X19_Y15_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[2]~1' + Info: 79: + IC(0.000 ns) + CELL(0.080 ns) = 19.744 ns; Loc. = LCCOMB_X19_Y15_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[3]~3' + Info: 80: + IC(0.000 ns) + CELL(0.080 ns) = 19.824 ns; Loc. = LCCOMB_X19_Y15_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[4]~5' + Info: 81: + IC(0.000 ns) + CELL(0.080 ns) = 19.904 ns; Loc. = LCCOMB_X19_Y15_N8; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[5]~7' + Info: 82: + IC(0.000 ns) + CELL(0.080 ns) = 19.984 ns; Loc. = LCCOMB_X19_Y15_N10; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[6]~9' + Info: 83: + IC(0.000 ns) + CELL(0.458 ns) = 20.442 ns; Loc. = LCCOMB_X19_Y15_N12; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_7_result_int[7]~10' + Info: 84: + IC(0.994 ns) + CELL(0.178 ns) = 21.614 ns; Loc. = LCCOMB_X20_Y18_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[50]~453' + Info: 85: + IC(0.551 ns) + CELL(0.517 ns) = 22.682 ns; Loc. = LCCOMB_X19_Y18_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[2]~1' + Info: 86: + IC(0.000 ns) + CELL(0.080 ns) = 22.762 ns; Loc. = LCCOMB_X19_Y18_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[3]~3' + Info: 87: + IC(0.000 ns) + CELL(0.080 ns) = 22.842 ns; Loc. = LCCOMB_X19_Y18_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[4]~5' + Info: 88: + IC(0.000 ns) + CELL(0.080 ns) = 22.922 ns; Loc. = LCCOMB_X19_Y18_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[5]~7' + Info: 89: + IC(0.000 ns) + CELL(0.080 ns) = 23.002 ns; Loc. = LCCOMB_X19_Y18_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[6]~9' + Info: 90: + IC(0.000 ns) + CELL(0.458 ns) = 23.460 ns; Loc. = LCCOMB_X19_Y18_N30; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_8_result_int[7]~10' + Info: 91: + IC(0.943 ns) + CELL(0.322 ns) = 24.725 ns; Loc. = LCCOMB_X19_Y22_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[57]~460' + Info: 92: + IC(0.909 ns) + CELL(0.517 ns) = 26.151 ns; Loc. = LCCOMB_X19_Y18_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[2]~1' + Info: 93: + IC(0.000 ns) + CELL(0.080 ns) = 26.231 ns; Loc. = LCCOMB_X19_Y18_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[3]~3' + Info: 94: + IC(0.000 ns) + CELL(0.080 ns) = 26.311 ns; Loc. = LCCOMB_X19_Y18_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[4]~5' + Info: 95: + IC(0.000 ns) + CELL(0.080 ns) = 26.391 ns; Loc. = LCCOMB_X19_Y18_N6; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[5]~7' + Info: 96: + IC(0.000 ns) + CELL(0.080 ns) = 26.471 ns; Loc. = LCCOMB_X19_Y18_N8; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[6]~9' + Info: 97: + IC(0.000 ns) + CELL(0.458 ns) = 26.929 ns; Loc. = LCCOMB_X19_Y18_N10; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_9_result_int[7]~10' + Info: 98: + IC(0.922 ns) + CELL(0.322 ns) = 28.173 ns; Loc. = LCCOMB_X19_Y22_N12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[68]~461' + Info: 99: + IC(0.793 ns) + CELL(0.495 ns) = 29.461 ns; Loc. = LCCOMB_X20_Y22_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_10_result_int[6]~9' + Info: 100: + IC(0.000 ns) + CELL(0.458 ns) = 29.919 ns; Loc. = LCCOMB_X20_Y22_N30; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_10_result_int[7]~10' + Info: 101: + IC(1.241 ns) + CELL(0.177 ns) = 31.337 ns; Loc. = LCCOMB_X20_Y21_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[71]~472' + Info: 102: + IC(0.872 ns) + CELL(0.517 ns) = 32.726 ns; Loc. = LCCOMB_X20_Y22_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_11_result_int[2]~1' + Info: 103: + IC(0.000 ns) + CELL(0.080 ns) = 32.806 ns; Loc. = LCCOMB_X20_Y22_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_11_result_int[3]~3' + Info: 104: + IC(0.000 ns) + CELL(0.458 ns) = 33.264 ns; Loc. = LCCOMB_X20_Y22_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_11_result_int[4]~4' + Info: 105: + IC(1.206 ns) + CELL(0.178 ns) = 34.648 ns; Loc. = LCCOMB_X20_Y21_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[81]~474' + Info: 106: + IC(0.839 ns) + CELL(0.517 ns) = 36.004 ns; Loc. = LCCOMB_X19_Y21_N20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_12_result_int[5]~7' + Info: 107: + IC(0.000 ns) + CELL(0.080 ns) = 36.084 ns; Loc. = LCCOMB_X19_Y21_N22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_12_result_int[6]~9' + Info: 108: + IC(0.000 ns) + CELL(0.458 ns) = 36.542 ns; Loc. = LCCOMB_X19_Y21_N24; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_12_result_int[7]~10' + Info: 109: + IC(0.602 ns) + CELL(0.178 ns) = 37.322 ns; Loc. = LCCOMB_X20_Y21_N30; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[89]~605' + Info: 110: + IC(0.814 ns) + CELL(0.517 ns) = 38.653 ns; Loc. = LCCOMB_X19_Y21_N8; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_13_result_int[6]~9' + Info: 111: + IC(0.000 ns) + CELL(0.458 ns) = 39.111 ns; Loc. = LCCOMB_X19_Y21_N10; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_13_result_int[7]~10' + Info: 112: + IC(0.634 ns) + CELL(0.322 ns) = 40.067 ns; Loc. = LCCOMB_X18_Y21_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[92]~490' + Info: 113: + IC(0.884 ns) + CELL(0.517 ns) = 41.468 ns; Loc. = LCCOMB_X19_Y20_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[2]~1' + Info: 114: + IC(0.000 ns) + CELL(0.080 ns) = 41.548 ns; Loc. = LCCOMB_X19_Y20_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[3]~3' + Info: 115: + IC(0.000 ns) + CELL(0.080 ns) = 41.628 ns; Loc. = LCCOMB_X19_Y20_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[4]~5' + Info: 116: + IC(0.000 ns) + CELL(0.174 ns) = 41.802 ns; Loc. = LCCOMB_X19_Y20_N14; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[5]~7' + Info: 117: + IC(0.000 ns) + CELL(0.080 ns) = 41.882 ns; Loc. = LCCOMB_X19_Y20_N16; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[6]~9' + Info: 118: + IC(0.000 ns) + CELL(0.458 ns) = 42.340 ns; Loc. = LCCOMB_X19_Y20_N18; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_14_result_int[7]~10' + Info: 119: + IC(0.917 ns) + CELL(0.322 ns) = 43.579 ns; Loc. = LCCOMB_X18_Y21_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[99]~495' + Info: 120: + IC(0.856 ns) + CELL(0.495 ns) = 44.930 ns; Loc. = LCCOMB_X18_Y20_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[2]~1' + Info: 121: + IC(0.000 ns) + CELL(0.080 ns) = 45.010 ns; Loc. = LCCOMB_X18_Y20_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[3]~3' + Info: 122: + IC(0.000 ns) + CELL(0.080 ns) = 45.090 ns; Loc. = LCCOMB_X18_Y20_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[4]~5' + Info: 123: + IC(0.000 ns) + CELL(0.080 ns) = 45.170 ns; Loc. = LCCOMB_X18_Y20_N6; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[5]~7' + Info: 124: + IC(0.000 ns) + CELL(0.080 ns) = 45.250 ns; Loc. = LCCOMB_X18_Y20_N8; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[6]~9' + Info: 125: + IC(0.000 ns) + CELL(0.458 ns) = 45.708 ns; Loc. = LCCOMB_X18_Y20_N10; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_15_result_int[7]~10' + Info: 126: + IC(0.897 ns) + CELL(0.177 ns) = 46.782 ns; Loc. = LCCOMB_X19_Y19_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[106]~502' + Info: 127: + IC(0.835 ns) + CELL(0.517 ns) = 48.134 ns; Loc. = LCCOMB_X19_Y20_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[2]~1' + Info: 128: + IC(0.000 ns) + CELL(0.080 ns) = 48.214 ns; Loc. = LCCOMB_X19_Y20_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[3]~3' + Info: 129: + IC(0.000 ns) + CELL(0.080 ns) = 48.294 ns; Loc. = LCCOMB_X19_Y20_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[4]~5' + Info: 130: + IC(0.000 ns) + CELL(0.080 ns) = 48.374 ns; Loc. = LCCOMB_X19_Y20_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[5]~7' + Info: 131: + IC(0.000 ns) + CELL(0.080 ns) = 48.454 ns; Loc. = LCCOMB_X19_Y20_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[6]~9' + Info: 132: + IC(0.000 ns) + CELL(0.458 ns) = 48.912 ns; Loc. = LCCOMB_X19_Y20_N30; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_16_result_int[7]~10' + Info: 133: + IC(0.961 ns) + CELL(0.177 ns) = 50.050 ns; Loc. = LCCOMB_X18_Y19_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[113]~508' + Info: 134: + IC(0.579 ns) + CELL(0.517 ns) = 51.146 ns; Loc. = LCCOMB_X18_Y19_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[2]~1' + Info: 135: + IC(0.000 ns) + CELL(0.080 ns) = 51.226 ns; Loc. = LCCOMB_X18_Y19_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[3]~3' + Info: 136: + IC(0.000 ns) + CELL(0.080 ns) = 51.306 ns; Loc. = LCCOMB_X18_Y19_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[4]~5' + Info: 137: + IC(0.000 ns) + CELL(0.080 ns) = 51.386 ns; Loc. = LCCOMB_X18_Y19_N12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[5]~7' + Info: 138: + IC(0.000 ns) + CELL(0.174 ns) = 51.560 ns; Loc. = LCCOMB_X18_Y19_N14; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[6]~9' + Info: 139: + IC(0.000 ns) + CELL(0.458 ns) = 52.018 ns; Loc. = LCCOMB_X18_Y19_N16; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_17_result_int[7]~10' + Info: 140: + IC(0.340 ns) + CELL(0.319 ns) = 52.677 ns; Loc. = LCCOMB_X18_Y19_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[120]~513' + Info: 141: + IC(0.549 ns) + CELL(0.517 ns) = 53.743 ns; Loc. = LCCOMB_X19_Y19_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_18_result_int[2]~1' + Info: 142: + IC(0.000 ns) + CELL(0.080 ns) = 53.823 ns; Loc. = LCCOMB_X19_Y19_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_18_result_int[3]~3' + Info: 143: + IC(0.000 ns) + CELL(0.080 ns) = 53.903 ns; Loc. = LCCOMB_X19_Y19_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_18_result_int[4]~5' + Info: 144: + IC(0.000 ns) + CELL(0.458 ns) = 54.361 ns; Loc. = LCCOMB_X19_Y19_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_18_result_int[5]~6' + Info: 145: + IC(0.552 ns) + CELL(0.521 ns) = 55.434 ns; Loc. = LCCOMB_X20_Y19_N0; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[131]~515' + Info: 146: + IC(0.552 ns) + CELL(0.517 ns) = 56.503 ns; Loc. = LCCOMB_X20_Y19_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_19_result_int[6]~9' + Info: 147: + IC(0.000 ns) + CELL(0.458 ns) = 56.961 ns; Loc. = LCCOMB_X20_Y19_N26; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_19_result_int[7]~10' + Info: 148: + IC(0.650 ns) + CELL(0.177 ns) = 57.788 ns; Loc. = LCCOMB_X21_Y19_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[134]~526' + Info: 149: + IC(0.544 ns) + CELL(0.517 ns) = 58.849 ns; Loc. = LCCOMB_X22_Y19_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[2]~1' + Info: 150: + IC(0.000 ns) + CELL(0.080 ns) = 58.929 ns; Loc. = LCCOMB_X22_Y19_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[3]~3' + Info: 151: + IC(0.000 ns) + CELL(0.080 ns) = 59.009 ns; Loc. = LCCOMB_X22_Y19_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[4]~5' + Info: 152: + IC(0.000 ns) + CELL(0.080 ns) = 59.089 ns; Loc. = LCCOMB_X22_Y19_N6; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[5]~7' + Info: 153: + IC(0.000 ns) + CELL(0.080 ns) = 59.169 ns; Loc. = LCCOMB_X22_Y19_N8; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[6]~9' + Info: 154: + IC(0.000 ns) + CELL(0.458 ns) = 59.627 ns; Loc. = LCCOMB_X22_Y19_N10; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_20_result_int[7]~10' + Info: 155: + IC(0.863 ns) + CELL(0.178 ns) = 60.668 ns; Loc. = LCCOMB_X22_Y22_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[141]~531' + Info: 156: + IC(0.901 ns) + CELL(0.517 ns) = 62.086 ns; Loc. = LCCOMB_X22_Y19_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[2]~1' + Info: 157: + IC(0.000 ns) + CELL(0.080 ns) = 62.166 ns; Loc. = LCCOMB_X22_Y19_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[3]~3' + Info: 158: + IC(0.000 ns) + CELL(0.080 ns) = 62.246 ns; Loc. = LCCOMB_X22_Y19_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[4]~5' + Info: 159: + IC(0.000 ns) + CELL(0.080 ns) = 62.326 ns; Loc. = LCCOMB_X22_Y19_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[5]~7' + Info: 160: + IC(0.000 ns) + CELL(0.080 ns) = 62.406 ns; Loc. = LCCOMB_X22_Y19_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[6]~9' + Info: 161: + IC(0.000 ns) + CELL(0.458 ns) = 62.864 ns; Loc. = LCCOMB_X22_Y19_N28; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_21_result_int[7]~10' + Info: 162: + IC(0.946 ns) + CELL(0.178 ns) = 63.988 ns; Loc. = LCCOMB_X22_Y22_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[148]~537' + Info: 163: + IC(0.805 ns) + CELL(0.495 ns) = 65.288 ns; Loc. = LCCOMB_X23_Y22_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_22_result_int[2]~1' + Info: 164: + IC(0.000 ns) + CELL(0.080 ns) = 65.368 ns; Loc. = LCCOMB_X23_Y22_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_22_result_int[3]~3' + Info: 165: + IC(0.000 ns) + CELL(0.080 ns) = 65.448 ns; Loc. = LCCOMB_X23_Y22_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_22_result_int[4]~5' + Info: 166: + IC(0.000 ns) + CELL(0.080 ns) = 65.528 ns; Loc. = LCCOMB_X23_Y22_N10; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_22_result_int[5]~7' + Info: 167: + IC(0.000 ns) + CELL(0.080 ns) = 65.608 ns; Loc. = LCCOMB_X23_Y22_N12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_22_result_int[6]~9' + Info: 168: + IC(0.000 ns) + CELL(0.458 ns) = 66.066 ns; Loc. = LCCOMB_X23_Y22_N14; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_22_result_int[7]~10' + Info: 169: + IC(0.562 ns) + CELL(0.322 ns) = 66.950 ns; Loc. = LCCOMB_X22_Y22_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[156]~663' + Info: 170: + IC(0.545 ns) + CELL(0.517 ns) = 68.012 ns; Loc. = LCCOMB_X23_Y22_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[3]~3' + Info: 171: + IC(0.000 ns) + CELL(0.080 ns) = 68.092 ns; Loc. = LCCOMB_X23_Y22_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[4]~5' + Info: 172: + IC(0.000 ns) + CELL(0.080 ns) = 68.172 ns; Loc. = LCCOMB_X23_Y22_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[5]~7' + Info: 173: + IC(0.000 ns) + CELL(0.080 ns) = 68.252 ns; Loc. = LCCOMB_X23_Y22_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[6]~9' + Info: 174: + IC(0.000 ns) + CELL(0.458 ns) = 68.710 ns; Loc. = LCCOMB_X23_Y22_N30; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_23_result_int[7]~10' + Info: 175: + IC(0.550 ns) + CELL(0.322 ns) = 69.582 ns; Loc. = LCCOMB_X24_Y22_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[162]~550' + Info: 176: + IC(0.550 ns) + CELL(0.517 ns) = 70.649 ns; Loc. = LCCOMB_X25_Y22_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_24_result_int[2]~1' + Info: 177: + IC(0.000 ns) + CELL(0.080 ns) = 70.729 ns; Loc. = LCCOMB_X25_Y22_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_24_result_int[3]~3' + Info: 178: + IC(0.000 ns) + CELL(0.080 ns) = 70.809 ns; Loc. = LCCOMB_X25_Y22_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_24_result_int[4]~5' + Info: 179: + IC(0.000 ns) + CELL(0.080 ns) = 70.889 ns; Loc. = LCCOMB_X25_Y22_N10; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_24_result_int[5]~7' + Info: 180: + IC(0.000 ns) + CELL(0.080 ns) = 70.969 ns; Loc. = LCCOMB_X25_Y22_N12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_24_result_int[6]~9' + Info: 181: + IC(0.000 ns) + CELL(0.458 ns) = 71.427 ns; Loc. = LCCOMB_X25_Y22_N14; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_24_result_int[7]~10' + Info: 182: + IC(1.167 ns) + CELL(0.177 ns) = 72.771 ns; Loc. = LCCOMB_X30_Y22_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[169]~556' + Info: 183: + IC(1.111 ns) + CELL(0.517 ns) = 74.399 ns; Loc. = LCCOMB_X25_Y22_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[2]~1' + Info: 184: + IC(0.000 ns) + CELL(0.080 ns) = 74.479 ns; Loc. = LCCOMB_X25_Y22_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[3]~3' + Info: 185: + IC(0.000 ns) + CELL(0.080 ns) = 74.559 ns; Loc. = LCCOMB_X25_Y22_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[4]~5' + Info: 186: + IC(0.000 ns) + CELL(0.080 ns) = 74.639 ns; Loc. = LCCOMB_X25_Y22_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[5]~7' + Info: 187: + IC(0.000 ns) + CELL(0.080 ns) = 74.719 ns; Loc. = LCCOMB_X25_Y22_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[6]~9' + Info: 188: + IC(0.000 ns) + CELL(0.458 ns) = 75.177 ns; Loc. = LCCOMB_X25_Y22_N30; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_25_result_int[7]~10' + Info: 189: + IC(1.167 ns) + CELL(0.177 ns) = 76.521 ns; Loc. = LCCOMB_X30_Y22_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[176]~562' + Info: 190: + IC(0.542 ns) + CELL(0.517 ns) = 77.580 ns; Loc. = LCCOMB_X31_Y22_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_26_result_int[2]~1' + Info: 191: + IC(0.000 ns) + CELL(0.080 ns) = 77.660 ns; Loc. = LCCOMB_X31_Y22_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_26_result_int[3]~3' + Info: 192: + IC(0.000 ns) + CELL(0.080 ns) = 77.740 ns; Loc. = LCCOMB_X31_Y22_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_26_result_int[4]~5' + Info: 193: + IC(0.000 ns) + CELL(0.080 ns) = 77.820 ns; Loc. = LCCOMB_X31_Y22_N22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_26_result_int[5]~7' + Info: 194: + IC(0.000 ns) + CELL(0.080 ns) = 77.900 ns; Loc. = LCCOMB_X31_Y22_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_26_result_int[6]~9' + Info: 195: + IC(0.000 ns) + CELL(0.458 ns) = 78.358 ns; Loc. = LCCOMB_X31_Y22_N26; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_26_result_int[7]~10' + Info: 196: + IC(1.188 ns) + CELL(0.178 ns) = 79.724 ns; Loc. = LCCOMB_X34_Y20_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[183]~567' + Info: 197: + IC(1.156 ns) + CELL(0.517 ns) = 81.397 ns; Loc. = LCCOMB_X31_Y22_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[2]~1' + Info: 198: + IC(0.000 ns) + CELL(0.080 ns) = 81.477 ns; Loc. = LCCOMB_X31_Y22_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[3]~3' + Info: 199: + IC(0.000 ns) + CELL(0.080 ns) = 81.557 ns; Loc. = LCCOMB_X31_Y22_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[4]~5' + Info: 200: + IC(0.000 ns) + CELL(0.080 ns) = 81.637 ns; Loc. = LCCOMB_X31_Y22_N10; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[5]~7' + Info: 201: + IC(0.000 ns) + CELL(0.080 ns) = 81.717 ns; Loc. = LCCOMB_X31_Y22_N12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[6]~9' + Info: 202: + IC(0.000 ns) + CELL(0.458 ns) = 82.175 ns; Loc. = LCCOMB_X31_Y22_N14; Fanout = 15; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_27_result_int[7]~10' + Info: 203: + IC(0.522 ns) + CELL(0.322 ns) = 83.019 ns; Loc. = LCCOMB_X30_Y22_N6; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[192]~692' + Info: 204: + IC(1.442 ns) + CELL(0.517 ns) = 84.978 ns; Loc. = LCCOMB_X35_Y20_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_28_result_int[4]~5' + Info: 205: + IC(0.000 ns) + CELL(0.080 ns) = 85.058 ns; Loc. = LCCOMB_X35_Y20_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_28_result_int[5]~7' + Info: 206: + IC(0.000 ns) + CELL(0.080 ns) = 85.138 ns; Loc. = LCCOMB_X35_Y20_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_28_result_int[6]~9' + Info: 207: + IC(0.000 ns) + CELL(0.458 ns) = 85.596 ns; Loc. = LCCOMB_X35_Y20_N30; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_28_result_int[7]~10' + Info: 208: + IC(0.554 ns) + CELL(0.177 ns) = 86.327 ns; Loc. = LCCOMB_X34_Y20_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[197]~580' + Info: 209: + IC(0.543 ns) + CELL(0.517 ns) = 87.387 ns; Loc. = LCCOMB_X35_Y20_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[2]~1' + Info: 210: + IC(0.000 ns) + CELL(0.080 ns) = 87.467 ns; Loc. = LCCOMB_X35_Y20_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[3]~3' + Info: 211: + IC(0.000 ns) + CELL(0.080 ns) = 87.547 ns; Loc. = LCCOMB_X35_Y20_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[4]~5' + Info: 212: + IC(0.000 ns) + CELL(0.080 ns) = 87.627 ns; Loc. = LCCOMB_X35_Y20_N12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[5]~7' + Info: 213: + IC(0.000 ns) + CELL(0.174 ns) = 87.801 ns; Loc. = LCCOMB_X35_Y20_N14; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[6]~9' + Info: 214: + IC(0.000 ns) + CELL(0.458 ns) = 88.259 ns; Loc. = LCCOMB_X35_Y20_N16; Fanout = 16; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_29_result_int[7]~10' + Info: 215: + IC(0.912 ns) + CELL(0.178 ns) = 89.349 ns; Loc. = LCCOMB_X36_Y18_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[205]~670' + Info: 216: + IC(0.537 ns) + CELL(0.517 ns) = 90.403 ns; Loc. = LCCOMB_X35_Y18_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_30_result_int[3]~3' + Info: 217: + IC(0.000 ns) + CELL(0.080 ns) = 90.483 ns; Loc. = LCCOMB_X35_Y18_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_30_result_int[4]~5' + Info: 218: + IC(0.000 ns) + CELL(0.080 ns) = 90.563 ns; Loc. = LCCOMB_X35_Y18_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_30_result_int[5]~7' + Info: 219: + IC(0.000 ns) + CELL(0.080 ns) = 90.643 ns; Loc. = LCCOMB_X35_Y18_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_30_result_int[6]~9' + Info: 220: + IC(0.000 ns) + CELL(0.458 ns) = 91.101 ns; Loc. = LCCOMB_X35_Y18_N28; Fanout = 13; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_30_result_int[7]~10' + Info: 221: + IC(0.898 ns) + CELL(0.178 ns) = 92.177 ns; Loc. = LCCOMB_X35_Y16_N12; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|StageOut[211]~591' + Info: 222: + IC(0.314 ns) + CELL(0.517 ns) = 93.008 ns; Loc. = LCCOMB_X35_Y16_N18; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[2]~1' + Info: 223: + IC(0.000 ns) + CELL(0.080 ns) = 93.088 ns; Loc. = LCCOMB_X35_Y16_N20; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[3]~3' + Info: 224: + IC(0.000 ns) + CELL(0.080 ns) = 93.168 ns; Loc. = LCCOMB_X35_Y16_N22; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[4]~5' + Info: 225: + IC(0.000 ns) + CELL(0.080 ns) = 93.248 ns; Loc. = LCCOMB_X35_Y16_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[5]~7' + Info: 226: + IC(0.000 ns) + CELL(0.080 ns) = 93.328 ns; Loc. = LCCOMB_X35_Y16_N26; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[6]~9' + Info: 227: + IC(0.000 ns) + CELL(0.458 ns) = 93.786 ns; Loc. = LCCOMB_X35_Y16_N28; Fanout = 3; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider|add_sub_31_result_int[7]~10' + Info: 228: + IC(0.825 ns) + CELL(0.521 ns) = 95.132 ns; Loc. = LCCOMB_X31_Y16_N14; Fanout = 1; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|op_1~0' + Info: 229: + IC(0.817 ns) + CELL(0.178 ns) = 96.127 ns; Loc. = LCCOMB_X35_Y16_N0; Fanout = 19; COMB Node = 'Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|quotient[0]~4' + Info: 230: + IC(0.322 ns) + CELL(0.178 ns) = 96.627 ns; Loc. = LCCOMB_X35_Y16_N4; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~15' + Info: 231: + IC(0.300 ns) + CELL(0.322 ns) = 97.249 ns; Loc. = LCCOMB_X35_Y16_N6; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~16' + Info: 232: + IC(1.103 ns) + CELL(0.178 ns) = 98.530 ns; Loc. = LCCOMB_X30_Y16_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~17' + Info: 233: + IC(0.296 ns) + CELL(0.178 ns) = 99.004 ns; Loc. = LCCOMB_X30_Y16_N0; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~18' + Info: 234: + IC(0.298 ns) + CELL(0.178 ns) = 99.480 ns; Loc. = LCCOMB_X30_Y16_N18; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~19' + Info: 235: + IC(0.289 ns) + CELL(0.178 ns) = 99.947 ns; Loc. = LCCOMB_X30_Y16_N22; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux0~22' + Info: 236: + IC(1.156 ns) + CELL(0.178 ns) = 101.281 ns; Loc. = LCCOMB_X27_Y18_N16; Fanout = 4; COMB Node = 'Arkanoid:inst|Mux3~3' + Info: 237: + IC(0.337 ns) + CELL(0.322 ns) = 101.940 ns; Loc. = LCCOMB_X27_Y18_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|blue_~1' + Info: 238: + IC(0.522 ns) + CELL(0.413 ns) = 102.875 ns; Loc. = LCFF_X26_Y18_N11; Fanout = 1; REG Node = 'Arkanoid:inst|blue_[0]' + Info: Total cell delay = 50.265 ns ( 48.86 % ) + Info: Total interconnect delay = 52.610 ns ( 51.14 % ) + Info: - Smallest clock skew is -0.021 ns + Info: + Shortest clock path from clock "clk_50MHz" to destination register is 4.594 ns + Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz' + Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'Arkanoid:inst|clk25MHz_' + Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G2; Fanout = 150; COMB Node = 'Arkanoid:inst|clk25MHz_~clkctrl' + Info: 4: + IC(0.980 ns) + CELL(0.602 ns) = 4.594 ns; Loc. = LCFF_X26_Y18_N11; Fanout = 1; REG Node = 'Arkanoid:inst|blue_[0]' + Info: Total cell delay = 2.507 ns ( 54.57 % ) + Info: Total interconnect delay = 2.087 ns ( 45.43 % ) + Info: - Longest clock path from clock "clk_50MHz" to source register is 4.615 ns + Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz' + Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'Arkanoid:inst|clk25MHz_' + Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G2; Fanout = 150; COMB Node = 'Arkanoid:inst|clk25MHz_~clkctrl' + Info: 4: + IC(1.001 ns) + CELL(0.602 ns) = 4.615 ns; Loc. = LCFF_X14_Y11_N3; Fanout = 6; REG Node = 'Arkanoid:inst|h_counter[1]' + Info: Total cell delay = 2.507 ns ( 54.32 % ) + Info: Total interconnect delay = 2.108 ns ( 45.68 % ) + Info: + Micro clock to output delay of source is 0.277 ns + Info: + Micro setup delay of destination is -0.038 ns +Info: tsu for register "Arkanoid:inst|blue_[0]" (data pin = "button3", clock pin = "clk_50MHz") is 32.749 ns + Info: + Longest pin to register delay is 37.381 ns + Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_R21; Fanout = 5; PIN Node = 'button3' + Info: 2: + IC(6.425 ns) + CELL(0.521 ns) = 7.810 ns; Loc. = LCCOMB_X34_Y21_N26; Fanout = 63; COMB Node = 'Arkanoid:inst|platform2_position~0' + Info: 3: + IC(0.990 ns) + CELL(0.495 ns) = 9.295 ns; Loc. = LCCOMB_X34_Y19_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~1' + Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 9.375 ns; Loc. = LCCOMB_X34_Y19_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~3' + Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 9.455 ns; Loc. = LCCOMB_X34_Y19_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~5' + Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 9.535 ns; Loc. = LCCOMB_X34_Y19_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~7' + Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 9.615 ns; Loc. = LCCOMB_X34_Y19_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~9' + Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 9.695 ns; Loc. = LCCOMB_X34_Y19_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~11' + Info: 9: + IC(0.000 ns) + CELL(0.080 ns) = 9.775 ns; Loc. = LCCOMB_X34_Y19_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~13' + Info: 10: + IC(0.000 ns) + CELL(0.174 ns) = 9.949 ns; Loc. = LCCOMB_X34_Y19_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~15' + Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 10.029 ns; Loc. = LCCOMB_X34_Y19_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~17' + Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 10.109 ns; Loc. = LCCOMB_X34_Y19_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~19' + Info: 13: + IC(0.000 ns) + CELL(0.080 ns) = 10.189 ns; Loc. = LCCOMB_X34_Y19_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~21' + Info: 14: + IC(0.000 ns) + CELL(0.080 ns) = 10.269 ns; Loc. = LCCOMB_X34_Y19_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~23' + Info: 15: + IC(0.000 ns) + CELL(0.080 ns) = 10.349 ns; Loc. = LCCOMB_X34_Y19_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~25' + Info: 16: + IC(0.000 ns) + CELL(0.080 ns) = 10.429 ns; Loc. = LCCOMB_X34_Y19_N26; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~27' + Info: 17: + IC(0.000 ns) + CELL(0.080 ns) = 10.509 ns; Loc. = LCCOMB_X34_Y19_N28; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~29' + Info: 18: + IC(0.000 ns) + CELL(0.161 ns) = 10.670 ns; Loc. = LCCOMB_X34_Y19_N30; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~31' + Info: 19: + IC(0.000 ns) + CELL(0.080 ns) = 10.750 ns; Loc. = LCCOMB_X34_Y18_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~33' + Info: 20: + IC(0.000 ns) + CELL(0.080 ns) = 10.830 ns; Loc. = LCCOMB_X34_Y18_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~35' + Info: 21: + IC(0.000 ns) + CELL(0.080 ns) = 10.910 ns; Loc. = LCCOMB_X34_Y18_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~37' + Info: 22: + IC(0.000 ns) + CELL(0.080 ns) = 10.990 ns; Loc. = LCCOMB_X34_Y18_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~39' + Info: 23: + IC(0.000 ns) + CELL(0.080 ns) = 11.070 ns; Loc. = LCCOMB_X34_Y18_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~41' + Info: 24: + IC(0.000 ns) + CELL(0.080 ns) = 11.150 ns; Loc. = LCCOMB_X34_Y18_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~43' + Info: 25: + IC(0.000 ns) + CELL(0.080 ns) = 11.230 ns; Loc. = LCCOMB_X34_Y18_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~45' + Info: 26: + IC(0.000 ns) + CELL(0.174 ns) = 11.404 ns; Loc. = LCCOMB_X34_Y18_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~47' + Info: 27: + IC(0.000 ns) + CELL(0.080 ns) = 11.484 ns; Loc. = LCCOMB_X34_Y18_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~49' + Info: 28: + IC(0.000 ns) + CELL(0.080 ns) = 11.564 ns; Loc. = LCCOMB_X34_Y18_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~51' + Info: 29: + IC(0.000 ns) + CELL(0.080 ns) = 11.644 ns; Loc. = LCCOMB_X34_Y18_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~53' + Info: 30: + IC(0.000 ns) + CELL(0.080 ns) = 11.724 ns; Loc. = LCCOMB_X34_Y18_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|Add4~55' + Info: 31: + IC(0.000 ns) + CELL(0.458 ns) = 12.182 ns; Loc. = LCCOMB_X34_Y18_N24; Fanout = 4; COMB Node = 'Arkanoid:inst|Add4~56' + Info: 32: + IC(0.917 ns) + CELL(0.455 ns) = 13.554 ns; Loc. = LCCOMB_X34_Y17_N16; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan3~8' + Info: 33: + IC(1.760 ns) + CELL(0.178 ns) = 15.492 ns; Loc. = LCCOMB_X35_Y19_N18; Fanout = 1; COMB Node = 'Arkanoid:inst|LessThan3~9' + Info: 34: + IC(0.293 ns) + CELL(0.521 ns) = 16.306 ns; Loc. = LCCOMB_X35_Y19_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|LessThan3~10' + Info: 35: + IC(0.884 ns) + CELL(0.495 ns) = 17.685 ns; Loc. = LCCOMB_X34_Y15_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~9' + Info: 36: + IC(0.000 ns) + CELL(0.080 ns) = 17.765 ns; Loc. = LCCOMB_X34_Y15_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~11' + Info: 37: + IC(0.000 ns) + CELL(0.080 ns) = 17.845 ns; Loc. = LCCOMB_X34_Y15_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~13' + Info: 38: + IC(0.000 ns) + CELL(0.080 ns) = 17.925 ns; Loc. = LCCOMB_X34_Y15_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~15' + Info: 39: + IC(0.000 ns) + CELL(0.080 ns) = 18.005 ns; Loc. = LCCOMB_X34_Y15_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~17' + Info: 40: + IC(0.000 ns) + CELL(0.080 ns) = 18.085 ns; Loc. = LCCOMB_X34_Y15_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~19' + Info: 41: + IC(0.000 ns) + CELL(0.080 ns) = 18.165 ns; Loc. = LCCOMB_X34_Y15_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~24' + Info: 42: + IC(0.000 ns) + CELL(0.174 ns) = 18.339 ns; Loc. = LCCOMB_X34_Y15_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~27' + Info: 43: + IC(0.000 ns) + CELL(0.080 ns) = 18.419 ns; Loc. = LCCOMB_X34_Y15_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~30' + Info: 44: + IC(0.000 ns) + CELL(0.080 ns) = 18.499 ns; Loc. = LCCOMB_X34_Y15_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~33' + Info: 45: + IC(0.000 ns) + CELL(0.080 ns) = 18.579 ns; Loc. = LCCOMB_X34_Y15_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~36' + Info: 46: + IC(0.000 ns) + CELL(0.080 ns) = 18.659 ns; Loc. = LCCOMB_X34_Y15_N22; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~39' + Info: 47: + IC(0.000 ns) + CELL(0.080 ns) = 18.739 ns; Loc. = LCCOMB_X34_Y15_N24; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~42' + Info: 48: + IC(0.000 ns) + CELL(0.080 ns) = 18.819 ns; Loc. = LCCOMB_X34_Y15_N26; Fanout = 2; COMB Node = 'Arkanoid:inst|Add5~45' + Info: 49: + IC(0.000 ns) + CELL(0.458 ns) = 19.277 ns; Loc. = LCCOMB_X34_Y15_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|Add5~47' + Info: 50: + IC(1.717 ns) + CELL(0.545 ns) = 21.539 ns; Loc. = LCCOMB_X34_Y21_N0; Fanout = 4; COMB Node = 'Arkanoid:inst|Add5~49' + Info: 51: + IC(1.176 ns) + CELL(0.517 ns) = 23.232 ns; Loc. = LCCOMB_X29_Y20_N26; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~23' + Info: 52: + IC(0.000 ns) + CELL(0.080 ns) = 23.312 ns; Loc. = LCCOMB_X29_Y20_N28; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~25' + Info: 53: + IC(0.000 ns) + CELL(0.161 ns) = 23.473 ns; Loc. = LCCOMB_X29_Y20_N30; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~27' + Info: 54: + IC(0.000 ns) + CELL(0.080 ns) = 23.553 ns; Loc. = LCCOMB_X29_Y19_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~29' + Info: 55: + IC(0.000 ns) + CELL(0.080 ns) = 23.633 ns; Loc. = LCCOMB_X29_Y19_N2; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~31' + Info: 56: + IC(0.000 ns) + CELL(0.080 ns) = 23.713 ns; Loc. = LCCOMB_X29_Y19_N4; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~33' + Info: 57: + IC(0.000 ns) + CELL(0.080 ns) = 23.793 ns; Loc. = LCCOMB_X29_Y19_N6; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~35' + Info: 58: + IC(0.000 ns) + CELL(0.080 ns) = 23.873 ns; Loc. = LCCOMB_X29_Y19_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~37' + Info: 59: + IC(0.000 ns) + CELL(0.080 ns) = 23.953 ns; Loc. = LCCOMB_X29_Y19_N10; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~39' + Info: 60: + IC(0.000 ns) + CELL(0.080 ns) = 24.033 ns; Loc. = LCCOMB_X29_Y19_N12; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~41' + Info: 61: + IC(0.000 ns) + CELL(0.174 ns) = 24.207 ns; Loc. = LCCOMB_X29_Y19_N14; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~43' + Info: 62: + IC(0.000 ns) + CELL(0.080 ns) = 24.287 ns; Loc. = LCCOMB_X29_Y19_N16; Fanout = 2; COMB Node = 'Arkanoid:inst|Add6~45' + Info: 63: + IC(0.000 ns) + CELL(0.458 ns) = 24.745 ns; Loc. = LCCOMB_X29_Y19_N18; Fanout = 1; COMB Node = 'Arkanoid:inst|Add6~46' + Info: 64: + IC(1.551 ns) + CELL(0.455 ns) = 26.751 ns; Loc. = LCCOMB_X30_Y19_N20; Fanout = 2; COMB Node = 'Arkanoid:inst|LessThan29~6' + Info: 65: + IC(0.300 ns) + CELL(0.322 ns) = 27.373 ns; Loc. = LCCOMB_X30_Y19_N22; Fanout = 15; COMB Node = 'Arkanoid:inst|LessThan29~8' + Info: 66: + IC(1.593 ns) + CELL(0.178 ns) = 29.144 ns; Loc. = LCCOMB_X32_Y15_N16; Fanout = 16; COMB Node = 'Arkanoid:inst|LessThan29~10' + Info: 67: + IC(0.994 ns) + CELL(0.545 ns) = 30.683 ns; Loc. = LCCOMB_X32_Y17_N22; Fanout = 1; COMB Node = 'Arkanoid:inst|always3~38' + Info: 68: + IC(0.297 ns) + CELL(0.521 ns) = 31.501 ns; Loc. = LCCOMB_X32_Y17_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|always3~39' + Info: 69: + IC(0.787 ns) + CELL(0.485 ns) = 32.773 ns; Loc. = LCCOMB_X32_Y17_N14; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux2~15' + Info: 70: + IC(0.889 ns) + CELL(0.322 ns) = 33.984 ns; Loc. = LCCOMB_X31_Y18_N2; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux2~16' + Info: 71: + IC(0.297 ns) + CELL(0.178 ns) = 34.459 ns; Loc. = LCCOMB_X31_Y18_N28; Fanout = 1; COMB Node = 'Arkanoid:inst|Mux2~19' + Info: 72: + IC(0.798 ns) + CELL(0.322 ns) = 35.579 ns; Loc. = LCCOMB_X27_Y18_N20; Fanout = 4; COMB Node = 'Arkanoid:inst|Mux3~1' + Info: 73: + IC(0.354 ns) + CELL(0.513 ns) = 36.446 ns; Loc. = LCCOMB_X27_Y18_N8; Fanout = 2; COMB Node = 'Arkanoid:inst|blue_~1' + Info: 74: + IC(0.522 ns) + CELL(0.413 ns) = 37.381 ns; Loc. = LCFF_X26_Y18_N11; Fanout = 1; REG Node = 'Arkanoid:inst|blue_[0]' + Info: Total cell delay = 14.837 ns ( 39.69 % ) + Info: Total interconnect delay = 22.544 ns ( 60.31 % ) + Info: + Micro setup delay of destination is -0.038 ns + Info: - Shortest clock path from clock "clk_50MHz" to destination register is 4.594 ns + Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz' + Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'Arkanoid:inst|clk25MHz_' + Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G2; Fanout = 150; COMB Node = 'Arkanoid:inst|clk25MHz_~clkctrl' + Info: 4: + IC(0.980 ns) + CELL(0.602 ns) = 4.594 ns; Loc. = LCFF_X26_Y18_N11; Fanout = 1; REG Node = 'Arkanoid:inst|blue_[0]' + Info: Total cell delay = 2.507 ns ( 54.57 % ) + Info: Total interconnect delay = 2.087 ns ( 45.43 % ) +Info: tco from clock "clk_50MHz" to destination pin "v_sync" through register "Arkanoid:inst|v_counter[8]" is 15.668 ns + Info: + Longest clock path from clock "clk_50MHz" to source register is 4.602 ns + Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz' + Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'Arkanoid:inst|clk25MHz_' + Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G2; Fanout = 150; COMB Node = 'Arkanoid:inst|clk25MHz_~clkctrl' + Info: 4: + IC(0.988 ns) + CELL(0.602 ns) = 4.602 ns; Loc. = LCFF_X15_Y13_N17; Fanout = 5; REG Node = 'Arkanoid:inst|v_counter[8]' + Info: Total cell delay = 2.507 ns ( 54.48 % ) + Info: Total interconnect delay = 2.095 ns ( 45.52 % ) + Info: + Micro clock to output delay of source is 0.277 ns + Info: + Longest register to pin delay is 10.789 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y13_N17; Fanout = 5; REG Node = 'Arkanoid:inst|v_counter[8]' + Info: 2: + IC(0.606 ns) + CELL(0.451 ns) = 1.057 ns; Loc. = LCCOMB_X15_Y13_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|LessThan132~0' + Info: 3: + IC(1.837 ns) + CELL(0.322 ns) = 3.216 ns; Loc. = LCCOMB_X15_Y14_N0; Fanout = 2; COMB Node = 'Arkanoid:inst|Equal1~7' + Info: 4: + IC(0.311 ns) + CELL(0.178 ns) = 3.705 ns; Loc. = LCCOMB_X15_Y14_N18; Fanout = 2; COMB Node = 'Arkanoid:inst|Equal2~0' + Info: 5: + IC(1.225 ns) + CELL(0.507 ns) = 5.437 ns; Loc. = LCCOMB_X18_Y11_N24; Fanout = 1; COMB Node = 'Arkanoid:inst|Equal2~1' + Info: 6: + IC(2.376 ns) + CELL(2.976 ns) = 10.789 ns; Loc. = PIN_B11; Fanout = 0; PIN Node = 'v_sync' + Info: Total cell delay = 4.434 ns ( 41.10 % ) + Info: Total interconnect delay = 6.355 ns ( 58.90 % ) +Info: th for register "Arkanoid:inst|platform1_position[29]" (data pin = "button2", clock pin = "clk_50MHz") is -2.062 ns + Info: + Longest clock path from clock "clk_50MHz" to destination register is 4.609 ns + Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_50MHz' + Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N29; Fanout = 2; REG Node = 'Arkanoid:inst|clk25MHz_' + Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G2; Fanout = 150; COMB Node = 'Arkanoid:inst|clk25MHz_~clkctrl' + Info: 4: + IC(0.995 ns) + CELL(0.602 ns) = 4.609 ns; Loc. = LCFF_X31_Y12_N9; Fanout = 3; REG Node = 'Arkanoid:inst|platform1_position[29]' + Info: Total cell delay = 2.507 ns ( 54.39 % ) + Info: Total interconnect delay = 2.102 ns ( 45.61 % ) + Info: + Micro hold delay of destination is 0.286 ns + Info: - Shortest pin to register delay is 6.957 ns + Info: 1: + IC(0.000 ns) + CELL(0.874 ns) = 0.874 ns; Loc. = PIN_T22; Fanout = 36; PIN Node = 'button2' + Info: 2: + IC(5.809 ns) + CELL(0.178 ns) = 6.861 ns; Loc. = LCCOMB_X31_Y12_N8; Fanout = 4; COMB Node = 'Arkanoid:inst|Add3~71' + Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 6.957 ns; Loc. = LCFF_X31_Y12_N9; Fanout = 3; REG Node = 'Arkanoid:inst|platform1_position[29]' + Info: Total cell delay = 1.148 ns ( 16.50 % ) + Info: Total interconnect delay = 5.809 ns ( 83.50 % ) +Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings + Info: Peak virtual memory: 166 megabytes + Info: Processing ended: Mon May 21 19:54:43 2012 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:06 + + diff --git a/myArkanoid.tan.summary b/myArkanoid.tan.summary new file mode 100644 index 0000000..8b46cf6 --- /dev/null +++ b/myArkanoid.tan.summary @@ -0,0 +1,56 @@ +-------------------------------------------------------------------------------------- +Timing Analyzer Summary +-------------------------------------------------------------------------------------- + +Type : Worst-case tsu +Slack : N/A +Required Time : None +Actual Time : 32.749 ns +From : button3 +To : Arkanoid:inst|blue_[0] +From Clock : -- +To Clock : clk_50MHz +Failed Paths : 0 + +Type : Worst-case tco +Slack : N/A +Required Time : None +Actual Time : 15.668 ns +From : Arkanoid:inst|v_counter[8] +To : v_sync +From Clock : clk_50MHz +To Clock : -- +Failed Paths : 0 + +Type : Worst-case th +Slack : N/A +Required Time : None +Actual Time : -2.062 ns +From : button2 +To : Arkanoid:inst|platform1_position[29] +From Clock : -- +To Clock : clk_50MHz +Failed Paths : 0 + +Type : Clock Setup: 'clk_50MHz' +Slack : N/A +Required Time : None +Actual Time : 9.70 MHz ( period = 103.135 ns ) +From : Arkanoid:inst|h_counter[1] +To : Arkanoid:inst|blue_[0] +From Clock : clk_50MHz +To Clock : clk_50MHz +Failed Paths : 0 + +Type : Total number of failed paths +Slack : +Required Time : +Actual Time : +From : +To : +From Clock : +To Clock : +Failed Paths : 0 + +-------------------------------------------------------------------------------------- + diff --git a/myArkanoid_assignment_defaults.qdf b/myArkanoid_assignment_defaults.qdf new file mode 100644 index 0000000..7efba58 --- /dev/null +++ b/myArkanoid_assignment_defaults.qdf @@ -0,0 +1,677 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.1 Build 222 10/21/2009 SJ Full Version +# Date created = 14:46:31 May 07, 2012 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus II software and is used +# to preserve global assignments across Quartus II versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name SMART_RECOMPILE Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name IGNORE_CLOCK_SETTINGS Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS Off +set_global_assignment -name ENABLE_CLOCK_LATENCY Off +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000B +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy II" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix IV" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy Stratix" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000AE +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Cyclone +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II GX" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "MAX II" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria II GX" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix GX" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy III" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000S +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Cyclone II" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone IV GX" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy IV" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III LS" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix III" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria GX" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX3000A +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Stratix +set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 10 +set_global_assignment -name NUMBER_OF_DESTINATION_TO_REPORT 10 +set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 200 +set_global_assignment -name DO_MIN_ANALYSIS Off +set_global_assignment -name DO_MIN_TIMING Off +set_global_assignment -name REPORT_IO_PATHS_SEPARATELY Off +set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK Off +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "HardCopy Stratix" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000B +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy Stratix" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000AE +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family Cyclone +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000S +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy III" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy IV" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX3000A +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family Stratix +set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy Stratix" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name DISABLE_OCP_HW_EVAL Off +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Stratix II" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS On +set_global_assignment -name PARALLEL_SYNTHESIS -value OFF +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Cyclone III LS" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Cyclone III" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Stratix III" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "HardCopy III" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Arria GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Cyclone II" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "HardCopy II" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Arria II GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "HardCopy IV" +set_global_assignment -name SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy III" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy Stratix" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone II" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Cyclone +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy II" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix II" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Stratix +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy IV" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Cyclone II" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family Cyclone +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II GX" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "HardCopy II" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Arria GX" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "As input tri-stated" -family "Cyclone IV GX" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy Stratix" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "Force All Tiles with Failing Timing Paths to High Speed" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III LS" +set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III" +set_global_assignment -name OPTIMIZE_SSN Off -family "Stratix III" +set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy III" +set_global_assignment -name OPTIMIZE_SSN Off -family "Stratix IV" +set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy IV" +set_global_assignment -name OPTIMIZE_SSN Off -family "Arria II GX" +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING On +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto +set_global_assignment -name AUTO_PACKED_REGISTERS Off +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO +set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name STOP_AFTER_CONGESTION_MAP Off +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION -value ON +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy Stratix" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT Off +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name INCREMENTAL_COMPILATION FULL_INCREMENTAL_COMPILATION +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE POST_FIT +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name DUTY_CYCLE 50 -section_id ? +set_global_assignment -name INVERT_BASE_CLOCK Off -section_id ? +set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id ? +set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id ? +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? diff --git a/myArkanoid_description.txt b/myArkanoid_description.txt new file mode 100644 index 0000000..e69de29 diff --git a/undo_redo.txt b/undo_redo.txt new file mode 100644 index 0000000..9a67bfb --- /dev/null +++ b/undo_redo.txt @@ -0,0 +1,60 @@ +GED + + Undo Commands + 1. Move + 2. Move + 3. Move + 4. Move + 5. Move + 6. Move + 7. Move + 8. Move + 9. Move + 10. Move + 11. Move + 12. Move + 13. Move + 14. Resize + 15. Move + 16. Move + 17. Move + 18. Move + 19. Move + 20. Move + 21. Move + 22. Move + 23. Move + 24. Move + 25. Move + 26. Move + 27. Move + 28. Move + 29. Move + 30. Move + 31. Move + 32. Move + 33. Move + 34. Move + 35. Delete Insert + 36. Move + 37. Move + 38. Move + 39. Move + 40. Move + 41. Move + 42. Move + 43. Move + 44. Move + 45. Move + 46. Delete Insert + 47. Update Symbol or Block + 48. Update Symbol or Block + 49. Insert Node + 50. Move + 51. Delete + 52. Delete + 53. Delete + 54. Move + 55. Delete + +