{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 28 14:18:56 2012 " "Info: Processing started: Mon May 28 14:18:56 2012" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "debouncer.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file debouncer.v" { { "Info" "ISGN_ENTITY_NAME" "1 Debouncer " "Info: Found entity 1: Debouncer" {  } { { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "totalscheme.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file totalscheme.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 TotalScheme " "Info: Found entity 1: TotalScheme" {  } { { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "arkanoid.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file arkanoid.v" { { "Info" "ISGN_ENTITY_NAME" "1 Arkanoid " "Info: Found entity 1: Arkanoid" {  } { { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "arkanoid_header.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file arkanoid_header.v" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "int_to_digital.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file int_to_digital.v" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga_sync.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file vga_sync.v" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clockdivider.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clockdivider.v" { { "Info" "ISGN_ENTITY_NAME" "1 ClockDivider " "Info: Found entity 1: ClockDivider" {  } { { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "TotalScheme " "Info: Elaborating entity \"TotalScheme\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Arkanoid Arkanoid:inst " "Info: Elaborating entity \"Arkanoid\" for hierarchy \"Arkanoid:inst\"" {  } { { "TotalScheme.bdf" "inst" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { 128 464 616 352 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_CANT_ANALYZE_CASE_STATEMENT" "int_to_digital.v(21) " "Warning (10762): Verilog HDL Case Statement warning at int_to_digital.v(21): can't check case statement for completeness because the case expression has too many possible states" {  } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 21 0 0 } }  } 0 10762 "Verilog HDL Case Statement warning at %1!s!: can't check case statement for completeness because the case expression has too many possible states" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_2104_UNCONVERTED" "n1 IntToDigital int_to_digital.v(10) " "Warning (10776): Verilog HDL warning at int_to_digital.v(10): variable n1 in static task or function IntToDigital may have unintended latch behavior" {  } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 10 0 0 } }  } 0 10776 "Verilog HDL warning at %3!s!: variable %1!s! in static task or function %2!s! may have unintended latch behavior" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_2104_UNCONVERTED" "n0 IntToDigital int_to_digital.v(10) " "Warning (10776): Verilog HDL warning at int_to_digital.v(10): variable n0 in static task or function IntToDigital may have unintended latch behavior" {  } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 10 0 0 } }  } 0 10776 "Verilog HDL warning at %3!s!: variable %1!s! in static task or function %2!s! may have unintended latch behavior" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_2104_UNCONVERTED" "low IntToDigital int_to_digital.v(9) " "Warning (10776): Verilog HDL warning at int_to_digital.v(9): variable low in static task or function IntToDigital may have unintended latch behavior" {  } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 9 0 0 } }  } 0 10776 "Verilog HDL warning at %3!s!: variable %1!s! in static task or function %2!s! may have unintended latch behavior" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "IntToDigital.low\[6..0\] 0 int_to_digital.v(9) " "Warning (10030): Net \"IntToDigital.low\[6..0\]\" at int_to_digital.v(9) has no driver or initial value, using a default initial value '0'" {  } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 9 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "" 0 -1}
{ "Info" "IVRFX_MULTI_DIMENSION_OBJECT_INFO" "field " "Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"field\" into its bus" {  } {  } 0 10008 "Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"%1!s!\" into its bus" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ClockDivider ClockDivider:inst1 " "Info: Elaborating entity \"ClockDivider\" for hierarchy \"ClockDivider:inst1\"" {  } { { "TotalScheme.bdf" "inst1" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -192 160 312 -128 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Debouncer Debouncer:inst2 " "Info: Elaborating entity \"Debouncer\" for hierarchy \"Debouncer:inst2\"" {  } { { "TotalScheme.bdf" "inst2" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -96 168 304 0 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "6 " "Info: Inferred 6 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div3 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div3\"" {  } { { "Arkanoid.v" "Div3" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 299 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div2 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div2\"" {  } { { "Arkanoid.v" "Div2" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 298 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Mod1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Mod1\"" {  } { { "int_to_digital.v" "Mod1" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div1\"" {  } { { "int_to_digital.v" "Div1" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Mod0 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Mod0\"" {  } { { "int_to_digital.v" "Mod0" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div0 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div0\"" {  } { { "int_to_digital.v" "Div0" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "Arkanoid:inst\|lpm_divide:Div3 " "Info: Elaborated megafunction instantiation \"Arkanoid:inst\|lpm_divide:Div3\"" {  } { { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 299 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "Arkanoid:inst\|lpm_divide:Div3 " "Info: Instantiated megafunction \"Arkanoid:inst\|lpm_divide:Div3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Info: Parameter \"LPM_WIDTHN\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 6 " "Info: Parameter \"LPM_WIDTHD\" = \"6\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION SIGNED " "Info: Parameter \"LPM_NREPRESENTATION\" = \"SIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION SIGNED " "Info: Parameter \"LPM_DREPRESENTATION\" = \"SIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT LPM_REMAINDERPOSITIVE=FALSE " "Info: Parameter \"LPM_HINT\" = \"LPM_REMAINDERPOSITIVE=FALSE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 299 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_8so.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_8so.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_8so " "Info: Found entity 1: lpm_divide_8so" {  } { { "db/lpm_divide_8so.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_divide_8so.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/abs_divider_lbg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/abs_divider_lbg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 abs_divider_lbg " "Info: Found entity 1: abs_divider_lbg" {  } { { "db/abs_divider_lbg.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/abs_divider_lbg.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_m2f.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_m2f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_m2f " "Info: Found entity 1: alt_u_div_m2f" {  } { { "db/alt_u_div_m2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_m2f.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_lkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_lkc " "Info: Found entity 1: add_sub_lkc" {  } { { "db/add_sub_lkc.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/add_sub_lkc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_mkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_mkc " "Info: Found entity 1: add_sub_mkc" {  } { { "db/add_sub_mkc.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/add_sub_mkc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_hq9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_hq9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_hq9 " "Info: Found entity 1: lpm_abs_hq9" {  } { { "db/lpm_abs_hq9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_hq9.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_0s9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_0s9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_0s9 " "Info: Found entity 1: lpm_abs_0s9" {  } { { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "Arkanoid:inst\|lpm_divide:Mod1 " "Info: Elaborated megafunction instantiation \"Arkanoid:inst\|lpm_divide:Mod1\"" {  } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "Arkanoid:inst\|lpm_divide:Mod1 " "Info: Instantiated megafunction \"Arkanoid:inst\|lpm_divide:Mod1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Info: Parameter \"LPM_WIDTHN\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 5 " "Info: Parameter \"LPM_WIDTHD\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION SIGNED " "Info: Parameter \"LPM_NREPRESENTATION\" = \"SIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION SIGNED " "Info: Parameter \"LPM_DREPRESENTATION\" = \"SIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT LPM_REMAINDERPOSITIVE=FALSE " "Info: Parameter \"LPM_HINT\" = \"LPM_REMAINDERPOSITIVE=FALSE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_ako.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_ako.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_ako " "Info: Found entity 1: lpm_divide_ako" {  } { { "db/lpm_divide_ako.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_divide_ako.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/abs_divider_kbg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/abs_divider_kbg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 abs_divider_kbg " "Info: Found entity 1: abs_divider_kbg" {  } { { "db/abs_divider_kbg.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/abs_divider_kbg.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_k2f.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_k2f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_k2f " "Info: Found entity 1: alt_u_div_k2f" {  } { { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_gq9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_gq9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_gq9 " "Info: Found entity 1: lpm_abs_gq9" {  } { { "db/lpm_abs_gq9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_gq9.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "Arkanoid:inst\|lpm_divide:Div1 " "Info: Elaborated megafunction instantiation \"Arkanoid:inst\|lpm_divide:Div1\"" {  } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "Arkanoid:inst\|lpm_divide:Div1 " "Info: Instantiated megafunction \"Arkanoid:inst\|lpm_divide:Div1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Info: Parameter \"LPM_WIDTHN\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 5 " "Info: Parameter \"LPM_WIDTHD\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION SIGNED " "Info: Parameter \"LPM_NREPRESENTATION\" = \"SIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION SIGNED " "Info: Parameter \"LPM_DREPRESENTATION\" = \"SIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT LPM_REMAINDERPOSITIVE=FALSE " "Info: Parameter \"LPM_HINT\" = \"LPM_REMAINDERPOSITIVE=FALSE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_7so.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_7so.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_7so " "Info: Found entity 1: lpm_divide_7so" {  } { { "db/lpm_divide_7so.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_divide_7so.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 2 " "Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Arkanoid:inst\|ball_direction~6 " "Info: Register \"Arkanoid:inst\|ball_direction~6\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Arkanoid:inst\|ball_direction~7 " "Info: Register \"Arkanoid:inst\|ball_direction~7\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "8037 " "Info: Implemented 8037 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "50 " "Info: Implemented 50 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "7982 " "Info: Implemented 7982 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "227 " "Info: Peak virtual memory: 227 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 28 14:21:58 2012 " "Info: Processing ended: Mon May 28 14:21:58 2012" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:03:02 " "Info: Elapsed time: 00:03:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:03:06 " "Info: Total CPU time (on all processors): 00:03:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}