Analysis & Synthesis report for myArkanoid Mon May 21 19:54:20 2012 Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Parallel Compilation 5. Analysis & Synthesis Source Files Read 6. Analysis & Synthesis Resource Usage Summary 7. Analysis & Synthesis Resource Utilization by Entity 8. Registers Removed During Synthesis 9. General Register Statistics 10. Inverted Register Statistics 11. Multiplexer Restructuring Statistics (Restructuring Performed) 12. Parameter Settings for User Entity Instance: Arkanoid:inst 13. Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Div0 14. Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Div1 15. Analysis & Synthesis Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2009 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+------------------------------------------+ ; Analysis & Synthesis Status ; Successful - Mon May 21 19:54:20 2012 ; ; Quartus II Version ; 9.1 Build 222 10/21/2009 SJ Full Version ; ; Revision Name ; myArkanoid ; ; Top-level Entity Name ; TotalScheme ; ; Family ; Cyclone II ; ; Total logic elements ; 1,810 ; ; Total combinational functions ; 1,793 ; ; Dedicated logic registers ; 151 ; ; Total registers ; 151 ; ; Total pins ; 55 ; ; Total virtual pins ; 0 ; ; Total memory bits ; 0 ; ; Embedded Multiplier 9-bit elements ; 0 ; ; Total PLLs ; 0 ; +------------------------------------+------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Settings ; +----------------------------------------------------------------------------+--------------------+--------------------+ ; Option ; Setting ; Default Value ; +----------------------------------------------------------------------------+--------------------+--------------------+ ; Device ; EP2C20F484C7 ; ; ; Top-level entity name ; TotalScheme ; myArkanoid ; ; Family name ; Cyclone II ; Stratix II ; ; Use smart compilation ; Off ; Off ; ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; ; Enable compact report table ; Off ; Off ; ; Restructure Multiplexers ; Auto ; Auto ; ; Create Debugging Nodes for IP Cores ; Off ; Off ; ; Preserve fewer node names ; On ; On ; ; Disable OpenCore Plus hardware evaluation ; Off ; Off ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL_1993 ; VHDL_1993 ; ; State Machine Processing ; Auto ; Auto ; ; Safe State Machine ; Off ; Off ; ; Extract Verilog State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ; ; Ignore Verilog initial constructs ; Off ; Off ; ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; ; Parallel Synthesis ; Off ; Off ; ; DSP Block Balancing ; Auto ; Auto ; ; NOT Gate Push-Back ; On ; On ; ; Power-Up Don't Care ; On ; On ; ; Remove Redundant Logic Cells ; Off ; Off ; ; Remove Duplicate Registers ; On ; On ; ; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore GLOBAL Buffers ; Off ; Off ; ; Ignore ROW GLOBAL Buffers ; Off ; Off ; ; Ignore LCELL Buffers ; Off ; Off ; ; Ignore SOFT Buffers ; On ; On ; ; Limit AHDL Integers to 32 Bits ; Off ; Off ; ; Optimization Technique ; Balanced ; Balanced ; ; Carry Chain Length ; 70 ; 70 ; ; Auto Carry Chains ; On ; On ; ; Auto Open-Drain Pins ; On ; On ; ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; ; Auto ROM Replacement ; On ; On ; ; Auto RAM Replacement ; On ; On ; ; Auto Shift Register Replacement ; Auto ; Auto ; ; Auto Clock Enable Replacement ; On ; On ; ; Strict RAM Replacement ; Off ; Off ; ; Allow Synchronous Control Signals ; On ; On ; ; Force Use of Synchronous Clear Signals ; Off ; Off ; ; Auto RAM to Logic Cell Conversion ; Off ; Off ; ; Auto Resource Sharing ; Off ; Off ; ; Allow Any RAM Size For Recognition ; Off ; Off ; ; Allow Any ROM Size For Recognition ; Off ; Off ; ; Allow Any Shift Register Size For Recognition ; Off ; Off ; ; Use LogicLock Constraints during Resource Balancing ; On ; On ; ; Ignore translate_off and synthesis_off directives ; Off ; Off ; ; Timing-Driven Synthesis ; Off ; Off ; ; Show Parameter Settings Tables in Synthesis Report ; On ; On ; ; Ignore Maximum Fan-Out Assignments ; Off ; Off ; ; Synchronization Register Chain Length ; 2 ; 2 ; ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; ; HDL message level ; Level2 ; Level2 ; ; Suppress Register Optimization Related Messages ; Off ; Off ; ; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; ; Clock MUX Protection ; On ; On ; ; Auto Gated Clock Conversion ; Off ; Off ; ; Block Design Naming ; Auto ; Auto ; ; SDC constraint protection ; Off ; Off ; ; Synthesis Effort ; Auto ; Auto ; ; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; ; Analysis & Synthesis Message Level ; Medium ; Medium ; ; Disable Register Merging Across Hierarchies ; Auto ; Auto ; ; Resource Aware Inference For Block RAM ; On ; On ; +----------------------------------------------------------------------------+--------------------+--------------------+ +------------------------------------------+ ; Parallel Compilation ; +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ ; Number detected on machine ; 2 ; ; Maximum allowed ; 2 ; ; ; ; ; Average used ; 1.00 ; ; Maximum used ; 1 ; ; ; ; ; Usage by Processor ; % Time Used ; ; 1 processor ; 100.0% ; ; 2 processors ; 0.0% ; +----------------------------+-------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Source Files Read ; +----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------+ ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; +----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------+ ; TotalScheme.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/TotalScheme.bdf ; ; Arkanoid.v ; yes ; User Verilog HDL File ; C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/Arkanoid.v ; ; lpm_divide.tdf ; yes ; Megafunction ; c:/quartus/quartus/libraries/megafunctions/lpm_divide.tdf ; ; db/lpm_divide_8so.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/db/lpm_divide_8so.tdf ; ; db/abs_divider_lbg.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/db/abs_divider_lbg.tdf ; ; db/alt_u_div_m2f.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/db/alt_u_div_m2f.tdf ; ; db/add_sub_lkc.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/db/add_sub_lkc.tdf ; ; db/add_sub_mkc.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/db/add_sub_mkc.tdf ; ; db/lpm_abs_hq9.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/db/lpm_abs_hq9.tdf ; ; db/lpm_abs_0s9.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Политех/Altera DE1/Arkanoid/db/lpm_abs_0s9.tdf ; +----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------+ +-----------------------------------------------------------------------+ ; Analysis & Synthesis Resource Usage Summary ; +---------------------------------------------+-------------------------+ ; Resource ; Usage ; +---------------------------------------------+-------------------------+ ; Estimated Total logic elements ; 1,810 ; ; ; ; ; Total combinational functions ; 1793 ; ; Logic element usage by number of LUT inputs ; ; ; -- 4 input functions ; 561 ; ; -- 3 input functions ; 452 ; ; -- <=2 input functions ; 780 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 1147 ; ; -- arithmetic mode ; 646 ; ; ; ; ; Total registers ; 151 ; ; -- Dedicated logic registers ; 151 ; ; -- I/O registers ; 0 ; ; ; ; ; I/O pins ; 55 ; ; Maximum fan-out node ; Arkanoid:inst|clk25MHz_ ; ; Maximum fan-out ; 151 ; ; Total fan-out ; 5397 ; ; Average fan-out ; 2.70 ; +---------------------------------------------+-------------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Utilization by Entity ; +------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------+--------------+ ; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; +------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------+--------------+ ; |TotalScheme ; 1793 (0) ; 151 (0) ; 0 ; 0 ; 0 ; 0 ; 55 ; 0 ; |TotalScheme ; work ; ; |Arkanoid:inst| ; 1793 (765) ; 151 (151) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst ; ; ; |lpm_divide:Div0| ; 475 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0 ; ; ; |lpm_divide_8so:auto_generated| ; 475 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated ; ; ; |abs_divider_lbg:divider| ; 475 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider ; ; ; |alt_u_div_m2f:divider| ; 433 (433) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider ; ; ; |lpm_abs_0s9:my_abs_num| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num ; ; ; |lpm_divide:Div1| ; 553 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1 ; ; ; |lpm_divide_8so:auto_generated| ; 553 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated ; ; ; |abs_divider_lbg:divider| ; 553 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider ; ; ; |alt_u_div_m2f:divider| ; 511 (511) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider ; ; ; |lpm_abs_0s9:my_abs_num| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num ; ; +------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. +--------------------------------------------------------------------------------+ ; Registers Removed During Synthesis ; +---------------------------------------+----------------------------------------+ ; Register name ; Reason for Removal ; +---------------------------------------+----------------------------------------+ ; Arkanoid:inst|green_[0..1] ; Stuck at GND due to stuck port data_in ; ; Total Number of Removed Registers = 2 ; ; +---------------------------------------+----------------------------------------+ +------------------------------------------------------+ ; General Register Statistics ; +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ ; Total registers ; 151 ; ; Number of registers using Synchronous Clear ; 32 ; ; Number of registers using Synchronous Load ; 0 ; ; Number of registers using Asynchronous Clear ; 0 ; ; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Clock Enable ; 12 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ +--------------------------------------------------+ ; Inverted Register Statistics ; +----------------------------------------+---------+ ; Inverted Register ; Fan out ; +----------------------------------------+---------+ ; Arkanoid:inst|platform2_position[3] ; 2 ; ; Arkanoid:inst|platform2_position[2] ; 2 ; ; Arkanoid:inst|platform1_position[2] ; 2 ; ; Arkanoid:inst|platform1_position[3] ; 2 ; ; Total number of inverted registers = 4 ; ; +----------------------------------------+---------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Multiplexer Restructuring Statistics (Restructuring Performed) ; +--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+ ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+ ; 3:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; No ; |TotalScheme|Arkanoid:inst|platform1_position ; ; 3:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; No ; |TotalScheme|Arkanoid:inst|platform2_position ; ; 4:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; No ; |TotalScheme|Arkanoid:inst|platform1_position ; ; 4:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; No ; |TotalScheme|Arkanoid:inst|platform2_position ; +--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+ +------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: Arkanoid:inst ; +------------------+-------+---------------------------------+ ; Parameter Name ; Value ; Type ; +------------------+-------+---------------------------------+ ; SCREEN_WIDTH ; 640 ; Signed Integer ; ; SCREEN_HEIGHT ; 480 ; Signed Integer ; ; CELL_SIZE ; 20 ; Signed Integer ; ; BALL_SIZE ; 1 ; Signed Integer ; ; BALL_SPEED ; 2 ; Signed Integer ; ; PLATFORM_WIDTH ; 8 ; Signed Integer ; ; PLATFORM_SPEED ; 1 ; Signed Integer ; ; BK_COLOR_R ; 0000 ; Unsigned Binary ; ; BK_COLOR_G ; 0000 ; Unsigned Binary ; ; BK_COLOR_B ; 0000 ; Unsigned Binary ; ; STABLE_COLOR_R ; 0011 ; Unsigned Binary ; ; STABLE_COLOR_G ; 1100 ; Unsigned Binary ; ; STABLE_COLOR_B ; 0110 ; Unsigned Binary ; ; BALL_COLOR_R ; 0000 ; Unsigned Binary ; ; BALL_COLOR_G ; 0000 ; Unsigned Binary ; ; BALL_COLOR_B ; 1111 ; Unsigned Binary ; ; PLATFORM_COLOR_R ; 1111 ; Unsigned Binary ; ; PLATFORM_COLOR_G ; 0000 ; Unsigned Binary ; ; PLATFORM_COLOR_B ; 0000 ; Unsigned Binary ; +------------------+-------+---------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Div0 ; +------------------------+----------------+--------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------+----------------+--------------------------------------+ ; LPM_WIDTHN ; 32 ; Untyped ; ; LPM_WIDTHD ; 6 ; Untyped ; ; LPM_NREPRESENTATION ; SIGNED ; Untyped ; ; LPM_DREPRESENTATION ; SIGNED ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; LPM_REMAINDERPOSITIVE ; FALSE ; Untyped ; ; MAXIMIZE_SPEED ; 5 ; Untyped ; ; CBXI_PARAMETER ; lpm_divide_8so ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +------------------------+----------------+--------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Div1 ; +------------------------+----------------+--------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------+----------------+--------------------------------------+ ; LPM_WIDTHN ; 32 ; Untyped ; ; LPM_WIDTHD ; 6 ; Untyped ; ; LPM_NREPRESENTATION ; SIGNED ; Untyped ; ; LPM_DREPRESENTATION ; SIGNED ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; LPM_REMAINDERPOSITIVE ; FALSE ; Untyped ; ; MAXIMIZE_SPEED ; 5 ; Untyped ; ; CBXI_PARAMETER ; lpm_divide_8so ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +------------------------+----------------+--------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus II Analysis & Synthesis Info: Version 9.1 Build 222 10/21/2009 SJ Full Version Info: Processing started: Mon May 21 19:54:04 2012 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid Info: Parallel compilation is enabled and will use 2 of the 2 processors detected Info: Found 1 design units, including 1 entities, in source file totalscheme.bdf Info: Found entity 1: TotalScheme Info: Found 1 design units, including 1 entities, in source file arkanoid.v Info: Found entity 1: Arkanoid Info: Elaborating entity "TotalScheme" for the top level hierarchy Info: Elaborating entity "Arkanoid" for hierarchy "Arkanoid:inst" Warning (10036): Verilog HDL or VHDL warning at Arkanoid.v(82): object "ball_state" assigned a value but never read Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "field" into its bus Info: Inferred 2 megafunctions from design logic Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Arkanoid:inst|Div0" Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Arkanoid:inst|Div1" Info: Elaborated megafunction instantiation "Arkanoid:inst|lpm_divide:Div0" Info: Instantiated megafunction "Arkanoid:inst|lpm_divide:Div0" with the following parameter: Info: Parameter "LPM_WIDTHN" = "32" Info: Parameter "LPM_WIDTHD" = "6" Info: Parameter "LPM_NREPRESENTATION" = "SIGNED" Info: Parameter "LPM_DREPRESENTATION" = "SIGNED" Info: Parameter "LPM_HINT" = "LPM_REMAINDERPOSITIVE=FALSE" Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_8so.tdf Info: Found entity 1: lpm_divide_8so Info: Found 1 design units, including 1 entities, in source file db/abs_divider_lbg.tdf Info: Found entity 1: abs_divider_lbg Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_m2f.tdf Info: Found entity 1: alt_u_div_m2f Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf Info: Found entity 1: add_sub_lkc Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf Info: Found entity 1: add_sub_mkc Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_hq9.tdf Info: Found entity 1: lpm_abs_hq9 Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_0s9.tdf Info: Found entity 1: lpm_abs_0s9 Warning: Output pins are stuck at VCC or GND Warning (13410): Pin "green[1]" is stuck at GND Warning (13410): Pin "green[0]" is stuck at GND Warning (13410): Pin "led1[6]" is stuck at GND Warning (13410): Pin "led1[5]" is stuck at GND Warning (13410): Pin "led1[4]" is stuck at GND Warning (13410): Pin "led1[3]" is stuck at GND Warning (13410): Pin "led1[2]" is stuck at GND Warning (13410): Pin "led1[1]" is stuck at GND Warning (13410): Pin "led1[0]" is stuck at GND Warning (13410): Pin "led2[6]" is stuck at GND Warning (13410): Pin "led2[5]" is stuck at GND Warning (13410): Pin "led2[4]" is stuck at GND Warning (13410): Pin "led2[3]" is stuck at GND Warning (13410): Pin "led2[2]" is stuck at GND Warning (13410): Pin "led2[1]" is stuck at GND Warning (13410): Pin "led2[0]" is stuck at GND Warning (13410): Pin "led3[6]" is stuck at GND Warning (13410): Pin "led3[5]" is stuck at GND Warning (13410): Pin "led3[4]" is stuck at GND Warning (13410): Pin "led3[3]" is stuck at GND Warning (13410): Pin "led3[2]" is stuck at GND Warning (13410): Pin "led3[1]" is stuck at GND Warning (13410): Pin "led3[0]" is stuck at GND Warning (13410): Pin "led4[6]" is stuck at GND Warning (13410): Pin "led4[5]" is stuck at GND Warning (13410): Pin "led4[4]" is stuck at GND Warning (13410): Pin "led4[3]" is stuck at GND Warning (13410): Pin "led4[2]" is stuck at GND Warning (13410): Pin "led4[1]" is stuck at GND Warning (13410): Pin "led4[0]" is stuck at GND Info: Implemented 1932 device resources after synthesis - the final resource count might be different Info: Implemented 5 input pins Info: Implemented 50 output pins Info: Implemented 1877 logic cells Info: Quartus II Analysis & Synthesis was successful. 0 errors, 32 warnings Info: Peak virtual memory: 204 megabytes Info: Processing ended: Mon May 21 19:54:20 2012 Info: Elapsed time: 00:00:16 Info: Total CPU time (on all processors): 00:00:17