121 lines
No EOL
5.9 KiB
Text
121 lines
No EOL
5.9 KiB
Text
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2009 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II
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# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
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# Date created = 14:07:51 October 21, 2009
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# myArkanoid_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone II"
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set_global_assignment -name DEVICE EP2C20F484C7
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set_global_assignment -name TOP_LEVEL_ENTITY myArkanoidSchematic
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:07:51 OCTOBER 21, 2009"
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set_global_assignment -name LAST_QUARTUS_VERSION 9.1
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
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set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name BDF_FILE myArkanoidSchematic.bdf
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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set_location_assignment PIN_L1 -to clk_50MHz
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set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE AREA
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set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
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set_global_assignment -name MUX_RESTRUCTURE ON
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set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION ALWAYS
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set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
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set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
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set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
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set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
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set_global_assignment -name IGNORE_LCELL_BUFFERS ON
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set_global_assignment -name IGNORE_CASCADE_BUFFERS ON
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set_global_assignment -name USE_CONFIGURATION_DEVICE ON
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set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
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set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
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set_location_assignment PIN_J2 -to led1[0]
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set_location_assignment PIN_J1 -to led1[1]
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set_location_assignment PIN_H2 -to led1[2]
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set_location_assignment PIN_H1 -to led1[3]
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set_location_assignment PIN_F2 -to led1[4]
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set_location_assignment PIN_F1 -to led1[5]
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set_location_assignment PIN_E2 -to led1[6]
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set_location_assignment PIN_E1 -to led2[0]
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set_location_assignment PIN_H6 -to led2[1]
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set_location_assignment PIN_H5 -to led2[2]
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set_location_assignment PIN_H4 -to led2[3]
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set_location_assignment PIN_G3 -to led2[4]
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set_location_assignment PIN_D2 -to led2[5]
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set_location_assignment PIN_D1 -to led2[6]
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set_location_assignment PIN_G5 -to led3[0]
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set_location_assignment PIN_G6 -to led3[1]
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set_location_assignment PIN_C2 -to led3[2]
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set_location_assignment PIN_C1 -to led3[3]
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set_location_assignment PIN_E3 -to led3[4]
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set_location_assignment PIN_E4 -to led3[5]
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set_location_assignment PIN_D3 -to led3[6]
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set_location_assignment PIN_F4 -to led4[0]
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set_location_assignment PIN_D5 -to led4[1]
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set_location_assignment PIN_D6 -to led4[2]
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set_location_assignment PIN_J4 -to led4[3]
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set_location_assignment PIN_L8 -to led4[4]
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set_location_assignment PIN_F3 -to led4[5]
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set_location_assignment PIN_D4 -to led4[6]
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set_global_assignment -name VHDL_FILE FrequencyDivider.vhd
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set_global_assignment -name VERILOG_FILE Arkanoid.v
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set_global_assignment -name MISC_FILE "C:/Users/ProGOLD/Desktop/<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>/Altera DE1/myArkanoid/myArkanoid.dpf"
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set_location_assignment PIN_D9 -to red[0]
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set_location_assignment PIN_C9 -to red[1]
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set_location_assignment PIN_A7 -to red[2]
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set_location_assignment PIN_B7 -to red[3]
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set_location_assignment PIN_B8 -to green[0]
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set_location_assignment PIN_C10 -to green[1]
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set_location_assignment PIN_B9 -to green[2]
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set_location_assignment PIN_A8 -to green[3]
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set_location_assignment PIN_A9 -to blue[0]
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set_location_assignment PIN_D11 -to blue[1]
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set_location_assignment PIN_A10 -to blue[2]
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set_location_assignment PIN_B10 -to blue[3]
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_location_assignment PIN_R22 -to button1
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set_location_assignment PIN_R21 -to button2
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set_location_assignment PIN_T22 -to button3
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set_location_assignment PIN_T21 -to button4
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set_location_assignment PIN_A11 -to h_sync
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set_location_assignment PIN_B11 -to v_sync |