289 lines
18 KiB
Text
289 lines
18 KiB
Text
Simulator report for myArkanoid
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Mon May 21 14:05:52 2012
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Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Simulator Summary
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3. Simulator Settings
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4. Simulation Waveforms
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5. Coverage Summary
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6. Complete 1/0-Value Coverage
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7. Missing 1-Value Coverage
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8. Missing 0-Value Coverage
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9. Simulator INI Usage
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10. Simulator Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2009 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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+--------------------------------------------+
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; Simulator Summary ;
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+-----------------------------+--------------+
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; Type ; Value ;
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+-----------------------------+--------------+
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; Simulation Start Time ; 0 ps ;
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; Simulation End Time ; 50.0 ms ;
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; Simulation Netlist Size ; 67 nodes ;
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; Simulation Coverage ; 0.00 % ;
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; Total Number of Transitions ; 0 ;
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; Simulation Breakpoints ; 0 ;
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; Family ; Cyclone II ;
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; Device ; EP2C20F484C7 ;
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+-----------------------------+--------------+
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+-----------------------------------------------------------------------------------------------------------------------------+
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; Simulator Settings ;
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+--------------------------------------------------------------------------------------------+----------------+---------------+
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; Option ; Setting ; Default Value ;
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+--------------------------------------------------------------------------------------------+----------------+---------------+
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; Simulation mode ; Timing ; Timing ;
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; Start time ; 0 ns ; 0 ns ;
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; Simulation results format ; CVWF ; ;
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; Vector input source ; myArkanoid.vwf ; ;
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; Add pins automatically to simulation output waveforms ; On ; On ;
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; Check outputs ; Off ; Off ;
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; Report simulation coverage ; On ; On ;
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; Display complete 1/0 value coverage report ; On ; On ;
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; Display missing 1-value coverage report ; On ; On ;
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; Display missing 0-value coverage report ; On ; On ;
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; Detect setup and hold time violations ; Off ; Off ;
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; Detect glitches ; Off ; Off ;
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; Disable timing delays in Timing Simulation ; Off ; Off ;
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; Generate Signal Activity File ; Off ; Off ;
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; Generate VCD File for PowerPlay Power Analyzer ; Off ; Off ;
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; Group bus channels in simulation results ; Off ; Off ;
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; Preserve fewer signal transitions to reduce memory requirements ; On ; On ;
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; Trigger vector comparison with the specified mode ; INPUT_EDGE ; INPUT_EDGE ;
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; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off ; Off ;
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; Overwrite Waveform Inputs With Simulation Outputs ; Off ; ;
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; Perform Glitch Filtering in Timing Simulation ; Auto ; Auto ;
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+--------------------------------------------------------------------------------------------+----------------+---------------+
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+----------------------+
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; Simulation Waveforms ;
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+----------------------+
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Waveform report data cannot be output to ASCII.
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Please use Quartus II to view the waveform report data.
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+--------------------------------------------------------------------+
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; Coverage Summary ;
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+-----------------------------------------------------+--------------+
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; Type ; Value ;
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+-----------------------------------------------------+--------------+
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; Total coverage as a percentage ; 0.00 % ;
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; Total nodes checked ; 67 ;
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; Total output ports checked ; 62 ;
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; Total output ports with complete 1/0-value coverage ; 0 ;
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; Total output ports with no 1/0-value coverage ; 62 ;
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; Total output ports with no 1-value coverage ; 62 ;
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; Total output ports with no 0-value coverage ; 62 ;
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+-----------------------------------------------------+--------------+
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The following table displays output ports that toggle between 1 and 0 during simulation.
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+-------------------------------------------------+
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; Complete 1/0-Value Coverage ;
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+-----------+------------------+------------------+
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; Node Name ; Output Port Name ; Output Port Type ;
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+-----------+------------------+------------------+
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The following table displays output ports that do not toggle to 1 during simulation.
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+------------------------------------------------------------------+
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; Missing 1-Value Coverage ;
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+-----------------------+-----------------------+------------------+
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; Node Name ; Output Port Name ; Output Port Type ;
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+-----------------------+-----------------------+------------------+
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; |TotalScheme|h_sync ; |TotalScheme|h_sync ; padio ;
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; |TotalScheme|v_sync ; |TotalScheme|v_sync ; padio ;
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; |TotalScheme|blue[3] ; |TotalScheme|blue[3] ; padio ;
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; |TotalScheme|blue[2] ; |TotalScheme|blue[2] ; padio ;
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; |TotalScheme|blue[1] ; |TotalScheme|blue[1] ; padio ;
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; |TotalScheme|blue[0] ; |TotalScheme|blue[0] ; padio ;
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; |TotalScheme|green[3] ; |TotalScheme|green[3] ; padio ;
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; |TotalScheme|green[2] ; |TotalScheme|green[2] ; padio ;
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; |TotalScheme|green[1] ; |TotalScheme|green[1] ; padio ;
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; |TotalScheme|green[0] ; |TotalScheme|green[0] ; padio ;
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; |TotalScheme|hort[9] ; |TotalScheme|hort[9] ; padio ;
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; |TotalScheme|hort[8] ; |TotalScheme|hort[8] ; padio ;
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; |TotalScheme|hort[7] ; |TotalScheme|hort[7] ; padio ;
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; |TotalScheme|hort[6] ; |TotalScheme|hort[6] ; padio ;
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; |TotalScheme|hort[5] ; |TotalScheme|hort[5] ; padio ;
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; |TotalScheme|hort[4] ; |TotalScheme|hort[4] ; padio ;
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; |TotalScheme|hort[3] ; |TotalScheme|hort[3] ; padio ;
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; |TotalScheme|hort[2] ; |TotalScheme|hort[2] ; padio ;
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; |TotalScheme|hort[1] ; |TotalScheme|hort[1] ; padio ;
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; |TotalScheme|hort[0] ; |TotalScheme|hort[0] ; padio ;
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; |TotalScheme|led1[6] ; |TotalScheme|led1[6] ; padio ;
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; |TotalScheme|led1[5] ; |TotalScheme|led1[5] ; padio ;
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; |TotalScheme|led1[4] ; |TotalScheme|led1[4] ; padio ;
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; |TotalScheme|led1[3] ; |TotalScheme|led1[3] ; padio ;
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; |TotalScheme|led1[2] ; |TotalScheme|led1[2] ; padio ;
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; |TotalScheme|led1[1] ; |TotalScheme|led1[1] ; padio ;
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; |TotalScheme|led1[0] ; |TotalScheme|led1[0] ; padio ;
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; |TotalScheme|led2[6] ; |TotalScheme|led2[6] ; padio ;
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; |TotalScheme|led2[5] ; |TotalScheme|led2[5] ; padio ;
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; |TotalScheme|led2[4] ; |TotalScheme|led2[4] ; padio ;
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; |TotalScheme|led2[3] ; |TotalScheme|led2[3] ; padio ;
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; |TotalScheme|led2[2] ; |TotalScheme|led2[2] ; padio ;
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; |TotalScheme|led2[1] ; |TotalScheme|led2[1] ; padio ;
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; |TotalScheme|led2[0] ; |TotalScheme|led2[0] ; padio ;
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; |TotalScheme|led3[6] ; |TotalScheme|led3[6] ; padio ;
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; |TotalScheme|led3[5] ; |TotalScheme|led3[5] ; padio ;
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; |TotalScheme|led3[4] ; |TotalScheme|led3[4] ; padio ;
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; |TotalScheme|led3[3] ; |TotalScheme|led3[3] ; padio ;
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; |TotalScheme|led3[2] ; |TotalScheme|led3[2] ; padio ;
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; |TotalScheme|led3[1] ; |TotalScheme|led3[1] ; padio ;
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; |TotalScheme|led3[0] ; |TotalScheme|led3[0] ; padio ;
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; |TotalScheme|led4[6] ; |TotalScheme|led4[6] ; padio ;
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; |TotalScheme|led4[5] ; |TotalScheme|led4[5] ; padio ;
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; |TotalScheme|led4[4] ; |TotalScheme|led4[4] ; padio ;
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; |TotalScheme|led4[3] ; |TotalScheme|led4[3] ; padio ;
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; |TotalScheme|led4[2] ; |TotalScheme|led4[2] ; padio ;
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; |TotalScheme|led4[1] ; |TotalScheme|led4[1] ; padio ;
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; |TotalScheme|led4[0] ; |TotalScheme|led4[0] ; padio ;
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; |TotalScheme|red[3] ; |TotalScheme|red[3] ; padio ;
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; |TotalScheme|red[2] ; |TotalScheme|red[2] ; padio ;
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; |TotalScheme|red[1] ; |TotalScheme|red[1] ; padio ;
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; |TotalScheme|red[0] ; |TotalScheme|red[0] ; padio ;
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; |TotalScheme|vert[9] ; |TotalScheme|vert[9] ; padio ;
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; |TotalScheme|vert[8] ; |TotalScheme|vert[8] ; padio ;
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; |TotalScheme|vert[7] ; |TotalScheme|vert[7] ; padio ;
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; |TotalScheme|vert[6] ; |TotalScheme|vert[6] ; padio ;
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; |TotalScheme|vert[5] ; |TotalScheme|vert[5] ; padio ;
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; |TotalScheme|vert[4] ; |TotalScheme|vert[4] ; padio ;
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; |TotalScheme|vert[3] ; |TotalScheme|vert[3] ; padio ;
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; |TotalScheme|vert[2] ; |TotalScheme|vert[2] ; padio ;
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; |TotalScheme|vert[1] ; |TotalScheme|vert[1] ; padio ;
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; |TotalScheme|vert[0] ; |TotalScheme|vert[0] ; padio ;
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+-----------------------+-----------------------+------------------+
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The following table displays output ports that do not toggle to 0 during simulation.
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+------------------------------------------------------------------+
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; Missing 0-Value Coverage ;
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+-----------------------+-----------------------+------------------+
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; Node Name ; Output Port Name ; Output Port Type ;
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+-----------------------+-----------------------+------------------+
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; |TotalScheme|h_sync ; |TotalScheme|h_sync ; padio ;
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; |TotalScheme|v_sync ; |TotalScheme|v_sync ; padio ;
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; |TotalScheme|blue[3] ; |TotalScheme|blue[3] ; padio ;
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; |TotalScheme|blue[2] ; |TotalScheme|blue[2] ; padio ;
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; |TotalScheme|blue[1] ; |TotalScheme|blue[1] ; padio ;
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; |TotalScheme|blue[0] ; |TotalScheme|blue[0] ; padio ;
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; |TotalScheme|green[3] ; |TotalScheme|green[3] ; padio ;
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; |TotalScheme|green[2] ; |TotalScheme|green[2] ; padio ;
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; |TotalScheme|green[1] ; |TotalScheme|green[1] ; padio ;
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; |TotalScheme|green[0] ; |TotalScheme|green[0] ; padio ;
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; |TotalScheme|hort[9] ; |TotalScheme|hort[9] ; padio ;
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; |TotalScheme|hort[8] ; |TotalScheme|hort[8] ; padio ;
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; |TotalScheme|hort[7] ; |TotalScheme|hort[7] ; padio ;
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; |TotalScheme|hort[6] ; |TotalScheme|hort[6] ; padio ;
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; |TotalScheme|hort[5] ; |TotalScheme|hort[5] ; padio ;
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; |TotalScheme|hort[4] ; |TotalScheme|hort[4] ; padio ;
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; |TotalScheme|hort[3] ; |TotalScheme|hort[3] ; padio ;
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; |TotalScheme|hort[2] ; |TotalScheme|hort[2] ; padio ;
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; |TotalScheme|hort[1] ; |TotalScheme|hort[1] ; padio ;
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; |TotalScheme|hort[0] ; |TotalScheme|hort[0] ; padio ;
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; |TotalScheme|led1[6] ; |TotalScheme|led1[6] ; padio ;
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; |TotalScheme|led1[5] ; |TotalScheme|led1[5] ; padio ;
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; |TotalScheme|led1[4] ; |TotalScheme|led1[4] ; padio ;
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; |TotalScheme|led1[3] ; |TotalScheme|led1[3] ; padio ;
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; |TotalScheme|led1[2] ; |TotalScheme|led1[2] ; padio ;
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; |TotalScheme|led1[1] ; |TotalScheme|led1[1] ; padio ;
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; |TotalScheme|led1[0] ; |TotalScheme|led1[0] ; padio ;
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; |TotalScheme|led2[6] ; |TotalScheme|led2[6] ; padio ;
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; |TotalScheme|led2[5] ; |TotalScheme|led2[5] ; padio ;
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; |TotalScheme|led2[4] ; |TotalScheme|led2[4] ; padio ;
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; |TotalScheme|led2[3] ; |TotalScheme|led2[3] ; padio ;
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; |TotalScheme|led2[2] ; |TotalScheme|led2[2] ; padio ;
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; |TotalScheme|led2[1] ; |TotalScheme|led2[1] ; padio ;
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; |TotalScheme|led2[0] ; |TotalScheme|led2[0] ; padio ;
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; |TotalScheme|led3[6] ; |TotalScheme|led3[6] ; padio ;
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; |TotalScheme|led3[5] ; |TotalScheme|led3[5] ; padio ;
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; |TotalScheme|led3[4] ; |TotalScheme|led3[4] ; padio ;
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; |TotalScheme|led3[3] ; |TotalScheme|led3[3] ; padio ;
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; |TotalScheme|led3[2] ; |TotalScheme|led3[2] ; padio ;
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; |TotalScheme|led3[1] ; |TotalScheme|led3[1] ; padio ;
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; |TotalScheme|led3[0] ; |TotalScheme|led3[0] ; padio ;
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; |TotalScheme|led4[6] ; |TotalScheme|led4[6] ; padio ;
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; |TotalScheme|led4[5] ; |TotalScheme|led4[5] ; padio ;
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; |TotalScheme|led4[4] ; |TotalScheme|led4[4] ; padio ;
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; |TotalScheme|led4[3] ; |TotalScheme|led4[3] ; padio ;
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; |TotalScheme|led4[2] ; |TotalScheme|led4[2] ; padio ;
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; |TotalScheme|led4[1] ; |TotalScheme|led4[1] ; padio ;
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; |TotalScheme|led4[0] ; |TotalScheme|led4[0] ; padio ;
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; |TotalScheme|red[3] ; |TotalScheme|red[3] ; padio ;
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; |TotalScheme|red[2] ; |TotalScheme|red[2] ; padio ;
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; |TotalScheme|red[1] ; |TotalScheme|red[1] ; padio ;
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; |TotalScheme|red[0] ; |TotalScheme|red[0] ; padio ;
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; |TotalScheme|vert[9] ; |TotalScheme|vert[9] ; padio ;
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; |TotalScheme|vert[8] ; |TotalScheme|vert[8] ; padio ;
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; |TotalScheme|vert[7] ; |TotalScheme|vert[7] ; padio ;
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; |TotalScheme|vert[6] ; |TotalScheme|vert[6] ; padio ;
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; |TotalScheme|vert[5] ; |TotalScheme|vert[5] ; padio ;
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; |TotalScheme|vert[4] ; |TotalScheme|vert[4] ; padio ;
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; |TotalScheme|vert[3] ; |TotalScheme|vert[3] ; padio ;
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; |TotalScheme|vert[2] ; |TotalScheme|vert[2] ; padio ;
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; |TotalScheme|vert[1] ; |TotalScheme|vert[1] ; padio ;
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; |TotalScheme|vert[0] ; |TotalScheme|vert[0] ; padio ;
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+-----------------------+-----------------------+------------------+
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+---------------------+
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; Simulator INI Usage ;
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+--------+------------+
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; Option ; Usage ;
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+--------+------------+
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+--------------------+
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; Simulator Messages ;
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+--------------------+
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Info: *******************************************************************
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Info: Running Quartus II Simulator
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Info: Version 9.1 Build 222 10/21/2009 SJ Full Version
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Info: Processing started: Mon May 21 14:02:19 2012
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Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid
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Info: Using vector source file "C:/Users/ProGOLD/Desktop/<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>/Altera DE1/Arkanoid/myArkanoid.vwf"
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Warning: Can't find signal in vector source file for input pin "|TotalScheme|button1"
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Warning: Can't find signal in vector source file for input pin "|TotalScheme|button2"
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Warning: Can't find signal in vector source file for input pin "|TotalScheme|button3"
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Warning: Can't find signal in vector source file for input pin "|TotalScheme|button4"
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Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
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Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
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Info: Simulation partitioned into 1 sub-simulations
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Info: Simulation coverage is 0.00 %
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Info: Number of transitions in simulation is 0
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Info: Quartus II Simulator was successful. 0 errors, 4 warnings
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Info: Peak virtual memory: 136 megabytes
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Info: Processing ended: Mon May 21 14:05:53 2012
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Info: Elapsed time: 00:03:34
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Info: Total CPU time (on all processors): 00:03:34
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