Version 1.0 released.

Implemented features: ball moving, platform moving, showing scores on digital table, game reset.

Arkanoid.bsf

@@ -26,8 +26,8 @@ applicable agreement for further details.
 	(port
 		(pt 0 32)
 		(input)
-		(text "clk50MHz" (rect 0 0 47 12)(font "Arial" ))
+		(text "clk25MHz" (rect 0 0 47 12)(font "Arial" ))
-		(text "clk50MHz" (rect 21 27 68 39)(font "Arial" ))
+		(text "clk25MHz" (rect 21 27 68 39)(font "Arial" ))
 		(line (pt 0 32)(pt 16 32)(line_width 1))
 	)
 	(port
@@ -96,29 +96,29 @@ applicable agreement for further details.
 	(port
 		(pt 152 112)
 		(output)
-		(text "num1[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "hex0[6..0]" (rect 0 0 49 12)(font "Arial" ))
-		(text "num1[6..0]" (rect 78 107 131 119)(font "Arial" ))
+		(text "hex0[6..0]" (rect 82 107 131 119)(font "Arial" ))
 		(line (pt 152 112)(pt 136 112)(line_width 3))
 	)
 	(port
 		(pt 152 128)
 		(output)
-		(text "num2[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "hex1[6..0]" (rect 0 0 49 12)(font "Arial" ))
-		(text "num2[6..0]" (rect 78 123 131 135)(font "Arial" ))
+		(text "hex1[6..0]" (rect 82 123 131 135)(font "Arial" ))
 		(line (pt 152 128)(pt 136 128)(line_width 3))
 	)
 	(port
 		(pt 152 144)
 		(output)
-		(text "num3[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "hex2[6..0]" (rect 0 0 49 12)(font "Arial" ))
-		(text "num3[6..0]" (rect 78 139 131 151)(font "Arial" ))
+		(text "hex2[6..0]" (rect 82 139 131 151)(font "Arial" ))
 		(line (pt 152 144)(pt 136 144)(line_width 3))
 	)
 	(port
 		(pt 152 160)
 		(output)
-		(text "num4[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "hex3[6..0]" (rect 0 0 49 12)(font "Arial" ))
-		(text "num4[6..0]" (rect 78 155 131 167)(font "Arial" ))
+		(text "hex3[6..0]" (rect 82 155 131 167)(font "Arial" ))
 		(line (pt 152 160)(pt 136 160)(line_width 3))
 	)
 	(port
@@ -128,16 +128,6 @@ applicable agreement for further details.
 		(text "led[7..0]" (rect 91 171 131 183)(font "Arial" ))
 		(line (pt 152 176)(pt 136 176)(line_width 3))
 	)
-	(parameter
-		"SCREEN_WIDTH"
-		"640"
-		""
-		(type "PARAMETER_SIGNED_DEC")	)
-	(parameter
-		"SCREEN_HEIGHT"
-		"480"
-		""
-		(type "PARAMETER_SIGNED_DEC")	)
 	(parameter
 		"CELL_SIZE"
 		"20"
@@ -150,17 +140,12 @@ applicable agreement for further details.
 		(type "PARAMETER_SIGNED_DEC")	)
 	(parameter
 		"BALL_SPEED"
-		"2"
+		"1"
 		""
 		(type "PARAMETER_SIGNED_DEC")	)
 	(parameter
 		"PLATFORM_WIDTH"
-		"8"
+		"7"
-		""
-		(type "PARAMETER_SIGNED_DEC")	)
-	(parameter
-		"PLATFORM_SPEED"
-		"1"
 		""
 		(type "PARAMETER_SIGNED_DEC")	)
 	(parameter

Arkanoid.v

@@ -1,179 +1,25 @@
 module Arkanoid
 
-#(
+	`include "arkanoid_header.v"
-	// Parameters
+	`include "int_to_digital.v"
-	parameter SCREEN_WIDTH = 640,       // Horizontal screen resolution (in pixels)
+	`include "vga_sync.v"
-	parameter SCREEN_HEIGHT = 480,      // Vertical screen resolution (in pixels)
 
-	parameter CELL_SIZE = 20,           // 1 cell has size of 20x20 pixels.
+	task GameRestart;
-	
-	parameter BALL_SIZE = 1,            // Game ball is a square of side 1 cell
-	parameter BALL_SPEED = 2,           // Number of cells per second
-	
-	parameter PLATFORM_WIDTH = 8,       // Game platform width
-	parameter PLATFORM_SPEED = 1,       // Number of cells per second
-	
-	parameter [3:0] BK_COLOR_R = 4'b1111,       // Red background
-	parameter [3:0] BK_COLOR_G = 4'b0000,
-	parameter [3:0] BK_COLOR_B = 4'b0000,
-	
-	parameter [3:0] STABLE_COLOR_R = 4'b0011,  // ??? color :)
-	parameter [3:0] STABLE_COLOR_G = 4'b1100,
-	parameter [3:0] STABLE_COLOR_B = 4'b0110,
-	
-	parameter [3:0] BALL_COLOR_R = 4'b0000,     // Blue ball
-	parameter [3:0] BALL_COLOR_G = 4'b0000,
-	parameter [3:0] BALL_COLOR_B = 4'b1111,
-	
-	parameter [3:0] PLATFORM_COLOR_R = 4'b1111, // Red platforms
-	parameter [3:0] PLATFORM_COLOR_G = 4'b0000,
-	parameter [3:0] PLATFORM_COLOR_B = 4'b0000
-)
-
-(
-	// Input Ports
-	input clk50MHz, // 50 MHz clock on DE1
-	input button1, button2, button3, button4, // 4 buttons on DE1 (left<->right for 2 players)
-
-	// Output Ports
-	output h_sync,
-	output v_sync,
-	output [3:0] red, green, blue, // Current pixel color (4096 colors = 12 bit)
-	output [6:0] num1, num2, num3, num4, // Digital LED's on DE1
-	output [7:0] led
-);
-	
-	//////////////////////////////////////
-	// **** BEGIN OF MODULE HEADER **** //
-	//////////////////////////////////////
-	
-	// Output registers
-	reg [3:0] red_, green_, blue_;
-	reg [6:0] num1_, num2_, num3_, num4_;
-	reg [7:0] led_;
-	
-	localparam FIELD_WIDTH = SCREEN_WIDTH/CELL_SIZE;   // Horizontal screen resolution (in cells)
-	localparam FIELD_HEIGHT = SCREEN_HEIGHT/CELL_SIZE; // Vertical screen resolution (in cells)
-	
-	// VGA Module
-	localparam line = 799;
-	localparam frame = 524;
-	
-	// 25 MHz clock
-	reg clk25MHz_;
-	wire clk25MHz;
-	
-	// 2D array of cells, stores game field state
-	reg [1:0] field[0:FIELD_HEIGHT-1][0:FIELD_WIDTH-1];
-	
-	// Possible cell values: (no comments)
-	localparam [1:0] EMPTY_CELL    = 2'b00;
-	localparam [1:0] STABLE_CELL   = 2'b11;
-	localparam [1:0] BALL_CELL     = 2'b01;
-	localparam [1:0] PLATFORM_CELL = 2'b10;
-	
-	// ATTENTION!!!
-	// All definitions below are in cells only.
-	//
-	
-	// Informaton about game ball
-	integer   ball_position_x; // Current coordinates
-	integer   ball_position_y; 
-	reg 	  ball_state;      // Current state (0 - stopped, 1 - moving)
-	reg [1:0] ball_direction;  // Current moving direction
-	
-	// Possible ball directions:
-	localparam [1:0] LEFT_UP    = 2'b00;
-	localparam [1:0] RIGHT_UP   = 2'b01;
-	localparam [1:0] LEFT_DOWN  = 2'b10;
-	localparam [1:0] RIGHT_DOWN = 2'b11;
-	
-	// Information about game platforms
-	integer platform1_position; // Current position (X axis, left border coordinate)
-	integer platform2_position; 
-	
-	// VGA variables
-	integer h_counter; // Horizontal pixel counter
-	integer v_counter; // Vertical pixel counter
-	integer h_cell;    // Horizontal cell counter
-	integer v_cell;    // Vertical cell counter
-	reg [1:0] current_cell; // Current cell value
-	
-	// Loops variables
-	integer i, j;
-		
-	// Last buttons state
-	reg button1_state;
-	reg button2_state;
-	reg button3_state;
-	reg button4_state;
-	
-	
-	////////////////////////////////////
-	// **** END OF MODULE HEADER **** //
-	////////////////////////////////////
-
-	// Initialization of all module variables
-	initial
 	begin
-		
+		ball_x = FIELD_WIDTH/2;
-		// Place ball to the center of the screen
+		ball_y = FIELD_HEIGHT-1;
-		ball_position_x = FIELD_WIDTH/2;
+		ball_direction = RIGHT_UP;
-		ball_position_y = FIELD_HEIGHT/2;
-		ball_state = 0;
-		
-		// Place platforms at the center of the borders
 		platform1_position = (FIELD_WIDTH-PLATFORM_WIDTH)/2; // central position
 		platform2_position = platform1_position;
-		
+		game_state = 1'b1;
-		button1_state = 1'b0;
-		button2_state = 1'b0;
-		button3_state = 1'b0;
-		button4_state = 1'b0;
-		
-		h_counter = 0;
-		v_counter = 0;
-		
-		for (i = 0; i < FIELD_HEIGHT; i = i + 1)
-			for (j = 0; j< FIELD_WIDTH; j = j + 1)
-				field[i][j] = EMPTY_CELL;
-		
-		field[ball_position_y][ball_position_x] = BALL_CELL;
-			
-		num1_ = 7'b0000000;
-		num2_ = 7'b0000000;
-		num3_ = 7'b0000000;
-		num4_ = 7'b0000000;
-	
 	end
+	endtask
 
-	// Frequency divider (50 MHz to 25 MHz, needed for VGA)
+	// Main logic
-	always @ (posedge clk50MHz)
-	begin
-		clk25MHz_ = ~clk25MHz_;
-	end
-	
-	// VGA sync
 	always @ (posedge clk25MHz)
 	begin
-		if(h_counter == line)
-			h_counter <= 0;
-		else
-			h_counter <= (h_counter + 1);
-	end
 				
-	always @ (posedge clk25MHz)
+		// Processing button presses
-	begin
-		if (v_counter == frame)
-			v_counter <= 0;
-		else if (h_counter == line)
-			v_counter <= (v_counter + 1);
-	end
-		
-
-	
-	always @ (posedge clk25MHz)
-	begin
 
 		if (button1 != button1_state)
 		begin
@@ -181,7 +27,10 @@ module Arkanoid
 			begin
 				led_[7] = 1'b1;
 				led_[6] = 1'b1;
-				if (platform1_position > 0)
+				
+				if (game_state == 1'b0)
+					GameRestart;
+				else if (platform1_position > 0)
 					platform1_position = platform1_position - 1;
 			end
 			else
@@ -198,7 +47,10 @@ module Arkanoid
 			begin
 				led_[5] = 1'b1;
 				led_[4] = 1'b1;
-				if (platform1_position < FIELD_WIDTH-PLATFORM_WIDTH-1)
+				
+				if (game_state == 1'b0)
+					GameRestart;
+				else if (platform1_position < FIELD_WIDTH-PLATFORM_WIDTH-1)
 					platform1_position = platform1_position + 1;
 			end
 			else
@@ -215,7 +67,10 @@ module Arkanoid
 			begin
 				led_[3] = 1'b1;
 				led_[2] = 1'b1;
-				if (platform2_position > 0)
+				
+				if (game_state == 1'b0)
+					GameRestart;
+				else if (platform2_position > 0)
 					platform2_position = platform2_position - 1;
 			end
 			else
@@ -232,7 +87,10 @@ module Arkanoid
 			begin
 				led_[1] = 1'b1;
 				led_[0] = 1'b1;
-				if (platform2_position < FIELD_WIDTH-PLATFORM_WIDTH-1)
+				
+				if (game_state == 1'b0)
+					GameRestart;
+				else if (platform2_position < FIELD_WIDTH-PLATFORM_WIDTH-1)
 					platform2_position = platform2_position + 1;
 			end
 			else
@@ -244,6 +102,7 @@ module Arkanoid
 		end
 		
 		
+		// Update field (move platforms)
 		for (i = 0; i < FIELD_WIDTH; i = i + 1)
 		begin
 			if ((i >= platform2_position) && (i <= platform2_position+PLATFORM_WIDTH))
@@ -258,6 +117,183 @@ module Arkanoid
 		end	
 		
 		
+		//Update field (move ball)
+		if (game_state)
+			if (ball_clock_counter < BALL_DELAY)
+				ball_clock_counter = ball_clock_counter + 1;
+			else
+			begin
+				ball_clock_counter = 0;
+				
+				field[ball_y][ball_x] = EMPTY_CELL;
+				
+				case (ball_direction)
+					
+					LEFT_UP:
+					begin
+					
+						if ((ball_x > 0) && (ball_y > 1))
+						begin
+							ball_x = ball_x - 1;
+							ball_y = ball_y - 1;
+						end
+						else if ((ball_x > 0) && (ball_y == 1))
+							if ((ball_x >= platform2_position) && (ball_x <= platform2_position + PLATFORM_WIDTH))
+							begin
+								ball_direction = LEFT_DOWN;
+								ball_x = ball_x - 1;
+								ball_y = ball_y + 1;
+							end
+							else
+							begin
+								// Goal
+								player1_score = player1_score + 1;
+								game_state = 1'b0;
+							end
+											
+						else if ((ball_x == 0) && (ball_y > 1))
+						begin
+							ball_direction = RIGHT_UP;
+							ball_x = ball_x + 1;
+							ball_y = ball_y - 1;
+						end
+						
+						else
+						begin
+							ball_direction = RIGHT_DOWN;
+							ball_x = ball_x + 1;
+							ball_y = ball_y + 1;
+						end
+
+					end
+					
+					RIGHT_UP:
+					begin
+					
+						if ((ball_x < FIELD_WIDTH-1) && (ball_y > 1))
+						begin
+							ball_x = ball_x + 1;
+							ball_y = ball_y - 1;
+						end
+						else if ((ball_x < FIELD_WIDTH-1) && (ball_y == 1))
+							if ((ball_x >= platform2_position) && (ball_x <= platform2_position + PLATFORM_WIDTH))
+							begin
+								ball_direction = RIGHT_DOWN;
+								ball_x = ball_x + 1;
+								ball_y = ball_y + 1;
+							end
+							else
+							begin
+								// Goal
+								player1_score = player1_score + 1;
+								game_state = 1'b0;
+							end
+											
+						else if ((ball_x == FIELD_WIDTH-1) && (ball_y > 1))
+						begin
+							ball_direction = LEFT_UP;
+							ball_x = ball_x - 1;
+							ball_y = ball_y - 1;
+						end
+						
+						else
+						begin
+							ball_direction = LEFT_DOWN;
+							ball_x = ball_x - 1;
+							ball_y = ball_y + 1;
+						end
+						
+					end
+					
+					LEFT_DOWN:
+					begin
+					
+						if ((ball_x > 0) && (ball_y < FIELD_HEIGHT-2))
+						begin
+							ball_x = ball_x - 1;
+							ball_y = ball_y + 1;
+						end
+						else if ((ball_x > 0) && (ball_y == FIELD_HEIGHT-2))
+							if ((ball_x >= platform1_position) && (ball_x <= platform1_position + PLATFORM_WIDTH))
+							begin
+								ball_direction = LEFT_UP;
+								ball_x = ball_x - 1;
+								ball_y = ball_y - 1;
+							end
+							else
+							begin
+								// Goal
+								player2_score = player2_score + 1;
+								game_state = 1'b0;
+							end
+											
+						else if ((ball_x == 0) && (ball_y < FIELD_HEIGHT-2))
+						begin
+							ball_direction = RIGHT_DOWN;
+							ball_x = ball_x + 1;
+							ball_y = ball_y + 1;
+						end
+						
+						else
+						begin
+							ball_direction = RIGHT_UP;
+							ball_x = ball_x + 1;
+							ball_y = ball_y - 1;
+						end
+									
+					end
+					
+					RIGHT_DOWN:
+					begin
+					
+						if ((ball_x < FIELD_WIDTH-1) && (ball_y < FIELD_HEIGHT-2))
+						begin
+							ball_x = ball_x + 1;
+							ball_y = ball_y + 1;
+						end
+						else if ((ball_x < FIELD_WIDTH-1) && (ball_y == FIELD_HEIGHT-2))
+							if ((ball_x >= platform1_position) && (ball_x <= platform1_position + PLATFORM_WIDTH))
+							begin
+								ball_direction = RIGHT_UP;
+								ball_x = ball_x + 1;
+								ball_y = ball_y - 1;
+							end
+							else
+							begin
+								// Goal
+								player2_score = player2_score + 1;
+								game_state = 1'b0;
+							end
+											
+						else if ((ball_x == FIELD_WIDTH-1) && (ball_y < FIELD_HEIGHT-2))
+						begin
+							ball_direction = LEFT_DOWN;
+							ball_x = ball_x - 1;
+							ball_y = ball_y + 1;
+						end
+						
+						else
+						begin
+							ball_direction = LEFT_UP;
+							ball_x = ball_x - 1;
+							ball_y = ball_y - 1;
+						end
+						
+					end
+					
+				endcase
+				
+				if (game_state)
+					field[ball_y][ball_x] = BALL_CELL;
+				
+			end
+		
+		
+		// Update scores
+		IntToDigital(player1_score, hex3_, hex2_);
+		IntToDigital(player2_score, hex1_, hex0_);
+		
+		
 		// VGA output
 		h_cell = (h_counter-143)/CELL_SIZE;
 		v_cell = (v_counter-34)/CELL_SIZE;
@@ -308,7 +344,43 @@ module Arkanoid
 		
 	end
 	
-	assign clk25MHz = clk25MHz_;
+	
+	// Initialization of all module variables
+	initial
+	begin
+		
+		game_state = 1'b0;
+		
+		// Reset scores
+		player1_score = 0;
+		player2_score = 0;
+		
+		// Place ball to the center of the screen
+		ball_clock_counter = 0;
+		ball_x = FIELD_WIDTH/2;
+		ball_y = FIELD_HEIGHT-1;
+		ball_direction = RIGHT_UP;
+		
+		// Place platforms at the center of the borders
+		platform1_position = (FIELD_WIDTH-PLATFORM_WIDTH)/2; // central position
+		platform2_position = platform1_position;
+		
+		// Clear field
+		for (i = 0; i < FIELD_HEIGHT; i = i + 1)
+			for (j = 0; j< FIELD_WIDTH; j = j + 1)
+				field[i][j] = EMPTY_CELL;
+		
+		// Reset buttons state
+		button1_state = 1'b0;
+		button2_state = 1'b0;
+		button3_state = 1'b0;
+		button4_state = 1'b0;
+				
+		// Reset VGA counters
+		h_counter = 0;
+		v_counter = 0;
+
+	end
 
 	assign h_sync = ~((h_counter > 0) && (h_counter < 95));
 	assign v_sync = ~((v_counter == 0) || (v_counter == 1));
@@ -317,10 +389,11 @@ module Arkanoid
 	assign green = green_;
 	assign blue = blue_;
 	
-	assign led = led_;
+	assign hex0 = ~hex0_;
-	assign num1 = num1_;
+	assign hex1 = ~hex1_;
-	assign num2 = num2_;
+	assign hex2 = ~hex2_;
-	assign num3 = num3_;
+	assign hex3 = ~hex3_;
-	assign num4 = num4_;
+	
+	assign led = ~led_;	
 	
 endmodule

Arkanoid.v.bak

@@ -1,328 +0,0 @@
-module Arkanoid
-
-#(
-	// Parameters
-	parameter SCREEN_WIDTH = 640,       // Horizontal screen resolution (in pixels)
-	parameter SCREEN_HEIGHT = 480,      // Vertical screen resolution (in pixels)
-	
-	parameter CELL_SIZE = 20,           // 1 cell has size of 20x20 pixels.
-	
-	parameter BALL_SIZE = 1,            // Game ball is a square of side 1 cell
-	parameter BALL_SPEED = 2,           // Number of cells per second
-	
-	parameter PLATFORM_WIDTH = 8,       // Game platform width
-	parameter PLATFORM_SPEED = 1,       // Number of cells per second
-	
-	parameter [3:0] BK_COLOR_R = 4'b1111,       // Red background
-	parameter [3:0] BK_COLOR_G = 4'b0000,
-	parameter [3:0] BK_COLOR_B = 4'b0000,
-	
-	parameter [3:0] STABLE_COLOR_R = 4'b0011,  // ??? color :)
-	parameter [3:0] STABLE_COLOR_G = 4'b1100,
-	parameter [3:0] STABLE_COLOR_B = 4'b0110,
-	
-	parameter [3:0] BALL_COLOR_R = 4'b0000,     // Blue ball
-	parameter [3:0] BALL_COLOR_G = 4'b0000,
-	parameter [3:0] BALL_COLOR_B = 4'b1111,
-	
-	parameter [3:0] PLATFORM_COLOR_R = 4'b1111, // Red platforms
-	parameter [3:0] PLATFORM_COLOR_G = 4'b0000,
-	parameter [3:0] PLATFORM_COLOR_B = 4'b0000
-)
-
-(
-	// Input Ports
-	input clk50MHz, // 50 MHz clock on DE1
-	input button1, button2, button3, button4, // 4 buttons on DE1 (left<->right for 2 players)
-
-	// Output Ports
-	output h_sync,
-	output v_sync,
-	output [3:0] red, green, blue, // Current pixel color (4096 colors = 12 bit)
-	output [6:0] num1, num2, num3, num4, // Digital LED's on DE1
-	output [7:0] led
-);
-	
-	//////////////////////////////////////
-	// **** BEGIN OF MODULE HEADER **** //
-	//////////////////////////////////////
-	
-	// Output registers
-	reg [3:0] red_, green_, blue_;
-	reg [6:0] num1_, num2_, num3_, num4_;
-	reg [7:0] led_;
-	
-	localparam FIELD_WIDTH = SCREEN_WIDTH/CELL_SIZE;   // Horizontal screen resolution (in cells)
-	localparam FIELD_HEIGHT = SCREEN_HEIGHT/CELL_SIZE; // Vertical screen resolution (in cells)
-	
-	// VGA Module
-	localparam line = 799;
-	localparam frame = 524;
-	
-	// 25 MHz clock
-	reg clk25MHz_;
-	wire clk25MHz;
-	
-	// 2D array of cells, stores game field state
-	reg [1:0] field[0:FIELD_HEIGHT-1][0:FIELD_WIDTH-1];
-	
-	// Possible cell values: (no comments)
-	localparam [1:0] EMPTY_CELL    = 2'b00;
-	localparam [1:0] STABLE_CELL   = 2'b11;
-	localparam [1:0] BALL_CELL     = 2'b01;
-	localparam [1:0] PLATFORM_CELL = 2'b10;
-	
-	// ATTENTION!!!
-	// All definitions below are in cells only.
-	//
-	
-	// Informaton about game ball
-	integer   ball_position_x; // Current coordinates
-	integer   ball_position_y; 
-	reg 	  ball_state;      // Current state (0 - stopped, 1 - moving)
-	reg [1:0] ball_direction;  // Current moving direction
-	
-	// Possible ball directions:
-	localparam [1:0] LEFT_UP    = 2'b00;
-	localparam [1:0] RIGHT_UP   = 2'b01;
-	localparam [1:0] LEFT_DOWN  = 2'b10;
-	localparam [1:0] RIGHT_DOWN = 2'b11;
-	
-	// Information about game platforms
-	integer platform1_position; // Current position (X axis, left border coordinate)
-	integer platform2_position; 
-	
-	// VGA variables
-	integer h_counter; // Horizontal pixel counter
-	integer v_counter; // Vertical pixel counter
-	integer h_cell;    // Horizontal cell counter
-	integer v_cell;    // Vertical cell counter
-	reg [1:0] current_cell; // Current cell value
-	
-	// Loops variables
-	integer i, j;
-		
-	// Last buttons state
-	reg button1_state;
-	reg button2_state;
-	reg button3_state;
-	reg button4_state;
-	
-	
-	////////////////////////////////////
-	// **** END OF MODULE HEADER **** //
-	////////////////////////////////////
-
-	// Initialization of all module variables
-	initial
-	begin
-		
-		// Place ball to the center of the screen
-		ball_position_x = FIELD_WIDTH/2;
-		ball_position_y = FIELD_HEIGHT/2;
-		ball_state = 0;
-		
-		// Place platforms at the center of the borders
-		platform1_position = (FIELD_WIDTH-PLATFORM_WIDTH)/2; // central position
-		platform2_position = platform1_position;
-		
-		button1_state = 1'b0;
-		button2_state = 1'b0;
-		button3_state = 1'b0;
-		button4_state = 1'b0;
-		
-		h_counter = 0;
-		v_counter = 0;
-		
-		for (i = 0; i < FIELD_HEIGHT; i = i + 1)
-			for (j = 0; j< FIELD_WIDTH; j = j + 1)
-				field[i][j] = EMPTY_CELL;
-		
-		field[ball_position_y][ball_position_x] = BALL_CELL;
-							
-		// Print platforms
-			
-		num1_ = 7'b0000000;
-		num2_ = 7'b0000000;
-		num3_ = 7'b0000000;
-		num4_ = 7'b0000000;
-	
-	end
-	
-	// Frequency divider (50 MHz to 25 MHz, needed for VGA)
-	always @ (posedge clk50MHz)
-	begin
-		clk25MHz_ = ~clk25MHz_;
-	end
-	
-	// VGA sync
-	always @ (posedge clk25MHz)
-	begin
-		if(h_counter == line)
-			h_counter <= 0;
-		else
-			h_counter <= (h_counter + 1);
-	end
-			
-	always @ (posedge clk25MHz)
-	begin
-		if (v_counter == frame)
-			v_counter <= 0;
-		else if (h_counter == line)
-			v_counter <= (v_counter + 1);
-	end
-		
-
-	
-	always @ (posedge clk25MHz)
-	begin
-				
-		if (button1 != button1_state)
-		begin
-			if (button1 == 1'b1)
-			begin
-				led_[7] = 1'b1;
-				led_[6] = 1'b1;
-				if (platform1_position > 0)
-					platform1_position = platform1_position - 1;
-			end
-			else
-			begin
-				led_[7] = 1'b0;
-				led_[6] = 1'b0;
-			end
-			button1_state = button1;
-		end
-		
-		if (button2 != button2_state)
-		begin
-			if (button2 == 1'b1)
-			begin
-				led_[5] = 1'b1;
-				led_[4] = 1'b1;
-				if (platform1_position < FIELD_WIDTH-PLATFORM_WIDTH-1)
-					platform1_position = platform1_position + 1;
-			end
-			else
-			begin
-				led_[5] = 1'b0;
-				led_[4] = 1'b0;
-			end
-			button2_state = button2;
-		end
-		
-		if (button3 != button3_state)
-		begin
-			if (button3 == 1'b1)
-			begin
-				led_[3] = 1'b1;
-				led_[2] = 1'b1;
-				if (platform2_position > 0)
-					platform2_position = platform2_position - 1;
-			end
-			else
-			begin
-				led_[3] = 1'b0;
-				led_[2] = 1'b0;
-			end
-			button3_state = button3;
-		end		
-		
-		if (button4 != button4_state)
-		begin
-			if (button4 == 1'b1)
-			begin
-				led_[1] = 1'b1;
-				led_[0] = 1'b1;
-				if (platform2_position < FIELD_WIDTH-PLATFORM_WIDTH-1)
-					platform2_position = platform2_position + 1;
-			end
-			else
-			begin
-				led_[1] = 1'b0;
-				led_[0] = 1'b0;
-			end 
-			button4_state = button4;
-		end		
-		
-		
-		for (i = 0; i < FIELD_WIDTH; i = i + 1)
-		begin
-			if ((i >= platform2_position) && (i <= platform2_position+PLATFORM_WIDTH))
-				field[0][i] = PLATFORM_CELL;
-			else
-				field[0][i] = EMPTY_CELL;
-			
-			if ((i >= platform1_position) && (i <= platform1_position+PLATFORM_WIDTH))
-				field[FIELD_HEIGHT-1][i] = PLATFORM_CELL;
-			else
-				field[FIELD_HEIGHT-1][i] = EMPTY_CELL;
-		end
-		
-		
-		// VGA output
-		h_cell = (h_counter-143)/CELL_SIZE;
-		v_cell = (v_counter-34)/CELL_SIZE;
-		if ((v_counter > 34) && (v_counter < 514) && (h_counter > 143) && (h_counter < 783))
-		begin
-			
-			current_cell = field[v_cell][h_cell];
-		
-			case(current_cell)
-				
-				EMPTY_CELL: 
-				begin
-					red_ = BK_COLOR_R;
-					green_ = BK_COLOR_G;
-					blue_ = BK_COLOR_B;
-				end
-				
-				STABLE_CELL:
-				begin
-					red_ = STABLE_COLOR_R;
-					green_ = STABLE_COLOR_G;
-					blue_ = STABLE_COLOR_B;
-				end
-				
-				BALL_CELL:
-				begin
-					red_ = BALL_COLOR_R;
-					green_ = BALL_COLOR_G;
-					blue_ = BALL_COLOR_B;
-				end
-				
-				PLATFORM_CELL:
-				begin
-					red_ = PLATFORM_COLOR_R;
-					green_ = PLATFORM_COLOR_G;
-					blue_ = PLATFORM_COLOR_B;
-				end
-				
-			endcase
-						
-		end
-		else
-		begin
-			red_ = 4'b0000;
-			green_ = 4'b0000;
-			blue_ = 4'b0000;
-		end
-		
-	end
-
-	assign clk25MHz = clk25MHz_;
-	
-	assign h_sync = ~((h_counter > 0) && (h_counter < 95));
-	assign v_sync = ~((v_counter == 0) || (v_counter == 1));
-	
-	assign red = red_;
-	assign green = green_;
-	assign blue = blue_;
-	
-	assign led = led_;
-	assign num1 = num1_;
-	assign num2 = num2_;
-	assign num3 = num3_;
-	assign num4 = num4_;
-	
-endmodule

ClockDivider.bsf

@@ -0,0 +1,43 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 64 64 216 128)
+	(text "ClockDivider" (rect 5 0 68 12)(font "Arial" ))
+	(text "inst" (rect 8 48 25 60)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk50MHz" (rect 0 0 47 12)(font "Arial" ))
+		(text "clk50MHz" (rect 21 27 68 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 152 32)
+		(output)
+		(text "clk25MHz" (rect 0 0 47 12)(font "Arial" ))
+		(text "clk25MHz" (rect 84 27 131 39)(font "Arial" ))
+		(line (pt 152 32)(pt 136 32)(line_width 1))
+	)
+	(drawing
+		(rectangle (rect 16 16 136 48)(line_width 1))
+	)
+)

ClockDivider.v

@@ -0,0 +1,14 @@
+module ClockDivider (clk50MHz, clk25MHz);
+input clk50MHz;
+output clk25MHz;
+
+reg clk25MHz_;
+
+always @ (posedge clk50MHz)
+begin
+	clk25MHz_ = ~clk25MHz_;
+end
+
+assign clk25MHz = clk25MHz_;
+
+endmodule

Debouncer.bsf

@@ -0,0 +1,50 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 152 112)
+	(text "Debouncer" (rect 5 0 58 12)(font "Arial" ))
+	(text "inst" (rect 8 80 25 92)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "noisy" (rect 0 0 27 12)(font "Arial" ))
+		(text "noisy" (rect 21 27 48 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clk" (rect 0 0 14 12)(font "Arial" ))
+		(text "clk" (rect 21 43 35 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 136 32)
+		(output)
+		(text "debounced" (rect 0 0 53 12)(font "Arial" ))
+		(text "debounced" (rect 62 27 115 39)(font "Arial" ))
+		(line (pt 136 32)(pt 120 32)(line_width 1))
+	)
+	(drawing
+		(rectangle (rect 16 16 120 80)(line_width 1))
+	)
+)

Debouncer.v

@@ -0,0 +1,22 @@
+module Debouncer (noisy, clk, debounced);
+
+input clk;
+input noisy;
+output reg debounced;
+
+reg [7:0] button_reg;
+
+always @ (posedge clk) 
+begin
+	
+	button_reg[7:0] <= {button_reg[6:0],noisy}; //shift register
+	
+	if(button_reg[7:0] == 8'b00000000)
+		debounced <= 1'b0;
+	else if(button_reg[7:0] == 8'b11111111)
+		debounced <= 1'b1;
+	else 
+		debounced <= debounced;
+end
+
+endmodule

TotalScheme.bdf

@@ -22,7 +22,7 @@ applicable agreement for further details.
 (header "graphic" (version "1.3"))
 (pin
 	(input)
-	(rect 296 152 464 168)
+	(rect -72 -168 96 -152)
 	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
 	(text "clk_50MHz" (rect 5 0 58 12)(font "Arial" ))
 	(pt 168 8)
@@ -35,11 +35,11 @@ applicable agreement for further details.
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
 	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 240 152 288 168))
+	(annotation_block (location)(rect -128 -168 -80 -152))
 )
 (pin
 	(input)
-	(rect 296 168 464 184)
+	(rect -72 -72 96 -56)
 	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
 	(text "button1" (rect 5 0 41 12)(font "Arial" ))
 	(pt 168 8)
@@ -52,11 +52,11 @@ applicable agreement for further details.
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
 	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 240 168 296 184))
+	(annotation_block (location)(rect -128 -72 -72 -56))
 )
 (pin
 	(input)
-	(rect 296 184 464 200)
+	(rect -72 24 96 40)
 	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
 	(text "button2" (rect 5 0 41 12)(font "Arial" ))
 	(pt 168 8)
@@ -69,11 +69,11 @@ applicable agreement for further details.
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
 	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 240 184 296 200))
+	(annotation_block (location)(rect -128 24 -72 40))
 )
 (pin
 	(input)
-	(rect 296 200 464 216)
+	(rect -72 120 96 136)
 	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
 	(text "button3" (rect 5 0 41 12)(font "Arial" ))
 	(pt 168 8)
@@ -86,11 +86,11 @@ applicable agreement for further details.
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
 	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 240 200 296 216))
+	(annotation_block (location)(rect -128 120 -72 136))
 )
 (pin
 	(input)
-	(rect 296 216 464 232)
+	(rect -72 216 96 232)
 	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
 	(text "button4" (rect 5 0 41 12)(font "Arial" ))
 	(pt 168 8)
@@ -103,79 +103,11 @@ applicable agreement for further details.
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
 	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 240 216 296 232))
+	(annotation_block (location)(rect -128 216 -72 232))
 )
 (pin
 	(output)
-	(rect 912 304 1088 320)
+	(rect 856 96 1032 112)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
-	(text "led1[6..0]" (rect 90 0 136 12)(font "Arial" ))
-	(pt 0 8)
-	(drawing
-		(line (pt 0 8)(pt 52 8)(line_width 1))
-		(line (pt 52 4)(pt 78 4)(line_width 1))
-		(line (pt 52 12)(pt 78 12)(line_width 1))
-		(line (pt 52 12)(pt 52 4)(line_width 1))
-		(line (pt 78 4)(pt 82 8)(line_width 1))
-		(line (pt 82 8)(pt 78 12)(line_width 1))
-		(line (pt 78 12)(pt 82 8)(line_width 1))
-	)
-	(annotation_block (location)(rect 1320 320 1368 424))
-)
-(pin
-	(output)
-	(rect 912 320 1088 336)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
-	(text "led2[6..0]" (rect 90 0 136 12)(font "Arial" ))
-	(pt 0 8)
-	(drawing
-		(line (pt 0 8)(pt 52 8)(line_width 1))
-		(line (pt 52 4)(pt 78 4)(line_width 1))
-		(line (pt 52 12)(pt 78 12)(line_width 1))
-		(line (pt 52 12)(pt 52 4)(line_width 1))
-		(line (pt 78 4)(pt 82 8)(line_width 1))
-		(line (pt 82 8)(pt 78 12)(line_width 1))
-		(line (pt 78 12)(pt 82 8)(line_width 1))
-	)
-	(annotation_block (location)(rect 1248 336 1296 440))
-)
-(pin
-	(output)
-	(rect 912 336 1088 352)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
-	(text "led3[6..0]" (rect 90 0 136 12)(font "Arial" ))
-	(pt 0 8)
-	(drawing
-		(line (pt 0 8)(pt 52 8)(line_width 1))
-		(line (pt 52 4)(pt 78 4)(line_width 1))
-		(line (pt 52 12)(pt 78 12)(line_width 1))
-		(line (pt 52 12)(pt 52 4)(line_width 1))
-		(line (pt 78 4)(pt 82 8)(line_width 1))
-		(line (pt 82 8)(pt 78 12)(line_width 1))
-		(line (pt 78 12)(pt 82 8)(line_width 1))
-	)
-	(annotation_block (location)(rect 1176 352 1224 456))
-)
-(pin
-	(output)
-	(rect 912 352 1088 368)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
-	(text "led4[6..0]" (rect 90 0 136 12)(font "Arial" ))
-	(pt 0 8)
-	(drawing
-		(line (pt 0 8)(pt 52 8)(line_width 1))
-		(line (pt 52 4)(pt 78 4)(line_width 1))
-		(line (pt 52 12)(pt 78 12)(line_width 1))
-		(line (pt 52 12)(pt 52 4)(line_width 1))
-		(line (pt 78 4)(pt 82 8)(line_width 1))
-		(line (pt 82 8)(pt 78 12)(line_width 1))
-		(line (pt 78 12)(pt 82 8)(line_width 1))
-	)
-	(annotation_block (location)(rect 1104 368 1152 472))
-)
-(pin
-	(output)
-	(rect 912 152 1088 168)
 	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
 	(text "h_sync" (rect 90 0 126 12)(font "Arial" ))
 	(pt 0 8)
@@ -188,11 +120,11 @@ applicable agreement for further details.
 		(line (pt 82 8)(pt 78 12)(line_width 1))
 		(line (pt 78 12)(pt 82 8)(line_width 1))
 	)
-	(annotation_block (location)(rect 1088 152 1144 168))
+	(annotation_block (location)(rect 1032 96 1088 112))
 )
 (pin
 	(output)
-	(rect 912 184 1088 200)
+	(rect 856 184 1032 200)
 	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
 	(text "red[3..0]" (rect 90 0 131 12)(font "Arial" ))
 	(pt 0 8)
@@ -205,11 +137,11 @@ applicable agreement for further details.
 		(line (pt 82 8)(pt 78 12)(line_width 1))
 		(line (pt 78 12)(pt 82 8)(line_width 1))
 	)
-	(annotation_block (location)(rect 1248 200 1296 256))
+	(annotation_block (location)(rect 1192 200 1240 256))
 )
 (pin
 	(output)
-	(rect 912 200 1088 216)
+	(rect 856 200 1032 216)
 	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
 	(text "green[3..0]" (rect 90 0 143 12)(font "Arial" ))
 	(pt 0 8)
@@ -222,11 +154,11 @@ applicable agreement for further details.
 		(line (pt 82 8)(pt 78 12)(line_width 1))
 		(line (pt 78 12)(pt 82 8)(line_width 1))
 	)
-	(annotation_block (location)(rect 1176 216 1232 272))
+	(annotation_block (location)(rect 1120 216 1176 272))
 )
 (pin
 	(output)
-	(rect 912 216 1088 232)
+	(rect 856 216 1032 232)
 	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
 	(text "blue[3..0]" (rect 90 0 136 12)(font "Arial" ))
 	(pt 0 8)
@@ -239,11 +171,11 @@ applicable agreement for further details.
 		(line (pt 82 8)(pt 78 12)(line_width 1))
 		(line (pt 78 12)(pt 82 8)(line_width 1))
 	)
-	(annotation_block (location)(rect 1104 232 1160 288))
+	(annotation_block (location)(rect 1048 232 1104 288))
 )
 (pin
 	(output)
-	(rect 912 168 1088 184)
+	(rect 856 112 1032 128)
 	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
 	(text "v_sync" (rect 90 0 127 12)(font "Arial" ))
 	(pt 0 8)
@@ -256,11 +188,11 @@ applicable agreement for further details.
 		(line (pt 82 8)(pt 78 12)(line_width 1))
 		(line (pt 78 12)(pt 82 8)(line_width 1))
 	)
-	(annotation_block (location)(rect 1088 168 1144 184))
+	(annotation_block (location)(rect 1032 112 1088 128))
 )
 (pin
 	(output)
-	(rect 912 424 1088 440)
+	(rect 856 448 1032 464)
 	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
 	(text "led[7..0]" (rect 90 0 130 12)(font "Arial" ))
 	(pt 0 8)
@@ -273,11 +205,80 @@ applicable agreement for further details.
 		(line (pt 82 8)(pt 78 12)(line_width 1))
 		(line (pt 78 12)(pt 82 8)(line_width 1))
 	)
+	(annotation_block (location)(rect 1048 464 1104 576))
+)
+(pin
+	(output)
+	(rect 856 280 1032 296)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "hex0[6..0]" (rect 90 0 139 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8)(line_width 1))
+		(line (pt 52 4)(pt 78 4)(line_width 1))
+		(line (pt 52 12)(pt 78 12)(line_width 1))
+		(line (pt 52 12)(pt 52 4)(line_width 1))
+		(line (pt 78 4)(pt 82 8)(line_width 1))
+		(line (pt 82 8)(pt 78 12)(line_width 1))
+		(line (pt 78 12)(pt 82 8)(line_width 1))
+	)
+	(annotation_block (location)(rect 1264 296 1312 400))
+)
+(pin
+	(output)
+	(rect 856 296 1032 312)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "hex1[6..0]" (rect 90 0 139 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8)(line_width 1))
+		(line (pt 52 4)(pt 78 4)(line_width 1))
+		(line (pt 52 12)(pt 78 12)(line_width 1))
+		(line (pt 52 12)(pt 52 4)(line_width 1))
+		(line (pt 78 4)(pt 82 8)(line_width 1))
+		(line (pt 82 8)(pt 78 12)(line_width 1))
+		(line (pt 78 12)(pt 82 8)(line_width 1))
+	)
+	(annotation_block (location)(rect 1192 312 1240 416))
+)
+(pin
+	(output)
+	(rect 856 312 1032 328)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "hex2[6..0]" (rect 90 0 139 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8)(line_width 1))
+		(line (pt 52 4)(pt 78 4)(line_width 1))
+		(line (pt 52 12)(pt 78 12)(line_width 1))
+		(line (pt 52 12)(pt 52 4)(line_width 1))
+		(line (pt 78 4)(pt 82 8)(line_width 1))
+		(line (pt 82 8)(pt 78 12)(line_width 1))
+		(line (pt 78 12)(pt 82 8)(line_width 1))
+	)
+	(annotation_block (location)(rect 1120 328 1168 432))
+)
+(pin
+	(output)
+	(rect 856 328 1032 344)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "hex3[6..0]" (rect 90 0 139 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8)(line_width 1))
+		(line (pt 52 4)(pt 78 4)(line_width 1))
+		(line (pt 52 12)(pt 78 12)(line_width 1))
+		(line (pt 52 12)(pt 52 4)(line_width 1))
+		(line (pt 78 4)(pt 82 8)(line_width 1))
+		(line (pt 82 8)(pt 78 12)(line_width 1))
+		(line (pt 78 12)(pt 82 8)(line_width 1))
+	)
+	(annotation_block (location)(rect 1048 344 1096 448))
 )
 (symbol
-	(rect 528 128 680 352)
+	(rect 160 -192 312 -128)
-	(text "Arkanoid" (rect 5 0 47 12)(font "Arial" ))
+	(text "ClockDivider" (rect 5 0 68 12)(font "Arial" ))
-	(text "inst" (rect 8 208 25 220)(font "Arial" ))
+	(text "inst1" (rect 8 48 31 60)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
@@ -285,6 +286,144 @@ applicable agreement for further details.
 		(text "clk50MHz" (rect 21 27 68 39)(font "Arial" ))
 		(line (pt 0 32)(pt 16 32)(line_width 1))
 	)
+	(port
+		(pt 152 32)
+		(output)
+		(text "clk25MHz" (rect 0 0 47 12)(font "Arial" ))
+		(text "clk25MHz" (rect 84 27 131 39)(font "Arial" ))
+		(line (pt 152 32)(pt 136 32)(line_width 1))
+	)
+	(drawing
+		(rectangle (rect 16 16 136 48)(line_width 1))
+	)
+)
+(symbol
+	(rect 168 -96 304 0)
+	(text "Debouncer" (rect 5 0 58 12)(font "Arial" ))
+	(text "inst2" (rect 8 80 31 92)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "noisy" (rect 0 0 27 12)(font "Arial" ))
+		(text "noisy" (rect 21 27 48 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clk" (rect 0 0 14 12)(font "Arial" ))
+		(text "clk" (rect 21 43 35 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 136 32)
+		(output)
+		(text "debounced" (rect 0 0 53 12)(font "Arial" ))
+		(text "debounced" (rect 62 27 115 39)(font "Arial" ))
+		(line (pt 136 32)(pt 120 32)(line_width 1))
+	)
+	(drawing
+		(rectangle (rect 16 16 120 80)(line_width 1))
+	)
+)
+(symbol
+	(rect 168 0 304 96)
+	(text "Debouncer" (rect 5 0 58 12)(font "Arial" ))
+	(text "inst3" (rect 8 80 31 92)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "noisy" (rect 0 0 27 12)(font "Arial" ))
+		(text "noisy" (rect 21 27 48 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clk" (rect 0 0 14 12)(font "Arial" ))
+		(text "clk" (rect 21 43 35 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 136 32)
+		(output)
+		(text "debounced" (rect 0 0 53 12)(font "Arial" ))
+		(text "debounced" (rect 62 27 115 39)(font "Arial" ))
+		(line (pt 136 32)(pt 120 32)(line_width 1))
+	)
+	(drawing
+		(rectangle (rect 16 16 120 80)(line_width 1))
+	)
+)
+(symbol
+	(rect 168 96 304 192)
+	(text "Debouncer" (rect 5 0 58 12)(font "Arial" ))
+	(text "inst4" (rect 8 80 31 92)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "noisy" (rect 0 0 27 12)(font "Arial" ))
+		(text "noisy" (rect 21 27 48 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clk" (rect 0 0 14 12)(font "Arial" ))
+		(text "clk" (rect 21 43 35 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 136 32)
+		(output)
+		(text "debounced" (rect 0 0 53 12)(font "Arial" ))
+		(text "debounced" (rect 62 27 115 39)(font "Arial" ))
+		(line (pt 136 32)(pt 120 32)(line_width 1))
+	)
+	(drawing
+		(rectangle (rect 16 16 120 80)(line_width 1))
+	)
+)
+(symbol
+	(rect 168 192 304 288)
+	(text "Debouncer" (rect 5 0 58 12)(font "Arial" ))
+	(text "inst5" (rect 8 80 31 92)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "noisy" (rect 0 0 27 12)(font "Arial" ))
+		(text "noisy" (rect 21 27 48 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clk" (rect 0 0 14 12)(font "Arial" ))
+		(text "clk" (rect 21 43 35 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 136 32)
+		(output)
+		(text "debounced" (rect 0 0 53 12)(font "Arial" ))
+		(text "debounced" (rect 62 27 115 39)(font "Arial" ))
+		(line (pt 136 32)(pt 120 32)(line_width 1))
+	)
+	(drawing
+		(rectangle (rect 16 16 120 80)(line_width 1))
+	)
+)
+(symbol
+	(rect 464 128 616 352)
+	(text "Arkanoid" (rect 5 0 47 12)(font "Arial" ))
+	(text "inst" (rect 8 208 25 220)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk25MHz" (rect 0 0 47 12)(font "Arial" ))
+		(text "clk25MHz" (rect 21 27 68 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
 	(port
 		(pt 0 48)
 		(input)
@@ -351,29 +490,29 @@ applicable agreement for further details.
 	(port
 		(pt 152 112)
 		(output)
-		(text "num1[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "hex0[6..0]" (rect 0 0 49 12)(font "Arial" ))
-		(text "num1[6..0]" (rect 78 107 131 119)(font "Arial" ))
+		(text "hex0[6..0]" (rect 82 107 131 119)(font "Arial" ))
 		(line (pt 152 112)(pt 136 112)(line_width 3))
 	)
 	(port
 		(pt 152 128)
 		(output)
-		(text "num2[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "hex1[6..0]" (rect 0 0 49 12)(font "Arial" ))
-		(text "num2[6..0]" (rect 78 123 131 135)(font "Arial" ))
+		(text "hex1[6..0]" (rect 82 123 131 135)(font "Arial" ))
 		(line (pt 152 128)(pt 136 128)(line_width 3))
 	)
 	(port
 		(pt 152 144)
 		(output)
-		(text "num3[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "hex2[6..0]" (rect 0 0 49 12)(font "Arial" ))
-		(text "num3[6..0]" (rect 78 139 131 151)(font "Arial" ))
+		(text "hex2[6..0]" (rect 82 139 131 151)(font "Arial" ))
 		(line (pt 152 144)(pt 136 144)(line_width 3))
 	)
 	(port
 		(pt 152 160)
 		(output)
-		(text "num4[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "hex3[6..0]" (rect 0 0 49 12)(font "Arial" ))
-		(text "num4[6..0]" (rect 78 155 131 167)(font "Arial" ))
+		(text "hex3[6..0]" (rect 82 155 131 167)(font "Arial" ))
 		(line (pt 152 160)(pt 136 160)(line_width 3))
 	)
 	(port
@@ -383,16 +522,6 @@ applicable agreement for further details.
 		(text "led[7..0]" (rect 91 171 131 183)(font "Arial" ))
 		(line (pt 152 176)(pt 136 176)(line_width 3))
 	)
-	(parameter
-		"SCREEN_WIDTH"
-		"640"
-		""
-		(type "PARAMETER_SIGNED_DEC")	)
-	(parameter
-		"SCREEN_HEIGHT"
-		"480"
-		""
-		(type "PARAMETER_SIGNED_DEC")	)
 	(parameter
 		"CELL_SIZE"
 		"20"
@@ -405,32 +534,27 @@ applicable agreement for further details.
 		(type "PARAMETER_SIGNED_DEC")	)
 	(parameter
 		"BALL_SPEED"
-		"2"
+		"3"
 		""
 		(type "PARAMETER_SIGNED_DEC")	)
 	(parameter
 		"PLATFORM_WIDTH"
-		"8"
+		"7"
-		""
-		(type "PARAMETER_SIGNED_DEC")	)
-	(parameter
-		"PLATFORM_SPEED"
-		"1"
 		""
 		(type "PARAMETER_SIGNED_DEC")	)
 	(parameter
 		"BK_COLOR_R"
-		"0000"
+		"1111"
 		""
 		(type "PARAMETER_UNSIGNED_BIN")	)
 	(parameter
 		"BK_COLOR_G"
-		"0000"
+		"1111"
 		""
 		(type "PARAMETER_UNSIGNED_BIN")	)
 	(parameter
 		"BK_COLOR_B"
-		"0000"
+		"1111"
 		""
 		(type "PARAMETER_UNSIGNED_BIN")	)
 	(parameter
@@ -478,161 +602,238 @@ applicable agreement for further details.
 		"0000"
 		""
 		(type "PARAMETER_UNSIGNED_BIN")	)
-	(parameter
-		"PLATFORM_HEIGHT"
-		"1"
-		""
-		(type "PARAMETER_SIGNED_DEC")	)
 	(drawing
 		(rectangle (rect 16 16 136 208)(line_width 1))
 	)
-	(annotation_block (parameter)(rect 528 -168 760 128))
+	(annotation_block (parameter)(rect 464 -112 696 128))
-)
-(symbol
-	(rect 816 416 864 448)
-	(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
-	(text "inst1" (rect 3 21 26 33)(font "Arial" ))
-	(port
-		(pt 0 16)
-		(input)
-		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
-		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
-		(line (pt 0 16)(pt 13 16)(line_width 1))
-	)
-	(port
-		(pt 48 16)
-		(output)
-		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
-		(line (pt 39 16)(pt 48 16)(line_width 1))
-	)
-	(drawing
-		(line (pt 13 25)(pt 13 7)(line_width 1))
-		(line (pt 13 7)(pt 31 16)(line_width 1))
-		(line (pt 13 25)(pt 31 16)(line_width 1))
-		(circle (rect 31 12 39 20)(line_width 1))
-	)
 )
 (connector
-	(pt 680 240)
+	(pt 792 104)
-	(pt 808 240)
+	(pt 856 104)
-	(bus)
 )
 (connector
-	(pt 680 256)
+	(pt 808 120)
-	(pt 792 256)
+	(pt 856 120)
-	(bus)
 )
 (connector
-	(pt 680 272)
+	(pt 792 104)
-	(pt 776 272)
+	(pt 792 160)
-	(bus)
 )
 (connector
-	(pt 680 288)
+	(pt 808 120)
-	(pt 760 288)
+	(pt 808 176)
-	(bus)
 )
 (connector
-	(pt 528 160)
+	(pt 320 208)
-	(pt 464 160)
-)
-(connector
-	(pt 528 176)
-	(pt 464 176)
-)
-(connector
-	(pt 528 192)
-	(pt 464 192)
-)
-(connector
-	(pt 528 208)
 	(pt 464 208)
 )
 (connector
-	(pt 528 224)
+	(pt 336 192)
-	(pt 464 224)
+	(pt 464 192)
 )
 (connector
-	(pt 680 160)
+	(pt 352 176)
-	(pt 912 160)
+	(pt 464 176)
 )
 (connector
-	(pt 680 176)
+	(pt 616 160)
-	(pt 912 176)
+	(pt 792 160)
 )
 (connector
-	(pt 680 192)
+	(pt 616 176)
-	(pt 912 192)
+	(pt 808 176)
+)
+(connector
+	(pt 616 192)
+	(pt 856 192)
 	(bus)
 )
 (connector
-	(pt 680 208)
+	(pt 616 208)
-	(pt 912 208)
+	(pt 856 208)
 	(bus)
 )
 (connector
-	(pt 680 224)
+	(pt 616 224)
-	(pt 912 224)
+	(pt 856 224)
+	(bus)
+)
+(connector
+	(pt 856 288)
+	(pt 808 288)
+	(bus)
+)
+(connector
+	(pt 616 240)
+	(pt 808 240)
 	(bus)
 )
 (connector
 	(pt 808 240)
-	(pt 808 312)
+	(pt 808 288)
 	(bus)
 )
 (connector
-	(pt 808 312)
+	(pt 856 304)
-	(pt 912 312)
+	(pt 792 304)
+	(bus)
+)
+(connector
+	(pt 616 256)
+	(pt 792 256)
 	(bus)
 )
 (connector
 	(pt 792 256)
-	(pt 792 328)
+	(pt 792 304)
 	(bus)
 )
 (connector
-	(pt 792 328)
+	(pt 856 320)
-	(pt 912 328)
+	(pt 776 320)
+	(bus)
+)
+(connector
+	(pt 856 336)
+	(pt 760 336)
+	(bus)
+)
+(connector
+	(pt 616 272)
+	(pt 776 272)
 	(bus)
 )
 (connector
 	(pt 776 272)
-	(pt 776 344)
+	(pt 776 320)
 	(bus)
 )
 (connector
-	(pt 776 344)
+	(pt 616 288)
-	(pt 912 344)
+	(pt 760 288)
 	(bus)
 )
 (connector
 	(pt 760 288)
-	(pt 760 360)
+	(pt 760 336)
 	(bus)
 )
 (connector
-	(pt 760 360)
+	(pt 856 456)
-	(pt 912 360)
+	(pt 696 456)
 	(bus)
 )
 (connector
-	(pt 680 304)
+	(pt 616 304)
-	(pt 720 304)
+	(pt 696 304)
 	(bus)
 )
 (connector
-	(pt 720 304)
+	(pt 696 456)
-	(pt 720 432)
+	(pt 696 304)
 	(bus)
 )
 (connector
-	(pt 912 432)
+	(pt 464 160)
-	(pt 864 432)
+	(pt 416 160)
-	(bus)
 )
 (connector
-	(pt 720 432)
+	(pt 144 240)
-	(pt 816 432)
+	(pt 168 240)
-	(bus)
 )
+(connector
+	(pt 96 224)
+	(pt 168 224)
+)
+(connector
+	(pt 304 224)
+	(pt 464 224)
+)
+(connector
+	(pt 144 144)
+	(pt 168 144)
+)
+(connector
+	(pt 320 208)
+	(pt 320 128)
+)
+(connector
+	(pt 320 128)
+	(pt 304 128)
+)
+(connector
+	(pt 144 144)
+	(pt 144 240)
+)
+(connector
+	(pt 96 128)
+	(pt 168 128)
+)
+(connector
+	(pt 416 -160)
+	(pt 312 -160)
+)
+(connector
+	(pt 96 -160)
+	(pt 160 -160)
+)
+(connector
+	(pt 144 -48)
+	(pt 168 -48)
+)
+(connector
+	(pt 352 176)
+	(pt 352 -64)
+)
+(connector
+	(pt 352 -64)
+	(pt 304 -64)
+)
+(connector
+	(pt 96 -64)
+	(pt 168 -64)
+)
+(connector
+	(pt 144 48)
+	(pt 168 48)
+)
+(connector
+	(pt 336 192)
+	(pt 336 32)
+)
+(connector
+	(pt 336 32)
+	(pt 304 32)
+)
+(connector
+	(pt 144 48)
+	(pt 144 144)
+)
+(connector
+	(pt 96 32)
+	(pt 168 32)
+)
+(connector
+	(pt 416 -112)
+	(pt 144 -112)
+)
+(connector
+	(pt 416 -160)
+	(pt 416 -112)
+)
+(connector
+	(pt 416 -112)
+	(pt 416 160)
+)
+(connector
+	(pt 144 -112)
+	(pt 144 -48)
+)
+(connector
+	(pt 144 -48)
+	(pt 144 48)
+)
+(junction (pt 144 144))
+(junction (pt 144 -48))
+(junction (pt 144 48))
+(junction (pt 416 -112))

arkanoid_header.v

@@ -0,0 +1,117 @@
+`ifndef _arkanoid_header_
+`define _arkanoid_header_
+
+#(
+	// Parameters
+
+	parameter CELL_SIZE = 20,           // 1 cell has size of 20x20 pixels.
+	
+	parameter BALL_SIZE = 1,            // Game ball is a square of side 1 cell
+	parameter BALL_SPEED = 1,           // Number of cells per second
+	
+	parameter PLATFORM_WIDTH = 7,       // Game platform width
+	
+	parameter [3:0] BK_COLOR_R = 4'b1111,       // Red background
+	parameter [3:0] BK_COLOR_G = 4'b0000,
+	parameter [3:0] BK_COLOR_B = 4'b0000,
+	
+	parameter [3:0] STABLE_COLOR_R = 4'b0011,  // ??? color :)
+	parameter [3:0] STABLE_COLOR_G = 4'b1100,
+	parameter [3:0] STABLE_COLOR_B = 4'b0110,
+	
+	parameter [3:0] BALL_COLOR_R = 4'b0000,     // Blue ball
+	parameter [3:0] BALL_COLOR_G = 4'b0000,
+	parameter [3:0] BALL_COLOR_B = 4'b1111,
+	
+	parameter [3:0] PLATFORM_COLOR_R = 4'b1111, // Red platforms
+	parameter [3:0] PLATFORM_COLOR_G = 4'b0000,
+	parameter [3:0] PLATFORM_COLOR_B = 4'b0000
+)
+
+(
+	// Input Ports
+	input clk25MHz, // 25 MHz clock
+	input button1, button2, button3, button4, // 4 buttons on DE1 (left<->right for 2 players)
+
+	// Output Ports
+	output h_sync,
+	output v_sync,
+	output [3:0] red, green, blue, // Current pixel color (4096 colors = 12 bit)
+	output [6:0] hex0, hex1, hex2, hex3, // Digital tables on DE1
+	output [7:0] led
+);
+	
+	//////////////////////////////////////
+	// **** BEGIN OF MODULE HEADER **** //
+	//////////////////////////////////////
+	
+	// Output registers
+	reg [3:0] red_, green_, blue_;
+	reg [6:0] hex0_, hex1_, hex2_, hex3_;
+	reg [7:0] led_;
+	
+	// Constants depending on the global parameters
+	localparam SCREEN_WIDTH  = 640;                     // Horizontal screen resolution (in pixels)
+	localparam SCREEN_HEIGHT = 480;                     // Vertical screen resolution (in pixels)
+	localparam FIELD_WIDTH   = SCREEN_WIDTH/CELL_SIZE;  // Horizontal screen resolution (in cells)
+	localparam FIELD_HEIGHT  = SCREEN_HEIGHT/CELL_SIZE; // Vertical screen resolution (in cells)
+	localparam BALL_DELAY    = 25000000/BALL_SPEED;     // Clocks per 1 move
+	
+		
+	// 2D array of cells, stores game field state
+	reg [1:0] field[0:FIELD_HEIGHT-1][0:FIELD_WIDTH-1];
+	
+	// Possible cell values: (no comments)
+	localparam [1:0] EMPTY_CELL    = 2'b00;
+	localparam [1:0] STABLE_CELL   = 2'b11;
+	localparam [1:0] BALL_CELL     = 2'b01;
+	localparam [1:0] PLATFORM_CELL = 2'b10;
+	
+	// Current game state (0 - stopped, 1 - active)
+	reg game_state;
+	
+	// Player's scores
+	integer player1_score;
+	integer player2_score;
+	
+	// ATTENTION!!!
+	// All definitions behigh are in cells only.
+	//
+	
+	// Informaton about game ball
+	integer    ball_clock_counter; // Clocks counter
+	integer    ball_x, ball_y;     // Current coordinates
+	reg [1:0]  ball_direction;  // Current moving direction
+	
+	// Possible ball directions:
+	localparam [1:0] LEFT_UP    = 2'b00;
+	localparam [1:0] RIGHT_UP   = 2'b01;
+	localparam [1:0] LEFT_DOWN  = 2'b10;
+	localparam [1:0] RIGHT_DOWN = 2'b11;
+	
+	// Information about game platforms
+	integer platform1_position; // Current position (X axis, left border coordinate)
+	integer platform2_position;
+	
+	// VGA variables
+	integer h_counter;      // Horizontal pixel counter
+	integer v_counter;      // Vertical pixel counter
+	integer h_cell;         // Horizontal cell counter
+	integer v_cell;         // Vertical cell counter
+	reg [1:0] current_cell; // Current cell value
+	
+	// Loops variables
+	integer i, j;
+			
+	// Last buttons state
+	reg button1_state;
+	reg button2_state;
+	reg button3_state;
+	reg button4_state;
+		
+	
+	////////////////////////////////////
+	// **** END OF MODULE HEADER **** //
+	////////////////////////////////////
+	
+`endif // _arkanoid_header_	

db/abs_divider_kbg.tdf

@@ -0,0 +1,88 @@
+--abs_divider DEN_REPRESENTATION="SIGNED" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="SIGNED" SKIP_BITS=0 WIDTH_D=5 WIDTH_N=32 denominator numerator quotient remainder
+--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_lpm_divide 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2009 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION alt_u_div_k2f (denominator[4..0], numerator[31..0])
+RETURNS ( quotient[31..0], remainder[4..0]);
+FUNCTION lpm_abs_gq9 (data[4..0])
+RETURNS ( overflow, result[4..0]);
+FUNCTION lpm_abs_0s9 (data[31..0])
+RETURNS ( result[31..0]);
+
+--synthesis_resources = lut 246 
+SUBDESIGN abs_divider_kbg
+( 
+	denominator[4..0]	:	input;
+	numerator[31..0]	:	input;
+	quotient[31..0]	:	output;
+	remainder[4..0]	:	output;
+) 
+VARIABLE 
+	divider : alt_u_div_k2f;
+	my_abs_den : lpm_abs_gq9;
+	my_abs_num : lpm_abs_0s9;
+	compl_add_quot_result_int[32..0]	:	WIRE;
+	compl_add_quot_cin	:	WIRE;
+	compl_add_quot_dataa[31..0]	:	WIRE;
+	compl_add_quot_datab[31..0]	:	WIRE;
+	compl_add_quot_result[31..0]	:	WIRE;
+	compl_add_rem_result_int[5..0]	:	WIRE;
+	compl_add_rem_cin	:	WIRE;
+	compl_add_rem_dataa[4..0]	:	WIRE;
+	compl_add_rem_datab[4..0]	:	WIRE;
+	compl_add_rem_result[4..0]	:	WIRE;
+	diff_signs	: WIRE;
+	gnd_wire	: WIRE;
+	neg_quot[31..0]	: WIRE;
+	neg_rem[4..0]	: WIRE;
+	norm_den[4..0]	: WIRE;
+	norm_num[31..0]	: WIRE;
+	num_sign	: WIRE;
+	protect_quotient[31..0]	: WIRE;
+	protect_remainder[4..0]	: WIRE;
+	vcc_wire	: WIRE;
+
+BEGIN 
+	divider.denominator[] = norm_den[];
+	divider.numerator[] = norm_num[];
+	my_abs_den.data[] = denominator[];
+	my_abs_num.data[] = numerator[];
+	compl_add_quot_result_int[] = (compl_add_quot_dataa[], compl_add_quot_cin) + (compl_add_quot_datab[], compl_add_quot_cin);
+	compl_add_quot_result[] = compl_add_quot_result_int[32..1];
+	compl_add_quot_cin = vcc_wire;
+	compl_add_quot_dataa[] = (! protect_quotient[]);
+	compl_add_quot_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
+	compl_add_rem_result_int[] = (compl_add_rem_dataa[], compl_add_rem_cin) + (compl_add_rem_datab[], compl_add_rem_cin);
+	compl_add_rem_result[] = compl_add_rem_result_int[5..1];
+	compl_add_rem_cin = vcc_wire;
+	compl_add_rem_dataa[] = (! protect_remainder[]);
+	compl_add_rem_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
+	diff_signs = (numerator[31..31] $ denominator[4..4]);
+	gnd_wire = B"0";
+	neg_quot[] = compl_add_quot_result[];
+	neg_rem[] = compl_add_rem_result[];
+	norm_den[] = my_abs_den.result[];
+	norm_num[] = my_abs_num.result[];
+	num_sign = numerator[31..31];
+	protect_quotient[] = divider.quotient[];
+	protect_remainder[] = divider.remainder[];
+	quotient[] = ((protect_quotient[] & (! diff_signs)) # (neg_quot[] & diff_signs));
+	remainder[] = ((protect_remainder[] & (! num_sign)) # (neg_rem[] & num_sign));
+	vcc_wire = B"1";
+END;
+--VALID FILE

db/abs_divider_lbg.tdf

@@ -0,0 +1,88 @@
+--abs_divider DEN_REPRESENTATION="SIGNED" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="SIGNED" SKIP_BITS=0 WIDTH_D=6 WIDTH_N=32 denominator numerator quotient remainder
+--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_lpm_divide 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2009 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION alt_u_div_m2f (denominator[5..0], numerator[31..0])
+RETURNS ( quotient[31..0], remainder[5..0]);
+FUNCTION lpm_abs_hq9 (data[5..0])
+RETURNS ( overflow, result[5..0]);
+FUNCTION lpm_abs_0s9 (data[31..0])
+RETURNS ( overflow, result[31..0]);
+
+--synthesis_resources = lut 306 
+SUBDESIGN abs_divider_lbg
+( 
+	denominator[5..0]	:	input;
+	numerator[31..0]	:	input;
+	quotient[31..0]	:	output;
+	remainder[5..0]	:	output;
+) 
+VARIABLE 
+	divider : alt_u_div_m2f;
+	my_abs_den : lpm_abs_hq9;
+	my_abs_num : lpm_abs_0s9;
+	compl_add_quot_result_int[32..0]	:	WIRE;
+	compl_add_quot_cin	:	WIRE;
+	compl_add_quot_dataa[31..0]	:	WIRE;
+	compl_add_quot_datab[31..0]	:	WIRE;
+	compl_add_quot_result[31..0]	:	WIRE;
+	compl_add_rem_result_int[6..0]	:	WIRE;
+	compl_add_rem_cin	:	WIRE;
+	compl_add_rem_dataa[5..0]	:	WIRE;
+	compl_add_rem_datab[5..0]	:	WIRE;
+	compl_add_rem_result[5..0]	:	WIRE;
+	diff_signs	: WIRE;
+	gnd_wire	: WIRE;
+	neg_quot[31..0]	: WIRE;
+	neg_rem[5..0]	: WIRE;
+	norm_den[5..0]	: WIRE;
+	norm_num[31..0]	: WIRE;
+	num_sign	: WIRE;
+	protect_quotient[31..0]	: WIRE;
+	protect_remainder[5..0]	: WIRE;
+	vcc_wire	: WIRE;
+
+BEGIN 
+	divider.denominator[] = norm_den[];
+	divider.numerator[] = norm_num[];
+	my_abs_den.data[] = denominator[];
+	my_abs_num.data[] = numerator[];
+	compl_add_quot_result_int[] = (compl_add_quot_dataa[], compl_add_quot_cin) + (compl_add_quot_datab[], compl_add_quot_cin);
+	compl_add_quot_result[] = compl_add_quot_result_int[32..1];
+	compl_add_quot_cin = vcc_wire;
+	compl_add_quot_dataa[] = (! protect_quotient[]);
+	compl_add_quot_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
+	compl_add_rem_result_int[] = (compl_add_rem_dataa[], compl_add_rem_cin) + (compl_add_rem_datab[], compl_add_rem_cin);
+	compl_add_rem_result[] = compl_add_rem_result_int[6..1];
+	compl_add_rem_cin = vcc_wire;
+	compl_add_rem_dataa[] = (! protect_remainder[]);
+	compl_add_rem_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
+	diff_signs = (numerator[31..31] $ denominator[5..5]);
+	gnd_wire = B"0";
+	neg_quot[] = compl_add_quot_result[];
+	neg_rem[] = compl_add_rem_result[];
+	norm_den[] = my_abs_den.result[];
+	norm_num[] = my_abs_num.result[];
+	num_sign = numerator[31..31];
+	protect_quotient[] = divider.quotient[];
+	protect_remainder[] = divider.remainder[];
+	quotient[] = ((protect_quotient[] & (! diff_signs)) # (neg_quot[] & diff_signs));
+	remainder[] = ((protect_remainder[] & (! num_sign)) # (neg_rem[] & num_sign));
+	vcc_wire = B"1";
+END;
+--VALID FILE

db/add_sub_lkc.tdf

@@ -0,0 +1,43 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone II" LPM_DIRECTION="SUB" LPM_WIDTH=1 cout dataa datab result
+--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2009 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = 
+SUBDESIGN add_sub_lkc
+( 
+	cout	:	output;
+	dataa[0..0]	:	input;
+	datab[0..0]	:	input;
+	result[0..0]	:	output;
+) 
+VARIABLE 
+	carry_eqn[0..0]	: WIRE;
+	cin_wire	: WIRE;
+	datab_node[0..0]	: WIRE;
+	sum_eqn[0..0]	: WIRE;
+
+BEGIN 
+	carry_eqn[] = ( ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & cin_wire)));
+	cin_wire = B"1";
+	cout = carry_eqn[0..0];
+	datab_node[] = (! datab[]);
+	result[] = sum_eqn[];
+	sum_eqn[] = ( ((dataa[0..0] $ datab_node[0..0]) $ cin_wire));
+END;
+--VALID FILE

db/add_sub_mkc.tdf

@@ -0,0 +1,43 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone II" LPM_DIRECTION="SUB" LPM_WIDTH=2 cout dataa datab result
+--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2009 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = 
+SUBDESIGN add_sub_mkc
+( 
+	cout	:	output;
+	dataa[1..0]	:	input;
+	datab[1..0]	:	input;
+	result[1..0]	:	output;
+) 
+VARIABLE 
+	carry_eqn[1..0]	: WIRE;
+	cin_wire	: WIRE;
+	datab_node[1..0]	: WIRE;
+	sum_eqn[1..0]	: WIRE;
+
+BEGIN 
+	carry_eqn[] = ( ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & carry_eqn[0..0])), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & cin_wire)));
+	cin_wire = B"1";
+	cout = carry_eqn[1..1];
+	datab_node[] = (! datab[]);
+	result[] = sum_eqn[];
+	sum_eqn[] = ( ((dataa[1..1] $ datab_node[1..1]) $ carry_eqn[0..0]), ((dataa[0..0] $ datab_node[0..0]) $ cin_wire));
+END;
+--VALID FILE

db/lpm_abs_0s9.tdf

@@ -0,0 +1,41 @@
+--lpm_abs CARRY_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone II" IGNORE_CARRY_BUFFERS="OFF" LPM_WIDTH=32 data result
+--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2009 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION carry_sum (cin, sin)
+RETURNS ( cout, sout);
+
+--synthesis_resources = lut 32 
+SUBDESIGN lpm_abs_0s9
+( 
+	data[31..0]	:	input;
+	overflow	:	output;
+	result[31..0]	:	output;
+) 
+VARIABLE 
+	cs2a[31..0] : carry_sum;
+	result_tmp[31..0]	: WIRE;
+
+BEGIN 
+	cs2a[].cin = ( ((data[31..31] $ data[31..1]) & cs2a[30..0].cout), ((! data[0..0]) & data[31..31]));
+	cs2a[].sin = ( ((data[31..31] $ data[31..1]) $ cs2a[30..0].cout), data[0..0]);
+	overflow = (result_tmp[31..31] & data[31..31]);
+	result[] = result_tmp[];
+	result_tmp[] = ( cs2a[31..1].sout, data[0..0]);
+END;
+--VALID FILE

db/lpm_abs_gq9.tdf

@@ -0,0 +1,41 @@
+--lpm_abs CARRY_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone II" IGNORE_CARRY_BUFFERS="OFF" LPM_WIDTH=5 data result
+--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2009 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION carry_sum (cin, sin)
+RETURNS ( cout, sout);
+
+--synthesis_resources = lut 5 
+SUBDESIGN lpm_abs_gq9
+( 
+	data[4..0]	:	input;
+	overflow	:	output;
+	result[4..0]	:	output;
+) 
+VARIABLE 
+	cs1a[4..0] : carry_sum;
+	result_tmp[4..0]	: WIRE;
+
+BEGIN 
+	cs1a[].cin = ( ((data[4..4] $ data[4..1]) & cs1a[3..0].cout), ((! data[0..0]) & data[4..4]));
+	cs1a[].sin = ( ((data[4..4] $ data[4..1]) $ cs1a[3..0].cout), data[0..0]);
+	overflow = (result_tmp[4..4] & data[4..4]);
+	result[] = result_tmp[];
+	result_tmp[] = ( cs1a[4..1].sout, data[0..0]);
+END;
+--VALID FILE

db/lpm_abs_hq9.tdf

@@ -0,0 +1,41 @@
+--lpm_abs CARRY_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone II" IGNORE_CARRY_BUFFERS="OFF" LPM_WIDTH=6 data result
+--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2009 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION carry_sum (cin, sin)
+RETURNS ( cout, sout);
+
+--synthesis_resources = lut 6 
+SUBDESIGN lpm_abs_hq9
+( 
+	data[5..0]	:	input;
+	overflow	:	output;
+	result[5..0]	:	output;
+) 
+VARIABLE 
+	cs1a[5..0] : carry_sum;
+	result_tmp[5..0]	: WIRE;
+
+BEGIN 
+	cs1a[].cin = ( ((data[5..5] $ data[5..1]) & cs1a[4..0].cout), ((! data[0..0]) & data[5..5]));
+	cs1a[].sin = ( ((data[5..5] $ data[5..1]) $ cs1a[4..0].cout), data[0..0]);
+	overflow = (result_tmp[5..5] & data[5..5]);
+	result[] = result_tmp[];
+	result_tmp[] = ( cs1a[5..1].sout, data[0..0]);
+END;
+--VALID FILE

db/lpm_divide_7so.tdf

@@ -0,0 +1,42 @@
+--lpm_divide DEVICE_FAMILY="Cyclone II" LPM_DREPRESENTATION="SIGNED" LPM_NREPRESENTATION="SIGNED" LPM_REMAINDERPOSITIVE="FALSE" LPM_WIDTHD=5 LPM_WIDTHN=32 OPTIMIZE_FOR_SPEED=5 denom numer quotient CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
+--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_lpm_divide 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2009 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION abs_divider_kbg (denominator[4..0], numerator[31..0])
+RETURNS ( quotient[31..0], remainder[4..0]);
+
+--synthesis_resources = 
+SUBDESIGN lpm_divide_7so
+( 
+	denom[4..0]	:	input;
+	numer[31..0]	:	input;
+	quotient[31..0]	:	output;
+	remain[4..0]	:	output;
+) 
+VARIABLE 
+	divider : abs_divider_kbg;
+	numer_tmp[31..0]	: WIRE;
+
+BEGIN 
+	divider.denominator[] = denom[];
+	divider.numerator[] = numer_tmp[];
+	numer_tmp[] = numer[];
+	quotient[] = divider.quotient[];
+	remain[] = divider.remainder[];
+END;
+--VALID FILE

db/lpm_divide_8so.tdf

@@ -0,0 +1,42 @@
+--lpm_divide DEVICE_FAMILY="Cyclone II" LPM_DREPRESENTATION="SIGNED" LPM_NREPRESENTATION="SIGNED" LPM_REMAINDERPOSITIVE="FALSE" LPM_WIDTHD=6 LPM_WIDTHN=32 OPTIMIZE_FOR_SPEED=5 denom numer quotient CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
+--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_lpm_divide 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2009 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION abs_divider_lbg (denominator[5..0], numerator[31..0])
+RETURNS ( quotient[31..0], remainder[5..0]);
+
+--synthesis_resources = lut 306 
+SUBDESIGN lpm_divide_8so
+( 
+	denom[5..0]	:	input;
+	numer[31..0]	:	input;
+	quotient[31..0]	:	output;
+	remain[5..0]	:	output;
+) 
+VARIABLE 
+	divider : abs_divider_lbg;
+	numer_tmp[31..0]	: WIRE;
+
+BEGIN 
+	divider.denominator[] = denom[];
+	divider.numerator[] = numer_tmp[];
+	numer_tmp[] = numer[];
+	quotient[] = divider.quotient[];
+	remain[] = divider.remainder[];
+END;
+--VALID FILE

db/lpm_divide_ako.tdf

@@ -0,0 +1,42 @@
+--lpm_divide DEVICE_FAMILY="Cyclone II" LPM_DREPRESENTATION="SIGNED" LPM_NREPRESENTATION="SIGNED" LPM_REMAINDERPOSITIVE="FALSE" LPM_WIDTHD=5 LPM_WIDTHN=32 OPTIMIZE_FOR_SPEED=5 denom numer remain CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
+--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_lpm_divide 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2009 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION abs_divider_kbg (denominator[4..0], numerator[31..0])
+RETURNS ( quotient[31..0], remainder[4..0]);
+
+--synthesis_resources = lut 246 
+SUBDESIGN lpm_divide_ako
+( 
+	denom[4..0]	:	input;
+	numer[31..0]	:	input;
+	quotient[31..0]	:	output;
+	remain[4..0]	:	output;
+) 
+VARIABLE 
+	divider : abs_divider_kbg;
+	numer_tmp[31..0]	: WIRE;
+
+BEGIN 
+	divider.denominator[] = denom[];
+	divider.numerator[] = numer_tmp[];
+	numer_tmp[] = numer[];
+	quotient[] = divider.quotient[];
+	remain[] = divider.remainder[];
+END;
+--VALID FILE

db/myArkanoid.analyze_file.qmsg

@@ -0,0 +1,5 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus II " "Info: Running Quartus II Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 27 20:01:25 2012 " "Info: Processing started: Sun May 27 20:01:25 2012" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid --analyze_file=TotalScheme.bdf " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid --analyze_file=TotalScheme.bdf" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 0 s Quartus II " "Info: Quartus II Analyze Current File was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "188 " "Info: Peak virtual memory: 188 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 27 20:01:25 2012 " "Info: Processing ended: Sun May 27 20:01:25 2012" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

db/myArkanoid.asm.qmsg

@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 28 14:22:29 2012 " "Info: Processing started: Mon May 28 14:22:29 2012" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "219 " "Info: Peak virtual memory: 219 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 28 14:22:31 2012 " "Info: Processing ended: Mon May 28 14:22:31 2012" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

db/myArkanoid.cbx.xml

@@ -0,0 +1,11 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="myArkanoid">
+		<CBX_INST_ENTRY INSTANCE_NAME="|TotalScheme|Arkanoid:inst|lpm_divide:Div0" CBX_FILE_NAME="lpm_divide_7so.tdf"/>
+		<CBX_INST_ENTRY INSTANCE_NAME="|TotalScheme|Arkanoid:inst|lpm_divide:Div2" CBX_FILE_NAME="lpm_divide_8so.tdf"/>
+		<CBX_INST_ENTRY INSTANCE_NAME="|TotalScheme|Arkanoid:inst|lpm_divide:Mod1" CBX_FILE_NAME="lpm_divide_ako.tdf"/>
+		<CBX_INST_ENTRY INSTANCE_NAME="|TotalScheme|Arkanoid:inst|lpm_divide:Div1" CBX_FILE_NAME="lpm_divide_7so.tdf"/>
+		<CBX_INST_ENTRY INSTANCE_NAME="|TotalScheme|Arkanoid:inst|lpm_divide:Div3" CBX_FILE_NAME="lpm_divide_8so.tdf"/>
+		<CBX_INST_ENTRY INSTANCE_NAME="|TotalScheme|Arkanoid:inst|lpm_divide:Mod0" CBX_FILE_NAME="lpm_divide_ako.tdf"/>
+	</PROJECT>
+</LOG_ROOT>

db/myArkanoid.cmp.logdb

@@ -0,0 +1 @@
+v1

db/myArkanoid.db_info

@@ -0,0 +1,3 @@
+Quartus_Version = Version 9.1 Build 222 10/21/2009 SJ Full Version
+Version_Index = 184606208
+Creation_Time = Tue May 22 14:45:50 2012

db/myArkanoid.lpc.html

@@ -0,0 +1,114 @@
+<TABLE BORDER="1" cellspacing="1" cellpadding="2">
+<TR valign="middle" bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR valign="middle">
+<TD ALIGN="LEFT">inst5</TD>
+<TD ALIGN="LEFT">2</TD>
+<TD ALIGN="LEFT">0</TD>
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+</TR>
+<TR valign="middle">
+<TD ALIGN="LEFT">inst4</TD>
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+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+</TR>
+<TR valign="middle">
+<TD ALIGN="LEFT">inst3</TD>
+<TD ALIGN="LEFT">2</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">1</TD>
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+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+</TR>
+<TR valign="middle">
+<TD ALIGN="LEFT">inst2</TD>
+<TD ALIGN="LEFT">2</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">1</TD>
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+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+</TR>
+<TR valign="middle">
+<TD ALIGN="LEFT">inst1</TD>
+<TD ALIGN="LEFT">1</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">1</TD>
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+<TD ALIGN="LEFT">0</TD>
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+</TR>
+<TR valign="middle">
+<TD ALIGN="LEFT">inst</TD>
+<TD ALIGN="LEFT">5</TD>
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+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">50</TD>
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+<TD ALIGN="LEFT">0</TD>
+</TR>
+</TABLE>

db/myArkanoid.lpc.txt

@@ -0,0 +1,12 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; inst5     ; 2     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst4     ; 2     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst3     ; 2     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst2     ; 2     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst1     ; 1     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst      ; 5     ; 0              ; 0            ; 0              ; 50     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

db/myArkanoid.map.logdb

@@ -0,0 +1 @@
+v1

db/myArkanoid.map.qmsg

@@ -0,0 +1,43 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 28 14:18:56 2012 " "Info: Processing started: Mon May 28 14:18:56 2012" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "debouncer.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file debouncer.v" { { "Info" "ISGN_ENTITY_NAME" "1 Debouncer " "Info: Found entity 1: Debouncer" {  } { { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "totalscheme.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file totalscheme.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 TotalScheme " "Info: Found entity 1: TotalScheme" {  } { { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "arkanoid.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file arkanoid.v" { { "Info" "ISGN_ENTITY_NAME" "1 Arkanoid " "Info: Found entity 1: Arkanoid" {  } { { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "arkanoid_header.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file arkanoid_header.v" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "int_to_digital.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file int_to_digital.v" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga_sync.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file vga_sync.v" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clockdivider.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clockdivider.v" { { "Info" "ISGN_ENTITY_NAME" "1 ClockDivider " "Info: Found entity 1: ClockDivider" {  } { { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_TOP" "TotalScheme " "Info: Elaborating entity \"TotalScheme\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Arkanoid Arkanoid:inst " "Info: Elaborating entity \"Arkanoid\" for hierarchy \"Arkanoid:inst\"" {  } { { "TotalScheme.bdf" "inst" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { 128 464 616 352 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VERI_CANT_ANALYZE_CASE_STATEMENT" "int_to_digital.v(21) " "Warning (10762): Verilog HDL Case Statement warning at int_to_digital.v(21): can't check case statement for completeness because the case expression has too many possible states" {  } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 21 0 0 } }  } 0 10762 "Verilog HDL Case Statement warning at %1!s!: can't check case statement for completeness because the case expression has too many possible states" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VERI_2104_UNCONVERTED" "n1 IntToDigital int_to_digital.v(10) " "Warning (10776): Verilog HDL warning at int_to_digital.v(10): variable n1 in static task or function IntToDigital may have unintended latch behavior" {  } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 10 0 0 } }  } 0 10776 "Verilog HDL warning at %3!s!: variable %1!s! in static task or function %2!s! may have unintended latch behavior" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VERI_2104_UNCONVERTED" "n0 IntToDigital int_to_digital.v(10) " "Warning (10776): Verilog HDL warning at int_to_digital.v(10): variable n0 in static task or function IntToDigital may have unintended latch behavior" {  } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 10 0 0 } }  } 0 10776 "Verilog HDL warning at %3!s!: variable %1!s! in static task or function %2!s! may have unintended latch behavior" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VERI_2104_UNCONVERTED" "low IntToDigital int_to_digital.v(9) " "Warning (10776): Verilog HDL warning at int_to_digital.v(9): variable low in static task or function IntToDigital may have unintended latch behavior" {  } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 9 0 0 } }  } 0 10776 "Verilog HDL warning at %3!s!: variable %1!s! in static task or function %2!s! may have unintended latch behavior" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "IntToDigital.low\[6..0\] 0 int_to_digital.v(9) " "Warning (10030): Net \"IntToDigital.low\[6..0\]\" at int_to_digital.v(9) has no driver or initial value, using a default initial value '0'" {  } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 9 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "" 0 -1}
+{ "Info" "IVRFX_MULTI_DIMENSION_OBJECT_INFO" "field " "Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"field\" into its bus" {  } {  } 0 10008 "Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"%1!s!\" into its bus" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ClockDivider ClockDivider:inst1 " "Info: Elaborating entity \"ClockDivider\" for hierarchy \"ClockDivider:inst1\"" {  } { { "TotalScheme.bdf" "inst1" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -192 160 312 -128 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Debouncer Debouncer:inst2 " "Info: Elaborating entity \"Debouncer\" for hierarchy \"Debouncer:inst2\"" {  } { { "TotalScheme.bdf" "inst2" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -96 168 304 0 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ILPMS_INFERENCING_SUMMARY" "6 " "Info: Inferred 6 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div3 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div3\"" {  } { { "Arkanoid.v" "Div3" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 299 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div2 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div2\"" {  } { { "Arkanoid.v" "Div2" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 298 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Mod1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Mod1\"" {  } { { "int_to_digital.v" "Mod1" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div1\"" {  } { { "int_to_digital.v" "Div1" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Mod0 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Mod0\"" {  } { { "int_to_digital.v" "Mod0" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div0 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div0\"" {  } { { "int_to_digital.v" "Div0" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 -1}
+{ "Info" "ISGN_ELABORATION_HEADER" "Arkanoid:inst\|lpm_divide:Div3 " "Info: Elaborated megafunction instantiation \"Arkanoid:inst\|lpm_divide:Div3\"" {  } { { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 299 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "Arkanoid:inst\|lpm_divide:Div3 " "Info: Instantiated megafunction \"Arkanoid:inst\|lpm_divide:Div3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Info: Parameter \"LPM_WIDTHN\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 6 " "Info: Parameter \"LPM_WIDTHD\" = \"6\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION SIGNED " "Info: Parameter \"LPM_NREPRESENTATION\" = \"SIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION SIGNED " "Info: Parameter \"LPM_DREPRESENTATION\" = \"SIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT LPM_REMAINDERPOSITIVE=FALSE " "Info: Parameter \"LPM_HINT\" = \"LPM_REMAINDERPOSITIVE=FALSE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 299 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_8so.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_8so.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_8so " "Info: Found entity 1: lpm_divide_8so" {  } { { "db/lpm_divide_8so.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_divide_8so.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/abs_divider_lbg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/abs_divider_lbg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 abs_divider_lbg " "Info: Found entity 1: abs_divider_lbg" {  } { { "db/abs_divider_lbg.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/abs_divider_lbg.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_m2f.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_m2f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_m2f " "Info: Found entity 1: alt_u_div_m2f" {  } { { "db/alt_u_div_m2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_m2f.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_lkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_lkc " "Info: Found entity 1: add_sub_lkc" {  } { { "db/add_sub_lkc.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/add_sub_lkc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_mkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_mkc " "Info: Found entity 1: add_sub_mkc" {  } { { "db/add_sub_mkc.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/add_sub_mkc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_hq9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_hq9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_hq9 " "Info: Found entity 1: lpm_abs_hq9" {  } { { "db/lpm_abs_hq9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_hq9.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_0s9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_0s9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_0s9 " "Info: Found entity 1: lpm_abs_0s9" {  } { { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_ELABORATION_HEADER" "Arkanoid:inst\|lpm_divide:Mod1 " "Info: Elaborated megafunction instantiation \"Arkanoid:inst\|lpm_divide:Mod1\"" {  } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "Arkanoid:inst\|lpm_divide:Mod1 " "Info: Instantiated megafunction \"Arkanoid:inst\|lpm_divide:Mod1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Info: Parameter \"LPM_WIDTHN\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 5 " "Info: Parameter \"LPM_WIDTHD\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION SIGNED " "Info: Parameter \"LPM_NREPRESENTATION\" = \"SIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION SIGNED " "Info: Parameter \"LPM_DREPRESENTATION\" = \"SIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT LPM_REMAINDERPOSITIVE=FALSE " "Info: Parameter \"LPM_HINT\" = \"LPM_REMAINDERPOSITIVE=FALSE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_ako.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_ako.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_ako " "Info: Found entity 1: lpm_divide_ako" {  } { { "db/lpm_divide_ako.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_divide_ako.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/abs_divider_kbg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/abs_divider_kbg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 abs_divider_kbg " "Info: Found entity 1: abs_divider_kbg" {  } { { "db/abs_divider_kbg.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/abs_divider_kbg.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_k2f.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_k2f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_k2f " "Info: Found entity 1: alt_u_div_k2f" {  } { { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_gq9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_gq9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_gq9 " "Info: Found entity 1: lpm_abs_gq9" {  } { { "db/lpm_abs_gq9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_gq9.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_ELABORATION_HEADER" "Arkanoid:inst\|lpm_divide:Div1 " "Info: Elaborated megafunction instantiation \"Arkanoid:inst\|lpm_divide:Div1\"" {  } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "Arkanoid:inst\|lpm_divide:Div1 " "Info: Instantiated megafunction \"Arkanoid:inst\|lpm_divide:Div1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Info: Parameter \"LPM_WIDTHN\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 5 " "Info: Parameter \"LPM_WIDTHD\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION SIGNED " "Info: Parameter \"LPM_NREPRESENTATION\" = \"SIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION SIGNED " "Info: Parameter \"LPM_DREPRESENTATION\" = \"SIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT LPM_REMAINDERPOSITIVE=FALSE " "Info: Parameter \"LPM_HINT\" = \"LPM_REMAINDERPOSITIVE=FALSE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_7so.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_7so.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_7so " "Info: Found entity 1: lpm_divide_7so" {  } { { "db/lpm_divide_7so.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_divide_7so.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 2 " "Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Arkanoid:inst\|ball_direction~6 " "Info: Register \"Arkanoid:inst\|ball_direction~6\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Arkanoid:inst\|ball_direction~7 " "Info: Register \"Arkanoid:inst\|ball_direction~7\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "8037 " "Info: Implemented 8037 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "50 " "Info: Implemented 50 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "7982 " "Info: Implemented 7982 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "227 " "Info: Peak virtual memory: 227 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 28 14:21:58 2012 " "Info: Processing ended: Mon May 28 14:21:58 2012" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:03:02 " "Info: Elapsed time: 00:03:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:03:06 " "Info: Total CPU time (on all processors): 00:03:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

db/myArkanoid.map_bb.logdb

@@ -0,0 +1 @@
+v1

db/myArkanoid.rpp.qmsg

@@ -0,0 +1,4 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus II " "Info: Running Quartus II Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 26 12:34:36 2012 " "Info: Processing started: Sat May 26 12:34:36 2012" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_rpp myArkanoid -c myArkanoid --netlist_type=sgate " "Info: Command: quartus_rpp myArkanoid -c myArkanoid --netlist_type=sgate" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus II " "Info: Quartus II Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "143 " "Info: Peak virtual memory: 143 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 26 12:34:37 2012 " "Info: Processing ended: Sat May 26 12:34:37 2012" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}