Removed ignored files.
This commit is contained in:
Kirill Kirilenko
parent
c4df6cb1e2
commit
cbbfc3dbbe
142 changed files with 0 additions and 12408 deletions
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--abs_divider DEN_REPRESENTATION="SIGNED" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="SIGNED" SKIP_BITS=0 WIDTH_D=5 WIDTH_N=32 denominator numerator quotient remainder
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--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_lpm_divide 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ VERSION_END
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-- Copyright (C) 1991-2009 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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FUNCTION alt_u_div_k2f (denominator[4..0], numerator[31..0])
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RETURNS ( quotient[31..0], remainder[4..0]);
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FUNCTION lpm_abs_gq9 (data[4..0])
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RETURNS ( overflow, result[4..0]);
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FUNCTION lpm_abs_0s9 (data[31..0])
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RETURNS ( result[31..0]);
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--synthesis_resources = lut 246
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SUBDESIGN abs_divider_kbg
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(
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denominator[4..0] : input;
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numerator[31..0] : input;
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quotient[31..0] : output;
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remainder[4..0] : output;
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)
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VARIABLE
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divider : alt_u_div_k2f;
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my_abs_den : lpm_abs_gq9;
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my_abs_num : lpm_abs_0s9;
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compl_add_quot_result_int[32..0] : WIRE;
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compl_add_quot_cin : WIRE;
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compl_add_quot_dataa[31..0] : WIRE;
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compl_add_quot_datab[31..0] : WIRE;
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compl_add_quot_result[31..0] : WIRE;
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compl_add_rem_result_int[5..0] : WIRE;
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compl_add_rem_cin : WIRE;
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compl_add_rem_dataa[4..0] : WIRE;
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compl_add_rem_datab[4..0] : WIRE;
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compl_add_rem_result[4..0] : WIRE;
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diff_signs : WIRE;
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gnd_wire : WIRE;
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neg_quot[31..0] : WIRE;
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neg_rem[4..0] : WIRE;
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norm_den[4..0] : WIRE;
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norm_num[31..0] : WIRE;
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num_sign : WIRE;
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protect_quotient[31..0] : WIRE;
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protect_remainder[4..0] : WIRE;
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vcc_wire : WIRE;
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BEGIN
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divider.denominator[] = norm_den[];
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divider.numerator[] = norm_num[];
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my_abs_den.data[] = denominator[];
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my_abs_num.data[] = numerator[];
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compl_add_quot_result_int[] = (compl_add_quot_dataa[], compl_add_quot_cin) + (compl_add_quot_datab[], compl_add_quot_cin);
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compl_add_quot_result[] = compl_add_quot_result_int[32..1];
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compl_add_quot_cin = vcc_wire;
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compl_add_quot_dataa[] = (! protect_quotient[]);
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compl_add_quot_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
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compl_add_rem_result_int[] = (compl_add_rem_dataa[], compl_add_rem_cin) + (compl_add_rem_datab[], compl_add_rem_cin);
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compl_add_rem_result[] = compl_add_rem_result_int[5..1];
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compl_add_rem_cin = vcc_wire;
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compl_add_rem_dataa[] = (! protect_remainder[]);
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compl_add_rem_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
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diff_signs = (numerator[31..31] $ denominator[4..4]);
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gnd_wire = B"0";
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neg_quot[] = compl_add_quot_result[];
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neg_rem[] = compl_add_rem_result[];
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norm_den[] = my_abs_den.result[];
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norm_num[] = my_abs_num.result[];
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num_sign = numerator[31..31];
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protect_quotient[] = divider.quotient[];
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protect_remainder[] = divider.remainder[];
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quotient[] = ((protect_quotient[] & (! diff_signs)) # (neg_quot[] & diff_signs));
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remainder[] = ((protect_remainder[] & (! num_sign)) # (neg_rem[] & num_sign));
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vcc_wire = B"1";
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END;
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--VALID FILE
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@ -1,88 +0,0 @@
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--abs_divider DEN_REPRESENTATION="SIGNED" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="SIGNED" SKIP_BITS=0 WIDTH_D=6 WIDTH_N=32 denominator numerator quotient remainder
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--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_lpm_divide 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ VERSION_END
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-- Copyright (C) 1991-2009 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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||||||
-- Subscription Agreement, Altera MegaCore Function License
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||||||
-- Agreement, or other applicable license agreement, including,
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|
||||||
-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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FUNCTION alt_u_div_m2f (denominator[5..0], numerator[31..0])
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RETURNS ( quotient[31..0], remainder[5..0]);
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FUNCTION lpm_abs_hq9 (data[5..0])
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RETURNS ( overflow, result[5..0]);
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FUNCTION lpm_abs_0s9 (data[31..0])
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RETURNS ( overflow, result[31..0]);
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--synthesis_resources = lut 306
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SUBDESIGN abs_divider_lbg
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(
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denominator[5..0] : input;
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numerator[31..0] : input;
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quotient[31..0] : output;
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remainder[5..0] : output;
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)
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VARIABLE
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divider : alt_u_div_m2f;
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my_abs_den : lpm_abs_hq9;
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my_abs_num : lpm_abs_0s9;
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compl_add_quot_result_int[32..0] : WIRE;
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compl_add_quot_cin : WIRE;
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compl_add_quot_dataa[31..0] : WIRE;
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compl_add_quot_datab[31..0] : WIRE;
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compl_add_quot_result[31..0] : WIRE;
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compl_add_rem_result_int[6..0] : WIRE;
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compl_add_rem_cin : WIRE;
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compl_add_rem_dataa[5..0] : WIRE;
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compl_add_rem_datab[5..0] : WIRE;
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compl_add_rem_result[5..0] : WIRE;
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diff_signs : WIRE;
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gnd_wire : WIRE;
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neg_quot[31..0] : WIRE;
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neg_rem[5..0] : WIRE;
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norm_den[5..0] : WIRE;
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norm_num[31..0] : WIRE;
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num_sign : WIRE;
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protect_quotient[31..0] : WIRE;
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protect_remainder[5..0] : WIRE;
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vcc_wire : WIRE;
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BEGIN
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divider.denominator[] = norm_den[];
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divider.numerator[] = norm_num[];
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my_abs_den.data[] = denominator[];
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my_abs_num.data[] = numerator[];
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compl_add_quot_result_int[] = (compl_add_quot_dataa[], compl_add_quot_cin) + (compl_add_quot_datab[], compl_add_quot_cin);
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compl_add_quot_result[] = compl_add_quot_result_int[32..1];
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compl_add_quot_cin = vcc_wire;
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compl_add_quot_dataa[] = (! protect_quotient[]);
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compl_add_quot_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
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compl_add_rem_result_int[] = (compl_add_rem_dataa[], compl_add_rem_cin) + (compl_add_rem_datab[], compl_add_rem_cin);
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compl_add_rem_result[] = compl_add_rem_result_int[6..1];
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compl_add_rem_cin = vcc_wire;
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compl_add_rem_dataa[] = (! protect_remainder[]);
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compl_add_rem_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
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diff_signs = (numerator[31..31] $ denominator[5..5]);
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gnd_wire = B"0";
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neg_quot[] = compl_add_quot_result[];
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neg_rem[] = compl_add_rem_result[];
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norm_den[] = my_abs_den.result[];
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norm_num[] = my_abs_num.result[];
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num_sign = numerator[31..31];
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protect_quotient[] = divider.quotient[];
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protect_remainder[] = divider.remainder[];
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quotient[] = ((protect_quotient[] & (! diff_signs)) # (neg_quot[] & diff_signs));
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remainder[] = ((protect_remainder[] & (! num_sign)) # (neg_rem[] & num_sign));
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vcc_wire = B"1";
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END;
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--VALID FILE
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@ -1,43 +0,0 @@
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--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone II" LPM_DIRECTION="SUB" LPM_WIDTH=1 cout dataa datab result
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--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ VERSION_END
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-- Copyright (C) 1991-2009 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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|
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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||||||
-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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|
||||||
-- Subscription Agreement, Altera MegaCore Function License
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|
||||||
-- Agreement, or other applicable license agreement, including,
|
|
||||||
-- without limitation, that your use is for the sole purpose of
|
|
||||||
-- programming logic devices manufactured by Altera and sold by
|
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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--synthesis_resources =
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SUBDESIGN add_sub_lkc
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(
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cout : output;
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dataa[0..0] : input;
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datab[0..0] : input;
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result[0..0] : output;
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)
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VARIABLE
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carry_eqn[0..0] : WIRE;
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cin_wire : WIRE;
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datab_node[0..0] : WIRE;
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sum_eqn[0..0] : WIRE;
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BEGIN
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carry_eqn[] = ( ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & cin_wire)));
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cin_wire = B"1";
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cout = carry_eqn[0..0];
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datab_node[] = (! datab[]);
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result[] = sum_eqn[];
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sum_eqn[] = ( ((dataa[0..0] $ datab_node[0..0]) $ cin_wire));
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END;
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--VALID FILE
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--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone II" LPM_DIRECTION="SUB" LPM_WIDTH=2 cout dataa datab result
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--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ VERSION_END
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-- Copyright (C) 1991-2009 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
|
|
||||||
-- and other software and tools, and its AMPP partner logic
|
|
||||||
-- functions, and any output files from any of the foregoing
|
|
||||||
-- (including device programming or simulation files), and any
|
|
||||||
-- associated documentation or information are expressly subject
|
|
||||||
-- to the terms and conditions of the Altera Program License
|
|
||||||
-- Subscription Agreement, Altera MegaCore Function License
|
|
||||||
-- Agreement, or other applicable license agreement, including,
|
|
||||||
-- without limitation, that your use is for the sole purpose of
|
|
||||||
-- programming logic devices manufactured by Altera and sold by
|
|
||||||
-- Altera or its authorized distributors. Please refer to the
|
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||||||
-- applicable agreement for further details.
|
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--synthesis_resources =
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SUBDESIGN add_sub_mkc
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(
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cout : output;
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dataa[1..0] : input;
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datab[1..0] : input;
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result[1..0] : output;
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)
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VARIABLE
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carry_eqn[1..0] : WIRE;
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cin_wire : WIRE;
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datab_node[1..0] : WIRE;
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sum_eqn[1..0] : WIRE;
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BEGIN
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carry_eqn[] = ( ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & carry_eqn[0..0])), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & cin_wire)));
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cin_wire = B"1";
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cout = carry_eqn[1..1];
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datab_node[] = (! datab[]);
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result[] = sum_eqn[];
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sum_eqn[] = ( ((dataa[1..1] $ datab_node[1..1]) $ carry_eqn[0..0]), ((dataa[0..0] $ datab_node[0..0]) $ cin_wire));
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END;
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--VALID FILE
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File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
Binary file not shown.
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@ -1,41 +0,0 @@
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--lpm_abs CARRY_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone II" IGNORE_CARRY_BUFFERS="OFF" LPM_WIDTH=32 data result
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--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ VERSION_END
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-- Copyright (C) 1991-2009 Altera Corporation
|
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||||||
-- Your use of Altera Corporation's design tools, logic functions
|
|
||||||
-- and other software and tools, and its AMPP partner logic
|
|
||||||
-- functions, and any output files from any of the foregoing
|
|
||||||
-- (including device programming or simulation files), and any
|
|
||||||
-- associated documentation or information are expressly subject
|
|
||||||
-- to the terms and conditions of the Altera Program License
|
|
||||||
-- Subscription Agreement, Altera MegaCore Function License
|
|
||||||
-- Agreement, or other applicable license agreement, including,
|
|
||||||
-- without limitation, that your use is for the sole purpose of
|
|
||||||
-- programming logic devices manufactured by Altera and sold by
|
|
||||||
-- Altera or its authorized distributors. Please refer to the
|
|
||||||
-- applicable agreement for further details.
|
|
||||||
|
|
||||||
|
|
||||||
FUNCTION carry_sum (cin, sin)
|
|
||||||
RETURNS ( cout, sout);
|
|
||||||
|
|
||||||
--synthesis_resources = lut 32
|
|
||||||
SUBDESIGN lpm_abs_0s9
|
|
||||||
(
|
|
||||||
data[31..0] : input;
|
|
||||||
overflow : output;
|
|
||||||
result[31..0] : output;
|
|
||||||
)
|
|
||||||
VARIABLE
|
|
||||||
cs2a[31..0] : carry_sum;
|
|
||||||
result_tmp[31..0] : WIRE;
|
|
||||||
|
|
||||||
BEGIN
|
|
||||||
cs2a[].cin = ( ((data[31..31] $ data[31..1]) & cs2a[30..0].cout), ((! data[0..0]) & data[31..31]));
|
|
||||||
cs2a[].sin = ( ((data[31..31] $ data[31..1]) $ cs2a[30..0].cout), data[0..0]);
|
|
||||||
overflow = (result_tmp[31..31] & data[31..31]);
|
|
||||||
result[] = result_tmp[];
|
|
||||||
result_tmp[] = ( cs2a[31..1].sout, data[0..0]);
|
|
||||||
END;
|
|
||||||
--VALID FILE
|
|
||||||
|
|
@ -1,41 +0,0 @@
|
||||||
--lpm_abs CARRY_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone II" IGNORE_CARRY_BUFFERS="OFF" LPM_WIDTH=5 data result
|
|
||||||
--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ VERSION_END
|
|
||||||
|
|
||||||
|
|
||||||
-- Copyright (C) 1991-2009 Altera Corporation
|
|
||||||
-- Your use of Altera Corporation's design tools, logic functions
|
|
||||||
-- and other software and tools, and its AMPP partner logic
|
|
||||||
-- functions, and any output files from any of the foregoing
|
|
||||||
-- (including device programming or simulation files), and any
|
|
||||||
-- associated documentation or information are expressly subject
|
|
||||||
-- to the terms and conditions of the Altera Program License
|
|
||||||
-- Subscription Agreement, Altera MegaCore Function License
|
|
||||||
-- Agreement, or other applicable license agreement, including,
|
|
||||||
-- without limitation, that your use is for the sole purpose of
|
|
||||||
-- programming logic devices manufactured by Altera and sold by
|
|
||||||
-- Altera or its authorized distributors. Please refer to the
|
|
||||||
-- applicable agreement for further details.
|
|
||||||
|
|
||||||
|
|
||||||
FUNCTION carry_sum (cin, sin)
|
|
||||||
RETURNS ( cout, sout);
|
|
||||||
|
|
||||||
--synthesis_resources = lut 5
|
|
||||||
SUBDESIGN lpm_abs_gq9
|
|
||||||
(
|
|
||||||
data[4..0] : input;
|
|
||||||
overflow : output;
|
|
||||||
result[4..0] : output;
|
|
||||||
)
|
|
||||||
VARIABLE
|
|
||||||
cs1a[4..0] : carry_sum;
|
|
||||||
result_tmp[4..0] : WIRE;
|
|
||||||
|
|
||||||
BEGIN
|
|
||||||
cs1a[].cin = ( ((data[4..4] $ data[4..1]) & cs1a[3..0].cout), ((! data[0..0]) & data[4..4]));
|
|
||||||
cs1a[].sin = ( ((data[4..4] $ data[4..1]) $ cs1a[3..0].cout), data[0..0]);
|
|
||||||
overflow = (result_tmp[4..4] & data[4..4]);
|
|
||||||
result[] = result_tmp[];
|
|
||||||
result_tmp[] = ( cs1a[4..1].sout, data[0..0]);
|
|
||||||
END;
|
|
||||||
--VALID FILE
|
|
||||||
|
|
@ -1,41 +0,0 @@
|
||||||
--lpm_abs CARRY_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone II" IGNORE_CARRY_BUFFERS="OFF" LPM_WIDTH=6 data result
|
|
||||||
--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ VERSION_END
|
|
||||||
|
|
||||||
|
|
||||||
-- Copyright (C) 1991-2009 Altera Corporation
|
|
||||||
-- Your use of Altera Corporation's design tools, logic functions
|
|
||||||
-- and other software and tools, and its AMPP partner logic
|
|
||||||
-- functions, and any output files from any of the foregoing
|
|
||||||
-- (including device programming or simulation files), and any
|
|
||||||
-- associated documentation or information are expressly subject
|
|
||||||
-- to the terms and conditions of the Altera Program License
|
|
||||||
-- Subscription Agreement, Altera MegaCore Function License
|
|
||||||
-- Agreement, or other applicable license agreement, including,
|
|
||||||
-- without limitation, that your use is for the sole purpose of
|
|
||||||
-- programming logic devices manufactured by Altera and sold by
|
|
||||||
-- Altera or its authorized distributors. Please refer to the
|
|
||||||
-- applicable agreement for further details.
|
|
||||||
|
|
||||||
|
|
||||||
FUNCTION carry_sum (cin, sin)
|
|
||||||
RETURNS ( cout, sout);
|
|
||||||
|
|
||||||
--synthesis_resources = lut 6
|
|
||||||
SUBDESIGN lpm_abs_hq9
|
|
||||||
(
|
|
||||||
data[5..0] : input;
|
|
||||||
overflow : output;
|
|
||||||
result[5..0] : output;
|
|
||||||
)
|
|
||||||
VARIABLE
|
|
||||||
cs1a[5..0] : carry_sum;
|
|
||||||
result_tmp[5..0] : WIRE;
|
|
||||||
|
|
||||||
BEGIN
|
|
||||||
cs1a[].cin = ( ((data[5..5] $ data[5..1]) & cs1a[4..0].cout), ((! data[0..0]) & data[5..5]));
|
|
||||||
cs1a[].sin = ( ((data[5..5] $ data[5..1]) $ cs1a[4..0].cout), data[0..0]);
|
|
||||||
overflow = (result_tmp[5..5] & data[5..5]);
|
|
||||||
result[] = result_tmp[];
|
|
||||||
result_tmp[] = ( cs1a[5..1].sout, data[0..0]);
|
|
||||||
END;
|
|
||||||
--VALID FILE
|
|
||||||
|
|
@ -1,42 +0,0 @@
|
||||||
--lpm_divide DEVICE_FAMILY="Cyclone II" LPM_DREPRESENTATION="SIGNED" LPM_NREPRESENTATION="SIGNED" LPM_REMAINDERPOSITIVE="FALSE" LPM_WIDTHD=5 LPM_WIDTHN=32 OPTIMIZE_FOR_SPEED=5 denom numer quotient CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
|
|
||||||
--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_lpm_divide 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ VERSION_END
|
|
||||||
|
|
||||||
|
|
||||||
-- Copyright (C) 1991-2009 Altera Corporation
|
|
||||||
-- Your use of Altera Corporation's design tools, logic functions
|
|
||||||
-- and other software and tools, and its AMPP partner logic
|
|
||||||
-- functions, and any output files from any of the foregoing
|
|
||||||
-- (including device programming or simulation files), and any
|
|
||||||
-- associated documentation or information are expressly subject
|
|
||||||
-- to the terms and conditions of the Altera Program License
|
|
||||||
-- Subscription Agreement, Altera MegaCore Function License
|
|
||||||
-- Agreement, or other applicable license agreement, including,
|
|
||||||
-- without limitation, that your use is for the sole purpose of
|
|
||||||
-- programming logic devices manufactured by Altera and sold by
|
|
||||||
-- Altera or its authorized distributors. Please refer to the
|
|
||||||
-- applicable agreement for further details.
|
|
||||||
|
|
||||||
|
|
||||||
FUNCTION abs_divider_kbg (denominator[4..0], numerator[31..0])
|
|
||||||
RETURNS ( quotient[31..0], remainder[4..0]);
|
|
||||||
|
|
||||||
--synthesis_resources =
|
|
||||||
SUBDESIGN lpm_divide_7so
|
|
||||||
(
|
|
||||||
denom[4..0] : input;
|
|
||||||
numer[31..0] : input;
|
|
||||||
quotient[31..0] : output;
|
|
||||||
remain[4..0] : output;
|
|
||||||
)
|
|
||||||
VARIABLE
|
|
||||||
divider : abs_divider_kbg;
|
|
||||||
numer_tmp[31..0] : WIRE;
|
|
||||||
|
|
||||||
BEGIN
|
|
||||||
divider.denominator[] = denom[];
|
|
||||||
divider.numerator[] = numer_tmp[];
|
|
||||||
numer_tmp[] = numer[];
|
|
||||||
quotient[] = divider.quotient[];
|
|
||||||
remain[] = divider.remainder[];
|
|
||||||
END;
|
|
||||||
--VALID FILE
|
|
||||||
|
|
@ -1,42 +0,0 @@
|
||||||
--lpm_divide DEVICE_FAMILY="Cyclone II" LPM_DREPRESENTATION="SIGNED" LPM_NREPRESENTATION="SIGNED" LPM_REMAINDERPOSITIVE="FALSE" LPM_WIDTHD=6 LPM_WIDTHN=32 OPTIMIZE_FOR_SPEED=5 denom numer quotient CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
|
|
||||||
--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_lpm_divide 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ VERSION_END
|
|
||||||
|
|
||||||
|
|
||||||
-- Copyright (C) 1991-2009 Altera Corporation
|
|
||||||
-- Your use of Altera Corporation's design tools, logic functions
|
|
||||||
-- and other software and tools, and its AMPP partner logic
|
|
||||||
-- functions, and any output files from any of the foregoing
|
|
||||||
-- (including device programming or simulation files), and any
|
|
||||||
-- associated documentation or information are expressly subject
|
|
||||||
-- to the terms and conditions of the Altera Program License
|
|
||||||
-- Subscription Agreement, Altera MegaCore Function License
|
|
||||||
-- Agreement, or other applicable license agreement, including,
|
|
||||||
-- without limitation, that your use is for the sole purpose of
|
|
||||||
-- programming logic devices manufactured by Altera and sold by
|
|
||||||
-- Altera or its authorized distributors. Please refer to the
|
|
||||||
-- applicable agreement for further details.
|
|
||||||
|
|
||||||
|
|
||||||
FUNCTION abs_divider_lbg (denominator[5..0], numerator[31..0])
|
|
||||||
RETURNS ( quotient[31..0], remainder[5..0]);
|
|
||||||
|
|
||||||
--synthesis_resources = lut 306
|
|
||||||
SUBDESIGN lpm_divide_8so
|
|
||||||
(
|
|
||||||
denom[5..0] : input;
|
|
||||||
numer[31..0] : input;
|
|
||||||
quotient[31..0] : output;
|
|
||||||
remain[5..0] : output;
|
|
||||||
)
|
|
||||||
VARIABLE
|
|
||||||
divider : abs_divider_lbg;
|
|
||||||
numer_tmp[31..0] : WIRE;
|
|
||||||
|
|
||||||
BEGIN
|
|
||||||
divider.denominator[] = denom[];
|
|
||||||
divider.numerator[] = numer_tmp[];
|
|
||||||
numer_tmp[] = numer[];
|
|
||||||
quotient[] = divider.quotient[];
|
|
||||||
remain[] = divider.remainder[];
|
|
||||||
END;
|
|
||||||
--VALID FILE
|
|
||||||
|
|
@ -1,42 +0,0 @@
|
||||||
--lpm_divide DEVICE_FAMILY="Cyclone II" LPM_DREPRESENTATION="SIGNED" LPM_NREPRESENTATION="SIGNED" LPM_REMAINDERPOSITIVE="FALSE" LPM_WIDTHD=5 LPM_WIDTHN=32 OPTIMIZE_FOR_SPEED=5 denom numer remain CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
|
|
||||||
--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_abs 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_lpm_divide 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ VERSION_END
|
|
||||||
|
|
||||||
|
|
||||||
-- Copyright (C) 1991-2009 Altera Corporation
|
|
||||||
-- Your use of Altera Corporation's design tools, logic functions
|
|
||||||
-- and other software and tools, and its AMPP partner logic
|
|
||||||
-- functions, and any output files from any of the foregoing
|
|
||||||
-- (including device programming or simulation files), and any
|
|
||||||
-- associated documentation or information are expressly subject
|
|
||||||
-- to the terms and conditions of the Altera Program License
|
|
||||||
-- Subscription Agreement, Altera MegaCore Function License
|
|
||||||
-- Agreement, or other applicable license agreement, including,
|
|
||||||
-- without limitation, that your use is for the sole purpose of
|
|
||||||
-- programming logic devices manufactured by Altera and sold by
|
|
||||||
-- Altera or its authorized distributors. Please refer to the
|
|
||||||
-- applicable agreement for further details.
|
|
||||||
|
|
||||||
|
|
||||||
FUNCTION abs_divider_kbg (denominator[4..0], numerator[31..0])
|
|
||||||
RETURNS ( quotient[31..0], remainder[4..0]);
|
|
||||||
|
|
||||||
--synthesis_resources = lut 246
|
|
||||||
SUBDESIGN lpm_divide_ako
|
|
||||||
(
|
|
||||||
denom[4..0] : input;
|
|
||||||
numer[31..0] : input;
|
|
||||||
quotient[31..0] : output;
|
|
||||||
remain[4..0] : output;
|
|
||||||
)
|
|
||||||
VARIABLE
|
|
||||||
divider : abs_divider_kbg;
|
|
||||||
numer_tmp[31..0] : WIRE;
|
|
||||||
|
|
||||||
BEGIN
|
|
||||||
divider.denominator[] = denom[];
|
|
||||||
divider.numerator[] = numer_tmp[];
|
|
||||||
numer_tmp[] = numer[];
|
|
||||||
quotient[] = divider.quotient[];
|
|
||||||
remain[] = divider.remainder[];
|
|
||||||
END;
|
|
||||||
--VALID FILE
|
|
||||||
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|
|
@ -1,5 +0,0 @@
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus II " "Info: Running Quartus II Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 27 20:01:25 2012 " "Info: Processing started: Sun May 27 20:01:25 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid --analyze_file=TotalScheme.bdf " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid --analyze_file=TotalScheme.bdf" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 0 s Quartus II " "Info: Quartus II Analyze Current File was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "188 " "Info: Peak virtual memory: 188 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 27 20:01:25 2012 " "Info: Processing ended: Sun May 27 20:01:25 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
|
|
||||||
|
|
@ -1,6 +0,0 @@
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 28 14:22:29 2012 " "Info: Processing started: Mon May 28 14:22:29 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "219 " "Info: Peak virtual memory: 219 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 28 14:22:31 2012 " "Info: Processing ended: Mon May 28 14:22:31 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
|
|
||||||
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|
|
@ -1,11 +0,0 @@
|
||||||
<?xml version="1.0" ?>
|
|
||||||
<LOG_ROOT>
|
|
||||||
<PROJECT NAME="myArkanoid">
|
|
||||||
<CBX_INST_ENTRY INSTANCE_NAME="|TotalScheme|Arkanoid:inst|lpm_divide:Div0" CBX_FILE_NAME="lpm_divide_7so.tdf"/>
|
|
||||||
<CBX_INST_ENTRY INSTANCE_NAME="|TotalScheme|Arkanoid:inst|lpm_divide:Div2" CBX_FILE_NAME="lpm_divide_8so.tdf"/>
|
|
||||||
<CBX_INST_ENTRY INSTANCE_NAME="|TotalScheme|Arkanoid:inst|lpm_divide:Mod1" CBX_FILE_NAME="lpm_divide_ako.tdf"/>
|
|
||||||
<CBX_INST_ENTRY INSTANCE_NAME="|TotalScheme|Arkanoid:inst|lpm_divide:Div1" CBX_FILE_NAME="lpm_divide_7so.tdf"/>
|
|
||||||
<CBX_INST_ENTRY INSTANCE_NAME="|TotalScheme|Arkanoid:inst|lpm_divide:Div3" CBX_FILE_NAME="lpm_divide_8so.tdf"/>
|
|
||||||
<CBX_INST_ENTRY INSTANCE_NAME="|TotalScheme|Arkanoid:inst|lpm_divide:Mod0" CBX_FILE_NAME="lpm_divide_ako.tdf"/>
|
|
||||||
</PROJECT>
|
|
||||||
</LOG_ROOT>
|
|
||||||
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|
@ -1 +0,0 @@
|
||||||
v1
|
|
||||||
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|
@ -1,3 +0,0 @@
|
||||||
Quartus_Version = Version 9.1 Build 222 10/21/2009 SJ Full Version
|
|
||||||
Version_Index = 184606208
|
|
||||||
Creation_Time = Tue May 22 14:45:50 2012
|
|
||||||
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3022
db/myArkanoid.hif
3022
db/myArkanoid.hif
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|
|
@ -1,114 +0,0 @@
|
||||||
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
|
|
||||||
<TR valign="middle" bgcolor="#C0C0C0">
|
|
||||||
<TH>Hierarchy</TH>
|
|
||||||
<TH>Input</TH>
|
|
||||||
<TH>Constant Input</TH>
|
|
||||||
<TH>Unused Input</TH>
|
|
||||||
<TH>Floating Input</TH>
|
|
||||||
<TH>Output</TH>
|
|
||||||
<TH>Constant Output</TH>
|
|
||||||
<TH>Unused Output</TH>
|
|
||||||
<TH>Floating Output</TH>
|
|
||||||
<TH>Bidir</TH>
|
|
||||||
<TH>Constant Bidir</TH>
|
|
||||||
<TH>Unused Bidir</TH>
|
|
||||||
<TH>Input only Bidir</TH>
|
|
||||||
<TH>Output only Bidir</TH>
|
|
||||||
</TR>
|
|
||||||
<TR valign="middle">
|
|
||||||
<TD ALIGN="LEFT">inst5</TD>
|
|
||||||
<TD ALIGN="LEFT">2</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">1</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
</TR>
|
|
||||||
<TR valign="middle">
|
|
||||||
<TD ALIGN="LEFT">inst4</TD>
|
|
||||||
<TD ALIGN="LEFT">2</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">1</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
</TR>
|
|
||||||
<TR valign="middle">
|
|
||||||
<TD ALIGN="LEFT">inst3</TD>
|
|
||||||
<TD ALIGN="LEFT">2</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">1</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
</TR>
|
|
||||||
<TR valign="middle">
|
|
||||||
<TD ALIGN="LEFT">inst2</TD>
|
|
||||||
<TD ALIGN="LEFT">2</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">1</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
</TR>
|
|
||||||
<TR valign="middle">
|
|
||||||
<TD ALIGN="LEFT">inst1</TD>
|
|
||||||
<TD ALIGN="LEFT">1</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">1</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
</TR>
|
|
||||||
<TR valign="middle">
|
|
||||||
<TD ALIGN="LEFT">inst</TD>
|
|
||||||
<TD ALIGN="LEFT">5</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">50</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
<TD ALIGN="LEFT">0</TD>
|
|
||||||
</TR>
|
|
||||||
</TABLE>
|
|
||||||
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|
|
@ -1,12 +0,0 @@
|
||||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
||||||
; Legal Partition Candidates ;
|
|
||||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
|
||||||
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
|
|
||||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
|
||||||
; inst5 ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
|
||||||
; inst4 ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
|
||||||
; inst3 ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
|
||||||
; inst2 ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
|
||||||
; inst1 ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
|
||||||
; inst ; 5 ; 0 ; 0 ; 0 ; 50 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
|
||||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
|
||||||
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|
|
@ -1 +0,0 @@
|
||||||
v1
|
|
||||||
|
|
@ -1,43 +0,0 @@
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 28 14:18:56 2012 " "Info: Processing started: Mon May 28 14:18:56 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "debouncer.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file debouncer.v" { { "Info" "ISGN_ENTITY_NAME" "1 Debouncer " "Info: Found entity 1: Debouncer" { } { { "debouncer.v" "" { Text "G:/Verilog/Arkanoid2PDE1/debouncer.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "totalscheme.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file totalscheme.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 TotalScheme " "Info: Found entity 1: TotalScheme" { } { { "TotalScheme.bdf" "" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "arkanoid.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file arkanoid.v" { { "Info" "ISGN_ENTITY_NAME" "1 Arkanoid " "Info: Found entity 1: Arkanoid" { } { { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "arkanoid_header.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file arkanoid_header.v" { } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "int_to_digital.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file int_to_digital.v" { } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga_sync.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file vga_sync.v" { } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clockdivider.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clockdivider.v" { { "Info" "ISGN_ENTITY_NAME" "1 ClockDivider " "Info: Found entity 1: ClockDivider" { } { { "ClockDivider.v" "" { Text "G:/Verilog/Arkanoid2PDE1/ClockDivider.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_START_ELABORATION_TOP" "TotalScheme " "Info: Elaborating entity \"TotalScheme\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Arkanoid Arkanoid:inst " "Info: Elaborating entity \"Arkanoid\" for hierarchy \"Arkanoid:inst\"" { } { { "TotalScheme.bdf" "inst" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { 128 464 616 352 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
|
|
||||||
{ "Warning" "WVRFX_VERI_CANT_ANALYZE_CASE_STATEMENT" "int_to_digital.v(21) " "Warning (10762): Verilog HDL Case Statement warning at int_to_digital.v(21): can't check case statement for completeness because the case expression has too many possible states" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 21 0 0 } } } 0 10762 "Verilog HDL Case Statement warning at %1!s!: can't check case statement for completeness because the case expression has too many possible states" 0 0 "" 0 -1}
|
|
||||||
{ "Warning" "WVRFX_VERI_2104_UNCONVERTED" "n1 IntToDigital int_to_digital.v(10) " "Warning (10776): Verilog HDL warning at int_to_digital.v(10): variable n1 in static task or function IntToDigital may have unintended latch behavior" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 10 0 0 } } } 0 10776 "Verilog HDL warning at %3!s!: variable %1!s! in static task or function %2!s! may have unintended latch behavior" 0 0 "" 0 -1}
|
|
||||||
{ "Warning" "WVRFX_VERI_2104_UNCONVERTED" "n0 IntToDigital int_to_digital.v(10) " "Warning (10776): Verilog HDL warning at int_to_digital.v(10): variable n0 in static task or function IntToDigital may have unintended latch behavior" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 10 0 0 } } } 0 10776 "Verilog HDL warning at %3!s!: variable %1!s! in static task or function %2!s! may have unintended latch behavior" 0 0 "" 0 -1}
|
|
||||||
{ "Warning" "WVRFX_VERI_2104_UNCONVERTED" "low IntToDigital int_to_digital.v(9) " "Warning (10776): Verilog HDL warning at int_to_digital.v(9): variable low in static task or function IntToDigital may have unintended latch behavior" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 9 0 0 } } } 0 10776 "Verilog HDL warning at %3!s!: variable %1!s! in static task or function %2!s! may have unintended latch behavior" 0 0 "" 0 -1}
|
|
||||||
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "IntToDigital.low\[6..0\] 0 int_to_digital.v(9) " "Warning (10030): Net \"IntToDigital.low\[6..0\]\" at int_to_digital.v(9) has no driver or initial value, using a default initial value '0'" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IVRFX_MULTI_DIMENSION_OBJECT_INFO" "field " "Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"field\" into its bus" { } { } 0 10008 "Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"%1!s!\" into its bus" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ClockDivider ClockDivider:inst1 " "Info: Elaborating entity \"ClockDivider\" for hierarchy \"ClockDivider:inst1\"" { } { { "TotalScheme.bdf" "inst1" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -192 160 312 -128 "inst1" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Debouncer Debouncer:inst2 " "Info: Elaborating entity \"Debouncer\" for hierarchy \"Debouncer:inst2\"" { } { { "TotalScheme.bdf" "inst2" { Schematic "G:/Verilog/Arkanoid2PDE1/TotalScheme.bdf" { { -96 168 304 0 "inst2" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ILPMS_INFERENCING_SUMMARY" "6 " "Info: Inferred 6 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div3 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div3\"" { } { { "Arkanoid.v" "Div3" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 299 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div2 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div2\"" { } { { "Arkanoid.v" "Div2" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 298 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Mod1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Mod1\"" { } { { "int_to_digital.v" "Mod1" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div1\"" { } { { "int_to_digital.v" "Div1" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Mod0 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Mod0\"" { } { { "int_to_digital.v" "Mod0" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Arkanoid:inst\|Div0 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Arkanoid:inst\|Div0\"" { } { { "int_to_digital.v" "Div0" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } } } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_ELABORATION_HEADER" "Arkanoid:inst\|lpm_divide:Div3 " "Info: Elaborated megafunction instantiation \"Arkanoid:inst\|lpm_divide:Div3\"" { } { { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 299 -1 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "Arkanoid:inst\|lpm_divide:Div3 " "Info: Instantiated megafunction \"Arkanoid:inst\|lpm_divide:Div3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Info: Parameter \"LPM_WIDTHN\" = \"32\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 6 " "Info: Parameter \"LPM_WIDTHD\" = \"6\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION SIGNED " "Info: Parameter \"LPM_NREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION SIGNED " "Info: Parameter \"LPM_DREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT LPM_REMAINDERPOSITIVE=FALSE " "Info: Parameter \"LPM_HINT\" = \"LPM_REMAINDERPOSITIVE=FALSE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { { "Arkanoid.v" "" { Text "G:/Verilog/Arkanoid2PDE1/Arkanoid.v" 299 -1 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_8so.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_8so.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_8so " "Info: Found entity 1: lpm_divide_8so" { } { { "db/lpm_divide_8so.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_divide_8so.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/abs_divider_lbg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/abs_divider_lbg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 abs_divider_lbg " "Info: Found entity 1: abs_divider_lbg" { } { { "db/abs_divider_lbg.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/abs_divider_lbg.tdf" 28 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_m2f.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_m2f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_m2f " "Info: Found entity 1: alt_u_div_m2f" { } { { "db/alt_u_div_m2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_m2f.tdf" 26 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_lkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_lkc " "Info: Found entity 1: add_sub_lkc" { } { { "db/add_sub_lkc.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/add_sub_lkc.tdf" 22 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_mkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_mkc " "Info: Found entity 1: add_sub_mkc" { } { { "db/add_sub_mkc.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/add_sub_mkc.tdf" 22 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_hq9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_hq9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_hq9 " "Info: Found entity 1: lpm_abs_hq9" { } { { "db/lpm_abs_hq9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_hq9.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_0s9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_0s9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_0s9 " "Info: Found entity 1: lpm_abs_0s9" { } { { "db/lpm_abs_0s9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_0s9.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_ELABORATION_HEADER" "Arkanoid:inst\|lpm_divide:Mod1 " "Info: Elaborated megafunction instantiation \"Arkanoid:inst\|lpm_divide:Mod1\"" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "Arkanoid:inst\|lpm_divide:Mod1 " "Info: Instantiated megafunction \"Arkanoid:inst\|lpm_divide:Mod1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Info: Parameter \"LPM_WIDTHN\" = \"32\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 5 " "Info: Parameter \"LPM_WIDTHD\" = \"5\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION SIGNED " "Info: Parameter \"LPM_NREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION SIGNED " "Info: Parameter \"LPM_DREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT LPM_REMAINDERPOSITIVE=FALSE " "Info: Parameter \"LPM_HINT\" = \"LPM_REMAINDERPOSITIVE=FALSE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 19 -1 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_ako.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_ako.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_ako " "Info: Found entity 1: lpm_divide_ako" { } { { "db/lpm_divide_ako.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_divide_ako.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/abs_divider_kbg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/abs_divider_kbg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 abs_divider_kbg " "Info: Found entity 1: abs_divider_kbg" { } { { "db/abs_divider_kbg.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/abs_divider_kbg.tdf" 28 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_k2f.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_k2f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_k2f " "Info: Found entity 1: alt_u_div_k2f" { } { { "db/alt_u_div_k2f.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/alt_u_div_k2f.tdf" 26 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_gq9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_gq9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_gq9 " "Info: Found entity 1: lpm_abs_gq9" { } { { "db/lpm_abs_gq9.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_abs_gq9.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_ELABORATION_HEADER" "Arkanoid:inst\|lpm_divide:Div1 " "Info: Elaborated megafunction instantiation \"Arkanoid:inst\|lpm_divide:Div1\"" { } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "Arkanoid:inst\|lpm_divide:Div1 " "Info: Instantiated megafunction \"Arkanoid:inst\|lpm_divide:Div1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Info: Parameter \"LPM_WIDTHN\" = \"32\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 5 " "Info: Parameter \"LPM_WIDTHD\" = \"5\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION SIGNED " "Info: Parameter \"LPM_NREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION SIGNED " "Info: Parameter \"LPM_DREPRESENTATION\" = \"SIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT LPM_REMAINDERPOSITIVE=FALSE " "Info: Parameter \"LPM_HINT\" = \"LPM_REMAINDERPOSITIVE=FALSE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { { "int_to_digital.v" "" { Text "G:/Verilog/Arkanoid2PDE1/int_to_digital.v" 18 -1 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_7so.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_7so.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_7so " "Info: Found entity 1: lpm_divide_7so" { } { { "db/lpm_divide_7so.tdf" "" { Text "G:/Verilog/Arkanoid2PDE1/db/lpm_divide_7so.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 2 " "Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Arkanoid:inst\|ball_direction~6 " "Info: Register \"Arkanoid:inst\|ball_direction~6\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Arkanoid:inst\|ball_direction~7 " "Info: Register \"Arkanoid:inst\|ball_direction~7\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} } { } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "8037 " "Info: Implemented 8037 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "50 " "Info: Implemented 50 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "7982 " "Info: Implemented 7982 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "227 " "Info: Peak virtual memory: 227 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 28 14:21:58 2012 " "Info: Processing ended: Mon May 28 14:21:58 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:03:02 " "Info: Elapsed time: 00:03:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:03:06 " "Info: Total CPU time (on all processors): 00:03:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
|
|
||||||
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|
@ -1 +0,0 @@
|
||||||
v1
|
|
||||||
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|
@ -1,4 +0,0 @@
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus II " "Info: Running Quartus II Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 26 12:34:36 2012 " "Info: Processing started: Sat May 26 12:34:36 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_rpp myArkanoid -c myArkanoid --netlist_type=sgate " "Info: Command: quartus_rpp myArkanoid -c myArkanoid --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus II " "Info: Quartus II Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "143 " "Info: Peak virtual memory: 143 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 26 12:34:37 2012 " "Info: Processing ended: Sat May 26 12:34:37 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
|
|
||||||
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|
|
@ -1,6 +0,0 @@
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 22 17:24:20 2012 " "Info: Processing started: Tue May 22 17:24:20 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISDB_NO_SPECIFIED_VECTOR_FILE_FOUND" "G:/Verilog/Arkanoid2PDE1/myArkanoid.vwf " "Info: Can't find specified vector source file \"G:/Verilog/Arkanoid2PDE1/myArkanoid.vwf\"" { } { } 0 0 "Can't find specified vector source file \"%1!s!\"" 0 0 "" 0 -1}
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||||||
{ "Error" "ESDB_NO_VECTOR_FILE_FOUND" "G:/Verilog/Arkanoid2PDE1/myArkanoid.cvwf " "Error: No valid vector source file specified and default file \"G:/Verilog/Arkanoid2PDE1/myArkanoid.cvwf\" does not exist" { } { } 0 0 "No valid vector source file specified and default file \"%1!s!\" does not exist" 0 0 "" 0 -1}
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|
||||||
{ "Error" "EQEXE_ERROR_COUNT" "Simulator 1 0 s Quartus II " "Error: Quartus II Simulator was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "144 " "Error: Peak virtual memory: 144 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Error" "EQEXE_END_BANNER_TIME" "Tue May 22 17:24:20 2012 " "Error: Processing ended: Tue May 22 17:24:20 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Error: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Error: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
|
|
||||||
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Reference in a new issue