UltraCoder/Arkanoid2PDE1
Archived
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

First commit.

Browse source
This commit is contained in:
Kirill Kirilenko 2012-05-21 20:59:39 +04:00
parent 346ce1b2b5
commit fedfad1352
29 changed files with 7081 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

230
Arkanoid.bsf Normal file
View file

@ -0,0 +1,230 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 168 240)
(text "Arkanoid" (rect 5 0 47 12)(font "Arial" ))
(text "inst" (rect 8 208 25 220)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk50MHz" (rect 0 0 47 12)(font "Arial" ))
(text "clk50MHz" (rect 21 27 68 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "button1" (rect 0 0 36 12)(font "Arial" ))
(text "button1" (rect 21 43 57 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "button2" (rect 0 0 36 12)(font "Arial" ))
(text "button2" (rect 21 59 57 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "button3" (rect 0 0 36 12)(font "Arial" ))
(text "button3" (rect 21 75 57 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "button4" (rect 0 0 36 12)(font "Arial" ))
(text "button4" (rect 21 91 57 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
(port
(pt 152 32)
(output)
(text "h_sync" (rect 0 0 36 12)(font "Arial" ))
(text "h_sync" (rect 95 27 131 39)(font "Arial" ))
(line (pt 152 32)(pt 136 32)(line_width 1))
)
(port
(pt 152 48)
(output)
(text "v_sync" (rect 0 0 37 12)(font "Arial" ))
(text "v_sync" (rect 94 43 131 55)(font "Arial" ))
(line (pt 152 48)(pt 136 48)(line_width 1))
)
(port
(pt 152 64)
(output)
(text "red[3..0]" (rect 0 0 41 12)(font "Arial" ))
(text "red[3..0]" (rect 90 59 131 71)(font "Arial" ))
(line (pt 152 64)(pt 136 64)(line_width 3))
)
(port
(pt 152 80)
(output)
(text "green[3..0]" (rect 0 0 53 12)(font "Arial" ))
(text "green[3..0]" (rect 78 75 131 87)(font "Arial" ))
(line (pt 152 80)(pt 136 80)(line_width 3))
)
(port
(pt 152 96)
(output)
(text "blue[3..0]" (rect 0 0 46 12)(font "Arial" ))
(text "blue[3..0]" (rect 85 91 131 103)(font "Arial" ))
(line (pt 152 96)(pt 136 96)(line_width 3))
)
(port
(pt 152 112)
(output)
(text "num1[6..0]" (rect 0 0 53 12)(font "Arial" ))
(text "num1[6..0]" (rect 78 107 131 119)(font "Arial" ))
(line (pt 152 112)(pt 136 112)(line_width 3))
)
(port
(pt 152 128)
(output)
(text "num2[6..0]" (rect 0 0 53 12)(font "Arial" ))
(text "num2[6..0]" (rect 78 123 131 135)(font "Arial" ))
(line (pt 152 128)(pt 136 128)(line_width 3))
)
(port
(pt 152 144)
(output)
(text "num3[6..0]" (rect 0 0 53 12)(font "Arial" ))
(text "num3[6..0]" (rect 78 139 131 151)(font "Arial" ))
(line (pt 152 144)(pt 136 144)(line_width 3))
)
(port
(pt 152 160)
(output)
(text "num4[6..0]" (rect 0 0 53 12)(font "Arial" ))
(text "num4[6..0]" (rect 78 155 131 167)(font "Arial" ))
(line (pt 152 160)(pt 136 160)(line_width 3))
)
(port
(pt 152 176)
(output)
(text "led[7..0]" (rect 0 0 40 12)(font "Arial" ))
(text "led[7..0]" (rect 91 171 131 183)(font "Arial" ))
(line (pt 152 176)(pt 136 176)(line_width 3))
)
(parameter
"SCREEN_WIDTH"
"640"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"SCREEN_HEIGHT"
"480"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"CELL_SIZE"
"20"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"BALL_SIZE"
"1"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"BALL_SPEED"
"2"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PLATFORM_WIDTH"
"8"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PLATFORM_SPEED"
"1"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"BK_COLOR_R"
"1111"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"BK_COLOR_G"
"0000"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"BK_COLOR_B"
"0000"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"STABLE_COLOR_R"
"0011"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"STABLE_COLOR_G"
"1100"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"STABLE_COLOR_B"
"0110"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"BALL_COLOR_R"
"0000"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"BALL_COLOR_G"
"0000"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"BALL_COLOR_B"
"1111"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"PLATFORM_COLOR_R"
"1111"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"PLATFORM_COLOR_G"
"0000"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"PLATFORM_COLOR_B"
"0000"
""
(type "PARAMETER_UNSIGNED_BIN") )
(drawing
(rectangle (rect 16 16 136 208)(line_width 1))
)
(annotation_block (parameter)(rect 168 -64 268 16))
)

14
Arkanoid.qws Normal file
View file

@ -0,0 +1,14 @@
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
[ProjectWorkspace.Frames.ChildFrames.Document-0]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
DocPathName=TotalScheme.bdf
DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde}
IsChildFrameDetached=False
IsActiveChildFrame=True
ptn_Child1=StateMap

326
Arkanoid.v Normal file
View file

@ -0,0 +1,326 @@
module Arkanoid
#(
// Parameters
parameter SCREEN_WIDTH = 640, // Horizontal screen resolution (in pixels)
parameter SCREEN_HEIGHT = 480, // Vertical screen resolution (in pixels)
parameter CELL_SIZE = 20, // 1 cell has size of 20x20 pixels.
parameter BALL_SIZE = 1, // Game ball is a square of side 1 cell
parameter BALL_SPEED = 2, // Number of cells per second
parameter PLATFORM_WIDTH = 8, // Game platform width
parameter PLATFORM_SPEED = 1, // Number of cells per second
parameter [3:0] BK_COLOR_R = 4'b1111, // Red background
parameter [3:0] BK_COLOR_G = 4'b0000,
parameter [3:0] BK_COLOR_B = 4'b0000,
parameter [3:0] STABLE_COLOR_R = 4'b0011, // ??? color :)
parameter [3:0] STABLE_COLOR_G = 4'b1100,
parameter [3:0] STABLE_COLOR_B = 4'b0110,
parameter [3:0] BALL_COLOR_R = 4'b0000, // Blue ball
parameter [3:0] BALL_COLOR_G = 4'b0000,
parameter [3:0] BALL_COLOR_B = 4'b1111,
parameter [3:0] PLATFORM_COLOR_R = 4'b1111, // Red platforms
parameter [3:0] PLATFORM_COLOR_G = 4'b0000,
parameter [3:0] PLATFORM_COLOR_B = 4'b0000
)
(
// Input Ports
input clk50MHz, // 50 MHz clock on DE1
input button1, button2, button3, button4, // 4 buttons on DE1 (left<->right for 2 players)
// Output Ports
output h_sync,
output v_sync,
output [3:0] red, green, blue, // Current pixel color (4096 colors = 12 bit)
output [6:0] num1, num2, num3, num4, // Digital LED's on DE1
output [7:0] led
);
//////////////////////////////////////
// **** BEGIN OF MODULE HEADER **** //
//////////////////////////////////////
// Output registers
reg [3:0] red_, green_, blue_;
reg [6:0] num1_, num2_, num3_, num4_;
reg [7:0] led_;
localparam FIELD_WIDTH = SCREEN_WIDTH/CELL_SIZE; // Horizontal screen resolution (in cells)
localparam FIELD_HEIGHT = SCREEN_HEIGHT/CELL_SIZE; // Vertical screen resolution (in cells)
// VGA Module
localparam line = 799;
localparam frame = 524;
// 25 MHz clock
reg clk25MHz_;
wire clk25MHz;
// 2D array of cells, stores game field state
reg [1:0] field[0:FIELD_HEIGHT-1][0:FIELD_WIDTH-1];
// Possible cell values: (no comments)
localparam [1:0] EMPTY_CELL = 2'b00;
localparam [1:0] STABLE_CELL = 2'b11;
localparam [1:0] BALL_CELL = 2'b01;
localparam [1:0] PLATFORM_CELL = 2'b10;
// ATTENTION!!!
// All definitions below are in cells only.
//
// Informaton about game ball
integer ball_position_x; // Current coordinates
integer ball_position_y;
reg ball_state; // Current state (0 - stopped, 1 - moving)
reg [1:0] ball_direction; // Current moving direction
// Possible ball directions:
localparam [1:0] LEFT_UP = 2'b00;
localparam [1:0] RIGHT_UP = 2'b01;
localparam [1:0] LEFT_DOWN = 2'b10;
localparam [1:0] RIGHT_DOWN = 2'b11;
// Information about game platforms
integer platform1_position; // Current position (X axis, left border coordinate)
integer platform2_position;
// VGA variables
integer h_counter; // Horizontal pixel counter
integer v_counter; // Vertical pixel counter
integer h_cell; // Horizontal cell counter
integer v_cell; // Vertical cell counter
reg [1:0] current_cell; // Current cell value
// Loops variables
integer i, j;
// Last buttons state
reg button1_state;
reg button2_state;
reg button3_state;
reg button4_state;
////////////////////////////////////
// **** END OF MODULE HEADER **** //
////////////////////////////////////
// Initialization of all module variables
initial
begin
// Place ball to the center of the screen
ball_position_x = FIELD_WIDTH/2;
ball_position_y = FIELD_HEIGHT/2;
ball_state = 0;
// Place platforms at the center of the borders
platform1_position = (FIELD_WIDTH-PLATFORM_WIDTH)/2; // central position
platform2_position = platform1_position;
button1_state = 1'b0;
button2_state = 1'b0;
button3_state = 1'b0;
button4_state = 1'b0;
h_counter = 0;
v_counter = 0;
for (i = 0; i < FIELD_HEIGHT; i = i + 1)
for (j = 0; j< FIELD_WIDTH; j = j + 1)
field[i][j] = EMPTY_CELL;
field[ball_position_y][ball_position_x] = BALL_CELL;
num1_ = 7'b0000000;
num2_ = 7'b0000000;
num3_ = 7'b0000000;
num4_ = 7'b0000000;
end
// Frequency divider (50 MHz to 25 MHz, needed for VGA)
always @ (posedge clk50MHz)
begin
clk25MHz_ = ~clk25MHz_;
end
// VGA sync
always @ (posedge clk25MHz)
begin
if(h_counter == line)
h_counter <= 0;
else
h_counter <= (h_counter + 1);
end
always @ (posedge clk25MHz)
begin
if (v_counter == frame)
v_counter <= 0;
else if (h_counter == line)
v_counter <= (v_counter + 1);
end
always @ (posedge clk25MHz)
begin
if (button1 != button1_state)
begin
if (button1 == 1'b1)
begin
led_[7] = 1'b1;
led_[6] = 1'b1;
if (platform1_position > 0)
platform1_position = platform1_position - 1;
end
else
begin
led_[7] = 1'b0;
led_[6] = 1'b0;
end
button1_state = button1;
end
if (button2 != button2_state)
begin
if (button2 == 1'b1)
begin
led_[5] = 1'b1;
led_[4] = 1'b1;
if (platform1_position < FIELD_WIDTH-PLATFORM_WIDTH-1)
platform1_position = platform1_position + 1;
end
else
begin
led_[5] = 1'b0;
led_[4] = 1'b0;
end
button2_state = button2;
end
if (button3 != button3_state)
begin
if (button3 == 1'b1)
begin
led_[3] = 1'b1;
led_[2] = 1'b1;
if (platform2_position > 0)
platform2_position = platform2_position - 1;
end
else
begin
led_[3] = 1'b0;
led_[2] = 1'b0;
end
button3_state = button3;
end
if (button4 != button4_state)
begin
if (button4 == 1'b1)
begin
led_[1] = 1'b1;
led_[0] = 1'b1;
if (platform2_position < FIELD_WIDTH-PLATFORM_WIDTH-1)
platform2_position = platform2_position + 1;
end
else
begin
led_[1] = 1'b0;
led_[0] = 1'b0;
end
button4_state = button4;
end
for (i = 0; i < FIELD_WIDTH; i = i + 1)
begin
if ((i >= platform2_position) && (i <= platform2_position+PLATFORM_WIDTH))
field[0][i] = PLATFORM_CELL;
else
field[0][i] = EMPTY_CELL;
if ((i >= platform1_position) && (i <= platform1_position+PLATFORM_WIDTH))
field[FIELD_HEIGHT-1][i] = PLATFORM_CELL;
else
field[FIELD_HEIGHT-1][i] = EMPTY_CELL;
end
// VGA output
h_cell = (h_counter-143)/CELL_SIZE;
v_cell = (v_counter-34)/CELL_SIZE;
if ((v_counter > 34) && (v_counter < 514) && (h_counter > 143) && (h_counter < 783))
begin
current_cell = field[v_cell][h_cell];
case(current_cell)
EMPTY_CELL:
begin
red_ = BK_COLOR_R;
green_ = BK_COLOR_G;
blue_ = BK_COLOR_B;
end
STABLE_CELL:
begin
red_ = STABLE_COLOR_R;
green_ = STABLE_COLOR_G;
blue_ = STABLE_COLOR_B;
end
BALL_CELL:
begin
red_ = BALL_COLOR_R;
green_ = BALL_COLOR_G;
blue_ = BALL_COLOR_B;
end
PLATFORM_CELL:
begin
red_ = PLATFORM_COLOR_R;
green_ = PLATFORM_COLOR_G;
blue_ = PLATFORM_COLOR_B;
end
endcase
end
else
begin
red_ = 4'b0000;
green_ = 4'b0000;
blue_ = 4'b0000;
end
end
assign clk25MHz = clk25MHz_;
assign h_sync = ~((h_counter > 0) && (h_counter < 95));
assign v_sync = ~((v_counter == 0) || (v_counter == 1));
assign red = red_;
assign green = green_;
assign blue = blue_;
assign led = led_;
assign num1 = num1_;
assign num2 = num2_;
assign num3 = num3_;
assign num4 = num4_;
endmodule

328
Arkanoid.v.bak Normal file
View file

@ -0,0 +1,328 @@
module Arkanoid
#(
// Parameters
parameter SCREEN_WIDTH = 640, // Horizontal screen resolution (in pixels)
parameter SCREEN_HEIGHT = 480, // Vertical screen resolution (in pixels)
parameter CELL_SIZE = 20, // 1 cell has size of 20x20 pixels.
parameter BALL_SIZE = 1, // Game ball is a square of side 1 cell
parameter BALL_SPEED = 2, // Number of cells per second
parameter PLATFORM_WIDTH = 8, // Game platform width
parameter PLATFORM_SPEED = 1, // Number of cells per second
parameter [3:0] BK_COLOR_R = 4'b1111, // Red background
parameter [3:0] BK_COLOR_G = 4'b0000,
parameter [3:0] BK_COLOR_B = 4'b0000,
parameter [3:0] STABLE_COLOR_R = 4'b0011, // ??? color :)
parameter [3:0] STABLE_COLOR_G = 4'b1100,
parameter [3:0] STABLE_COLOR_B = 4'b0110,
parameter [3:0] BALL_COLOR_R = 4'b0000, // Blue ball
parameter [3:0] BALL_COLOR_G = 4'b0000,
parameter [3:0] BALL_COLOR_B = 4'b1111,
parameter [3:0] PLATFORM_COLOR_R = 4'b1111, // Red platforms
parameter [3:0] PLATFORM_COLOR_G = 4'b0000,
parameter [3:0] PLATFORM_COLOR_B = 4'b0000
)
(
// Input Ports
input clk50MHz, // 50 MHz clock on DE1
input button1, button2, button3, button4, // 4 buttons on DE1 (left<->right for 2 players)
// Output Ports
output h_sync,
output v_sync,
output [3:0] red, green, blue, // Current pixel color (4096 colors = 12 bit)
output [6:0] num1, num2, num3, num4, // Digital LED's on DE1
output [7:0] led
);
//////////////////////////////////////
// **** BEGIN OF MODULE HEADER **** //
//////////////////////////////////////
// Output registers
reg [3:0] red_, green_, blue_;
reg [6:0] num1_, num2_, num3_, num4_;
reg [7:0] led_;
localparam FIELD_WIDTH = SCREEN_WIDTH/CELL_SIZE; // Horizontal screen resolution (in cells)
localparam FIELD_HEIGHT = SCREEN_HEIGHT/CELL_SIZE; // Vertical screen resolution (in cells)
// VGA Module
localparam line = 799;
localparam frame = 524;
// 25 MHz clock
reg clk25MHz_;
wire clk25MHz;
// 2D array of cells, stores game field state
reg [1:0] field[0:FIELD_HEIGHT-1][0:FIELD_WIDTH-1];
// Possible cell values: (no comments)
localparam [1:0] EMPTY_CELL = 2'b00;
localparam [1:0] STABLE_CELL = 2'b11;
localparam [1:0] BALL_CELL = 2'b01;
localparam [1:0] PLATFORM_CELL = 2'b10;
// ATTENTION!!!
// All definitions below are in cells only.
//
// Informaton about game ball
integer ball_position_x; // Current coordinates
integer ball_position_y;
reg ball_state; // Current state (0 - stopped, 1 - moving)
reg [1:0] ball_direction; // Current moving direction
// Possible ball directions:
localparam [1:0] LEFT_UP = 2'b00;
localparam [1:0] RIGHT_UP = 2'b01;
localparam [1:0] LEFT_DOWN = 2'b10;
localparam [1:0] RIGHT_DOWN = 2'b11;
// Information about game platforms
integer platform1_position; // Current position (X axis, left border coordinate)
integer platform2_position;
// VGA variables
integer h_counter; // Horizontal pixel counter
integer v_counter; // Vertical pixel counter
integer h_cell; // Horizontal cell counter
integer v_cell; // Vertical cell counter
reg [1:0] current_cell; // Current cell value
// Loops variables
integer i, j;
// Last buttons state
reg button1_state;
reg button2_state;
reg button3_state;
reg button4_state;
////////////////////////////////////
// **** END OF MODULE HEADER **** //
////////////////////////////////////
// Initialization of all module variables
initial
begin
// Place ball to the center of the screen
ball_position_x = FIELD_WIDTH/2;
ball_position_y = FIELD_HEIGHT/2;
ball_state = 0;
// Place platforms at the center of the borders
platform1_position = (FIELD_WIDTH-PLATFORM_WIDTH)/2; // central position
platform2_position = platform1_position;
button1_state = 1'b0;
button2_state = 1'b0;
button3_state = 1'b0;
button4_state = 1'b0;
h_counter = 0;
v_counter = 0;
for (i = 0; i < FIELD_HEIGHT; i = i + 1)
for (j = 0; j< FIELD_WIDTH; j = j + 1)
field[i][j] = EMPTY_CELL;
field[ball_position_y][ball_position_x] = BALL_CELL;
// Print platforms
num1_ = 7'b0000000;
num2_ = 7'b0000000;
num3_ = 7'b0000000;
num4_ = 7'b0000000;
end
// Frequency divider (50 MHz to 25 MHz, needed for VGA)
always @ (posedge clk50MHz)
begin
clk25MHz_ = ~clk25MHz_;
end
// VGA sync
always @ (posedge clk25MHz)
begin
if(h_counter == line)
h_counter <= 0;
else
h_counter <= (h_counter + 1);
end
always @ (posedge clk25MHz)
begin
if (v_counter == frame)
v_counter <= 0;
else if (h_counter == line)
v_counter <= (v_counter + 1);
end
always @ (posedge clk25MHz)
begin
if (button1 != button1_state)
begin
if (button1 == 1'b1)
begin
led_[7] = 1'b1;
led_[6] = 1'b1;
if (platform1_position > 0)
platform1_position = platform1_position - 1;
end
else
begin
led_[7] = 1'b0;
led_[6] = 1'b0;
end
button1_state = button1;
end
if (button2 != button2_state)
begin
if (button2 == 1'b1)
begin
led_[5] = 1'b1;
led_[4] = 1'b1;
if (platform1_position < FIELD_WIDTH-PLATFORM_WIDTH-1)
platform1_position = platform1_position + 1;
end
else
begin
led_[5] = 1'b0;
led_[4] = 1'b0;
end
button2_state = button2;
end
if (button3 != button3_state)
begin
if (button3 == 1'b1)
begin
led_[3] = 1'b1;
led_[2] = 1'b1;
if (platform2_position > 0)
platform2_position = platform2_position - 1;
end
else
begin
led_[3] = 1'b0;
led_[2] = 1'b0;
end
button3_state = button3;
end
if (button4 != button4_state)
begin
if (button4 == 1'b1)
begin
led_[1] = 1'b1;
led_[0] = 1'b1;
if (platform2_position < FIELD_WIDTH-PLATFORM_WIDTH-1)
platform2_position = platform2_position + 1;
end
else
begin
led_[1] = 1'b0;
led_[0] = 1'b0;
end
button4_state = button4;
end
for (i = 0; i < FIELD_WIDTH; i = i + 1)
begin
if ((i >= platform2_position) && (i <= platform2_position+PLATFORM_WIDTH))
field[0][i] = PLATFORM_CELL;
else
field[0][i] = EMPTY_CELL;
if ((i >= platform1_position) && (i <= platform1_position+PLATFORM_WIDTH))
field[FIELD_HEIGHT-1][i] = PLATFORM_CELL;
else
field[FIELD_HEIGHT-1][i] = EMPTY_CELL;
end
// VGA output
h_cell = (h_counter-143)/CELL_SIZE;
v_cell = (v_counter-34)/CELL_SIZE;
if ((v_counter > 34) && (v_counter < 514) && (h_counter > 143) && (h_counter < 783))
begin
current_cell = field[v_cell][h_cell];
case(current_cell)
EMPTY_CELL:
begin
red_ = BK_COLOR_R;
green_ = BK_COLOR_G;
blue_ = BK_COLOR_B;
end
STABLE_CELL:
begin
red_ = STABLE_COLOR_R;
green_ = STABLE_COLOR_G;
blue_ = STABLE_COLOR_B;
end
BALL_CELL:
begin
red_ = BALL_COLOR_R;
green_ = BALL_COLOR_G;
blue_ = BALL_COLOR_B;
end
PLATFORM_CELL:
begin
red_ = PLATFORM_COLOR_R;
green_ = PLATFORM_COLOR_G;
blue_ = PLATFORM_COLOR_B;
end
endcase
end
else
begin
red_ = 4'b0000;
green_ = 4'b0000;
blue_ = 4'b0000;
end
end
assign clk25MHz = clk25MHz_;
assign h_sync = ~((h_counter > 0) && (h_counter < 95));
assign v_sync = ~((v_counter == 0) || (v_counter == 1));
assign red = red_;
assign green = green_;
assign blue = blue_;
assign led = led_;
assign num1 = num1_;
assign num2 = num2_;
assign num3 = num3_;
assign num4 = num4_;
endmodule

638
TotalScheme.bdf Normal file
View file

@ -0,0 +1,638 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
//#pragma file_not_in_maxplusii_format
(header "graphic" (version "1.3"))
(pin
(input)
(rect 296 152 464 168)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "clk_50MHz" (rect 5 0 58 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 92 12)(pt 117 12)(line_width 1))
(line (pt 92 4)(pt 117 4)(line_width 1))
(line (pt 121 8)(pt 168 8)(line_width 1))
(line (pt 92 12)(pt 92 4)(line_width 1))
(line (pt 117 4)(pt 121 8)(line_width 1))
(line (pt 117 12)(pt 121 8)(line_width 1))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 240 152 288 168))
)
(pin
(input)
(rect 296 168 464 184)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "button1" (rect 5 0 41 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 92 12)(pt 117 12)(line_width 1))
(line (pt 92 4)(pt 117 4)(line_width 1))
(line (pt 121 8)(pt 168 8)(line_width 1))
(line (pt 92 12)(pt 92 4)(line_width 1))
(line (pt 117 4)(pt 121 8)(line_width 1))
(line (pt 117 12)(pt 121 8)(line_width 1))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 240 168 296 184))
)
(pin
(input)
(rect 296 184 464 200)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "button2" (rect 5 0 41 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 92 12)(pt 117 12)(line_width 1))
(line (pt 92 4)(pt 117 4)(line_width 1))
(line (pt 121 8)(pt 168 8)(line_width 1))
(line (pt 92 12)(pt 92 4)(line_width 1))
(line (pt 117 4)(pt 121 8)(line_width 1))
(line (pt 117 12)(pt 121 8)(line_width 1))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 240 184 296 200))
)
(pin
(input)
(rect 296 200 464 216)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "button3" (rect 5 0 41 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 92 12)(pt 117 12)(line_width 1))
(line (pt 92 4)(pt 117 4)(line_width 1))
(line (pt 121 8)(pt 168 8)(line_width 1))
(line (pt 92 12)(pt 92 4)(line_width 1))
(line (pt 117 4)(pt 121 8)(line_width 1))
(line (pt 117 12)(pt 121 8)(line_width 1))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 240 200 296 216))
)
(pin
(input)
(rect 296 216 464 232)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "button4" (rect 5 0 41 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 92 12)(pt 117 12)(line_width 1))
(line (pt 92 4)(pt 117 4)(line_width 1))
(line (pt 121 8)(pt 168 8)(line_width 1))
(line (pt 92 12)(pt 92 4)(line_width 1))
(line (pt 117 4)(pt 121 8)(line_width 1))
(line (pt 117 12)(pt 121 8)(line_width 1))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 240 216 296 232))
)
(pin
(output)
(rect 912 304 1088 320)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "led1[6..0]" (rect 90 0 136 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8)(line_width 1))
(line (pt 52 4)(pt 78 4)(line_width 1))
(line (pt 52 12)(pt 78 12)(line_width 1))
(line (pt 52 12)(pt 52 4)(line_width 1))
(line (pt 78 4)(pt 82 8)(line_width 1))
(line (pt 82 8)(pt 78 12)(line_width 1))
(line (pt 78 12)(pt 82 8)(line_width 1))
)
(annotation_block (location)(rect 1320 320 1368 424))
)
(pin
(output)
(rect 912 320 1088 336)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "led2[6..0]" (rect 90 0 136 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8)(line_width 1))
(line (pt 52 4)(pt 78 4)(line_width 1))
(line (pt 52 12)(pt 78 12)(line_width 1))
(line (pt 52 12)(pt 52 4)(line_width 1))
(line (pt 78 4)(pt 82 8)(line_width 1))
(line (pt 82 8)(pt 78 12)(line_width 1))
(line (pt 78 12)(pt 82 8)(line_width 1))
)
(annotation_block (location)(rect 1248 336 1296 440))
)
(pin
(output)
(rect 912 336 1088 352)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "led3[6..0]" (rect 90 0 136 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8)(line_width 1))
(line (pt 52 4)(pt 78 4)(line_width 1))
(line (pt 52 12)(pt 78 12)(line_width 1))
(line (pt 52 12)(pt 52 4)(line_width 1))
(line (pt 78 4)(pt 82 8)(line_width 1))
(line (pt 82 8)(pt 78 12)(line_width 1))
(line (pt 78 12)(pt 82 8)(line_width 1))
)
(annotation_block (location)(rect 1176 352 1224 456))
)
(pin
(output)
(rect 912 352 1088 368)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "led4[6..0]" (rect 90 0 136 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8)(line_width 1))
(line (pt 52 4)(pt 78 4)(line_width 1))
(line (pt 52 12)(pt 78 12)(line_width 1))
(line (pt 52 12)(pt 52 4)(line_width 1))
(line (pt 78 4)(pt 82 8)(line_width 1))
(line (pt 82 8)(pt 78 12)(line_width 1))
(line (pt 78 12)(pt 82 8)(line_width 1))
)
(annotation_block (location)(rect 1104 368 1152 472))
)
(pin
(output)
(rect 912 152 1088 168)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "h_sync" (rect 90 0 126 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8)(line_width 1))
(line (pt 52 4)(pt 78 4)(line_width 1))
(line (pt 52 12)(pt 78 12)(line_width 1))
(line (pt 52 12)(pt 52 4)(line_width 1))
(line (pt 78 4)(pt 82 8)(line_width 1))
(line (pt 82 8)(pt 78 12)(line_width 1))
(line (pt 78 12)(pt 82 8)(line_width 1))
)
(annotation_block (location)(rect 1088 152 1144 168))
)
(pin
(output)
(rect 912 184 1088 200)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "red[3..0]" (rect 90 0 131 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8)(line_width 1))
(line (pt 52 4)(pt 78 4)(line_width 1))
(line (pt 52 12)(pt 78 12)(line_width 1))
(line (pt 52 12)(pt 52 4)(line_width 1))
(line (pt 78 4)(pt 82 8)(line_width 1))
(line (pt 82 8)(pt 78 12)(line_width 1))
(line (pt 78 12)(pt 82 8)(line_width 1))
)
(annotation_block (location)(rect 1248 200 1296 256))
)
(pin
(output)
(rect 912 200 1088 216)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "green[3..0]" (rect 90 0 143 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8)(line_width 1))
(line (pt 52 4)(pt 78 4)(line_width 1))
(line (pt 52 12)(pt 78 12)(line_width 1))
(line (pt 52 12)(pt 52 4)(line_width 1))
(line (pt 78 4)(pt 82 8)(line_width 1))
(line (pt 82 8)(pt 78 12)(line_width 1))
(line (pt 78 12)(pt 82 8)(line_width 1))
)
(annotation_block (location)(rect 1176 216 1232 272))
)
(pin
(output)
(rect 912 216 1088 232)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "blue[3..0]" (rect 90 0 136 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8)(line_width 1))
(line (pt 52 4)(pt 78 4)(line_width 1))
(line (pt 52 12)(pt 78 12)(line_width 1))
(line (pt 52 12)(pt 52 4)(line_width 1))
(line (pt 78 4)(pt 82 8)(line_width 1))
(line (pt 82 8)(pt 78 12)(line_width 1))
(line (pt 78 12)(pt 82 8)(line_width 1))
)
(annotation_block (location)(rect 1104 232 1160 288))
)
(pin
(output)
(rect 912 168 1088 184)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "v_sync" (rect 90 0 127 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8)(line_width 1))
(line (pt 52 4)(pt 78 4)(line_width 1))
(line (pt 52 12)(pt 78 12)(line_width 1))
(line (pt 52 12)(pt 52 4)(line_width 1))
(line (pt 78 4)(pt 82 8)(line_width 1))
(line (pt 82 8)(pt 78 12)(line_width 1))
(line (pt 78 12)(pt 82 8)(line_width 1))
)
(annotation_block (location)(rect 1088 168 1144 184))
)
(pin
(output)
(rect 912 424 1088 440)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "led[7..0]" (rect 90 0 130 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8)(line_width 1))
(line (pt 52 4)(pt 78 4)(line_width 1))
(line (pt 52 12)(pt 78 12)(line_width 1))
(line (pt 52 12)(pt 52 4)(line_width 1))
(line (pt 78 4)(pt 82 8)(line_width 1))
(line (pt 82 8)(pt 78 12)(line_width 1))
(line (pt 78 12)(pt 82 8)(line_width 1))
)
)
(symbol
(rect 528 128 680 352)
(text "Arkanoid" (rect 5 0 47 12)(font "Arial" ))
(text "inst" (rect 8 208 25 220)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk50MHz" (rect 0 0 47 12)(font "Arial" ))
(text "clk50MHz" (rect 21 27 68 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "button1" (rect 0 0 36 12)(font "Arial" ))
(text "button1" (rect 21 43 57 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "button2" (rect 0 0 36 12)(font "Arial" ))
(text "button2" (rect 21 59 57 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "button3" (rect 0 0 36 12)(font "Arial" ))
(text "button3" (rect 21 75 57 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "button4" (rect 0 0 36 12)(font "Arial" ))
(text "button4" (rect 21 91 57 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
(port
(pt 152 32)
(output)
(text "h_sync" (rect 0 0 36 12)(font "Arial" ))
(text "h_sync" (rect 95 27 131 39)(font "Arial" ))
(line (pt 152 32)(pt 136 32)(line_width 1))
)
(port
(pt 152 48)
(output)
(text "v_sync" (rect 0 0 37 12)(font "Arial" ))
(text "v_sync" (rect 94 43 131 55)(font "Arial" ))
(line (pt 152 48)(pt 136 48)(line_width 1))
)
(port
(pt 152 64)
(output)
(text "red[3..0]" (rect 0 0 41 12)(font "Arial" ))
(text "red[3..0]" (rect 90 59 131 71)(font "Arial" ))
(line (pt 152 64)(pt 136 64)(line_width 3))
)
(port
(pt 152 80)
(output)
(text "green[3..0]" (rect 0 0 53 12)(font "Arial" ))
(text "green[3..0]" (rect 78 75 131 87)(font "Arial" ))
(line (pt 152 80)(pt 136 80)(line_width 3))
)
(port
(pt 152 96)
(output)
(text "blue[3..0]" (rect 0 0 46 12)(font "Arial" ))
(text "blue[3..0]" (rect 85 91 131 103)(font "Arial" ))
(line (pt 152 96)(pt 136 96)(line_width 3))
)
(port
(pt 152 112)
(output)
(text "num1[6..0]" (rect 0 0 53 12)(font "Arial" ))
(text "num1[6..0]" (rect 78 107 131 119)(font "Arial" ))
(line (pt 152 112)(pt 136 112)(line_width 3))
)
(port
(pt 152 128)
(output)
(text "num2[6..0]" (rect 0 0 53 12)(font "Arial" ))
(text "num2[6..0]" (rect 78 123 131 135)(font "Arial" ))
(line (pt 152 128)(pt 136 128)(line_width 3))
)
(port
(pt 152 144)
(output)
(text "num3[6..0]" (rect 0 0 53 12)(font "Arial" ))
(text "num3[6..0]" (rect 78 139 131 151)(font "Arial" ))
(line (pt 152 144)(pt 136 144)(line_width 3))
)
(port
(pt 152 160)
(output)
(text "num4[6..0]" (rect 0 0 53 12)(font "Arial" ))
(text "num4[6..0]" (rect 78 155 131 167)(font "Arial" ))
(line (pt 152 160)(pt 136 160)(line_width 3))
)
(port
(pt 152 176)
(output)
(text "led[7..0]" (rect 0 0 40 12)(font "Arial" ))
(text "led[7..0]" (rect 91 171 131 183)(font "Arial" ))
(line (pt 152 176)(pt 136 176)(line_width 3))
)
(parameter
"SCREEN_WIDTH"
"640"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"SCREEN_HEIGHT"
"480"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"CELL_SIZE"
"20"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"BALL_SIZE"
"1"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"BALL_SPEED"
"2"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PLATFORM_WIDTH"
"8"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PLATFORM_SPEED"
"1"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"BK_COLOR_R"
"0000"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"BK_COLOR_G"
"0000"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"BK_COLOR_B"
"0000"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"STABLE_COLOR_R"
"0011"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"STABLE_COLOR_G"
"1100"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"STABLE_COLOR_B"
"0110"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"BALL_COLOR_R"
"0000"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"BALL_COLOR_G"
"0000"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"BALL_COLOR_B"
"1111"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"PLATFORM_COLOR_R"
"1111"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"PLATFORM_COLOR_G"
"0000"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"PLATFORM_COLOR_B"
"0000"
""
(type "PARAMETER_UNSIGNED_BIN") )
(parameter
"PLATFORM_HEIGHT"
"1"
""
(type "PARAMETER_SIGNED_DEC") )
(drawing
(rectangle (rect 16 16 136 208)(line_width 1))
)
(annotation_block (parameter)(rect 528 -168 760 128))
)
(symbol
(rect 816 416 864 448)
(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
(text "inst1" (rect 3 21 26 33)(font "Arial" ))
(port
(pt 0 16)
(input)
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 13 16)(line_width 1))
)
(port
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16)(line_width 1))
)
(drawing
(line (pt 13 25)(pt 13 7)(line_width 1))
(line (pt 13 7)(pt 31 16)(line_width 1))
(line (pt 13 25)(pt 31 16)(line_width 1))
(circle (rect 31 12 39 20)(line_width 1))
)
)
(connector
(pt 680 240)
(pt 808 240)
(bus)
)
(connector
(pt 680 256)
(pt 792 256)
(bus)
)
(connector
(pt 680 272)
(pt 776 272)
(bus)
)
(connector
(pt 680 288)
(pt 760 288)
(bus)
)
(connector
(pt 528 160)
(pt 464 160)
)
(connector
(pt 528 176)
(pt 464 176)
)
(connector
(pt 528 192)
(pt 464 192)
)
(connector
(pt 528 208)
(pt 464 208)
)
(connector
(pt 528 224)
(pt 464 224)
)
(connector
(pt 680 160)
(pt 912 160)
)
(connector
(pt 680 176)
(pt 912 176)
)
(connector
(pt 680 192)
(pt 912 192)
(bus)
)
(connector
(pt 680 208)
(pt 912 208)
(bus)
)
(connector
(pt 680 224)
(pt 912 224)
(bus)
)
(connector
(pt 808 240)
(pt 808 312)
(bus)
)
(connector
(pt 808 312)
(pt 912 312)
(bus)
)
(connector
(pt 792 256)
(pt 792 328)
(bus)
)
(connector
(pt 792 328)
(pt 912 328)
(bus)
)
(connector
(pt 776 272)
(pt 776 344)
(bus)
)
(connector
(pt 776 344)
(pt 912 344)
(bus)
)
(connector
(pt 760 288)
(pt 760 360)
(bus)
)
(connector
(pt 760 360)
(pt 912 360)
(bus)
)
(connector
(pt 680 304)
(pt 720 304)
(bus)
)
(connector
(pt 720 304)
(pt 720 432)
(bus)
)
(connector
(pt 912 432)
(pt 864 432)
(bus)
)
(connector
(pt 720 432)
(pt 816 432)
(bus)
)

130
myArkanoid.asm.rpt Normal file
View file

@ -0,0 +1,130 @@
Assembler report for myArkanoid
Mon May 21 19:54:38 2012
Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/myArkanoid.sof
6. Assembler Device Options: C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/myArkanoid.pof
7. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Mon May 21 19:54:38 2012 ;
; Revision Name ; myArkanoid ;
; Top-level Entity Name ; TotalScheme ;
; Family ; Cyclone II ;
; Device ; EP2C20F484C7 ;
+-----------------------+---------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+-----------------------------------------------------------------------------+----------+---------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------------+----------+---------------+
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Generate compressed bitstreams ; On ; On ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; Auto user code ; Off ; Off ;
; Use configuration device ; On ; On ;
; Configuration device ; Auto ; Auto ;
; Configuration device auto user code ; Off ; Off ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File start address ; 0 ; 0 ;
; Hexadecimal Output File count direction ; Up ; Up ;
; Release clears before tri-states ; Off ; Off ;
; Auto-restart configuration after error ; On ; On ;
; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ;
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
+-----------------------------------------------------------------------------+----------+---------------+
+---------------------------------------------------------------------+
; Assembler Generated Files ;
+---------------------------------------------------------------------+
; File Name ;
+---------------------------------------------------------------------+
; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/myArkanoid.sof ;
; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/myArkanoid.pof ;
+---------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------+
; Assembler Device Options: C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/myArkanoid.sof ;
+----------------+------------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+------------------------------------------------------------------------------+
; Device ; EP2C20F484C7 ;
; JTAG usercode ; 0xFFFFFFFF ;
; Checksum ; 0x002DEAD6 ;
+----------------+------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------+
; Assembler Device Options: C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/myArkanoid.pof ;
+--------------------+--------------------------------------------------------------------------+
; Option ; Setting ;
+--------------------+--------------------------------------------------------------------------+
; Device ; EPCS16 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x1DBBF76B ;
; Compression Ratio ; 2 ;
+--------------------+--------------------------------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 9.1 Build 222 10/21/2009 SJ Full Version
Info: Processing started: Mon May 21 19:54:35 2012
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 207 megabytes
Info: Processing ended: Mon May 21 19:54:38 2012
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:03

13
myArkanoid.cdf Normal file
View file

@ -0,0 +1,13 @@
/* Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EP2C20F484) Path("C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/") File("myArkanoid.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

1
myArkanoid.done Normal file
View file

@ -0,0 +1 @@
Mon May 21 19:54:46 2012

12
myArkanoid.dpf Normal file
View file

@ -0,0 +1,12 @@
<?xml version="1.0" encoding="UTF-8"?>
<pin_planner>
<pin_info>
</pin_info>
<buses>
</buses>
<group_file_association>
</group_file_association>
<pin_planner_file_specifies>
</pin_planner_file_specifies>
</pin_planner>

1699
myArkanoid.fit.rpt Normal file
View file

File diff suppressed because it is too large Load diff

6
myArkanoid.fit.smsg Normal file
View file

@ -0,0 +1,6 @@
Extra Info: Performing register packing on registers with non-logic cell location assignments
Extra Info: Completed register packing on registers with non-logic cell location assignments
Extra Info: Started Fast Input/Output/OE register processing
Extra Info: Finished Fast Input/Output/OE register processing
Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks

16
myArkanoid.fit.summary Normal file
View file

@ -0,0 +1,16 @@
Fitter Status : Successful - Mon May 21 19:54:32 2012
Quartus II Version : 9.1 Build 222 10/21/2009 SJ Full Version
Revision Name : myArkanoid
Top-level Entity Name : TotalScheme
Family : Cyclone II
Device : EP2C20F484C7
Timing Models : Final
Total logic elements : 1,806 / 18,752 ( 10 % )
Total combinational functions : 1,793 / 18,752 ( 10 % )
Dedicated logic registers : 151 / 18,752 ( < 1 % )
Total registers : 151
Total pins : 55 / 315 ( 17 % )
Total virtual pins : 0
Total memory bits : 0 / 239,616 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )

122
myArkanoid.flow.rpt Normal file
View file

@ -0,0 +1,122 @@
Flow report for myArkanoid
Mon May 21 19:54:43 2012
Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+------------------------------------------+
; Flow Status ; Successful - Mon May 21 19:54:41 2012 ;
; Quartus II Version ; 9.1 Build 222 10/21/2009 SJ Full Version ;
; Revision Name ; myArkanoid ;
; Top-level Entity Name ; TotalScheme ;
; Family ; Cyclone II ;
; Device ; EP2C20F484C7 ;
; Timing Models ; Final ;
; Met timing requirements ; Yes ;
; Total logic elements ; 1,806 / 18,752 ( 10 % ) ;
; Total combinational functions ; 1,793 / 18,752 ( 10 % ) ;
; Dedicated logic registers ; 151 / 18,752 ( < 1 % ) ;
; Total registers ; 151 ;
; Total pins ; 55 / 315 ( 17 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 239,616 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
+------------------------------------+------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 05/21/2012 19:54:04 ;
; Main task ; Compilation ;
; Revision Name ; myArkanoid ;
+-------------------+---------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+------------------------+-----------------------------------------------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+------------------------+-----------------------------------------------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 1097476773127.133761564404376 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; MISC_FILE ; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/myArkanoid/myArkanoid.dpf ; -- ; -- ; -- ;
; MISC_FILE ; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/myArkanoid.dpf ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; TotalScheme ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; TotalScheme ; Top ;
; TOP_LEVEL_ENTITY ; TotalScheme ; myArkanoid ; -- ; -- ;
+------------------------+-----------------------------------------------------------------------+---------------+-------------+------------+
+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:15 ; 1.0 ; 204 MB ; 00:00:16 ;
; Fitter ; 00:00:11 ; 1.2 ; 237 MB ; 00:00:13 ;
; Assembler ; 00:00:03 ; 1.0 ; 207 MB ; 00:00:04 ;
; Classic Timing Analyzer ; 00:00:02 ; 1.0 ; 151 MB ; 00:00:02 ;
; Total ; 00:00:31 ; -- ; -- ; 00:00:35 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+------------------------------------------------------------------------------------------+
; Flow OS Summary ;
+-------------------------+------------------+---------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+-------------------------+------------------+---------------+------------+----------------+
; Analysis & Synthesis ; ProGOLD-laptop ; Windows Vista ; 6.1 ; i686 ;
; Fitter ; ProGOLD-laptop ; Windows Vista ; 6.1 ; i686 ;
; Assembler ; ProGOLD-laptop ; Windows Vista ; 6.1 ; i686 ;
; Classic Timing Analyzer ; ProGOLD-laptop ; Windows Vista ; 6.1 ; i686 ;
+-------------------------+------------------+---------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid
quartus_fit --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid
quartus_asm --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid
quartus_tan --read_settings_files=off --write_settings_files=off myArkanoid -c myArkanoid --timing_analysis_only

435
myArkanoid.map.rpt Normal file
View file

@ -0,0 +1,435 @@
Analysis & Synthesis report for myArkanoid
Mon May 21 19:54:20 2012
Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Registers Removed During Synthesis
9. General Register Statistics
10. Inverted Register Statistics
11. Multiplexer Restructuring Statistics (Restructuring Performed)
12. Parameter Settings for User Entity Instance: Arkanoid:inst
13. Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Div0
14. Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Div1
15. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon May 21 19:54:20 2012 ;
; Quartus II Version ; 9.1 Build 222 10/21/2009 SJ Full Version ;
; Revision Name ; myArkanoid ;
; Top-level Entity Name ; TotalScheme ;
; Family ; Cyclone II ;
; Total logic elements ; 1,810 ;
; Total combinational functions ; 1,793 ;
; Dedicated logic registers ; 151 ;
; Total registers ; 151 ;
; Total pins ; 55 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP2C20F484C7 ; ;
; Top-level entity name ; TotalScheme ; myArkanoid ;
; Family name ; Cyclone II ; Stratix II ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
+----------------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 2 ;
; Maximum allowed ; 2 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2 processors ; 0.0% ;
+----------------------------+-------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------+
; TotalScheme.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/TotalScheme.bdf ;
; Arkanoid.v ; yes ; User Verilog HDL File ; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/Arkanoid.v ;
; lpm_divide.tdf ; yes ; Megafunction ; c:/quartus/quartus/libraries/megafunctions/lpm_divide.tdf ;
; db/lpm_divide_8so.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/db/lpm_divide_8so.tdf ;
; db/abs_divider_lbg.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/db/abs_divider_lbg.tdf ;
; db/alt_u_div_m2f.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/db/alt_u_div_m2f.tdf ;
; db/add_sub_lkc.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/db/add_sub_lkc.tdf ;
; db/add_sub_mkc.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/db/add_sub_mkc.tdf ;
; db/lpm_abs_hq9.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/db/lpm_abs_hq9.tdf ;
; db/lpm_abs_0s9.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/db/lpm_abs_0s9.tdf ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------+
+-----------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------------------------+
; Resource ; Usage ;
+---------------------------------------------+-------------------------+
; Estimated Total logic elements ; 1,810 ;
; ; ;
; Total combinational functions ; 1793 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 561 ;
; -- 3 input functions ; 452 ;
; -- <=2 input functions ; 780 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 1147 ;
; -- arithmetic mode ; 646 ;
; ; ;
; Total registers ; 151 ;
; -- Dedicated logic registers ; 151 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 55 ;
; Maximum fan-out node ; Arkanoid:inst|clk25MHz_ ;
; Maximum fan-out ; 151 ;
; Total fan-out ; 5397 ;
; Average fan-out ; 2.70 ;
+---------------------------------------------+-------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------+--------------+
; |TotalScheme ; 1793 (0) ; 151 (0) ; 0 ; 0 ; 0 ; 0 ; 55 ; 0 ; |TotalScheme ; work ;
; |Arkanoid:inst| ; 1793 (765) ; 151 (151) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst ; ;
; |lpm_divide:Div0| ; 475 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0 ; ;
; |lpm_divide_8so:auto_generated| ; 475 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated ; ;
; |abs_divider_lbg:divider| ; 475 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider ; ;
; |alt_u_div_m2f:divider| ; 433 (433) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider ; ;
; |lpm_abs_0s9:my_abs_num| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div0|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num ; ;
; |lpm_divide:Div1| ; 553 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1 ; ;
; |lpm_divide_8so:auto_generated| ; 553 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated ; ;
; |abs_divider_lbg:divider| ; 553 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider ; ;
; |alt_u_div_m2f:divider| ; 511 (511) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|alt_u_div_m2f:divider ; ;
; |lpm_abs_0s9:my_abs_num| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TotalScheme|Arkanoid:inst|lpm_divide:Div1|lpm_divide_8so:auto_generated|abs_divider_lbg:divider|lpm_abs_0s9:my_abs_num ; ;
+------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+----------------------------------------+
; Arkanoid:inst|green_[0..1] ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 2 ; ;
+---------------------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 151 ;
; Number of registers using Synchronous Clear ; 32 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 12 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; Arkanoid:inst|platform2_position[3] ; 2 ;
; Arkanoid:inst|platform2_position[2] ; 2 ;
; Arkanoid:inst|platform1_position[2] ; 2 ;
; Arkanoid:inst|platform1_position[3] ; 2 ;
; Total number of inverted registers = 4 ; ;
+----------------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+
; 3:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; No ; |TotalScheme|Arkanoid:inst|platform1_position ;
; 3:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; No ; |TotalScheme|Arkanoid:inst|platform2_position ;
; 4:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; No ; |TotalScheme|Arkanoid:inst|platform1_position ;
; 4:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; No ; |TotalScheme|Arkanoid:inst|platform2_position ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+
+------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Arkanoid:inst ;
+------------------+-------+---------------------------------+
; Parameter Name ; Value ; Type ;
+------------------+-------+---------------------------------+
; SCREEN_WIDTH ; 640 ; Signed Integer ;
; SCREEN_HEIGHT ; 480 ; Signed Integer ;
; CELL_SIZE ; 20 ; Signed Integer ;
; BALL_SIZE ; 1 ; Signed Integer ;
; BALL_SPEED ; 2 ; Signed Integer ;
; PLATFORM_WIDTH ; 8 ; Signed Integer ;
; PLATFORM_SPEED ; 1 ; Signed Integer ;
; BK_COLOR_R ; 0000 ; Unsigned Binary ;
; BK_COLOR_G ; 0000 ; Unsigned Binary ;
; BK_COLOR_B ; 0000 ; Unsigned Binary ;
; STABLE_COLOR_R ; 0011 ; Unsigned Binary ;
; STABLE_COLOR_G ; 1100 ; Unsigned Binary ;
; STABLE_COLOR_B ; 0110 ; Unsigned Binary ;
; BALL_COLOR_R ; 0000 ; Unsigned Binary ;
; BALL_COLOR_G ; 0000 ; Unsigned Binary ;
; BALL_COLOR_B ; 1111 ; Unsigned Binary ;
; PLATFORM_COLOR_R ; 1111 ; Unsigned Binary ;
; PLATFORM_COLOR_G ; 0000 ; Unsigned Binary ;
; PLATFORM_COLOR_B ; 0000 ; Unsigned Binary ;
+------------------+-------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Div0 ;
+------------------------+----------------+--------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+----------------+--------------------------------------+
; LPM_WIDTHN ; 32 ; Untyped ;
; LPM_WIDTHD ; 6 ; Untyped ;
; LPM_NREPRESENTATION ; SIGNED ; Untyped ;
; LPM_DREPRESENTATION ; SIGNED ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; LPM_REMAINDERPOSITIVE ; FALSE ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; CBXI_PARAMETER ; lpm_divide_8so ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+----------------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: Arkanoid:inst|lpm_divide:Div1 ;
+------------------------+----------------+--------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+----------------+--------------------------------------+
; LPM_WIDTHN ; 32 ; Untyped ;
; LPM_WIDTHD ; 6 ; Untyped ;
; LPM_NREPRESENTATION ; SIGNED ; Untyped ;
; LPM_DREPRESENTATION ; SIGNED ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; LPM_REMAINDERPOSITIVE ; FALSE ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; CBXI_PARAMETER ; lpm_divide_8so ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+----------------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.1 Build 222 10/21/2009 SJ Full Version
Info: Processing started: Mon May 21 19:54:04 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Found 1 design units, including 1 entities, in source file totalscheme.bdf
Info: Found entity 1: TotalScheme
Info: Found 1 design units, including 1 entities, in source file arkanoid.v
Info: Found entity 1: Arkanoid
Info: Elaborating entity "TotalScheme" for the top level hierarchy
Info: Elaborating entity "Arkanoid" for hierarchy "Arkanoid:inst"
Warning (10036): Verilog HDL or VHDL warning at Arkanoid.v(82): object "ball_state" assigned a value but never read
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "field" into its bus
Info: Inferred 2 megafunctions from design logic
Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Arkanoid:inst|Div0"
Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Arkanoid:inst|Div1"
Info: Elaborated megafunction instantiation "Arkanoid:inst|lpm_divide:Div0"
Info: Instantiated megafunction "Arkanoid:inst|lpm_divide:Div0" with the following parameter:
Info: Parameter "LPM_WIDTHN" = "32"
Info: Parameter "LPM_WIDTHD" = "6"
Info: Parameter "LPM_NREPRESENTATION" = "SIGNED"
Info: Parameter "LPM_DREPRESENTATION" = "SIGNED"
Info: Parameter "LPM_HINT" = "LPM_REMAINDERPOSITIVE=FALSE"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_8so.tdf
Info: Found entity 1: lpm_divide_8so
Info: Found 1 design units, including 1 entities, in source file db/abs_divider_lbg.tdf
Info: Found entity 1: abs_divider_lbg
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_m2f.tdf
Info: Found entity 1: alt_u_div_m2f
Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf
Info: Found entity 1: add_sub_lkc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf
Info: Found entity 1: add_sub_mkc
Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_hq9.tdf
Info: Found entity 1: lpm_abs_hq9
Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_0s9.tdf
Info: Found entity 1: lpm_abs_0s9
Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "green[1]" is stuck at GND
Warning (13410): Pin "green[0]" is stuck at GND
Warning (13410): Pin "led1[6]" is stuck at GND
Warning (13410): Pin "led1[5]" is stuck at GND
Warning (13410): Pin "led1[4]" is stuck at GND
Warning (13410): Pin "led1[3]" is stuck at GND
Warning (13410): Pin "led1[2]" is stuck at GND
Warning (13410): Pin "led1[1]" is stuck at GND
Warning (13410): Pin "led1[0]" is stuck at GND
Warning (13410): Pin "led2[6]" is stuck at GND
Warning (13410): Pin "led2[5]" is stuck at GND
Warning (13410): Pin "led2[4]" is stuck at GND
Warning (13410): Pin "led2[3]" is stuck at GND
Warning (13410): Pin "led2[2]" is stuck at GND
Warning (13410): Pin "led2[1]" is stuck at GND
Warning (13410): Pin "led2[0]" is stuck at GND
Warning (13410): Pin "led3[6]" is stuck at GND
Warning (13410): Pin "led3[5]" is stuck at GND
Warning (13410): Pin "led3[4]" is stuck at GND
Warning (13410): Pin "led3[3]" is stuck at GND
Warning (13410): Pin "led3[2]" is stuck at GND
Warning (13410): Pin "led3[1]" is stuck at GND
Warning (13410): Pin "led3[0]" is stuck at GND
Warning (13410): Pin "led4[6]" is stuck at GND
Warning (13410): Pin "led4[5]" is stuck at GND
Warning (13410): Pin "led4[4]" is stuck at GND
Warning (13410): Pin "led4[3]" is stuck at GND
Warning (13410): Pin "led4[2]" is stuck at GND
Warning (13410): Pin "led4[1]" is stuck at GND
Warning (13410): Pin "led4[0]" is stuck at GND
Info: Implemented 1932 device resources after synthesis - the final resource count might be different
Info: Implemented 5 input pins
Info: Implemented 50 output pins
Info: Implemented 1877 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 32 warnings
Info: Peak virtual memory: 204 megabytes
Info: Processing ended: Mon May 21 19:54:20 2012
Info: Elapsed time: 00:00:16
Info: Total CPU time (on all processors): 00:00:17

1
myArkanoid.map.smsg Normal file
View file

@ -0,0 +1 @@
Warning (10268): Verilog HDL information at Arkanoid.v(168): always construct contains both blocking and non-blocking assignments

14
myArkanoid.map.summary Normal file
View file

@ -0,0 +1,14 @@
Analysis & Synthesis Status : Successful - Mon May 21 19:54:20 2012
Quartus II Version : 9.1 Build 222 10/21/2009 SJ Full Version
Revision Name : myArkanoid
Top-level Entity Name : TotalScheme
Family : Cyclone II
Total logic elements : 1,810
Total combinational functions : 1,793
Dedicated logic registers : 151
Total registers : 151
Total pins : 55
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0

558
myArkanoid.pin Normal file
View file

@ -0,0 +1,558 @@
-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 4: 3.3V
-- Bank 5: 3.3V
-- Bank 6: 3.3V
-- Bank 7: 3.3V
-- Bank 8: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17),
-- connect each pin marked GND* either individually through a 10k Ohm resistor
-- to GND or tie all pins together and connect through a single 10k Ohm resistor
-- to GND.
-- For non-transceiver I/O banks, connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version
CHIP "myArkanoid" ASSIGNED TO AN: EP2C20F484C7
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
GND : A1 : gnd : : : :
VCCIO3 : A2 : power : : 3.3V : 3 :
GND* : A3 : : : : 3 :
GND* : A4 : : : : 3 :
GND* : A5 : : : : 3 :
GND* : A6 : : : : 3 :
red[2] : A7 : output : 3.3-V LVTTL : : 3 : Y
green[3] : A8 : output : 3.3-V LVTTL : : 3 : Y
blue[0] : A9 : output : 3.3-V LVTTL : : 3 : Y
blue[2] : A10 : output : 3.3-V LVTTL : : 3 : Y
h_sync : A11 : output : 3.3-V LVTTL : : 3 : Y
GND+ : A12 : : : : 4 :
GND* : A13 : : : : 4 :
GND* : A14 : : : : 4 :
GND* : A15 : : : : 4 :
GND* : A16 : : : : 4 :
GND* : A17 : : : : 4 :
GND* : A18 : : : : 4 :
GND* : A19 : : : : 4 :
GND* : A20 : : : : 4 :
VCCIO4 : A21 : power : : 3.3V : 4 :
GND : A22 : gnd : : : :
VCCIO1 : AA1 : power : : 3.3V : 1 :
GND : AA2 : gnd : : : :
GND* : AA3 : : : : 8 :
GND* : AA4 : : : : 8 :
GND* : AA5 : : : : 8 :
GND* : AA6 : : : : 8 :
GND* : AA7 : : : : 8 :
GND* : AA8 : : : : 8 :
GND* : AA9 : : : : 8 :
GND* : AA10 : : : : 8 :
GND* : AA11 : : : : 8 :
GND* : AA12 : : : : 7 :
GND* : AA13 : : : : 7 :
GND* : AA14 : : : : 7 :
GND* : AA15 : : : : 7 :
GND* : AA16 : : : : 7 :
GND* : AA17 : : : : 7 :
GND* : AA18 : : : : 7 :
GND* : AA19 : : : : 7 :
GND* : AA20 : : : : 7 :
GND : AA21 : gnd : : : :
VCCIO6 : AA22 : power : : 3.3V : 6 :
GND : AB1 : gnd : : : :
VCCIO8 : AB2 : power : : 3.3V : 8 :
GND* : AB3 : : : : 8 :
GND* : AB4 : : : : 8 :
GND* : AB5 : : : : 8 :
GND* : AB6 : : : : 8 :
GND* : AB7 : : : : 8 :
GND* : AB8 : : : : 8 :
GND* : AB9 : : : : 8 :
GND* : AB10 : : : : 8 :
GND* : AB11 : : : : 8 :
GND* : AB12 : : : : 7 :
GND* : AB13 : : : : 7 :
GND* : AB14 : : : : 7 :
GND* : AB15 : : : : 7 :
GND* : AB16 : : : : 7 :
GND* : AB17 : : : : 7 :
GND* : AB18 : : : : 7 :
GND* : AB19 : : : : 7 :
GND* : AB20 : : : : 7 :
VCCIO7 : AB21 : power : : 3.3V : 7 :
GND : AB22 : gnd : : : :
VCCIO2 : B1 : power : : 3.3V : 2 :
GND : B2 : gnd : : : :
GND* : B3 : : : : 3 :
GND* : B4 : : : : 3 :
GND* : B5 : : : : 3 :
GND* : B6 : : : : 3 :
red[3] : B7 : output : 3.3-V LVTTL : : 3 : Y
green[0] : B8 : output : 3.3-V LVTTL : : 3 : Y
green[2] : B9 : output : 3.3-V LVTTL : : 3 : Y
blue[3] : B10 : output : 3.3-V LVTTL : : 3 : Y
v_sync : B11 : output : 3.3-V LVTTL : : 3 : Y
GND+ : B12 : : : : 4 :
GND* : B13 : : : : 4 :
GND* : B14 : : : : 4 :
GND* : B15 : : : : 4 :
GND* : B16 : : : : 4 :
GND* : B17 : : : : 4 :
GND* : B18 : : : : 4 :
GND* : B19 : : : : 4 :
GND* : B20 : : : : 4 :
GND : B21 : gnd : : : :
VCCIO5 : B22 : power : : 3.3V : 5 :
led3[3] : C1 : output : 3.3-V LVTTL : : 2 : Y
led3[2] : C2 : output : 3.3-V LVTTL : : 2 : Y
~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : input : 3.3-V LVTTL : : 2 : N
~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : input : 3.3-V LVTTL : : 2 : N
GND : C5 : gnd : : : :
VCCIO3 : C6 : power : : 3.3V : 3 :
GND* : C7 : : : : 3 :
GND : C8 : gnd : : : :
red[1] : C9 : output : 3.3-V LVTTL : : 3 : Y
green[1] : C10 : output : 3.3-V LVTTL : : 3 : Y
VCCIO3 : C11 : power : : 3.3V : 3 :
VCCIO4 : C12 : power : : 3.3V : 4 :
GND* : C13 : : : : 4 :
GND* : C14 : : : : 4 :
GND : C15 : gnd : : : :
GND* : C16 : : : : 4 :
GND* : C17 : : : : 4 :
GND* : C18 : : : : 4 :
GND* : C19 : : : : 5 :
GND* : C20 : : : : 5 :
GND* : C21 : : : : 5 :
GND* : C22 : : : : 5 :
led2[6] : D1 : output : 3.3-V LVTTL : : 2 : Y
led2[5] : D2 : output : 3.3-V LVTTL : : 2 : Y
led3[6] : D3 : output : 3.3-V LVTTL : : 2 : Y
led4[6] : D4 : output : 3.3-V LVTTL : : 2 : Y
led4[1] : D5 : output : 3.3-V LVTTL : : 2 : Y
led4[2] : D6 : output : 3.3-V LVTTL : : 2 : Y
GND* : D7 : : : : 3 :
GND* : D8 : : : : 3 :
red[0] : D9 : output : 3.3-V LVTTL : : 3 : Y
GND : D10 : gnd : : : :
blue[1] : D11 : output : 3.3-V LVTTL : : 3 : Y
GND+ : D12 : : : : 3 :
GND : D13 : gnd : : : :
GND* : D14 : : : : 4 :
GND* : D15 : : : : 4 :
GND* : D16 : : : : 4 :
VCCIO4 : D17 : power : : 3.3V : 4 :
GND : D18 : gnd : : : :
GND* : D19 : : : : 5 :
GND* : D20 : : : : 5 :
GND* : D21 : : : : 5 :
GND* : D22 : : : : 5 :
led2[0] : E1 : output : 3.3-V LVTTL : : 2 : Y
led1[6] : E2 : output : 3.3-V LVTTL : : 2 : Y
led3[4] : E3 : output : 3.3-V LVTTL : : 2 : Y
led3[5] : E4 : output : 3.3-V LVTTL : : 2 : Y
VCCD_PLL3 : E5 : power : : 1.2V : :
VCCA_PLL3 : E6 : power : : 1.2V : :
GND* : E7 : : : : 3 :
GND* : E8 : : : : 3 :
GND* : E9 : : : : 3 :
VCCIO3 : E10 : power : : 3.3V : 3 :
GND* : E11 : : : : 3 :
GND+ : E12 : : : : 3 :
VCCIO4 : E13 : power : : 3.3V : 4 :
GND* : E14 : : : : 4 :
GND* : E15 : : : : 4 :
GNDA_PLL2 : E16 : gnd : : : :
GND_PLL2 : E17 : gnd : : : :
GND* : E18 : : : : 5 :
GND* : E19 : : : : 5 :
GND* : E20 : : : : 5 :
GND* : E21 : : : : 5 :
GND* : E22 : : : : 5 :
led1[5] : F1 : output : 3.3-V LVTTL : : 2 : Y
led1[4] : F2 : output : 3.3-V LVTTL : : 2 : Y
led4[5] : F3 : output : 3.3-V LVTTL : : 2 : Y
led4[0] : F4 : output : 3.3-V LVTTL : : 2 : Y
GND_PLL3 : F5 : gnd : : : :
GND_PLL3 : F6 : gnd : : : :
GNDA_PLL3 : F7 : gnd : : : :
GND* : F8 : : : : 3 :
GND* : F9 : : : : 3 :
GND* : F10 : : : : 3 :
GND* : F11 : : : : 3 :
GND* : F12 : : : : 4 :
GND* : F13 : : : : 4 :
GND* : F14 : : : : 4 :
GND* : F15 : : : : 4 :
VCCA_PLL2 : F16 : power : : 1.2V : :
VCCD_PLL2 : F17 : power : : 1.2V : :
GND_PLL2 : F18 : gnd : : : :
GND : F19 : gnd : : : :
GND* : F20 : : : : 5 :
GND* : F21 : : : : 5 :
GND* : F22 : : : : 5 :
NC : G1 : : : : :
NC : G2 : : : : :
led2[4] : G3 : output : 3.3-V LVTTL : : 2 : Y
GND : G4 : gnd : : : :
led3[0] : G5 : output : 3.3-V LVTTL : : 2 : Y
led3[1] : G6 : output : 3.3-V LVTTL : : 2 : Y
GND* : G7 : : : : 3 :
GND* : G8 : : : : 3 :
VCCIO3 : G9 : power : : 3.3V : 3 :
GND : G10 : gnd : : : :
GND* : G11 : : : : 3 :
GND* : G12 : : : : 4 :
GND : G13 : gnd : : : :
VCCIO4 : G14 : power : : 3.3V : 4 :
GND* : G15 : : : : 4 :
GND* : G16 : : : : 4 :
GND* : G17 : : : : 5 :
GND* : G18 : : : : 5 :
VCCIO5 : G19 : power : : 3.3V : 5 :
GND* : G20 : : : : 5 :
GND* : G21 : : : : 5 :
GND* : G22 : : : : 5 :
led1[3] : H1 : output : 3.3-V LVTTL : : 2 : Y
led1[2] : H2 : output : 3.3-V LVTTL : : 2 : Y
GND* : H3 : : : : 2 :
led2[3] : H4 : output : 3.3-V LVTTL : : 2 : Y
led2[2] : H5 : output : 3.3-V LVTTL : : 2 : Y
led2[1] : H6 : output : 3.3-V LVTTL : : 2 : Y
GND* : H7 : : : : 3 :
GND* : H8 : : : : 3 :
GND* : H9 : : : : 3 :
GND* : H10 : : : : 3 :
GND* : H11 : : : : 3 :
GND* : H12 : : : : 4 :
GND* : H13 : : : : 4 :
GND* : H14 : : : : 4 :
GND* : H15 : : : : 4 :
GND* : H16 : : : : 5 :
GND* : H17 : : : : 5 :
GND* : H18 : : : : 5 :
GND* : H19 : : : : 5 :
GND : H20 : gnd : : : :
NC : H21 : : : : :
NC : H22 : : : : :
led1[1] : J1 : output : 3.3-V LVTTL : : 2 : Y
led1[0] : J2 : output : 3.3-V LVTTL : : 2 : Y
NC : J3 : : : : :
led4[3] : J4 : output : 3.3-V LVTTL : : 2 : Y
NC : J5 : : : : :
NC : J6 : : : : :
VCCIO2 : J7 : power : : 3.3V : 2 :
NC : J8 : : : : :
NC : J9 : : : : :
VCCINT : J10 : power : : 1.2V : :
VCCINT : J11 : power : : 1.2V : :
VCCINT : J12 : power : : 1.2V : :
VCCINT : J13 : power : : 1.2V : :
GND* : J14 : : : : 4 :
GND* : J15 : : : : 5 :
VCCIO5 : J16 : power : : 3.3V : 5 :
GND* : J17 : : : : 5 :
GND* : J18 : : : : 5 :
GND* : J19 : : : : 5 :
GND* : J20 : : : : 5 :
GND* : J21 : : : : 5 :
GND* : J22 : : : : 5 :
nCE : K1 : : : : 2 :
TCK : K2 : input : : : 2 :
GND : K3 : gnd : : : :
DATA0 : K4 : input : : : 2 :
TDI : K5 : input : : : 2 :
TMS : K6 : input : : : 2 :
GND : K7 : gnd : : : :
NC : K8 : : : : :
VCCINT : K9 : power : : 1.2V : :
GND : K10 : gnd : : : :
GND : K11 : gnd : : : :
GND : K12 : gnd : : : :
GND : K13 : gnd : : : :
VCCINT : K14 : power : : 1.2V : :
NC : K15 : : : : :
GND : K16 : gnd : : : :
NC : K17 : : : : :
NC : K18 : : : : :
GND : K19 : gnd : : : :
GND* : K20 : : : : 5 :
GND* : K21 : : : : 5 :
GND* : K22 : : : : 5 :
clk_50MHz : L1 : input : 3.3-V LVTTL : : 2 : Y
GND+ : L2 : : : : 2 :
VCCIO2 : L3 : power : : 3.3V : 2 :
nCONFIG : L4 : : : : 2 :
TDO : L5 : output : : : 2 :
DCLK : L6 : : : : 2 :
NC : L7 : : : : :
led4[4] : L8 : output : 3.3-V LVTTL : : 2 : Y
VCCINT : L9 : power : : 1.2V : :
GND : L10 : gnd : : : :
GND : L11 : gnd : : : :
GND : L12 : gnd : : : :
GND : L13 : gnd : : : :
VCCINT : L14 : power : : 1.2V : :
NC : L15 : : : : :
NC : L16 : : : : :
NC : L17 : : : : :
GND* : L18 : : : : 5 :
GND* : L19 : : : : 5 :
VCCIO5 : L20 : power : : 3.3V : 5 :
GND+ : L21 : : : : 5 :
GND+ : L22 : : : : 5 :
GND+ : M1 : : : : 1 :
GND+ : M2 : : : : 1 :
VCCIO1 : M3 : power : : 3.3V : 1 :
GND : M4 : gnd : : : :
GND* : M5 : : : : 1 :
GND* : M6 : : : : 1 :
NC : M7 : : : : :
NC : M8 : : : : :
VCCINT : M9 : power : : 1.2V : :
GND : M10 : gnd : : : :
GND : M11 : gnd : : : :
GND : M12 : gnd : : : :
GND : M13 : gnd : : : :
VCCINT : M14 : power : : 1.2V : :
NC : M15 : : : : :
NC : M16 : : : : :
MSEL0 : M17 : : : : 6 :
GND* : M18 : : : : 6 :
GND* : M19 : : : : 6 :
VCCIO6 : M20 : power : : 3.3V : 6 :
GND+ : M21 : : : : 6 :
GND+ : M22 : : : : 6 :
GND* : N1 : : : : 1 :
GND* : N2 : : : : 1 :
GND* : N3 : : : : 1 :
GND* : N4 : : : : 1 :
NC : N5 : : : : :
GND* : N6 : : : : 1 :
GND : N7 : gnd : : : :
NC : N8 : : : : :
VCCINT : N9 : power : : 1.2V : :
GND : N10 : gnd : : : :
GND : N11 : gnd : : : :
GND : N12 : gnd : : : :
GND : N13 : gnd : : : :
VCCINT : N14 : power : : 1.2V : :
GND* : N15 : : : : 6 :
GND : N16 : gnd : : : :
MSEL1 : N17 : : : : 6 :
CONF_DONE : N18 : : : : 6 :
GND : N19 : gnd : : : :
nSTATUS : N20 : : : : 6 :
GND* : N21 : : : : 6 :
GND* : N22 : : : : 6 :
GND* : P1 : : : : 1 :
GND* : P2 : : : : 1 :
GND* : P3 : : : : 1 :
NC : P4 : : : : :
GND* : P5 : : : : 1 :
GND* : P6 : : : : 1 :
VCCIO1 : P7 : power : : 3.3V : 1 :
GND* : P8 : : : : 8 :
GND* : P9 : : : : 8 :
VCCINT : P10 : power : : 1.2V : :
VCCINT : P11 : power : : 1.2V : :
VCCINT : P12 : power : : 1.2V : :
VCCINT : P13 : power : : 1.2V : :
NC : P14 : : : : :
GND* : P15 : : : : 6 :
VCCIO6 : P16 : power : : 3.3V : 6 :
GND* : P17 : : : : 6 :
GND* : P18 : : : : 6 :
NC : P19 : : : : :
NC : P20 : : : : :
NC : P21 : : : : :
NC : P22 : : : : :
GND* : R1 : : : : 1 :
GND* : R2 : : : : 1 :
GND : R3 : gnd : : : :
NC : R4 : : : : :
GND* : R5 : : : : 1 :
GND* : R6 : : : : 1 :
GND* : R7 : : : : 1 :
GND* : R8 : : : : 1 :
GND* : R9 : : : : 8 :
GND* : R10 : : : : 8 :
GND* : R11 : : : : 8 :
GND* : R12 : : : : 7 :
GND* : R13 : : : : 7 :
GND* : R14 : : : : 7 :
GND* : R15 : : : : 7 :
GND* : R16 : : : : 7 :
GND* : R17 : : : : 6 :
GND* : R18 : : : : 6 :
GND* : R19 : : : : 6 :
GND* : R20 : : : : 6 :
button3 : R21 : input : 3.3-V LVTTL : : 6 : Y
button4 : R22 : input : 3.3-V LVTTL : : 6 : Y
GND* : T1 : : : : 1 :
GND* : T2 : : : : 1 :
GND* : T3 : : : : 1 :
VCCIO1 : T4 : power : : 3.3V : 1 :
GND* : T5 : : : : 1 :
GND* : T6 : : : : 1 :
GND* : T7 : : : : 8 :
GND* : T8 : : : : 8 :
VCCIO8 : T9 : power : : 3.3V : 8 :
GND : T10 : gnd : : : :
GND* : T11 : : : : 8 :
GND* : T12 : : : : 7 :
GND : T13 : gnd : : : :
VCCIO7 : T14 : power : : 3.3V : 7 :
GND* : T15 : : : : 7 :
GND* : T16 : : : : 7 :
GND_PLL4 : T17 : gnd : : : :
GND* : T18 : : : : 6 :
VCCIO6 : T19 : power : : 3.3V : 6 :
GND : T20 : gnd : : : :
button1 : T21 : input : 3.3-V LVTTL : : 6 : Y
button2 : T22 : input : 3.3-V LVTTL : : 6 : Y
GND* : U1 : : : : 1 :
GND* : U2 : : : : 1 :
GND* : U3 : : : : 1 :
GND* : U4 : : : : 1 :
GND_PLL1 : U5 : gnd : : : :
VCCD_PLL1 : U6 : power : : 1.2V : :
VCCA_PLL1 : U7 : power : : 1.2V : :
GND* : U8 : : : : 8 :
GND* : U9 : : : : 8 :
GND* : U10 : : : : 8 :
GND+ : U11 : : : : 8 :
GND+ : U12 : : : : 8 :
GND* : U13 : : : : 7 :
GND* : U14 : : : : 7 :
GND* : U15 : : : : 7 :
VCCA_PLL4 : U16 : power : : 1.2V : :
VCCD_PLL4 : U17 : power : : 1.2V : :
GND* : U18 : : : : 6 :
GND* : U19 : : : : 6 :
GND* : U20 : : : : 6 :
led[1] : U21 : output : 3.3-V LVTTL : : 6 : Y
led[0] : U22 : output : 3.3-V LVTTL : : 6 : Y
GND* : V1 : : : : 1 :
GND* : V2 : : : : 1 :
GND : V3 : gnd : : : :
GND* : V4 : : : : 1 :
GND_PLL1 : V5 : gnd : : : :
GND : V6 : gnd : : : :
GNDA_PLL1 : V7 : gnd : : : :
GND* : V8 : : : : 8 :
GND* : V9 : : : : 8 :
VCCIO8 : V10 : power : : 3.3V : 8 :
GND* : V11 : : : : 8 :
GND+ : V12 : : : : 7 :
VCCIO7 : V13 : power : : 3.3V : 7 :
GND* : V14 : : : : 7 :
GND* : V15 : : : : 7 :
GNDA_PLL4 : V16 : gnd : : : :
GND : V17 : gnd : : : :
GND_PLL4 : V18 : gnd : : : :
GND* : V19 : : : : 6 :
GND* : V20 : : : : 6 :
led[3] : V21 : output : 3.3-V LVTTL : : 6 : Y
led[2] : V22 : output : 3.3-V LVTTL : : 6 : Y
GND* : W1 : : : : 1 :
GND* : W2 : : : : 1 :
GND* : W3 : : : : 1 :
GND* : W4 : : : : 1 :
GND* : W5 : : : : 1 :
VCCIO8 : W6 : power : : 3.3V : 8 :
GND* : W7 : : : : 8 :
GND* : W8 : : : : 8 :
GND* : W9 : : : : 8 :
GND : W10 : gnd : : : :
GND* : W11 : : : : 8 :
GND+ : W12 : : : : 7 :
GND : W13 : gnd : : : :
GND* : W14 : : : : 7 :
GND* : W15 : : : : 7 :
GND* : W16 : : : : 7 :
VCCIO7 : W17 : power : : 3.3V : 7 :
NC : W18 : : : : :
GND : W19 : gnd : : : :
~LVDS91p/nCEO~ : W20 : output : 3.3-V LVTTL : : 6 : N
led[5] : W21 : output : 3.3-V LVTTL : : 6 : Y
led[4] : W22 : output : 3.3-V LVTTL : : 6 : Y
GND* : Y1 : : : : 1 :
GND* : Y2 : : : : 1 :
GND* : Y3 : : : : 1 :
GND* : Y4 : : : : 1 :
GND* : Y5 : : : : 8 :
GND* : Y6 : : : : 8 :
GND* : Y7 : : : : 8 :
GND : Y8 : gnd : : : :
GND* : Y9 : : : : 8 :
GND* : Y10 : : : : 8 :
VCCIO8 : Y11 : power : : 3.3V : 8 :
VCCIO7 : Y12 : power : : 3.3V : 7 :
GND* : Y13 : : : : 7 :
GND* : Y14 : : : : 7 :
GND : Y15 : gnd : : : :
GND* : Y16 : : : : 7 :
GND* : Y17 : : : : 7 :
GND* : Y18 : : : : 6 :
GND* : Y19 : : : : 6 :
GND* : Y20 : : : : 6 :
led[7] : Y21 : output : 3.3-V LVTTL : : 6 : Y
led[6] : Y22 : output : 3.3-V LVTTL : : 6 : Y

BIN
myArkanoid.pof Normal file
View file

Binary file not shown.

30
myArkanoid.qpf Normal file
View file

@ -0,0 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 14:07:51 October 21, 2009
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "9.0"
DATE = "14:07:51 October 21, 2009"
# Revisions
PROJECT_REVISION = "myArkanoid"

120
myArkanoid.qsf Normal file
View file

@ -0,0 +1,120 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 14:07:51 October 21, 2009
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# myArkanoid_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C20F484C7
set_global_assignment -name TOP_LEVEL_ENTITY TotalScheme
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:07:51 OCTOBER 21, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION 9.1
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_location_assignment PIN_L1 -to clk_50MHz
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE AUTO
set_location_assignment PIN_J2 -to led1[0]
set_location_assignment PIN_J1 -to led1[1]
set_location_assignment PIN_H2 -to led1[2]
set_location_assignment PIN_H1 -to led1[3]
set_location_assignment PIN_F2 -to led1[4]
set_location_assignment PIN_F1 -to led1[5]
set_location_assignment PIN_E2 -to led1[6]
set_location_assignment PIN_E1 -to led2[0]
set_location_assignment PIN_H6 -to led2[1]
set_location_assignment PIN_H5 -to led2[2]
set_location_assignment PIN_H4 -to led2[3]
set_location_assignment PIN_G3 -to led2[4]
set_location_assignment PIN_D2 -to led2[5]
set_location_assignment PIN_D1 -to led2[6]
set_location_assignment PIN_G5 -to led3[0]
set_location_assignment PIN_G6 -to led3[1]
set_location_assignment PIN_C2 -to led3[2]
set_location_assignment PIN_C1 -to led3[3]
set_location_assignment PIN_E3 -to led3[4]
set_location_assignment PIN_E4 -to led3[5]
set_location_assignment PIN_D3 -to led3[6]
set_location_assignment PIN_F4 -to led4[0]
set_location_assignment PIN_D5 -to led4[1]
set_location_assignment PIN_D6 -to led4[2]
set_location_assignment PIN_J4 -to led4[3]
set_location_assignment PIN_L8 -to led4[4]
set_location_assignment PIN_F3 -to led4[5]
set_location_assignment PIN_D4 -to led4[6]
set_global_assignment -name MISC_FILE "C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/myArkanoid/myArkanoid.dpf"
set_location_assignment PIN_D9 -to red[0]
set_location_assignment PIN_C9 -to red[1]
set_location_assignment PIN_A7 -to red[2]
set_location_assignment PIN_B7 -to red[3]
set_location_assignment PIN_B8 -to green[0]
set_location_assignment PIN_C10 -to green[1]
set_location_assignment PIN_B9 -to green[2]
set_location_assignment PIN_A8 -to green[3]
set_location_assignment PIN_A9 -to blue[0]
set_location_assignment PIN_D11 -to blue[1]
set_location_assignment PIN_A10 -to blue[2]
set_location_assignment PIN_B10 -to blue[3]
set_location_assignment PIN_T21 -to button1
set_location_assignment PIN_T22 -to button2
set_location_assignment PIN_R21 -to button3
set_location_assignment PIN_R22 -to button4
set_location_assignment PIN_A11 -to h_sync
set_location_assignment PIN_B11 -to v_sync
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name MISC_FILE "C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/myArkanoid.dpf"
set_global_assignment -name BDF_FILE TotalScheme.bdf
set_global_assignment -name VERILOG_FILE Arkanoid.v
set_global_assignment -name VECTOR_WAVEFORM_FILE myArkanoid.vwf
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE myArkanoid.vwf
set_location_assignment PIN_U22 -to led[0]
set_location_assignment PIN_U21 -to led[1]
set_location_assignment PIN_V22 -to led[2]
set_location_assignment PIN_V21 -to led[3]
set_location_assignment PIN_W22 -to led[4]
set_location_assignment PIN_W21 -to led[5]
set_location_assignment PIN_Y22 -to led[6]
set_location_assignment PIN_Y21 -to led[7]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

121
myArkanoid.qsf.bak Normal file
View file

@ -0,0 +1,121 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 14:07:51 October 21, 2009
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# myArkanoid_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C20F484C7
set_global_assignment -name TOP_LEVEL_ENTITY myArkanoidSchematic
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:07:51 OCTOBER 21, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION 9.1
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name BDF_FILE myArkanoidSchematic.bdf
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_location_assignment PIN_L1 -to clk_50MHz
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name MUX_RESTRUCTURE ON
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION ALWAYS
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
set_global_assignment -name IGNORE_LCELL_BUFFERS ON
set_global_assignment -name IGNORE_CASCADE_BUFFERS ON
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_location_assignment PIN_J2 -to led1[0]
set_location_assignment PIN_J1 -to led1[1]
set_location_assignment PIN_H2 -to led1[2]
set_location_assignment PIN_H1 -to led1[3]
set_location_assignment PIN_F2 -to led1[4]
set_location_assignment PIN_F1 -to led1[5]
set_location_assignment PIN_E2 -to led1[6]
set_location_assignment PIN_E1 -to led2[0]
set_location_assignment PIN_H6 -to led2[1]
set_location_assignment PIN_H5 -to led2[2]
set_location_assignment PIN_H4 -to led2[3]
set_location_assignment PIN_G3 -to led2[4]
set_location_assignment PIN_D2 -to led2[5]
set_location_assignment PIN_D1 -to led2[6]
set_location_assignment PIN_G5 -to led3[0]
set_location_assignment PIN_G6 -to led3[1]
set_location_assignment PIN_C2 -to led3[2]
set_location_assignment PIN_C1 -to led3[3]
set_location_assignment PIN_E3 -to led3[4]
set_location_assignment PIN_E4 -to led3[5]
set_location_assignment PIN_D3 -to led3[6]
set_location_assignment PIN_F4 -to led4[0]
set_location_assignment PIN_D5 -to led4[1]
set_location_assignment PIN_D6 -to led4[2]
set_location_assignment PIN_J4 -to led4[3]
set_location_assignment PIN_L8 -to led4[4]
set_location_assignment PIN_F3 -to led4[5]
set_location_assignment PIN_D4 -to led4[6]
set_global_assignment -name VHDL_FILE FrequencyDivider.vhd
set_global_assignment -name VERILOG_FILE Arkanoid.v
set_global_assignment -name MISC_FILE "C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/myArkanoid/myArkanoid.dpf"
set_location_assignment PIN_D9 -to red[0]
set_location_assignment PIN_C9 -to red[1]
set_location_assignment PIN_A7 -to red[2]
set_location_assignment PIN_B7 -to red[3]
set_location_assignment PIN_B8 -to green[0]
set_location_assignment PIN_C10 -to green[1]
set_location_assignment PIN_B9 -to green[2]
set_location_assignment PIN_A8 -to green[3]
set_location_assignment PIN_A9 -to blue[0]
set_location_assignment PIN_D11 -to blue[1]
set_location_assignment PIN_A10 -to blue[2]
set_location_assignment PIN_B10 -to blue[3]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_location_assignment PIN_R22 -to button1
set_location_assignment PIN_R21 -to button2
set_location_assignment PIN_T22 -to button3
set_location_assignment PIN_T21 -to button4
set_location_assignment PIN_A11 -to h_sync
set_location_assignment PIN_B11 -to v_sync

16
myArkanoid.qws Normal file
View file

@ -0,0 +1,16 @@
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
[ProjectWorkspace.Frames.ChildFrames.Document-0]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
DocPathName=Arkanoid.v
DocumentCLSID={84678d98-dc76-11d0-a0d8-0020affa5bde}
IsChildFrameDetached=False
IsActiveChildFrame=True
ptn_Child1=StateMap
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0.StateMap]
AFC_IN_REPORT=False

289
myArkanoid.sim.rpt Normal file
View file

@ -0,0 +1,289 @@
Simulator report for myArkanoid
Mon May 21 14:05:52 2012
Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Simulator Summary
3. Simulator Settings
4. Simulation Waveforms
5. Coverage Summary
6. Complete 1/0-Value Coverage
7. Missing 1-Value Coverage
8. Missing 0-Value Coverage
9. Simulator INI Usage
10. Simulator Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------+
; Simulator Summary ;
+-----------------------------+--------------+
; Type ; Value ;
+-----------------------------+--------------+
; Simulation Start Time ; 0 ps ;
; Simulation End Time ; 50.0 ms ;
; Simulation Netlist Size ; 67 nodes ;
; Simulation Coverage ; 0.00 % ;
; Total Number of Transitions ; 0 ;
; Simulation Breakpoints ; 0 ;
; Family ; Cyclone II ;
; Device ; EP2C20F484C7 ;
+-----------------------------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------+
; Simulator Settings ;
+--------------------------------------------------------------------------------------------+----------------+---------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------------------------------+----------------+---------------+
; Simulation mode ; Timing ; Timing ;
; Start time ; 0 ns ; 0 ns ;
; Simulation results format ; CVWF ; ;
; Vector input source ; myArkanoid.vwf ; ;
; Add pins automatically to simulation output waveforms ; On ; On ;
; Check outputs ; Off ; Off ;
; Report simulation coverage ; On ; On ;
; Display complete 1/0 value coverage report ; On ; On ;
; Display missing 1-value coverage report ; On ; On ;
; Display missing 0-value coverage report ; On ; On ;
; Detect setup and hold time violations ; Off ; Off ;
; Detect glitches ; Off ; Off ;
; Disable timing delays in Timing Simulation ; Off ; Off ;
; Generate Signal Activity File ; Off ; Off ;
; Generate VCD File for PowerPlay Power Analyzer ; Off ; Off ;
; Group bus channels in simulation results ; Off ; Off ;
; Preserve fewer signal transitions to reduce memory requirements ; On ; On ;
; Trigger vector comparison with the specified mode ; INPUT_EDGE ; INPUT_EDGE ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off ; Off ;
; Overwrite Waveform Inputs With Simulation Outputs ; Off ; ;
; Perform Glitch Filtering in Timing Simulation ; Auto ; Auto ;
+--------------------------------------------------------------------------------------------+----------------+---------------+
+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.
+--------------------------------------------------------------------+
; Coverage Summary ;
+-----------------------------------------------------+--------------+
; Type ; Value ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage ; 0.00 % ;
; Total nodes checked ; 67 ;
; Total output ports checked ; 62 ;
; Total output ports with complete 1/0-value coverage ; 0 ;
; Total output ports with no 1/0-value coverage ; 62 ;
; Total output ports with no 1-value coverage ; 62 ;
; Total output ports with no 0-value coverage ; 62 ;
+-----------------------------------------------------+--------------+
The following table displays output ports that toggle between 1 and 0 during simulation.
+-------------------------------------------------+
; Complete 1/0-Value Coverage ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+-----------------------+-----------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------------------+-----------------------+------------------+
; |TotalScheme|h_sync ; |TotalScheme|h_sync ; padio ;
; |TotalScheme|v_sync ; |TotalScheme|v_sync ; padio ;
; |TotalScheme|blue[3] ; |TotalScheme|blue[3] ; padio ;
; |TotalScheme|blue[2] ; |TotalScheme|blue[2] ; padio ;
; |TotalScheme|blue[1] ; |TotalScheme|blue[1] ; padio ;
; |TotalScheme|blue[0] ; |TotalScheme|blue[0] ; padio ;
; |TotalScheme|green[3] ; |TotalScheme|green[3] ; padio ;
; |TotalScheme|green[2] ; |TotalScheme|green[2] ; padio ;
; |TotalScheme|green[1] ; |TotalScheme|green[1] ; padio ;
; |TotalScheme|green[0] ; |TotalScheme|green[0] ; padio ;
; |TotalScheme|hort[9] ; |TotalScheme|hort[9] ; padio ;
; |TotalScheme|hort[8] ; |TotalScheme|hort[8] ; padio ;
; |TotalScheme|hort[7] ; |TotalScheme|hort[7] ; padio ;
; |TotalScheme|hort[6] ; |TotalScheme|hort[6] ; padio ;
; |TotalScheme|hort[5] ; |TotalScheme|hort[5] ; padio ;
; |TotalScheme|hort[4] ; |TotalScheme|hort[4] ; padio ;
; |TotalScheme|hort[3] ; |TotalScheme|hort[3] ; padio ;
; |TotalScheme|hort[2] ; |TotalScheme|hort[2] ; padio ;
; |TotalScheme|hort[1] ; |TotalScheme|hort[1] ; padio ;
; |TotalScheme|hort[0] ; |TotalScheme|hort[0] ; padio ;
; |TotalScheme|led1[6] ; |TotalScheme|led1[6] ; padio ;
; |TotalScheme|led1[5] ; |TotalScheme|led1[5] ; padio ;
; |TotalScheme|led1[4] ; |TotalScheme|led1[4] ; padio ;
; |TotalScheme|led1[3] ; |TotalScheme|led1[3] ; padio ;
; |TotalScheme|led1[2] ; |TotalScheme|led1[2] ; padio ;
; |TotalScheme|led1[1] ; |TotalScheme|led1[1] ; padio ;
; |TotalScheme|led1[0] ; |TotalScheme|led1[0] ; padio ;
; |TotalScheme|led2[6] ; |TotalScheme|led2[6] ; padio ;
; |TotalScheme|led2[5] ; |TotalScheme|led2[5] ; padio ;
; |TotalScheme|led2[4] ; |TotalScheme|led2[4] ; padio ;
; |TotalScheme|led2[3] ; |TotalScheme|led2[3] ; padio ;
; |TotalScheme|led2[2] ; |TotalScheme|led2[2] ; padio ;
; |TotalScheme|led2[1] ; |TotalScheme|led2[1] ; padio ;
; |TotalScheme|led2[0] ; |TotalScheme|led2[0] ; padio ;
; |TotalScheme|led3[6] ; |TotalScheme|led3[6] ; padio ;
; |TotalScheme|led3[5] ; |TotalScheme|led3[5] ; padio ;
; |TotalScheme|led3[4] ; |TotalScheme|led3[4] ; padio ;
; |TotalScheme|led3[3] ; |TotalScheme|led3[3] ; padio ;
; |TotalScheme|led3[2] ; |TotalScheme|led3[2] ; padio ;
; |TotalScheme|led3[1] ; |TotalScheme|led3[1] ; padio ;
; |TotalScheme|led3[0] ; |TotalScheme|led3[0] ; padio ;
; |TotalScheme|led4[6] ; |TotalScheme|led4[6] ; padio ;
; |TotalScheme|led4[5] ; |TotalScheme|led4[5] ; padio ;
; |TotalScheme|led4[4] ; |TotalScheme|led4[4] ; padio ;
; |TotalScheme|led4[3] ; |TotalScheme|led4[3] ; padio ;
; |TotalScheme|led4[2] ; |TotalScheme|led4[2] ; padio ;
; |TotalScheme|led4[1] ; |TotalScheme|led4[1] ; padio ;
; |TotalScheme|led4[0] ; |TotalScheme|led4[0] ; padio ;
; |TotalScheme|red[3] ; |TotalScheme|red[3] ; padio ;
; |TotalScheme|red[2] ; |TotalScheme|red[2] ; padio ;
; |TotalScheme|red[1] ; |TotalScheme|red[1] ; padio ;
; |TotalScheme|red[0] ; |TotalScheme|red[0] ; padio ;
; |TotalScheme|vert[9] ; |TotalScheme|vert[9] ; padio ;
; |TotalScheme|vert[8] ; |TotalScheme|vert[8] ; padio ;
; |TotalScheme|vert[7] ; |TotalScheme|vert[7] ; padio ;
; |TotalScheme|vert[6] ; |TotalScheme|vert[6] ; padio ;
; |TotalScheme|vert[5] ; |TotalScheme|vert[5] ; padio ;
; |TotalScheme|vert[4] ; |TotalScheme|vert[4] ; padio ;
; |TotalScheme|vert[3] ; |TotalScheme|vert[3] ; padio ;
; |TotalScheme|vert[2] ; |TotalScheme|vert[2] ; padio ;
; |TotalScheme|vert[1] ; |TotalScheme|vert[1] ; padio ;
; |TotalScheme|vert[0] ; |TotalScheme|vert[0] ; padio ;
+-----------------------+-----------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+-----------------------+-----------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------------------+-----------------------+------------------+
; |TotalScheme|h_sync ; |TotalScheme|h_sync ; padio ;
; |TotalScheme|v_sync ; |TotalScheme|v_sync ; padio ;
; |TotalScheme|blue[3] ; |TotalScheme|blue[3] ; padio ;
; |TotalScheme|blue[2] ; |TotalScheme|blue[2] ; padio ;
; |TotalScheme|blue[1] ; |TotalScheme|blue[1] ; padio ;
; |TotalScheme|blue[0] ; |TotalScheme|blue[0] ; padio ;
; |TotalScheme|green[3] ; |TotalScheme|green[3] ; padio ;
; |TotalScheme|green[2] ; |TotalScheme|green[2] ; padio ;
; |TotalScheme|green[1] ; |TotalScheme|green[1] ; padio ;
; |TotalScheme|green[0] ; |TotalScheme|green[0] ; padio ;
; |TotalScheme|hort[9] ; |TotalScheme|hort[9] ; padio ;
; |TotalScheme|hort[8] ; |TotalScheme|hort[8] ; padio ;
; |TotalScheme|hort[7] ; |TotalScheme|hort[7] ; padio ;
; |TotalScheme|hort[6] ; |TotalScheme|hort[6] ; padio ;
; |TotalScheme|hort[5] ; |TotalScheme|hort[5] ; padio ;
; |TotalScheme|hort[4] ; |TotalScheme|hort[4] ; padio ;
; |TotalScheme|hort[3] ; |TotalScheme|hort[3] ; padio ;
; |TotalScheme|hort[2] ; |TotalScheme|hort[2] ; padio ;
; |TotalScheme|hort[1] ; |TotalScheme|hort[1] ; padio ;
; |TotalScheme|hort[0] ; |TotalScheme|hort[0] ; padio ;
; |TotalScheme|led1[6] ; |TotalScheme|led1[6] ; padio ;
; |TotalScheme|led1[5] ; |TotalScheme|led1[5] ; padio ;
; |TotalScheme|led1[4] ; |TotalScheme|led1[4] ; padio ;
; |TotalScheme|led1[3] ; |TotalScheme|led1[3] ; padio ;
; |TotalScheme|led1[2] ; |TotalScheme|led1[2] ; padio ;
; |TotalScheme|led1[1] ; |TotalScheme|led1[1] ; padio ;
; |TotalScheme|led1[0] ; |TotalScheme|led1[0] ; padio ;
; |TotalScheme|led2[6] ; |TotalScheme|led2[6] ; padio ;
; |TotalScheme|led2[5] ; |TotalScheme|led2[5] ; padio ;
; |TotalScheme|led2[4] ; |TotalScheme|led2[4] ; padio ;
; |TotalScheme|led2[3] ; |TotalScheme|led2[3] ; padio ;
; |TotalScheme|led2[2] ; |TotalScheme|led2[2] ; padio ;
; |TotalScheme|led2[1] ; |TotalScheme|led2[1] ; padio ;
; |TotalScheme|led2[0] ; |TotalScheme|led2[0] ; padio ;
; |TotalScheme|led3[6] ; |TotalScheme|led3[6] ; padio ;
; |TotalScheme|led3[5] ; |TotalScheme|led3[5] ; padio ;
; |TotalScheme|led3[4] ; |TotalScheme|led3[4] ; padio ;
; |TotalScheme|led3[3] ; |TotalScheme|led3[3] ; padio ;
; |TotalScheme|led3[2] ; |TotalScheme|led3[2] ; padio ;
; |TotalScheme|led3[1] ; |TotalScheme|led3[1] ; padio ;
; |TotalScheme|led3[0] ; |TotalScheme|led3[0] ; padio ;
; |TotalScheme|led4[6] ; |TotalScheme|led4[6] ; padio ;
; |TotalScheme|led4[5] ; |TotalScheme|led4[5] ; padio ;
; |TotalScheme|led4[4] ; |TotalScheme|led4[4] ; padio ;
; |TotalScheme|led4[3] ; |TotalScheme|led4[3] ; padio ;
; |TotalScheme|led4[2] ; |TotalScheme|led4[2] ; padio ;
; |TotalScheme|led4[1] ; |TotalScheme|led4[1] ; padio ;
; |TotalScheme|led4[0] ; |TotalScheme|led4[0] ; padio ;
; |TotalScheme|red[3] ; |TotalScheme|red[3] ; padio ;
; |TotalScheme|red[2] ; |TotalScheme|red[2] ; padio ;
; |TotalScheme|red[1] ; |TotalScheme|red[1] ; padio ;
; |TotalScheme|red[0] ; |TotalScheme|red[0] ; padio ;
; |TotalScheme|vert[9] ; |TotalScheme|vert[9] ; padio ;
; |TotalScheme|vert[8] ; |TotalScheme|vert[8] ; padio ;
; |TotalScheme|vert[7] ; |TotalScheme|vert[7] ; padio ;
; |TotalScheme|vert[6] ; |TotalScheme|vert[6] ; padio ;
; |TotalScheme|vert[5] ; |TotalScheme|vert[5] ; padio ;
; |TotalScheme|vert[4] ; |TotalScheme|vert[4] ; padio ;
; |TotalScheme|vert[3] ; |TotalScheme|vert[3] ; padio ;
; |TotalScheme|vert[2] ; |TotalScheme|vert[2] ; padio ;
; |TotalScheme|vert[1] ; |TotalScheme|vert[1] ; padio ;
; |TotalScheme|vert[0] ; |TotalScheme|vert[0] ; padio ;
+-----------------------+-----------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 9.1 Build 222 10/21/2009 SJ Full Version
Info: Processing started: Mon May 21 14:02:19 2012
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off myArkanoid -c myArkanoid
Info: Using vector source file "C:/Users/ProGOLD/Desktop/Ïîëèòåõ/Altera DE1/Arkanoid/myArkanoid.vwf"
Warning: Can't find signal in vector source file for input pin "|TotalScheme|button1"
Warning: Can't find signal in vector source file for input pin "|TotalScheme|button2"
Warning: Can't find signal in vector source file for input pin "|TotalScheme|button3"
Warning: Can't find signal in vector source file for input pin "|TotalScheme|button4"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 0.00 %
Info: Number of transitions in simulation is 0
Info: Quartus II Simulator was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 136 megabytes
Info: Processing ended: Mon May 21 14:05:53 2012
Info: Elapsed time: 00:03:34
Info: Total CPU time (on all processors): 00:03:34

BIN
myArkanoid.sof Normal file
View file

Binary file not shown.

1169
myArkanoid.tan.rpt Normal file
View file

File diff suppressed because it is too large Load diff

56
myArkanoid.tan.summary Normal file
View file

@ -0,0 +1,56 @@
--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------
Type : Worst-case tsu
Slack : N/A
Required Time : None
Actual Time : 32.749 ns
From : button3
To : Arkanoid:inst|blue_[0]
From Clock : --
To Clock : clk_50MHz
Failed Paths : 0
Type : Worst-case tco
Slack : N/A
Required Time : None
Actual Time : 15.668 ns
From : Arkanoid:inst|v_counter[8]
To : v_sync
From Clock : clk_50MHz
To Clock : --
Failed Paths : 0
Type : Worst-case th
Slack : N/A
Required Time : None
Actual Time : -2.062 ns
From : button2
To : Arkanoid:inst|platform1_position[29]
From Clock : --
To Clock : clk_50MHz
Failed Paths : 0
Type : Clock Setup: 'clk_50MHz'
Slack : N/A
Required Time : None
Actual Time : 9.70 MHz ( period = 103.135 ns )
From : Arkanoid:inst|h_counter[1]
To : Arkanoid:inst|blue_[0]
From Clock : clk_50MHz
To Clock : clk_50MHz
Failed Paths : 0
Type : Total number of failed paths
Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 0
--------------------------------------------------------------------------------------

677
myArkanoid_assignment_defaults.qdf Normal file
View file

@ -0,0 +1,677 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.1 Build 222 10/21/2009 SJ Full Version
# Date created = 14:46:31 May 07, 2012
#
# -------------------------------------------------------------------------- #
#
# Note:
#
# 1) Do not modify this file. This file was generated
# automatically by the Quartus II software and is used
# to preserve global assignments across Quartus II versions.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
set_global_assignment -name SMART_RECOMPILE Off
set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
set_global_assignment -name HC_OUTPUT_DIR hc_output
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
set_global_assignment -name DO_COMBINED_ANALYSIS Off
set_global_assignment -name IGNORE_CLOCK_SETTINGS Off
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS Off
set_global_assignment -name ENABLE_CLOCK_LATENCY Off
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000B
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy II"
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix IV"
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III"
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy Stratix"
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000AE
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Cyclone
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II GX"
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "MAX II"
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria II GX"
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix GX"
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy III"
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000S
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Cyclone II"
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone IV GX"
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy IV"
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III LS"
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix III"
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria GX"
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX3000A
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II"
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Stratix
set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 10
set_global_assignment -name NUMBER_OF_DESTINATION_TO_REPORT 10
set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 200
set_global_assignment -name DO_MIN_ANALYSIS Off
set_global_assignment -name DO_MIN_TIMING Off
set_global_assignment -name REPORT_IO_PATHS_SEPARATELY Off
set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK Off
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "HardCopy Stratix"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000B
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy II"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy Stratix"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000AE
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II GX"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family Cyclone
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix GX"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000S
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy III"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone II"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy IV"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria GX"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX3000A
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family Stratix
set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy Stratix"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix
set_global_assignment -name MUX_RESTRUCTURE Auto
set_global_assignment -name ENABLE_IP_DEBUG Off
set_global_assignment -name SAVE_DISK_SPACE On
set_global_assignment -name DISABLE_OCP_HW_EVAL Off
set_global_assignment -name DEVICE_FILTER_PACKAGE Any
set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
set_global_assignment -name FAMILY "Stratix II"
set_global_assignment -name TRUE_WYSIWYG_FLOW Off
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
set_global_assignment -name SAFE_STATE_MACHINE Off
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS On
set_global_assignment -name PARALLEL_SYNTHESIS -value OFF
set_global_assignment -name DSP_BLOCK_BALANCING Auto
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
set_global_assignment -name NOT_GATE_PUSH_BACK On
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
set_global_assignment -name IGNORE_CARRY_BUFFERS Off
set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_LCELL_BUFFERS Off
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
set_global_assignment -name IGNORE_SOFT_BUFFERS On
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
set_global_assignment -name AUTO_GLOBAL_OE_MAX On
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name ALLOW_XOR_GATE_USAGE On
set_global_assignment -name AUTO_LCELL_INSERTION On
set_global_assignment -name CARRY_CHAIN_LENGTH 48
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
set_global_assignment -name CASCADE_CHAIN_LENGTH 2
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
set_global_assignment -name AUTO_CARRY_CHAINS On
set_global_assignment -name AUTO_CASCADE_CHAINS On
set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
set_global_assignment -name AUTO_ROM_RECOGNITION On
set_global_assignment -name AUTO_RAM_RECOGNITION On
set_global_assignment -name AUTO_DSP_RECOGNITION On
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
set_global_assignment -name STRICT_RAM_RECOGNITION Off
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
set_global_assignment -name FORCE_SYNCH_CLEAR Off
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
set_global_assignment -name AUTO_RESOURCE_SHARING Off
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
set_global_assignment -name MAX7000_FANIN_PER_CELL 100
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Cyclone III LS"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Cyclone III"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Stratix III"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "HardCopy III"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Arria GX"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Cyclone II"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "HardCopy II"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II GX"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Cyclone IV GX"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Stratix IV"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Arria II GX"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "HardCopy IV"
set_global_assignment -name SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT On
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
set_global_assignment -name HDL_MESSAGE_LEVEL Level2
set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 100
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
set_global_assignment -name BLOCK_DESIGN_NAMING Auto
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
set_global_assignment -name SYNTHESIS_EFFORT Auto
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy III"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy Stratix"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone II"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Cyclone
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy II"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix II"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Stratix
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy IV"
set_global_assignment -name MAX_LABS "-1 (Unlimited)"
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
set_global_assignment -name DEVICE AUTO
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
set_global_assignment -name STRATIX_UPDATE_MODE Standard
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name USER_START_UP_CLOCK Off
set_global_assignment -name ENABLE_VREFA_PIN Off
set_global_assignment -name ENABLE_VREFB_PIN Off
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Cyclone II"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family Cyclone
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II GX"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "HardCopy II"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Arria GX"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "As input tri-stated" -family "Cyclone IV GX"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name CRC_ERROR_CHECKING Off
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy III"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy IV"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy Stratix"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria GX"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "Force All Tiles with Failing Timing Paths to High Speed"
set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III LS"
set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III"
set_global_assignment -name OPTIMIZE_SSN Off -family "Stratix III"
set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy III"
set_global_assignment -name OPTIMIZE_SSN Off -family "Stratix IV"
set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy IV"
set_global_assignment -name OPTIMIZE_SSN Off -family "Arria II GX"
set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
set_global_assignment -name ECO_OPTIMIZE_TIMING Off
set_global_assignment -name ECO_REGENERATE_REPORT Off
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING On
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
set_global_assignment -name SEED 1
set_global_assignment -name SLOW_SLEW_RATE Off
set_global_assignment -name PCI_IO Off
set_global_assignment -name TURBO_BIT On
set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
set_global_assignment -name AUTO_PACKED_REGISTERS Off
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
set_global_assignment -name NORMAL_LCELL_INSERT On
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
set_global_assignment -name AUTO_DELAY_CHAINS On
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
set_global_assignment -name AUTO_MERGE_PLLS On
set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
set_global_assignment -name AUTO_TURBO_BIT ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
set_global_assignment -name FITTER_EFFORT "Auto Fit"
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
set_global_assignment -name AUTO_GLOBAL_CLOCK On
set_global_assignment -name AUTO_GLOBAL_OE On
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
set_global_assignment -name STOP_AFTER_CONGESTION_MAP Off
set_global_assignment -name ENABLE_HOLD_BACK_OFF On
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION -value ON
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
set_global_assignment -name COMPRESSION_MODE Off
set_global_assignment -name CLOCK_SOURCE Internal
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name SECURITY_BIT Off
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy Stratix"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
set_global_assignment -name GENERATE_TTF_FILE Off
set_global_assignment -name GENERATE_RBF_FILE Off
set_global_assignment -name GENERATE_HEX_FILE Off
set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
set_global_assignment -name AUTO_RESTART_CONFIGURATION On
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
set_global_assignment -name ENABLE_OCT_DONE Off
set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT Off
set_global_assignment -name START_TIME 0ns
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
set_global_assignment -name SETUP_HOLD_DETECTION Off
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
set_global_assignment -name CHECK_OUTPUTS Off
set_global_assignment -name SIMULATION_COVERAGE On
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name GLITCH_DETECTION Off
set_global_assignment -name GLITCH_INTERVAL 1ns
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
set_global_assignment -name DRC_TOP_FANOUT 50
set_global_assignment -name DRC_FANOUT_EXCEEDING 30
set_global_assignment -name DRC_GATED_CLOCK_FEED 30
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
set_global_assignment -name ENABLE_DRC_SETTINGS Off
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
set_global_assignment -name MERGE_HEX_FILE Off
set_global_assignment -name GENERATE_SVF_FILE Off
set_global_assignment -name GENERATE_ISC_FILE Off
set_global_assignment -name GENERATE_JAM_FILE Off
set_global_assignment -name GENERATE_JBC_FILE Off
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT Off
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_USE_PVA On
set_global_assignment -name POWER_USE_INPUT_FILE "No File"
set_global_assignment -name POWER_USE_INPUT_FILES Off
set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
set_global_assignment -name POWER_TJ_VALUE 25
set_global_assignment -name POWER_USE_TA_VALUE 25
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
set_global_assignment -name POWER_BOARD_TEMPERATURE 25
set_global_assignment -name INCREMENTAL_COMPILATION FULL_INCREMENTAL_COMPILATION
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE POST_FIT
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
set_global_assignment -name RTLV_GROUP_RELATED_NODES On
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
set_global_assignment -name EQC_BBOX_MERGE On
set_global_assignment -name EQC_LVDS_MERGE On
set_global_assignment -name EQC_RAM_UNMERGING On
set_global_assignment -name EQC_DFF_SS_EMULATION On
set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
set_global_assignment -name EQC_STRUCTURE_MATCHING On
set_global_assignment -name EQC_AUTO_BREAK_CONE On
set_global_assignment -name EQC_POWER_UP_COMPARE Off
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
set_global_assignment -name EQC_AUTO_INVERSION On
set_global_assignment -name EQC_AUTO_TERMINATE On
set_global_assignment -name EQC_SUB_CONE_REPORT Off
set_global_assignment -name EQC_RENAMING_RULES On
set_global_assignment -name EQC_PARAMETER_CHECK On
set_global_assignment -name EQC_AUTO_PORTSWAP On
set_global_assignment -name EQC_DETECT_DONT_CARES On
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
set_global_assignment -name DUTY_CYCLE 50 -section_id ?
set_global_assignment -name INVERT_BASE_CLOCK Off -section_id ?
set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id ?
set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id ?
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ?
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?

0
myArkanoid_description.txt Normal file
View file

60
undo_redo.txt Normal file
View file

@ -0,0 +1,60 @@
GED
Undo Commands
1. Move
2. Move
3. Move
4. Move
5. Move
6. Move
7. Move
8. Move
9. Move
10. Move
11. Move
12. Move
13. Move
14. Resize
15. Move
16. Move
17. Move
18. Move
19. Move
20. Move
21. Move
22. Move
23. Move
24. Move
25. Move
26. Move
27. Move
28. Move
29. Move
30. Move
31. Move
32. Move
33. Move
34. Move
35. Delete Insert
36. Move
37. Move
38. Move
39. Move
40. Move
41. Move
42. Move
43. Move
44. Move
45. Move
46. Delete Insert
47. Update Symbol or Block
48. Update Symbol or Block
49. Insert Node
50. Move
51. Delete
52. Delete
53. Delete
54. Move
55. Delete